drm/amdgpu: remove duplicate definition of cik_mqd

+54 -81

1 changed file

expand all

drivers

gpu

drm

amd

amdgpu

gfx_v7_0.c

+54 -81

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

··· 27 27 #include "amdgpu_gfx.h" 28 28 #include "cikd.h" 29 29 #include "cik.h" 30 + #include "cik_structs.h" 30 31 #include "atom.h" 31 32 #include "amdgpu_ucode.h" 32 33 #include "clearstate_ci.h" ··· 2917 2916 u32 cp_mqd_control; 2918 2917 }; 2919 2918 2920 - struct bonaire_mqd 2921 - { 2922 - u32 header; 2923 - u32 dispatch_initiator; 2924 - u32 dimensions[3]; 2925 - u32 start_idx[3]; 2926 - u32 num_threads[3]; 2927 - u32 pipeline_stat_enable; 2928 - u32 perf_counter_enable; 2929 - u32 pgm[2]; 2930 - u32 tba[2]; 2931 - u32 tma[2]; 2932 - u32 pgm_rsrc[2]; 2933 - u32 vmid; 2934 - u32 resource_limits; 2935 - u32 static_thread_mgmt01[2]; 2936 - u32 tmp_ring_size; 2937 - u32 static_thread_mgmt23[2]; 2938 - u32 restart[3]; 2939 - u32 thread_trace_enable; 2940 - u32 reserved1; 2941 - u32 user_data[16]; 2942 - u32 vgtcs_invoke_count[2]; 2943 - struct hqd_registers queue_state; 2944 - u32 dequeue_cntr; 2945 - u32 interrupt_queue[64]; 2946 - }; 2947 - 2948 2919 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, int me, int pipe) 2949 2920 { 2950 2921 u64 eop_gpu_addr; ··· 2970 2997 } 2971 2998 2972 2999 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, 2973 - struct bonaire_mqd *mqd, 3000 + struct cik_mqd *mqd, 2974 3001 uint64_t mqd_gpu_addr, 2975 3002 struct amdgpu_ring *ring) 2976 3003 { ··· 2978 3005 u64 wb_gpu_addr; 2979 3006 2980 3007 /* init the mqd struct */ 2981 - memset(mqd, 0, sizeof(struct bonaire_mqd)); 3008 + memset(mqd, 0, sizeof(struct cik_mqd)); 2982 3009 2983 3010 mqd->header = 0xC0310800; 2984 - mqd->static_thread_mgmt01[0] = 0xffffffff; 2985 - mqd->static_thread_mgmt01[1] = 0xffffffff; 2986 - mqd->static_thread_mgmt23[0] = 0xffffffff; 2987 - mqd->static_thread_mgmt23[1] = 0xffffffff; 3011 + mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3012 + mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3013 + mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3014 + mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2988 3015 2989 3016 /* enable doorbell? */ 2990 - mqd->queue_state.cp_hqd_pq_doorbell_control = 3017 + mqd->cp_hqd_pq_doorbell_control = 2991 3018 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2992 3019 if (ring->use_doorbell) 2993 - mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3020 + mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2994 3021 else 2995 - mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3022 + mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2996 3023 2997 3024 /* set the pointer to the MQD */ 2998 - mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc; 2999 - mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 3025 + mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 3026 + mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 3000 3027 3001 3028 /* set MQD vmid to 0 */ 3002 - mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 3003 - mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 3029 + mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 3030 + mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 3004 3031 3005 3032 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3006 3033 hqd_gpu_addr = ring->gpu_addr >> 8; 3007 - mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr; 3008 - mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3034 + mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3035 + mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3009 3036 3010 3037 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3011 - mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 3012 - mqd->queue_state.cp_hqd_pq_control &= 3038 + mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 3039 + mqd->cp_hqd_pq_control &= 3013 3040 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 3014 3041 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 3015 3042 3016 - mqd->queue_state.cp_hqd_pq_control |= 3043 + mqd->cp_hqd_pq_control |= 3017 3044 order_base_2(ring->ring_size / 8); 3018 - mqd->queue_state.cp_hqd_pq_control |= 3045 + mqd->cp_hqd_pq_control |= 3019 3046 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 3020 3047 #ifdef __BIG_ENDIAN 3021 - mqd->queue_state.cp_hqd_pq_control |= 3048 + mqd->cp_hqd_pq_control |= 3022 3049 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 3023 3050 #endif 3024 - mqd->queue_state.cp_hqd_pq_control &= 3051 + mqd->cp_hqd_pq_control &= 3025 3052 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 3026 3053 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 3027 3054 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 3028 - mqd->queue_state.cp_hqd_pq_control |= 3055 + mqd->cp_hqd_pq_control |= 3029 3056 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 3030 3057 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 3031 3058 3032 3059 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3033 3060 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3034 - mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; 3035 - mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3061 + mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3062 + mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3036 3063 3037 3064 /* set the wb address wether it's enabled or not */ 3038 3065 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3039 - mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc; 3040 - mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi = 3066 + mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3067 + mqd->cp_hqd_pq_rptr_report_addr_hi = 3041 3068 upper_32_bits(wb_gpu_addr) & 0xffff; 3042 3069 3043 3070 /* enable the doorbell if requested */ 3044 3071 if (ring->use_doorbell) { 3045 - mqd->queue_state.cp_hqd_pq_doorbell_control = 3072 + mqd->cp_hqd_pq_doorbell_control = 3046 3073 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3047 - mqd->queue_state.cp_hqd_pq_doorbell_control &= 3074 + mqd->cp_hqd_pq_doorbell_control &= 3048 3075 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 3049 - mqd->queue_state.cp_hqd_pq_doorbell_control |= 3076 + mqd->cp_hqd_pq_doorbell_control |= 3050 3077 (ring->doorbell_index << 3051 3078 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 3052 - mqd->queue_state.cp_hqd_pq_doorbell_control |= 3079 + mqd->cp_hqd_pq_doorbell_control |= 3053 3080 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3054 - mqd->queue_state.cp_hqd_pq_doorbell_control &= 3081 + mqd->cp_hqd_pq_doorbell_control &= 3055 3082 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 3056 3083 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 3057 3084 3058 3085 } else { 3059 - mqd->queue_state.cp_hqd_pq_doorbell_control = 0; 3086 + mqd->cp_hqd_pq_doorbell_control = 0; 3060 3087 } 3061 3088 3062 3089 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3063 3090 ring->wptr = 0; 3064 - mqd->queue_state.cp_hqd_pq_wptr = lower_32_bits(ring->wptr); 3065 - mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3091 + mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); 3092 + mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3066 3093 3067 3094 /* set the vmid for the queue */ 3068 - mqd->queue_state.cp_hqd_vmid = 0; 3095 + mqd->cp_hqd_vmid = 0; 3069 3096 3070 3097 /* activate the queue */ 3071 - mqd->queue_state.cp_hqd_active = 1; 3098 + mqd->cp_hqd_active = 1; 3072 3099 } 3073 3100 3074 3101 static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, 3075 - struct bonaire_mqd *mqd) 3102 + struct cik_mqd *mqd) 3076 3103 { 3077 3104 u32 tmp; 3078 3105 ··· 3082 3109 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 3083 3110 3084 3111 /* program MQD field to HW */ 3085 - WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); 3086 - WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); 3087 - WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); 3088 - WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); 3089 - WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); 3090 - WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); 3091 - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); 3092 - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi); 3093 - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, mqd->queue_state.cp_hqd_pq_rptr_report_addr); 3094 - WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi); 3095 - WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->queue_state.cp_hqd_pq_doorbell_control); 3096 - WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); 3097 - WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); 3112 + WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 3113 + WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3114 + WREG32(mmCP_MQD_CONTROL, mqd->cp_mqd_control); 3115 + WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 3116 + WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 3117 + WREG32(mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 3118 + WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo); 3119 + WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, mqd->cp_hqd_pq_wptr_poll_addr_hi); 3120 + WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, mqd->cp_hqd_pq_rptr_report_addr_lo); 3121 + WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, mqd->cp_hqd_pq_rptr_report_addr_hi); 3122 + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control); 3123 + WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); 3124 + WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3098 3125 3099 3126 /* activate the HQD */ 3100 - WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); 3127 + WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active); 3101 3128 3102 3129 return 0; 3103 3130 } ··· 3106 3133 { 3107 3134 int r; 3108 3135 u64 mqd_gpu_addr; 3109 - struct bonaire_mqd *mqd; 3136 + struct cik_mqd *mqd; 3110 3137 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 3111 3138 3112 3139 if (ring->mqd_obj == NULL) { 3113 3140 r = amdgpu_bo_create(adev, 3114 - sizeof(struct bonaire_mqd), 3141 + sizeof(struct cik_mqd), 3115 3142 PAGE_SIZE, true, 3116 3143 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 3117 3144 &ring->mqd_obj);

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