Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_cpu_for_v6.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpuid updates from Borislav Petkov:
- Remove the less generic CPU matching infra around struct x86_cpu_desc
and use the generic struct x86_cpu_id thing
- Remove magic naked numbers for CPUID functions and use proper defines
of the prefix CPUID_LEAF_*. Consolidate some of the crazy use around
the tree
- Smaller cleanups and improvements
* tag 'x86_cpu_for_v6.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/cpu: Make all all CPUID leaf names consistent
x86/fpu: Remove unnecessary CPUID level check
x86/fpu: Move CPUID leaf definitions to common code
x86/tsc: Remove CPUID "frequency" leaf magic numbers.
x86/tsc: Move away from TSC leaf magic numbers
x86/cpu: Move TSC CPUID leaf definition
x86/cpu: Refresh DCA leaf reading code
x86/cpu: Remove unnecessary MwAIT leaf checks
x86/cpu: Use MWAIT leaf definition
x86/cpu: Move MWAIT leaf definition to common header
x86/cpu: Remove 'x86_cpu_desc' infrastructure
x86/cpu: Move AMD erratum 1386 table over to 'x86_cpu_id'
x86/cpu: Replace PEBS use of 'x86_cpu_desc' use with 'x86_cpu_id'
x86/cpu: Expose only stepping min/max interface
x86/cpu: Introduce new microcode matching helper
x86/cpufeature: Document cpu_feature_enabled() as the default to use
x86/paravirt: Remove the WBINVD callback
x86/cpufeatures: Free up unused feature bits
+179
-278
+26
-36
arch/x86/events/intel/core.c
+26
-36
arch/x86/events/intel/core.c
···
5381
5381
x86_pmu.pebs_constraints = NULL;
5382
5382
}
5383
5383
5384
-
static const struct x86_cpu_desc isolation_ucodes[] = {
5385
-
INTEL_CPU_DESC(INTEL_HASWELL, 3, 0x0000001f),
5386
-
INTEL_CPU_DESC(INTEL_HASWELL_L, 1, 0x0000001e),
5387
-
INTEL_CPU_DESC(INTEL_HASWELL_G, 1, 0x00000015),
5388
-
INTEL_CPU_DESC(INTEL_HASWELL_X, 2, 0x00000037),
5389
-
INTEL_CPU_DESC(INTEL_HASWELL_X, 4, 0x0000000a),
5390
-
INTEL_CPU_DESC(INTEL_BROADWELL, 4, 0x00000023),
5391
-
INTEL_CPU_DESC(INTEL_BROADWELL_G, 1, 0x00000014),
5392
-
INTEL_CPU_DESC(INTEL_BROADWELL_D, 2, 0x00000010),
5393
-
INTEL_CPU_DESC(INTEL_BROADWELL_D, 3, 0x07000009),
5394
-
INTEL_CPU_DESC(INTEL_BROADWELL_D, 4, 0x0f000009),
5395
-
INTEL_CPU_DESC(INTEL_BROADWELL_D, 5, 0x0e000002),
5396
-
INTEL_CPU_DESC(INTEL_BROADWELL_X, 1, 0x0b000014),
5397
-
INTEL_CPU_DESC(INTEL_SKYLAKE_X, 3, 0x00000021),
5398
-
INTEL_CPU_DESC(INTEL_SKYLAKE_X, 4, 0x00000000),
5399
-
INTEL_CPU_DESC(INTEL_SKYLAKE_X, 5, 0x00000000),
5400
-
INTEL_CPU_DESC(INTEL_SKYLAKE_X, 6, 0x00000000),
5401
-
INTEL_CPU_DESC(INTEL_SKYLAKE_X, 7, 0x00000000),
5402
-
INTEL_CPU_DESC(INTEL_SKYLAKE_X, 11, 0x00000000),
5403
-
INTEL_CPU_DESC(INTEL_SKYLAKE_L, 3, 0x0000007c),
5404
-
INTEL_CPU_DESC(INTEL_SKYLAKE, 3, 0x0000007c),
5405
-
INTEL_CPU_DESC(INTEL_KABYLAKE, 9, 0x0000004e),
5406
-
INTEL_CPU_DESC(INTEL_KABYLAKE_L, 9, 0x0000004e),
5407
-
INTEL_CPU_DESC(INTEL_KABYLAKE_L, 10, 0x0000004e),
5408
-
INTEL_CPU_DESC(INTEL_KABYLAKE_L, 11, 0x0000004e),
5409
-
INTEL_CPU_DESC(INTEL_KABYLAKE_L, 12, 0x0000004e),
5410
-
INTEL_CPU_DESC(INTEL_KABYLAKE, 10, 0x0000004e),
5411
-
INTEL_CPU_DESC(INTEL_KABYLAKE, 11, 0x0000004e),
5412
-
INTEL_CPU_DESC(INTEL_KABYLAKE, 12, 0x0000004e),
5413
-
INTEL_CPU_DESC(INTEL_KABYLAKE, 13, 0x0000004e),
5384
+
static const struct x86_cpu_id isolation_ucodes[] = {
5385
+
X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f),
5386
+
X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e),
5387
+
X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015),
5388
+
X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037),
5389
+
X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a),
5390
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023),
5391
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014),
5392
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010),
5393
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009),
5394
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009),
5395
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002),
5396
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014),
5397
+
X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021),
5398
+
X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000),
5399
+
X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000),
5400
+
X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c),
5401
+
X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c),
5402
+
X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e),
5403
+
X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e),
5414
5404
{}
5415
5405
};
5416
5406
5417
5407
static void intel_check_pebs_isolation(void)
5418
5408
{
5419
-
x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
5409
+
x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);
5420
5410
}
5421
5411
5422
5412
static __init void intel_pebs_isolation_quirk(void)
···
5416
5426
intel_check_pebs_isolation();
5417
5427
}
5418
5428
5419
-
static const struct x86_cpu_desc pebs_ucodes[] = {
5420
-
INTEL_CPU_DESC(INTEL_SANDYBRIDGE, 7, 0x00000028),
5421
-
INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 6, 0x00000618),
5422
-
INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 7, 0x0000070c),
5429
+
static const struct x86_cpu_id pebs_ucodes[] = {
5430
+
X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028),
5431
+
X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618),
5432
+
X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c),
5423
5433
{}
5424
5434
};
5425
5435
5426
5436
static bool intel_snb_pebs_broken(void)
5427
5437
{
5428
-
return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
5438
+
return !x86_match_min_microcode_rev(pebs_ucodes);
5429
5439
}
5430
5440
5431
5441
static void intel_snb_check_microcode(void)
+3
-2
arch/x86/events/intel/pt.c
+3
-2
arch/x86/events/intel/pt.c
···
18
18
#include <linux/slab.h>
19
19
#include <linux/device.h>
20
20
21
+
#include <asm/cpuid.h>
21
22
#include <asm/perf_event.h>
22
23
#include <asm/insn.h>
23
24
#include <asm/io.h>
···
202
201
* otherwise, zero for numerator stands for "not enumerated"
203
202
* as per SDM
204
203
*/
205
-
if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) {
204
+
if (boot_cpu_data.cpuid_level >= CPUID_LEAF_TSC) {
206
205
u32 eax, ebx, ecx, edx;
207
206
208
-
cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx);
207
+
cpuid(CPUID_LEAF_TSC, &eax, &ebx, &ecx, &edx);
209
208
210
209
pt_pmu.tsc_art_num = ebx;
211
210
pt_pmu.tsc_art_den = eax;
-3
arch/x86/events/intel/pt.h
-3
arch/x86/events/intel/pt.h
+9
-42
arch/x86/include/asm/cpu_device_id.h
+9
-42
arch/x86/include/asm/cpu_device_id.h
···
56
56
/* x86_cpu_id::flags */
57
57
#define X86_CPU_ID_FLAG_ENTRY_VALID BIT(0)
58
58
59
-
#define X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins)
60
59
/**
61
60
* X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE - Base macro for CPU matching
62
61
* @_vendor: The vendor name, e.g. INTEL, AMD, HYGON, ..., ANY
···
207
208
VFM_MODEL(vfm), \
208
209
X86_STEPPING_ANY, X86_FEATURE_ANY, data)
209
210
211
+
#define __X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins)
210
212
/**
211
213
* X86_MATCH_VFM_STEPPINGS - Match encoded vendor/family/model/stepping
212
214
* @vfm: Encoded 8-bits each for vendor, family, model
···
218
218
*
219
219
* feature is set to wildcard
220
220
*/
221
-
#define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \
222
-
X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \
223
-
VFM_VENDOR(vfm), \
224
-
VFM_FAMILY(vfm), \
225
-
VFM_MODEL(vfm), \
226
-
steppings, X86_FEATURE_ANY, data)
221
+
#define X86_MATCH_VFM_STEPS(vfm, min_step, max_step, data) \
222
+
X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \
223
+
VFM_VENDOR(vfm), \
224
+
VFM_FAMILY(vfm), \
225
+
VFM_MODEL(vfm), \
226
+
__X86_STEPPINGS(min_step, max_step), \
227
+
X86_FEATURE_ANY, data)
227
228
228
229
/**
229
230
* X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature
···
243
242
VFM_MODEL(vfm), \
244
243
X86_STEPPING_ANY, feature, data)
245
244
246
-
/*
247
-
* Match specific microcode revisions.
248
-
*
249
-
* vendor/family/model/stepping must be all set.
250
-
*
251
-
* Only checks against the boot CPU. When mixed-stepping configs are
252
-
* valid for a CPU model, add a quirk for every valid stepping and
253
-
* do the fine-tuning in the quirk handler.
254
-
*/
255
-
256
-
struct x86_cpu_desc {
257
-
u8 x86_family;
258
-
u8 x86_vendor;
259
-
u8 x86_model;
260
-
u8 x86_stepping;
261
-
u32 x86_microcode_rev;
262
-
};
263
-
264
-
#define INTEL_CPU_DESC(vfm, stepping, revision) { \
265
-
.x86_family = VFM_FAMILY(vfm), \
266
-
.x86_vendor = VFM_VENDOR(vfm), \
267
-
.x86_model = VFM_MODEL(vfm), \
268
-
.x86_stepping = (stepping), \
269
-
.x86_microcode_rev = (revision), \
270
-
}
271
-
272
-
#define AMD_CPU_DESC(fam, model, stepping, revision) { \
273
-
.x86_family = (fam), \
274
-
.x86_vendor = X86_VENDOR_AMD, \
275
-
.x86_model = (model), \
276
-
.x86_stepping = (stepping), \
277
-
.x86_microcode_rev = (revision), \
278
-
}
279
-
280
245
extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match);
281
-
extern bool x86_cpu_has_min_microcode_rev(const struct x86_cpu_desc *table);
246
+
extern bool x86_match_min_microcode_rev(const struct x86_cpu_id *table);
282
247
283
248
#endif /* _ASM_X86_CPU_DEVICE_ID */
+6
-12
arch/x86/include/asm/cpufeature.h
+6
-12
arch/x86/include/asm/cpufeature.h
···
132
132
x86_this_cpu_test_bit(bit, cpu_info.x86_capability))
133
133
134
134
/*
135
-
* This macro is for detection of features which need kernel
136
-
* infrastructure to be used. It may *not* directly test the CPU
137
-
* itself. Use the cpu_has() family if you want true runtime
138
-
* testing of CPU features, like in hypervisor code where you are
139
-
* supporting a possible guest feature where host support for it
135
+
* This is the default CPU features testing macro to use in code.
136
+
*
137
+
* It is for detection of features which need kernel infrastructure to be
138
+
* used. It may *not* directly test the CPU itself. Use the cpu_has() family
139
+
* if you want true runtime testing of CPU features, like in hypervisor code
140
+
* where you are supporting a possible guest feature where host support for it
140
141
* is not relevant.
141
142
*/
142
143
#define cpu_feature_enabled(bit) \
···
162
161
#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit)
163
162
164
163
/*
165
-
* Static testing of CPU features. Used the same as boot_cpu_has(). It
166
-
* statically patches the target code for additional performance. Use
167
-
* static_cpu_has() only in fast paths, where every cycle counts. Which
168
-
* means that the boot_cpu_has() variant is already fast enough for the
169
-
* majority of cases and you should stick to using it as it is generally
170
-
* only two instructions: a RIP-relative MOV and a TEST.
171
-
*
172
164
* Do not use an "m" constraint for [cap_byte] here: gcc doesn't know
173
165
* that this is only used on a fallback path and will sometimes cause
174
166
* it to manifest the address of boot_cpu_data in a register, fouling
+2
-2
arch/x86/include/asm/cpufeatures.h
+2
-2
arch/x86/include/asm/cpufeatures.h
···
83
83
#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* "centaur_mcr" Centaur MCRs (= MTRRs) */
84
84
#define X86_FEATURE_K8 ( 3*32+ 4) /* Opteron, Athlon64 */
85
85
#define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitecture */
86
-
#define X86_FEATURE_P3 ( 3*32+ 6) /* P3 */
87
-
#define X86_FEATURE_P4 ( 3*32+ 7) /* P4 */
86
+
/* Free ( 3*32+ 6) */
87
+
/* Free ( 3*32+ 7) */
88
88
#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* "constant_tsc" TSC ticks at a constant rate */
89
89
#define X86_FEATURE_UP ( 3*32+ 9) /* "up" SMP kernel running on UP */
90
90
#define X86_FEATURE_ART ( 3*32+10) /* "art" Always running timer (ART) */
+7
arch/x86/include/asm/cpuid.h
+7
arch/x86/include/asm/cpuid.h
···
21
21
CPUID_EDX,
22
22
};
23
23
24
+
#define CPUID_LEAF_MWAIT 0x5
25
+
#define CPUID_LEAF_DCA 0x9
26
+
#define CPUID_LEAF_XSTATE 0x0d
27
+
#define CPUID_LEAF_TSC 0x15
28
+
#define CPUID_LEAF_FREQ 0x16
29
+
#define CPUID_LEAF_TILE 0x1d
30
+
24
31
#ifdef CONFIG_X86_32
25
32
bool have_cpuid_p(void);
26
33
#else
-4
arch/x86/include/asm/fpu/xstate.h
-4
arch/x86/include/asm/fpu/xstate.h
-1
arch/x86/include/asm/mwait.h
-1
arch/x86/include/asm/mwait.h
-7
arch/x86/include/asm/paravirt.h
-7
arch/x86/include/asm/paravirt.h
···
180
180
PVOP_VCALL0(irq.halt);
181
181
}
182
182
183
-
extern noinstr void pv_native_wbinvd(void);
184
-
185
-
static __always_inline void wbinvd(void)
186
-
{
187
-
PVOP_ALT_VCALL0(cpu.wbinvd, "wbinvd", ALT_NOT_XEN);
188
-
}
189
-
190
183
static inline u64 paravirt_read_msr(unsigned msr)
191
184
{
192
185
return PVOP_CALL1(u64, cpu.read_msr, msr);
-2
arch/x86/include/asm/paravirt_types.h
-2
arch/x86/include/asm/paravirt_types.h
+1
-7
arch/x86/include/asm/special_insns.h
+1
-7
arch/x86/include/asm/special_insns.h
···
115
115
}
116
116
#endif
117
117
118
-
static __always_inline void native_wbinvd(void)
118
+
static __always_inline void wbinvd(void)
119
119
{
120
120
asm volatile("wbinvd": : :"memory");
121
121
}
···
167
167
{
168
168
native_write_cr4(x);
169
169
}
170
-
171
-
static __always_inline void wbinvd(void)
172
-
{
173
-
native_wbinvd();
174
-
}
175
-
176
170
#endif /* CONFIG_PARAVIRT_XXL */
177
171
178
172
static __always_inline void clflush(volatile void *__p)
+3
-2
arch/x86/kernel/acpi/cstate.c
+3
-2
arch/x86/kernel/acpi/cstate.c
···
13
13
#include <linux/sched.h>
14
14
15
15
#include <acpi/processor.h>
16
+
#include <asm/cpuid.h>
16
17
#include <asm/mwait.h>
17
18
#include <asm/special_insns.h>
18
19
···
129
128
unsigned int cstate_type; /* C-state type and not ACPI C-state type */
130
129
unsigned int num_cstate_subtype;
131
130
132
-
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
131
+
cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx);
133
132
134
133
/* Check whether this particular cx_type (in CST) is supported or not */
135
134
cstate_type = (((cx->address >> MWAIT_SUBSTATE_SIZE) &
···
173
172
struct cpuinfo_x86 *c = &cpu_data(cpu);
174
173
long retval;
175
174
176
-
if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
175
+
if (!cpu_cstate_entry || c->cpuid_level < CPUID_LEAF_MWAIT)
177
176
return -1;
178
177
179
178
if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
+9
-9
arch/x86/kernel/apic/apic.c
+9
-9
arch/x86/kernel/apic/apic.c
···
509
509
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
510
510
511
511
static const struct x86_cpu_id deadline_match[] __initconst = {
512
-
X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */
513
-
X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */
512
+
X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 0x2, 0x2, 0x3a), /* EP */
513
+
X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 0x4, 0x4, 0x0f), /* EX */
514
514
515
515
X86_MATCH_VFM(INTEL_BROADWELL_X, 0x0b000020),
516
516
517
-
X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011),
518
-
X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e),
519
-
X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c),
520
-
X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003),
517
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 0x2, 0x2, 0x00000011),
518
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 0x3, 0x3, 0x0700000e),
519
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 0x4, 0x4, 0x0f00000c),
520
+
X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 0x5, 0x5, 0x0e000003),
521
521
522
-
X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136),
523
-
X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014),
524
-
X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0),
522
+
X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 0x3, 0x3, 0x01000136),
523
+
X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 0x4, 0x4, 0x02000014),
524
+
X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 0x5, 0xf, 0),
525
525
526
526
X86_MATCH_VFM(INTEL_HASWELL, 0x22),
527
527
X86_MATCH_VFM(INTEL_HASWELL_L, 0x20),
+4
-5
arch/x86/kernel/cpu/amd.c
+4
-5
arch/x86/kernel/cpu/amd.c
···
800
800
clear_rdrand_cpuid_bit(c);
801
801
}
802
802
803
-
static const struct x86_cpu_desc erratum_1386_microcode[] = {
804
-
AMD_CPU_DESC(0x17, 0x1, 0x2, 0x0800126e),
805
-
AMD_CPU_DESC(0x17, 0x31, 0x0, 0x08301052),
806
-
{},
803
+
static const struct x86_cpu_id erratum_1386_microcode[] = {
804
+
X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x01), 0x2, 0x2, 0x0800126e),
805
+
X86_MATCH_VFM_STEPS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x31), 0x0, 0x0, 0x08301052),
807
806
};
808
807
809
808
static void fix_erratum_1386(struct cpuinfo_x86 *c)
···
818
819
* Clear the feature flag only on microcode revisions which
819
820
* don't have the fix.
820
821
*/
821
-
if (x86_cpu_has_min_microcode_rev(erratum_1386_microcode))
822
+
if (x86_match_min_microcode_rev(erratum_1386_microcode))
822
823
return;
823
824
824
825
clear_cpu_cap(c, X86_FEATURE_XSAVES);
+43
-42
arch/x86/kernel/cpu/common.c
+43
-42
arch/x86/kernel/cpu/common.c
···
29
29
30
30
#include <asm/alternative.h>
31
31
#include <asm/cmdline.h>
32
+
#include <asm/cpuid.h>
32
33
#include <asm/perf_event.h>
33
34
#include <asm/mmu_context.h>
34
35
#include <asm/doublefault.h>
···
637
636
638
637
static const struct cpuid_dependent_feature
639
638
cpuid_dependent_features[] = {
640
-
{ X86_FEATURE_MWAIT, 0x00000005 },
641
-
{ X86_FEATURE_DCA, 0x00000009 },
642
-
{ X86_FEATURE_XSAVE, 0x0000000d },
639
+
{ X86_FEATURE_MWAIT, CPUID_LEAF_MWAIT },
640
+
{ X86_FEATURE_DCA, CPUID_LEAF_DCA },
641
+
{ X86_FEATURE_XSAVE, CPUID_LEAF_XSTATE },
643
642
{ 0, 0 }
644
643
};
645
644
···
1202
1201
#define VULNBL(vendor, family, model, blacklist) \
1203
1202
X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1204
1203
1205
-
#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \
1206
-
X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues)
1204
+
#define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \
1205
+
X86_MATCH_VFM_STEPS(vfm, X86_STEP_MIN, max_stepping, issues)
1207
1206
1208
1207
#define VULNBL_AMD(family, blacklist) \
1209
1208
VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
···
1228
1227
#define RFDS BIT(7)
1229
1228
1230
1229
static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1231
-
VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1232
-
VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS),
1233
-
VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS),
1234
-
VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS),
1235
-
VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO),
1236
-
VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO),
1237
-
VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1238
-
VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO),
1239
-
VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS),
1240
-
VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1241
-
VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1242
-
VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1243
-
VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1244
-
VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1245
-
VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED),
1246
-
VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1247
-
VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS),
1248
-
VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS),
1249
-
VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1250
-
VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
1251
-
VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1252
-
VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS),
1253
-
VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS),
1254
-
VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
1255
-
VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1256
-
VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS),
1257
-
VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS),
1258
-
VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS),
1259
-
VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS),
1260
-
VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS),
1261
-
VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS),
1262
-
VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS),
1263
-
VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS),
1264
-
VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS),
1265
-
VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS),
1266
-
VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS),
1267
-
VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS),
1230
+
VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS),
1231
+
VULNBL_INTEL_STEPS(INTEL_HASWELL, X86_STEP_MAX, SRBDS),
1232
+
VULNBL_INTEL_STEPS(INTEL_HASWELL_L, X86_STEP_MAX, SRBDS),
1233
+
VULNBL_INTEL_STEPS(INTEL_HASWELL_G, X86_STEP_MAX, SRBDS),
1234
+
VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO),
1235
+
VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO),
1236
+
VULNBL_INTEL_STEPS(INTEL_BROADWELL_G, X86_STEP_MAX, SRBDS),
1237
+
VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO),
1238
+
VULNBL_INTEL_STEPS(INTEL_BROADWELL, X86_STEP_MAX, SRBDS),
1239
+
VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS),
1240
+
VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS),
1241
+
VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS),
1242
+
VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS),
1243
+
VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS),
1244
+
VULNBL_INTEL_STEPS(INTEL_CANNONLAKE_L, X86_STEP_MAX, RETBLEED),
1245
+
VULNBL_INTEL_STEPS(INTEL_ICELAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS),
1246
+
VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS),
1247
+
VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS),
1248
+
VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS),
1249
+
VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED),
1250
+
VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS),
1251
+
VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS),
1252
+
VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS),
1253
+
VULNBL_INTEL_STEPS(INTEL_LAKEFIELD, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED),
1254
+
VULNBL_INTEL_STEPS(INTEL_ROCKETLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS),
1255
+
VULNBL_INTEL_STEPS(INTEL_ALDERLAKE, X86_STEP_MAX, RFDS),
1256
+
VULNBL_INTEL_STEPS(INTEL_ALDERLAKE_L, X86_STEP_MAX, RFDS),
1257
+
VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE, X86_STEP_MAX, RFDS),
1258
+
VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_P, X86_STEP_MAX, RFDS),
1259
+
VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_S, X86_STEP_MAX, RFDS),
1260
+
VULNBL_INTEL_STEPS(INTEL_ATOM_GRACEMONT, X86_STEP_MAX, RFDS),
1261
+
VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS),
1262
+
VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS),
1263
+
VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS),
1264
+
VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT, X86_STEP_MAX, RFDS),
1265
+
VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_D, X86_STEP_MAX, RFDS),
1266
+
VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEP_MAX, RFDS),
1268
1267
1269
1268
VULNBL_AMD(0x15, RETBLEED),
1270
1269
VULNBL_AMD(0x16, RETBLEED),
-5
arch/x86/kernel/cpu/intel.c
-5
arch/x86/kernel/cpu/intel.c
+4
-24
arch/x86/kernel/cpu/match.c
+4
-24
arch/x86/kernel/cpu/match.c
···
56
56
}
57
57
EXPORT_SYMBOL(x86_match_cpu);
58
58
59
-
static const struct x86_cpu_desc *
60
-
x86_match_cpu_with_stepping(const struct x86_cpu_desc *match)
59
+
bool x86_match_min_microcode_rev(const struct x86_cpu_id *table)
61
60
{
62
-
struct cpuinfo_x86 *c = &boot_cpu_data;
63
-
const struct x86_cpu_desc *m;
61
+
const struct x86_cpu_id *res = x86_match_cpu(table);
64
62
65
-
for (m = match; m->x86_family | m->x86_model; m++) {
66
-
if (c->x86_vendor != m->x86_vendor)
67
-
continue;
68
-
if (c->x86 != m->x86_family)
69
-
continue;
70
-
if (c->x86_model != m->x86_model)
71
-
continue;
72
-
if (c->x86_stepping != m->x86_stepping)
73
-
continue;
74
-
return m;
75
-
}
76
-
return NULL;
77
-
}
78
-
79
-
bool x86_cpu_has_min_microcode_rev(const struct x86_cpu_desc *table)
80
-
{
81
-
const struct x86_cpu_desc *res = x86_match_cpu_with_stepping(table);
82
-
83
-
if (!res || res->x86_microcode_rev > boot_cpu_data.microcode)
63
+
if (!res || res->driver_data > boot_cpu_data.microcode)
84
64
return false;
85
65
86
66
return true;
87
67
}
88
-
EXPORT_SYMBOL_GPL(x86_cpu_has_min_microcode_rev);
68
+
EXPORT_SYMBOL_GPL(x86_match_min_microcode_rev);
+1
-1
arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+1
-1
arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+11
-15
arch/x86/kernel/fpu/xstate.c
+11
-15
arch/x86/kernel/fpu/xstate.c
···
20
20
#include <asm/fpu/signal.h>
21
21
#include <asm/fpu/xcr.h>
22
22
23
+
#include <asm/cpuid.h>
23
24
#include <asm/tlbflush.h>
24
25
#include <asm/prctl.h>
25
26
#include <asm/elf.h>
···
233
232
xmm_space);
234
233
235
234
for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {
236
-
cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
235
+
cpuid_count(CPUID_LEAF_XSTATE, i, &eax, &ebx, &ecx, &edx);
237
236
238
237
xstate_sizes[i] = eax;
239
238
xstate_flags[i] = ecx;
···
399
398
u32 eax, ebx, ecx, edx;
400
399
401
400
CHECK_XFEATURE(xfeature_nr);
402
-
cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
401
+
cpuid_count(CPUID_LEAF_XSTATE, xfeature_nr, &eax, &ebx, &ecx, &edx);
403
402
return eax;
404
403
}
405
404
···
442
441
* just in case there are some goodies up there
443
442
*/
444
443
for (i = 0; i < XFEATURE_MAX + 10; i++) {
445
-
cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
444
+
cpuid_count(CPUID_LEAF_XSTATE, i, &eax, &ebx, &ecx, &edx);
446
445
pr_warn("CPUID[%02x, %02x]: eax=%08x ebx=%08x ecx=%08x edx=%08x\n",
447
-
XSTATE_CPUID, i, eax, ebx, ecx, edx);
446
+
CPUID_LEAF_XSTATE, i, eax, ebx, ecx, edx);
448
447
}
449
448
}
450
449
···
485
484
* Check the maximum palette id:
486
485
* eax: the highest numbered palette subleaf.
487
486
*/
488
-
cpuid_count(TILE_CPUID, 0, &max_palid, &ebx, &ecx, &edx);
487
+
cpuid_count(CPUID_LEAF_TILE, 0, &max_palid, &ebx, &ecx, &edx);
489
488
490
489
/*
491
490
* Cross-check each tile size and find the maximum number of
···
499
498
* eax[31:16]: bytes per title
500
499
* ebx[31:16]: the max names (or max number of tiles)
501
500
*/
502
-
cpuid_count(TILE_CPUID, palid, &eax, &ebx, &edx, &edx);
501
+
cpuid_count(CPUID_LEAF_TILE, palid, &eax, &ebx, &edx, &edx);
503
502
tile_size = eax >> 16;
504
503
max = ebx >> 16;
505
504
···
634
633
* are no supervisor states, but XSAVEC still uses compacted
635
634
* format.
636
635
*/
637
-
cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);
636
+
cpuid_count(CPUID_LEAF_XSTATE, 1, &eax, &ebx, &ecx, &edx);
638
637
return ebx;
639
638
}
640
639
···
675
674
* containing all the *user* state components
676
675
* corresponding to bits currently set in XCR0.
677
676
*/
678
-
cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
677
+
cpuid_count(CPUID_LEAF_XSTATE, 0, &eax, &ebx, &ecx, &edx);
679
678
return ebx;
680
679
}
681
680
···
764
763
return;
765
764
}
766
765
767
-
if (boot_cpu_data.cpuid_level < XSTATE_CPUID) {
768
-
WARN_ON_FPU(1);
769
-
return;
770
-
}
771
-
772
766
/*
773
767
* Find user xstates supported by the processor.
774
768
*/
775
-
cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
769
+
cpuid_count(CPUID_LEAF_XSTATE, 0, &eax, &ebx, &ecx, &edx);
776
770
fpu_kernel_cfg.max_features = eax + ((u64)edx << 32);
777
771
778
772
/*
779
773
* Find supervisor xstates supported by the processor.
780
774
*/
781
-
cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);
775
+
cpuid_count(CPUID_LEAF_XSTATE, 1, &eax, &ebx, &ecx, &edx);
782
776
fpu_kernel_cfg.max_features |= ecx + ((u64)edx << 32);
783
777
784
778
if ((fpu_kernel_cfg.max_features & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) {
+2
-4
arch/x86/kernel/hpet.c
+2
-4
arch/x86/kernel/hpet.c
···
7
7
#include <linux/cpu.h>
8
8
#include <linux/irq.h>
9
9
10
+
#include <asm/cpuid.h>
10
11
#include <asm/irq_remapping.h>
11
12
#include <asm/hpet.h>
12
13
#include <asm/time.h>
···
928
927
if (!cpu_feature_enabled(X86_FEATURE_MWAIT))
929
928
return false;
930
929
931
-
if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
932
-
return false;
933
-
934
-
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
930
+
cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &mwait_substates);
935
931
936
932
return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) &&
937
933
(ecx & CPUID5_ECX_INTERRUPT_BREAK) &&
-6
arch/x86/kernel/paravirt.c
-6
arch/x86/kernel/paravirt.c
···
116
116
native_set_debugreg(regno, val);
117
117
}
118
118
119
-
noinstr void pv_native_wbinvd(void)
120
-
{
121
-
native_wbinvd();
122
-
}
123
-
124
119
static noinstr void pv_native_safe_halt(void)
125
120
{
126
121
native_safe_halt();
···
143
148
.cpu.read_cr0 = native_read_cr0,
144
149
.cpu.write_cr0 = native_write_cr0,
145
150
.cpu.write_cr4 = native_write_cr4,
146
-
.cpu.wbinvd = pv_native_wbinvd,
147
151
.cpu.read_msr = native_read_msr,
148
152
.cpu.write_msr = native_write_msr,
149
153
.cpu.read_msr_safe = native_read_msr_safe,
+4
-3
arch/x86/kernel/process.c
+4
-3
arch/x86/kernel/process.c
···
30
30
#include <linux/hw_breakpoint.h>
31
31
#include <linux/entry-common.h>
32
32
#include <asm/cpu.h>
33
+
#include <asm/cpuid.h>
33
34
#include <asm/apic.h>
34
35
#include <linux/uaccess.h>
35
36
#include <asm/mwait.h>
···
826
825
* X86_FEATURE_SME due to cmdline options.
827
826
*/
828
827
if (c->extended_cpuid_level >= 0x8000001f && (cpuid_eax(0x8000001f) & BIT(0)))
829
-
native_wbinvd();
828
+
wbinvd();
830
829
831
830
/*
832
831
* This brings a cache line back and dirties it, but
···
847
846
/*
848
847
* Use native_halt() so that memory contents don't change
849
848
* (stack usage and variables) after possibly issuing the
850
-
* native_wbinvd() above.
849
+
* wbinvd() above.
851
850
*/
852
851
native_halt();
853
852
}
···
878
877
if (boot_cpu_has_bug(X86_BUG_MONITOR) || boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E))
879
878
return false;
880
879
881
-
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
880
+
cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx);
882
881
883
882
/*
884
883
* If MWAIT extensions are not available, it is safe to use MWAIT
+2
-3
arch/x86/kernel/smpboot.c
+2
-3
arch/x86/kernel/smpboot.c
···
64
64
65
65
#include <asm/acpi.h>
66
66
#include <asm/cacheinfo.h>
67
+
#include <asm/cpuid.h>
67
68
#include <asm/desc.h>
68
69
#include <asm/nmi.h>
69
70
#include <asm/irq.h>
···
1292
1291
return;
1293
1292
if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1294
1293
return;
1295
-
if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1296
-
return;
1297
1294
1298
-
eax = CPUID_MWAIT_LEAF;
1295
+
eax = CPUID_LEAF_MWAIT;
1299
1296
ecx = 0;
1300
1297
native_cpuid(&eax, &ebx, &ecx, &edx);
1301
1298
+11
-12
arch/x86/kernel/tsc.c
+11
-12
arch/x86/kernel/tsc.c
···
16
16
#include <linux/static_key.h>
17
17
#include <linux/static_call.h>
18
18
19
+
#include <asm/cpuid.h>
19
20
#include <asm/hpet.h>
20
21
#include <asm/timer.h>
21
22
#include <asm/vgtod.h>
···
667
666
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
668
667
return 0;
669
668
670
-
if (boot_cpu_data.cpuid_level < 0x15)
669
+
if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC)
671
670
return 0;
672
671
673
672
eax_denominator = ebx_numerator = ecx_hz = edx = 0;
674
673
675
674
/* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
676
-
cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
675
+
cpuid(CPUID_LEAF_TSC, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
677
676
678
677
if (ebx_numerator == 0 || eax_denominator == 0)
679
678
return 0;
···
682
681
683
682
/*
684
683
* Denverton SoCs don't report crystal clock, and also don't support
685
-
* CPUID.0x16 for the calculation below, so hardcode the 25MHz crystal
686
-
* clock.
684
+
* CPUID_LEAF_FREQ for the calculation below, so hardcode the 25MHz
685
+
* crystal clock.
687
686
*/
688
687
if (crystal_khz == 0 &&
689
688
boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT_D)
···
702
701
* clock, but we can easily calculate it to a high degree of accuracy
703
702
* by considering the crystal ratio and the CPU speed.
704
703
*/
705
-
if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= 0x16) {
704
+
if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= CPUID_LEAF_FREQ) {
706
705
unsigned int eax_base_mhz, ebx, ecx, edx;
707
706
708
-
cpuid(0x16, &eax_base_mhz, &ebx, &ecx, &edx);
707
+
cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx);
709
708
crystal_khz = eax_base_mhz * 1000 *
710
709
eax_denominator / ebx_numerator;
711
710
}
···
740
739
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
741
740
return 0;
742
741
743
-
if (boot_cpu_data.cpuid_level < 0x16)
742
+
if (boot_cpu_data.cpuid_level < CPUID_LEAF_FREQ)
744
743
return 0;
745
744
746
745
eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
747
746
748
-
cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
747
+
cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
749
748
750
749
return eax_base_mhz * 1000;
751
750
}
···
1069
1068
1070
1069
#endif /* CONFIG_CPU_FREQ */
1071
1070
1072
-
#define ART_CPUID_LEAF (0x15)
1073
1071
#define ART_MIN_DENOMINATOR (1)
1074
-
1075
1072
1076
1073
/*
1077
1074
* If ART is present detect the numerator:denominator to convert to TSC
···
1078
1079
{
1079
1080
unsigned int unused;
1080
1081
1081
-
if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
1082
+
if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC)
1082
1083
return;
1083
1084
1084
1085
/*
···
1091
1092
tsc_async_resets)
1092
1093
return;
1093
1094
1094
-
cpuid(ART_CPUID_LEAF, &art_base_clk.denominator,
1095
+
cpuid(CPUID_LEAF_TSC, &art_base_clk.denominator,
1095
1096
&art_base_clk.numerator, &art_base_clk.freq_khz, &unused);
1096
1097
1097
1098
art_base_clk.freq_khz /= KHZ;
+3
-4
arch/x86/xen/enlighten_pv.c
+3
-4
arch/x86/xen/enlighten_pv.c
···
49
49
#include <xen/hvc-console.h>
50
50
#include <xen/acpi.h>
51
51
52
+
#include <asm/cpuid.h>
52
53
#include <asm/paravirt.h>
53
54
#include <asm/apic.h>
54
55
#include <asm/page.h>
···
231
230
or_ebx = smp_processor_id() << 24;
232
231
break;
233
232
234
-
case CPUID_MWAIT_LEAF:
233
+
case CPUID_LEAF_MWAIT:
235
234
/* Synthesize the values.. */
236
235
*ax = 0;
237
236
*bx = 0;
···
301
300
* ecx and edx. The hypercall provides only partial information.
302
301
*/
303
302
304
-
ax = CPUID_MWAIT_LEAF;
303
+
ax = CPUID_LEAF_MWAIT;
305
304
bx = 0;
306
305
cx = 0;
307
306
dx = 0;
···
1161
1160
.write_cr0 = xen_write_cr0,
1162
1161
1163
1162
.write_cr4 = xen_write_cr4,
1164
-
1165
-
.wbinvd = pv_native_wbinvd,
1166
1163
1167
1164
.read_msr = xen_read_msr,
1168
1165
.write_msr = xen_write_msr,
+2
-3
drivers/acpi/acpi_pad.c
+2
-3
drivers/acpi/acpi_pad.c
···
19
19
#include <linux/acpi.h>
20
20
#include <linux/perf_event.h>
21
21
#include <linux/platform_device.h>
22
+
#include <asm/cpuid.h>
22
23
#include <asm/mwait.h>
23
24
#include <xen/xen.h>
24
25
···
47
46
48
47
if (!boot_cpu_has(X86_FEATURE_MWAIT))
49
48
return;
50
-
if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
51
-
return;
52
49
53
-
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
50
+
cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx);
54
51
55
52
if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
56
53
!(ecx & CPUID5_ECX_INTERRUPT_BREAK))
+5
-3
drivers/dma/ioat/dca.c
+5
-3
drivers/dma/ioat/dca.c
···
10
10
#include <linux/interrupt.h>
11
11
#include <linux/dca.h>
12
12
13
+
#include <asm/cpuid.h>
14
+
13
15
/* either a kernel change is needed, or we need something like this in kernel */
14
16
#ifndef CONFIG_SMP
15
17
#include <asm/smp.h>
···
60
58
{
61
59
/* CPUID level 9 returns DCA configuration */
62
60
/* Bit 0 indicates DCA enabled by the BIOS */
63
-
unsigned long cpuid_level_9;
61
+
u32 eax;
64
62
int res;
65
63
66
-
cpuid_level_9 = cpuid_eax(9);
67
-
res = test_bit(0, &cpuid_level_9);
64
+
eax = cpuid_eax(CPUID_LEAF_DCA);
65
+
res = eax & BIT(0);
68
66
if (!res)
69
67
dev_dbg(&pdev->dev, "DCA is disabled in BIOS\n");
70
68
+12
-11
drivers/edac/i10nm_base.c
+12
-11
drivers/edac/i10nm_base.c
···
938
938
};
939
939
940
940
static const struct x86_cpu_id i10nm_cpuids[] = {
941
-
X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
942
-
X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
943
-
X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
944
-
X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
945
-
X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
946
-
X86_MATCH_VFM_STEPPINGS(INTEL_SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg),
947
-
X86_MATCH_VFM_STEPPINGS(INTEL_EMERALDRAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg),
948
-
X86_MATCH_VFM_STEPPINGS(INTEL_GRANITERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
949
-
X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT_X, X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
950
-
X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT, X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
951
-
X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_DARKMONT_X, X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
941
+
X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MIN, 0x3, &i10nm_cfg0),
942
+
X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, 0x4, X86_STEP_MAX, &i10nm_cfg1),
943
+
X86_MATCH_VFM_STEPS(INTEL_ICELAKE_X, X86_STEP_MIN, 0x3, &i10nm_cfg0),
944
+
X86_MATCH_VFM_STEPS(INTEL_ICELAKE_X, 0x4, X86_STEP_MAX, &i10nm_cfg1),
945
+
X86_MATCH_VFM( INTEL_ICELAKE_D, &i10nm_cfg1),
946
+
947
+
X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_cfg),
948
+
X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_cfg),
949
+
X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_cfg),
950
+
X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &gnr_cfg),
951
+
X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &gnr_cfg),
952
+
X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &gnr_cfg),
952
953
{}
953
954
};
954
955
MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
+1
-1
drivers/edac/skx_base.c
+1
-1
drivers/edac/skx_base.c
+2
-4
drivers/idle/intel_idle.c
+2
-4
drivers/idle/intel_idle.c
···
51
51
#include <linux/notifier.h>
52
52
#include <linux/cpu.h>
53
53
#include <linux/moduleparam.h>
54
+
#include <asm/cpuid.h>
54
55
#include <asm/cpu_device_id.h>
55
56
#include <asm/intel-family.h>
56
57
#include <asm/mwait.h>
···
2317
2316
return -ENODEV;
2318
2317
}
2319
2318
2320
-
if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
2321
-
return -ENODEV;
2322
-
2323
-
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
2319
+
cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &mwait_substates);
2324
2320
2325
2321
if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
2326
2322
!(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
+4
-3
drivers/platform/x86/intel/pmc/core.c
+4
-3
drivers/platform/x86/intel/pmc/core.c
···
22
22
#include <linux/suspend.h>
23
23
#include <linux/units.h>
24
24
25
+
#include <asm/cpuid.h>
25
26
#include <asm/cpu_device_id.h>
26
27
#include <asm/intel-family.h>
27
28
#include <asm/msr.h>
···
936
935
{
937
936
unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
938
937
939
-
if (boot_cpu_data.cpuid_level < 0x15)
938
+
if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC)
940
939
return 0;
941
940
942
941
eax_denominator = ebx_numerator = ecx_hz = edx = 0;
943
942
944
-
/* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
945
-
cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
943
+
/* TSC/Crystal ratio, plus optionally Crystal Hz */
944
+
cpuid(CPUID_LEAF_TSC, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
946
945
947
946
if (ebx_numerator == 0 || eax_denominator == 0)
948
947
return 0;