tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64

Pull arm64 fixes from Catalin Marinas:
- correct argument type (pgprot_t) when calling __ioremap()
- PCI_IOBASE virtual address change
- use architected event for CPU cycle counter
- fix ELF core dumping
- select CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION
- missing completion for secondary CPU boot
- booting on systems with all memory beyond 4GB

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64:
arm64: mm: fix booting on systems with no memory below 4GB
arm64: smp: add missing completion for secondary boot
arm64: compat: select CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION
arm64: elf: fix core dumping definitions for GP and FP registers
arm64: perf: use architected event for CPU cycle counter
arm64: Move PCI_IOBASE closer to MODULES_VADDR
arm64: Use pgprot_t as the last argument when invoking __ioremap()

Linus Torvalds 487bda54 0020dd0b

+21 -48
+7 -7
Documentation/arm64/memory.txt
··· 27 27 ----------------------------------------------------------------------- 28 28 0000000000000000 0000007fffffffff 512GB user 29 29 30 - ffffff8000000000 ffffffbbfffcffff ~240GB vmalloc 30 + ffffff8000000000 ffffffbbfffeffff ~240GB vmalloc 31 31 32 - ffffffbbfffd0000 ffffffbcfffdffff 64KB [guard page] 33 - 34 - ffffffbbfffe0000 ffffffbcfffeffff 64KB PCI I/O space 35 - 36 - ffffffbbffff0000 ffffffbcffffffff 64KB [guard page] 32 + ffffffbbffff0000 ffffffbbffffffff 64KB [guard page] 37 33 38 34 ffffffbc00000000 ffffffbdffffffff 8GB vmemmap 39 35 40 - ffffffbe00000000 ffffffbffbffffff ~8GB [guard, future vmmemap] 36 + ffffffbe00000000 ffffffbffbbfffff ~8GB [guard, future vmmemap] 37 + 38 + ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O space 39 + 40 + ffffffbbffff0000 ffffffbcffffffff ~2MB [guard] 41 41 42 42 ffffffbffc000000 ffffffbfffffffff 64MB modules 43 43
+1
arch/arm64/Kconfig
··· 1 1 config ARM64 2 2 def_bool y 3 3 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 4 + select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 4 5 select GENERIC_CLOCKEVENTS 5 6 select GENERIC_HARDIRQS_NO_DEPRECATED 6 7 select GENERIC_IOMAP
+1 -4
arch/arm64/include/asm/elf.h
··· 25 25 #include <asm/user.h> 26 26 27 27 typedef unsigned long elf_greg_t; 28 - typedef unsigned long elf_freg_t[3]; 29 28 30 29 #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) 31 30 typedef elf_greg_t elf_gregset_t[ELF_NGREG]; 32 - 33 - typedef struct user_fp elf_fpregset_t; 31 + typedef struct user_fpsimd_state elf_fpregset_t; 34 32 35 33 #define EM_AARCH64 183 36 34 ··· 84 86 #define R_AARCH64_MOVW_PREL_G2 291 85 87 #define R_AARCH64_MOVW_PREL_G2_NC 292 86 88 #define R_AARCH64_MOVW_PREL_G3 293 87 - 88 89 89 90 /* 90 91 * These are used to set parameters in the core dumps.
+2 -3
arch/arm64/include/asm/fpsimd.h
··· 25 25 * - FPSR and FPCR 26 26 * - 32 128-bit data registers 27 27 * 28 - * Note that user_fp forms a prefix of this structure, which is relied 29 - * upon in the ptrace FP/SIMD accessors. struct user_fpsimd_state must 30 - * form a prefix of struct fpsimd_state. 28 + * Note that user_fpsimd forms a prefix of this structure, which is 29 + * relied upon in the ptrace FP/SIMD accessors. 31 30 */ 32 31 struct fpsimd_state { 33 32 union {
+4 -4
arch/arm64/include/asm/io.h
··· 114 114 * I/O port access primitives. 115 115 */ 116 116 #define IO_SPACE_LIMIT 0xffff 117 - #define PCI_IOBASE ((void __iomem *)0xffffffbbfffe0000UL) 117 + #define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_2M)) 118 118 119 119 static inline u8 inb(unsigned long addr) 120 120 { ··· 225 225 #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_XN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 226 226 #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC)) 227 227 228 - #define ioremap(addr, size) __ioremap((addr), (size), PROT_DEVICE_nGnRE) 229 - #define ioremap_nocache(addr, size) __ioremap((addr), (size), PROT_DEVICE_nGnRE) 230 - #define ioremap_wc(addr, size) __ioremap((addr), (size), PROT_NORMAL_NC) 228 + #define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) 229 + #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) 230 + #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) 231 231 #define iounmap __iounmap 232 232 233 233 #define ARCH_HAS_IOREMAP_WC
+2
arch/arm64/include/asm/processor.h
··· 43 43 #else 44 44 #define STACK_TOP STACK_TOP_MAX 45 45 #endif /* CONFIG_COMPAT */ 46 + 47 + #define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK 46 48 #endif /* __KERNEL__ */ 47 49 48 50 struct debug_info {
-1
arch/arm64/include/asm/unistd.h
··· 14 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 15 */ 16 16 #ifdef CONFIG_COMPAT 17 - #define __ARCH_WANT_COMPAT_IPC_PARSE_VERSION 18 17 #define __ARCH_WANT_COMPAT_STAT64 19 18 #define __ARCH_WANT_SYS_GETHOSTNAME 20 19 #define __ARCH_WANT_SYS_PAUSE
+2 -8
arch/arm64/kernel/perf_event.c
··· 613 613 ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19, 614 614 ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A, 615 615 ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D, 616 - 617 - /* 618 - * This isn't an architected event. 619 - * We detect this event number and use the cycle counter instead. 620 - */ 621 - ARMV8_PMUV3_PERFCTR_CPU_CYCLES = 0xFF, 622 616 }; 623 617 624 618 /* PMUv3 HW events mapping. */ 625 619 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = { 626 - [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, 620 + [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES, 627 621 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED, 628 622 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS, 629 623 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL, ··· 1100 1106 unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT; 1101 1107 1102 1108 /* Always place a cycle counter into the cycle counter. */ 1103 - if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { 1109 + if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) { 1104 1110 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) 1105 1111 return -EAGAIN; 1106 1112
-18
arch/arm64/kernel/process.c
··· 310 310 } 311 311 312 312 /* 313 - * Fill in the task's elfregs structure for a core dump. 314 - */ 315 - int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs) 316 - { 317 - elf_core_copy_regs(elfregs, task_pt_regs(t)); 318 - return 1; 319 - } 320 - 321 - /* 322 - * fill in the fpe structure for a core dump... 323 - */ 324 - int dump_fpu (struct pt_regs *regs, struct user_fp *fp) 325 - { 326 - return 0; 327 - } 328 - EXPORT_SYMBOL(dump_fpu); 329 - 330 - /* 331 313 * Shuffle the argument into the correct register before calling the 332 314 * thread function. x1 is the thread argument, x2 is the pointer to 333 315 * the thread function, and x3 points to the exit function.
+1 -2
arch/arm64/kernel/smp.c
··· 211 211 * before we continue. 212 212 */ 213 213 set_cpu_online(cpu, true); 214 - while (!cpu_active(cpu)) 215 - cpu_relax(); 214 + complete(&cpu_running); 216 215 217 216 /* 218 217 * OK, it's off to the idle thread for us
+1 -1
arch/arm64/mm/init.c
··· 80 80 #ifdef CONFIG_ZONE_DMA32 81 81 /* 4GB maximum for 32-bit only capable devices */ 82 82 max_dma32 = min(max, MAX_DMA32_PFN); 83 - zone_size[ZONE_DMA32] = max_dma32 - min; 83 + zone_size[ZONE_DMA32] = max(min, max_dma32) - min; 84 84 #endif 85 85 zone_size[ZONE_NORMAL] = max - max_dma32; 86 86