Merge tag 'powerpc-6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

+4 -4

Documentation/admin-guide/kernel-parameters.txt

··· 3629 3629 (bounds check bypass). With this option data leaks are 3630 3630 possible in the system. 3631 3631 3632 - nospectre_v2 [X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for 3632 + nospectre_v2 [X86,PPC_E500,ARM64] Disable all mitigations for 3633 3633 the Spectre variant 2 (indirect branch prediction) 3634 3634 vulnerability. System may allow data leaks with this 3635 3635 option. ··· 3748 3748 [X86,PV_OPS] Disable paravirtualized VMware scheduler 3749 3749 clock and use the default one. 3750 3750 3751 - no-steal-acc [X86,PV_OPS,ARM64] Disable paravirtualized steal time 3752 - accounting. steal time is computed, but won't 3753 - influence scheduler behaviour 3751 + no-steal-acc [X86,PV_OPS,ARM64,PPC/PSERIES] Disable paravirtualized 3752 + steal time accounting. steal time is computed, but 3753 + won't influence scheduler behaviour 3754 3754 3755 3755 nolapic [X86-32,APIC] Do not enable or use the local APIC. 3756 3756

+22

Documentation/powerpc/isa-versions.rst

··· 4 4 5 5 Mapping of some CPU versions to relevant ISA versions. 6 6 7 + Note Power4 and Power4+ are not supported. 8 + 7 9 ========= ==================================================================== 8 10 CPU Architecture version 9 11 ========= ==================================================================== 10 12 Power10 Power ISA v3.1 11 13 Power9 Power ISA v3.0B 12 14 Power8 Power ISA v2.07 15 + e6500 Power ISA v2.06 with some exceptions 16 + e5500 Power ISA v2.06 with some exceptions, no Altivec 13 17 Power7 Power ISA v2.06 14 18 Power6 Power ISA v2.05 15 19 PA6T Power ISA v2.04 ··· 28 24 - PowerPC Virtual Environment Architecture Book II v2.01 29 25 - PowerPC Operating Environment Architecture Book III v2.01 30 26 - Plus Altivec/VMX ~= 2.03 27 + Power4+ - PowerPC User Instruction Set Architecture Book I v2.01 28 + - PowerPC Virtual Environment Architecture Book II v2.01 29 + - PowerPC Operating Environment Architecture Book III v2.01 30 + Power4 - PowerPC User Instruction Set Architecture Book I v2.00 31 + - PowerPC Virtual Environment Architecture Book II v2.00 32 + - PowerPC Operating Environment Architecture Book III v2.00 31 33 ========= ==================================================================== 32 34 33 35 ··· 46 36 Power10 Yes 47 37 Power9 Yes 48 38 Power8 Yes 39 + e6500 Yes 40 + e5500 No 49 41 Power7 Yes 50 42 Power6 Yes 51 43 PA6T Yes ··· 56 44 Power5+ No 57 45 Power5 No 58 46 PPC970 Yes 47 + Power4+ No 48 + Power4 No 59 49 ========== ================== 60 50 61 51 ========== ==== ··· 66 52 Power10 Yes 67 53 Power9 Yes 68 54 Power8 Yes 55 + e6500 No 56 + e5500 No 69 57 Power7 Yes 70 58 Power6 No 71 59 PA6T No ··· 76 60 Power5+ No 77 61 Power5 No 78 62 PPC970 No 63 + Power4+ No 64 + Power4 No 79 65 ========== ==== 80 66 81 67 ========== ==================================== ··· 86 68 Power10 No (* see Power ISA v3.1, "Appendix A. Notes on the Removal of Transactional Memory from the Architecture") 87 69 Power9 Yes (* see transactional_memory.txt) 88 70 Power8 Yes 71 + e6500 No 72 + e5500 No 89 73 Power7 No 90 74 Power6 No 91 75 PA6T No ··· 96 76 Power5+ No 97 77 Power5 No 98 78 PPC970 No 79 + Power4+ No 80 + Power4 No 99 81 ========== ====================================

+18 -17

arch/powerpc/Kconfig

··· 135 135 select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64 136 136 select ARCH_HAS_SET_MEMORY 137 137 select ARCH_HAS_STRICT_KERNEL_RWX if (PPC_BOOK3S || PPC_8xx || 40x) && !HIBERNATION 138 - select ARCH_HAS_STRICT_KERNEL_RWX if FSL_BOOKE && !HIBERNATION && !RANDOMIZE_BASE 138 + select ARCH_HAS_STRICT_KERNEL_RWX if PPC_85xx && !HIBERNATION && !RANDOMIZE_BASE 139 139 select ARCH_HAS_STRICT_MODULE_RWX if ARCH_HAS_STRICT_KERNEL_RWX 140 + select ARCH_HAS_SYSCALL_WRAPPER if !SPU_BASE && !COMPAT 140 141 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 141 142 select ARCH_HAS_UACCESS_FLUSHCACHE 142 143 select ARCH_HAS_UBSAN_SANITIZE_ALL ··· 195 194 select HAVE_ARCH_KASAN if PPC_RADIX_MMU 196 195 select HAVE_ARCH_KASAN if PPC_BOOK3E_64 197 196 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 198 - select HAVE_ARCH_KFENCE if PPC_BOOK3S_32 || PPC_8xx || 40x 197 + select HAVE_ARCH_KFENCE if ARCH_SUPPORTS_DEBUG_PAGEALLOC 199 198 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 200 199 select HAVE_ARCH_KGDB 201 200 select HAVE_ARCH_MMAP_RND_BITS ··· 212 211 select HAVE_DYNAMIC_FTRACE_WITH_ARGS if MPROFILE_KERNEL || PPC32 213 212 select HAVE_DYNAMIC_FTRACE_WITH_REGS if MPROFILE_KERNEL || PPC32 214 213 select HAVE_EBPF_JIT 215 - select HAVE_EFFICIENT_UNALIGNED_ACCESS if !(CPU_LITTLE_ENDIAN && POWER7_CPU) 214 + select HAVE_EFFICIENT_UNALIGNED_ACCESS 216 215 select HAVE_FAST_GUP 217 216 select HAVE_FTRACE_MCOUNT_RECORD 218 217 select HAVE_FUNCTION_DESCRIPTORS if PPC64_ELF_ABI_V1 ··· 291 290 config PPC_BARRIER_NOSPEC 292 291 bool 293 292 default y 294 - depends on PPC_BOOK3S_64 || PPC_FSL_BOOK3E 293 + depends on PPC_BOOK3S_64 || PPC_E500 295 294 296 295 config EARLY_PRINTK 297 296 bool ··· 549 548 550 549 config KEXEC 551 550 bool "kexec system call" 552 - depends on (PPC_BOOK3S || FSL_BOOKE || (44x && !SMP)) || PPC_BOOK3E 551 + depends on PPC_BOOK3S || PPC_E500 || (44x && !SMP) 553 552 select KEXEC_CORE 554 553 help 555 554 kexec is a system call that implements the ability to shutdown your ··· 584 583 585 584 config RELOCATABLE 586 585 bool "Build a relocatable kernel" 587 - depends on PPC64 || (FLATMEM && (44x || FSL_BOOKE)) 586 + depends on PPC64 || (FLATMEM && (44x || PPC_85xx)) 588 587 select NONSTATIC_KERNEL 589 588 help 590 589 This builds a kernel image that is capable of running at the ··· 607 606 608 607 config RANDOMIZE_BASE 609 608 bool "Randomize the address of the kernel image" 610 - depends on (FSL_BOOKE && FLATMEM && PPC32) 609 + depends on PPC_85xx && FLATMEM 611 610 depends on RELOCATABLE 612 611 help 613 612 Randomizes the virtual address at which the kernel image is ··· 626 625 627 626 config CRASH_DUMP 628 627 bool "Build a dump capture kernel" 629 - depends on PPC64 || PPC_BOOK3S_32 || FSL_BOOKE || (44x && !SMP) 630 - select RELOCATABLE if PPC64 || 44x || FSL_BOOKE 628 + depends on PPC64 || PPC_BOOK3S_32 || PPC_85xx || (44x && !SMP) 629 + select RELOCATABLE if PPC64 || 44x || PPC_85xx 631 630 help 632 631 Build a kernel suitable for use as a dump capture kernel. 633 632 The same kernel binary can be used as production kernel and dump ··· 816 815 depends on ADVANCED_OPTIONS 817 816 depends on STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE 818 817 depends on PPC_BOOK3S_32 || (PPC_8xx && !PIN_TLB_DATA && !STRICT_KERNEL_RWX) || \ 819 - FSL_BOOKE 818 + PPC_85xx 820 819 help 821 820 This option allows you to set the kernel data alignment. When 822 821 RAM is mapped by blocks, the alignment needs to fit the size and ··· 829 828 default 24 if STRICT_KERNEL_RWX && PPC64 830 829 range 17 28 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE) && PPC_BOOK3S_32 831 830 range 19 23 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE) && PPC_8xx 832 - range 20 24 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE) && PPC_FSL_BOOKE 831 + range 20 24 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC || KFENCE) && PPC_85xx 833 832 default 22 if STRICT_KERNEL_RWX && PPC_BOOK3S_32 834 833 default 18 if (DEBUG_PAGEALLOC || KFENCE) && PPC_BOOK3S_32 835 834 default 23 if STRICT_KERNEL_RWX && PPC_8xx 836 835 default 23 if (DEBUG_PAGEALLOC || KFENCE) && PPC_8xx && PIN_TLB_DATA 837 836 default 19 if (DEBUG_PAGEALLOC || KFENCE) && PPC_8xx 838 - default 24 if STRICT_KERNEL_RWX && FSL_BOOKE 837 + default 24 if STRICT_KERNEL_RWX && PPC_85xx 839 838 default PPC_PAGE_SHIFT 840 839 help 841 840 On Book3S 32 (603+), DBATs are used to map kernel text and rodata RO. ··· 1151 1150 1152 1151 config LOWMEM_CAM_NUM_BOOL 1153 1152 bool "Set number of CAMs to use to map low memory" 1154 - depends on ADVANCED_OPTIONS && FSL_BOOKE 1153 + depends on ADVANCED_OPTIONS && PPC_85xx 1155 1154 help 1156 1155 This option allows you to set the maximum number of CAM slots that 1157 1156 will be used to map low memory. There are a limited number of slots ··· 1162 1161 Say N here unless you know what you are doing. 1163 1162 1164 1163 config LOWMEM_CAM_NUM 1165 - depends on FSL_BOOKE 1164 + depends on PPC_85xx 1166 1165 int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL 1167 1166 default 3 if !STRICT_KERNEL_RWX 1168 1167 default 9 if DATA_SHIFT >= 24 ··· 1171 1170 1172 1171 config DYNAMIC_MEMSTART 1173 1172 bool "Enable page aligned dynamic load address for kernel" 1174 - depends on ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || 44x) 1173 + depends on ADVANCED_OPTIONS && FLATMEM && (PPC_85xx || 44x) 1175 1174 select NONSTATIC_KERNEL 1176 1175 help 1177 1176 This option enables the kernel to be loaded at any page aligned ··· 1220 1219 1221 1220 config PHYSICAL_START_BOOL 1222 1221 bool "Set physical address where the kernel is loaded" 1223 - depends on ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE 1222 + depends on ADVANCED_OPTIONS && FLATMEM && PPC_85xx 1224 1223 help 1225 1224 This gives the physical address where the kernel is loaded. 1226 1225 ··· 1233 1232 1234 1233 config PHYSICAL_ALIGN 1235 1234 hex 1236 - default "0x04000000" if FSL_BOOKE 1235 + default "0x04000000" if PPC_85xx 1237 1236 help 1238 1237 This value puts the alignment restrictions on physical address 1239 1238 where kernel is loaded and run from. Kernel is compiled for an

+15

arch/powerpc/Kconfig.debug

··· 283 283 This console provides input and output buffers stored within the 284 284 kernel BSS and should be safe to select on any system. A debugger 285 285 can then be used to read kernel output or send input to the console. 286 + 287 + config PPC_EARLY_DEBUG_16550 288 + bool "Serial 16550" 289 + depends on PPC_UDBG_16550 290 + help 291 + Select this to enable early debugging via Serial 16550 console 286 292 endchoice 287 293 288 294 config PPC_MEMCONS_OUTPUT_SIZE ··· 359 353 used for early debug output. Because it is needed before 360 354 platform probing is done, all platforms selected must 361 355 share the same address. 356 + 357 + config PPC_EARLY_DEBUG_16550_PHYSADDR 358 + hex "Early debug Serial 16550 physical address" 359 + depends on PPC_EARLY_DEBUG_16550 360 + 361 + config PPC_EARLY_DEBUG_16550_STRIDE 362 + int "Early debug Serial 16550 stride" 363 + depends on PPC_EARLY_DEBUG_16550 364 + default 1 362 365 363 366 config FAIL_IOMMU 364 367 bool "Fault-injection capability for IOMMU"

+12 -6

arch/powerpc/Makefile

··· 149 149 ifdef CONFIG_PPC_BOOK3S_64 150 150 ifdef CONFIG_CPU_LITTLE_ENDIAN 151 151 CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=power8 152 - CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power9,-mtune=power8) 153 152 else 154 - CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power7,$(call cc-option,-mtune=power5)) 155 - CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mcpu=power5,-mcpu=power4) 153 + CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=power4 156 154 endif 155 + CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power10, \ 156 + $(call cc-option,-mtune=power9, \ 157 + $(call cc-option,-mtune=power8))) 157 158 else ifdef CONFIG_PPC_BOOK3E_64 158 159 CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=powerpc64 159 160 endif ··· 192 191 -T $(srctree)/arch/powerpc/platforms/44x/ppc476_modules.lds 193 192 endif 194 193 195 - # No AltiVec or VSX instructions when building kernel 194 + # No prefix or pcrel 195 + KBUILD_CFLAGS += $(call cc-option,-mno-prefixed) 196 + KBUILD_CFLAGS += $(call cc-option,-mno-pcrel) 197 + 198 + # No AltiVec or VSX or MMA instructions when building kernel 196 199 KBUILD_CFLAGS += $(call cc-option,-mno-altivec) 197 200 KBUILD_CFLAGS += $(call cc-option,-mno-vsx) 201 + KBUILD_CFLAGS += $(call cc-option,-mno-mma) 198 202 199 203 # No SPE instruction when building kernel 200 204 # (We use all available options to help semi-broken compilers) ··· 216 210 cpu-as-$(CONFIG_40x) += -Wa,-m405 217 211 cpu-as-$(CONFIG_44x) += -Wa,-m440 218 212 cpu-as-$(CONFIG_ALTIVEC) += $(call as-option,-Wa$(comma)-maltivec) 219 - cpu-as-$(CONFIG_E500) += -Wa,-me500 213 + cpu-as-$(CONFIG_PPC_E500) += -Wa,-me500 220 214 221 215 # When using '-many -mpower4' gas will first try and find a matching power4 222 216 # mnemonic and failing that it will allow any valid mnemonic that GAS knows ··· 237 231 head-$(CONFIG_PPC_8xx) := arch/powerpc/kernel/head_8xx.o 238 232 head-$(CONFIG_40x) := arch/powerpc/kernel/head_40x.o 239 233 head-$(CONFIG_44x) := arch/powerpc/kernel/head_44x.o 240 - head-$(CONFIG_FSL_BOOKE) := arch/powerpc/kernel/head_fsl_booke.o 234 + head-$(CONFIG_PPC_85xx) := arch/powerpc/kernel/head_85xx.o 241 235 242 236 head-$(CONFIG_PPC64) += arch/powerpc/kernel/entry_64.o 243 237 head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o

+1 -4

arch/powerpc/boot/44x.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 2 3 * PowerPC 44x related functions 3 4 * 4 5 * Copyright 2007 David Gibson, IBM Corporation. 5 - * 6 - * This file is licensed under the terms of the GNU General Public 7 - * License version 2. This program is licensed "as is" without any 8 - * warranty of any kind, whether express or implied. 9 6 */ 10 7 #ifndef _PPC_BOOT_44X_H_ 11 8 #define _PPC_BOOT_44X_H_

+1 -4

arch/powerpc/boot/4xx.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 2 3 * PowerPC 4xx related functions 3 4 * 4 5 * Copyright 2007 IBM Corporation. 5 6 * Josh Boyer <jwboyer@linux.vnet.ibm.com> 6 - * 7 - * This file is licensed under the terms of the GNU General Public 8 - * License version 2. This program is licensed "as is" without any 9 - * warranty of any kind, whether express or implied. 10 7 */ 11 8 #ifndef _POWERPC_BOOT_4XX_H_ 12 9 #define _POWERPC_BOOT_4XX_H_

+1

arch/powerpc/boot/Makefile

··· 34 34 35 35 BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ 36 36 -fno-strict-aliasing -O2 -msoft-float -mno-altivec -mno-vsx \ 37 + $(call cc-option,-mno-spe) $(call cc-option,-mspe=no) \ 37 38 -pipe -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \ 38 39 $(LINUXINCLUDE) 39 40

+51

arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi

··· 1 + /* 2 + * e500v1 Power ISA Device Tree Source (include) 3 + * 4 + * Copyright 2012 Freescale Semiconductor Inc. 5 + * 6 + * Redistribution and use in source and binary forms, with or without 7 + * modification, are permitted provided that the following conditions are met: 8 + * * Redistributions of source code must retain the above copyright 9 + * notice, this list of conditions and the following disclaimer. 10 + * * Redistributions in binary form must reproduce the above copyright 11 + * notice, this list of conditions and the following disclaimer in the 12 + * documentation and/or other materials provided with the distribution. 13 + * * Neither the name of Freescale Semiconductor nor the 14 + * names of its contributors may be used to endorse or promote products 15 + * derived from this software without specific prior written permission. 16 + * 17 + * 18 + * ALTERNATIVELY, this software may be distributed under the terms of the 19 + * GNU General Public License ("GPL") as published by the Free Software 20 + * Foundation, either version 2 of that License or (at your option) any 21 + * later version. 22 + * 23 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 + */ 34 + 35 + / { 36 + cpus { 37 + power-isa-version = "2.03"; 38 + power-isa-b; // Base 39 + power-isa-e; // Embedded 40 + power-isa-atb; // Alternate Time Base 41 + power-isa-cs; // Cache Specification 42 + power-isa-e.le; // Embedded.Little-Endian 43 + power-isa-e.pm; // Embedded.Performance Monitor 44 + power-isa-ecl; // Embedded Cache Locking 45 + power-isa-mmc; // Memory Coherence 46 + power-isa-sp; // Signal Processing Engine 47 + power-isa-sp.fs; // SPE.Embedded Float Scalar Single 48 + power-isa-sp.fv; // SPE.Embedded Float Vector 49 + mmu-type = "power-embedded"; 50 + }; 51 + };

+1 -1

arch/powerpc/boot/dts/fsl/mpc8540ads.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 - /include/ "e500v2_power_isa.dtsi" 10 + /include/ "e500v1_power_isa.dtsi" 11 11 12 12 / { 13 13 model = "MPC8540ADS";

+1 -1

arch/powerpc/boot/dts/fsl/mpc8541cds.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 - /include/ "e500v2_power_isa.dtsi" 10 + /include/ "e500v1_power_isa.dtsi" 11 11 12 12 / { 13 13 model = "MPC8541CDS";

+1 -1

arch/powerpc/boot/dts/fsl/mpc8555cds.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 - /include/ "e500v2_power_isa.dtsi" 10 + /include/ "e500v1_power_isa.dtsi" 11 11 12 12 / { 13 13 model = "MPC8555CDS";

+1 -1

arch/powerpc/boot/dts/fsl/mpc8560ads.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 - /include/ "e500v2_power_isa.dtsi" 10 + /include/ "e500v1_power_isa.dtsi" 11 11 12 12 / { 13 13 model = "MPC8560ADS";

+2

arch/powerpc/boot/dts/ksi8560.dts

··· 14 14 15 15 /dts-v1/; 16 16 17 + /include/ "fsl/e500v1_power_isa.dtsi" 18 + 17 19 / { 18 20 model = "KSI8560"; 19 21 compatible = "emerson,KSI8560";

-7

arch/powerpc/boot/dts/mgcoge.dts

··· 225 225 interrupts = <2 8>; 226 226 interrupt-parent = <&PIC>; 227 227 cs-gpios = < &cpm2_pio_d 19 0>; 228 - #address-cells = <1>; 229 - #size-cells = <0>; 230 - ds3106@1 { 231 - compatible = "gen,spidev"; 232 - reg = <0>; 233 - spi-max-frequency = <8000000>; 234 - }; 235 228 }; 236 229 237 230 };

+2

arch/powerpc/boot/dts/stx_gp3_8560.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 + /include/ "fsl/e500v1_power_isa.dtsi" 11 + 10 12 / { 11 13 model = "stx,gp3"; 12 14 compatible = "stx,gp3-8560", "stx,gp3";

+2

arch/powerpc/boot/dts/stxssa8555.dts

··· 9 9 10 10 /dts-v1/; 11 11 12 + /include/ "fsl/e500v1_power_isa.dtsi" 13 + 12 14 / { 13 15 model = "stx,gp3"; 14 16 compatible = "stx,gp3-8560", "stx,gp3";

+2

arch/powerpc/boot/dts/tqm8540.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 + /include/ "fsl/e500v1_power_isa.dtsi" 11 + 10 12 / { 11 13 model = "tqc,tqm8540"; 12 14 compatible = "tqc,tqm8540";

+2

arch/powerpc/boot/dts/tqm8541.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 + /include/ "fsl/e500v1_power_isa.dtsi" 11 + 10 12 / { 11 13 model = "tqc,tqm8541"; 12 14 compatible = "tqc,tqm8541";

+2

arch/powerpc/boot/dts/tqm8555.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 + /include/ "fsl/e500v1_power_isa.dtsi" 11 + 10 12 / { 11 13 model = "tqc,tqm8555"; 12 14 compatible = "tqc,tqm8555";

+2

arch/powerpc/boot/dts/tqm8560.dts

··· 8 8 9 9 /dts-v1/; 10 10 11 + /include/ "fsl/e500v1_power_isa.dtsi" 12 + 11 13 / { 12 14 model = "tqc,tqm8560"; 13 15 compatible = "tqc,tqm8560";

+7 -7

arch/powerpc/boot/dts/turris1x.dts

··· 147 147 148 148 port@0 { 149 149 reg = <0>; 150 - label = "cpu1"; 150 + label = "cpu"; 151 151 ethernet = <&enet1>; 152 152 phy-mode = "rgmii-id"; 153 153 ··· 184 184 185 185 port@6 { 186 186 reg = <6>; 187 - label = "cpu0"; 187 + label = "cpu"; 188 188 ethernet = <&enet0>; 189 189 phy-mode = "rgmii-id"; 190 190 ··· 263 263 }; 264 264 265 265 partition@20000 { 266 - /* 1.7 MB for Rescue Linux Kernel Image */ 266 + /* 1.7 MB for Linux Kernel Image */ 267 267 reg = <0x00020000 0x001a0000>; 268 - label = "rescue-kernel"; 268 + label = "kernel"; 269 269 }; 270 270 271 271 partition@1c0000 { 272 272 /* 1.5 MB for Rescue JFFS2 Root File System */ 273 273 reg = <0x001c0000 0x00180000>; 274 - label = "rescue-rootfs"; 274 + label = "rescue"; 275 275 }; 276 276 277 277 partition@340000 { 278 - /* 11 MB for TAR.XZ Backup with content of NAND Root File System */ 278 + /* 11 MB for TAR.XZ Archive with Factory content of NAND Root File System */ 279 279 reg = <0x00340000 0x00b00000>; 280 - label = "backup-rootfs"; 280 + label = "factory"; 281 281 }; 282 282 283 283 partition@e40000 {

-4

arch/powerpc/boot/dummy.c

··· 1 - int main(void) 2 - { 3 - return 0; 4 - }

+3 -3

arch/powerpc/boot/opal-calls.S

··· 16 16 li r5, 0 17 17 li r6, 0 18 18 li r7, 0 19 - ld r11,opal@got(r2) 19 + LOAD_REG_ADDR(r11, opal) 20 20 ld r8,0(r11) 21 21 ld r9,8(r11) 22 22 bctr ··· 35 35 mr r13,r2 36 36 37 37 /* Set opal return address */ 38 - ld r11,opal_return@got(r2) 38 + LOAD_REG_ADDR(r11, opal_return) 39 39 mtlr r11 40 40 mfmsr r12 41 41 ··· 45 45 mtspr SPRN_HSRR1,r12 46 46 47 47 /* load the opal call entry point and base */ 48 - ld r11,opal@got(r2) 48 + LOAD_REG_ADDR(r11, opal) 49 49 ld r12,8(r11) 50 50 ld r2,0(r11) 51 51 mtspr SPRN_HSRR0,r12

+2 -4

arch/powerpc/boot/ops.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 2 3 * Global definition of all the bootwrapper operations. 3 4 * 4 5 * Author: Mark A. Greer <mgreer@mvista.com> 5 6 * 6 - * 2006 (c) MontaVista Software, Inc. This file is licensed under 7 - * the terms of the GNU General Public License version 2. This program 8 - * is licensed "as is" without any warranty of any kind, whether express 9 - * or implied. 7 + * 2006 (c) MontaVista Software, Inc. 10 8 */ 11 9 #ifndef _PPC_BOOT_OPS_H_ 12 10 #define _PPC_BOOT_OPS_H_

+10

arch/powerpc/boot/ppc_asm.h

··· 84 84 #define MFTBU(dest) mfspr dest, SPRN_TBRU 85 85 #endif 86 86 87 + #ifdef CONFIG_PPC64_BOOT_WRAPPER 88 + #define LOAD_REG_ADDR(reg,name) \ 89 + addis reg,r2,name@toc@ha; \ 90 + addi reg,reg,name@toc@l 91 + #else 92 + #define LOAD_REG_ADDR(reg,name) \ 93 + lis reg,name@ha; \ 94 + addi reg,reg,name@l 95 + #endif 96 + 87 97 #endif /* _PPC64_PPC_ASM_H */

+2 -4

arch/powerpc/boot/serial.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * Generic serial console support 3 4 * ··· 7 6 * Code in serial_edit_cmdline() copied from <file:arch/ppc/boot/simple/misc.c> 8 7 * and was written by Matt Porter <mporter@kernel.crashing.org>. 9 8 * 10 - * 2001,2006 (c) MontaVista Software, Inc. This file is licensed under 11 - * the terms of the GNU General Public License version 2. This program 12 - * is licensed "as is" without any warranty of any kind, whether express 13 - * or implied. 9 + * 2001,2006 (c) MontaVista Software, Inc. 14 10 */ 15 11 #include <stdarg.h> 16 12 #include <stddef.h>

+2 -4

arch/powerpc/boot/simple_alloc.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * Implement primitive realloc(3) functionality. 3 4 * 4 5 * Author: Mark A. Greer <mgreer@mvista.com> 5 6 * 6 - * 2006 (c) MontaVista, Software, Inc. This file is licensed under 7 - * the terms of the GNU General Public License version 2. This program 8 - * is licensed "as is" without any warranty of any kind, whether express 9 - * or implied. 7 + * 2006 (c) MontaVista, Software, Inc. 10 8 */ 11 9 12 10 #include <stddef.h>

-1

arch/powerpc/configs/83xx/mpc837x_rdb_defconfig

··· 77 77 CONFIG_NFS_V4=y 78 78 CONFIG_ROOT_NFS=y 79 79 CONFIG_CRC_T10DIF=y 80 - # CONFIG_ENABLE_MUST_CHECK is not set 81 80 CONFIG_CRYPTO_ECB=m 82 81 CONFIG_CRYPTO_PCBC=m

-1

arch/powerpc/configs/85xx/ge_imp3a_defconfig

··· 74 74 CONFIG_MTD_RAW_NAND=y 75 75 CONFIG_MTD_NAND_FSL_ELBC=y 76 76 CONFIG_BLK_DEV_LOOP=m 77 - CONFIG_BLK_DEV_CRYPTOLOOP=m 78 77 CONFIG_BLK_DEV_NBD=m 79 78 CONFIG_BLK_DEV_RAM=y 80 79 CONFIG_BLK_DEV_RAM_SIZE=131072

-2

arch/powerpc/configs/85xx/ppa8548_defconfig

··· 7 7 CONFIG_FSL_RIO=y 8 8 CONFIG_RAPIDIO_DMA_ENGINE=y 9 9 CONFIG_RAPIDIO_ENUM_BASIC=y 10 - CONFIG_RAPIDIO_TSI57X=y 11 10 CONFIG_RAPIDIO_CPS_XX=y 12 - CONFIG_RAPIDIO_TSI568=y 13 11 CONFIG_RAPIDIO_CPS_GEN2=y 14 12 CONFIG_ADVANCED_OPTIONS=y 15 13 CONFIG_LOWMEM_SIZE_BOOL=y

-1

arch/powerpc/configs/cell_defconfig

··· 195 195 CONFIG_NLS_ISO8859_13=m 196 196 CONFIG_NLS_ISO8859_14=m 197 197 CONFIG_NLS_ISO8859_15=m 198 - # CONFIG_ENABLE_MUST_CHECK is not set 199 198 CONFIG_MAGIC_SYSRQ=y 200 199 CONFIG_DEBUG_KERNEL=y 201 200 CONFIG_DEBUG_MUTEXES=y

-1

arch/powerpc/configs/g5_defconfig

··· 119 119 # CONFIG_SERIO_I8042 is not set 120 120 # CONFIG_SERIO_SERPORT is not set 121 121 # CONFIG_HW_RANDOM is not set 122 - CONFIG_RAW_DRIVER=y 123 122 CONFIG_I2C_CHARDEV=y 124 123 CONFIG_AGP=m 125 124 CONFIG_AGP_UNINORTH=m

+5

arch/powerpc/configs/microwatt_defconfig

··· 75 75 CONFIG_SPI_SPIDEV=y 76 76 # CONFIG_HWMON is not set 77 77 # CONFIG_USB_SUPPORT is not set 78 + CONFIG_MMC=y 79 + # CONFIG_PWRSEQ_EMMC is not set 80 + # CONFIG_PWRSEQ_SIMPLE is not set 81 + CONFIG_MMC_LITEX=y 78 82 # CONFIG_VIRTIO_MENU is not set 83 + CONFIG_COMMON_CLK=y 79 84 # CONFIG_IOMMU_SUPPORT is not set 80 85 # CONFIG_NVMEM is not set 81 86 CONFIG_EXT4_FS=y

-1

arch/powerpc/configs/mpc512x_defconfig

··· 114 114 CONFIG_ROOT_NFS=y 115 115 CONFIG_NLS_CODEPAGE_437=y 116 116 CONFIG_NLS_ISO8859_1=y 117 - # CONFIG_ENABLE_MUST_CHECK is not set 118 117 # CONFIG_CRYPTO_HW is not set

+1 -1

arch/powerpc/configs/mpc885_ads_defconfig

··· 78 78 CONFIG_DETECT_HUNG_TASK=y 79 79 CONFIG_BDI_SWITCH=y 80 80 CONFIG_PPC_EARLY_DEBUG=y 81 - CONFIG_PPC_PTDUMP=y 81 + CONFIG_GENERIC_PTDUMP=y

-1

arch/powerpc/configs/pasemi_defconfig

··· 92 92 CONFIG_SERIAL_8250=y 93 93 CONFIG_SERIAL_8250_CONSOLE=y 94 94 CONFIG_HW_RANDOM=y 95 - CONFIG_RAW_DRIVER=y 96 95 CONFIG_I2C_CHARDEV=y 97 96 CONFIG_I2C_PASEMI=y 98 97 CONFIG_SENSORS_LM85=y

-1

arch/powerpc/configs/pmac32_defconfig

··· 284 284 CONFIG_CRYPTO_PCBC=m 285 285 CONFIG_CRYPTO_MD4=m 286 286 CONFIG_CRYPTO_SHA512=m 287 - CONFIG_CRYPTO_TGR192=m 288 287 CONFIG_CRYPTO_WP512=m 289 288 CONFIG_CRYPTO_ANUBIS=m 290 289 CONFIG_CRYPTO_BLOWFISH=m

+3 -3

arch/powerpc/configs/powernv_defconfig

··· 50 50 CONFIG_HZ_100=y 51 51 CONFIG_BINFMT_MISC=m 52 52 CONFIG_PPC_TRANSACTIONAL_MEM=y 53 + CONFIG_PPC_UV=y 53 54 CONFIG_HOTPLUG_CPU=y 54 55 CONFIG_KEXEC=y 55 56 CONFIG_KEXEC_FILE=y ··· 66 65 CONFIG_SCHED_SMT=y 67 66 CONFIG_PM=y 68 67 CONFIG_HOTPLUG_PCI=y 68 + CONFIG_ZONE_DEVICE=y 69 + CONFIG_DEVICE_PRIVATE=y 69 70 CONFIG_NET=y 70 71 CONFIG_PACKET=y 71 72 CONFIG_UNIX=y ··· 255 252 CONFIG_RTC_DRV_GENERIC=y 256 253 # CONFIG_VIRTIO_MENU is not set 257 254 CONFIG_LIBNVDIMM=y 258 - # CONFIG_ND_BLK is not set 259 255 CONFIG_EXT2_FS=y 260 256 CONFIG_EXT2_FS_XATTR=y 261 257 CONFIG_EXT2_FS_POSIX_ACL=y ··· 327 325 CONFIG_CRYPTO_MICHAEL_MIC=m 328 326 CONFIG_CRYPTO_SHA1_PPC=m 329 327 CONFIG_CRYPTO_SHA256=y 330 - CONFIG_CRYPTO_TGR192=m 331 328 CONFIG_CRYPTO_WP512=m 332 329 CONFIG_CRYPTO_ANUBIS=m 333 330 CONFIG_CRYPTO_BLOWFISH=m 334 331 CONFIG_CRYPTO_CAST6=m 335 332 CONFIG_CRYPTO_KHAZAD=m 336 - CONFIG_CRYPTO_SALSA20=m 337 333 CONFIG_CRYPTO_SERPENT=m 338 334 CONFIG_CRYPTO_TEA=m 339 335 CONFIG_CRYPTO_TWOFISH=m

+2 -3

arch/powerpc/configs/ppc64_defconfig

··· 1 1 CONFIG_SYSVIPC=y 2 2 CONFIG_POSIX_MQUEUE=y 3 + # CONFIG_CONTEXT_TRACKING_USER_FORCE is not set 3 4 CONFIG_NO_HZ=y 4 5 CONFIG_HIGH_RES_TIMERS=y 6 + CONFIG_VIRT_CPU_ACCOUNTING_GEN=y 5 7 CONFIG_TASKSTATS=y 6 8 CONFIG_TASK_DELAY_ACCT=y 7 9 CONFIG_IKCONFIG=y ··· 215 213 CONFIG_HVCS=m 216 214 CONFIG_VIRTIO_CONSOLE=m 217 215 CONFIG_IBM_BSR=m 218 - CONFIG_RAW_DRIVER=y 219 216 CONFIG_I2C_CHARDEV=y 220 217 CONFIG_I2C_AMD8111=y 221 218 CONFIG_I2C_PASEMI=y ··· 343 342 CONFIG_CRYPTO_MICHAEL_MIC=m 344 343 CONFIG_CRYPTO_SHA1_PPC=m 345 344 CONFIG_CRYPTO_SHA256=y 346 - CONFIG_CRYPTO_TGR192=m 347 345 CONFIG_CRYPTO_WP512=m 348 346 CONFIG_CRYPTO_ANUBIS=m 349 347 CONFIG_CRYPTO_BLOWFISH=m 350 348 CONFIG_CRYPTO_CAST6=m 351 349 CONFIG_CRYPTO_KHAZAD=m 352 - CONFIG_CRYPTO_SALSA20=m 353 350 CONFIG_CRYPTO_SERPENT=m 354 351 CONFIG_CRYPTO_TEA=m 355 352 CONFIG_CRYPTO_TWOFISH=m

-3

arch/powerpc/configs/ppc64e_defconfig

··· 118 118 CONFIG_SERIAL_8250=y 119 119 CONFIG_SERIAL_8250_CONSOLE=y 120 120 # CONFIG_HW_RANDOM is not set 121 - CONFIG_RAW_DRIVER=y 122 121 CONFIG_I2C_CHARDEV=y 123 122 CONFIG_I2C_AMD8111=y 124 123 CONFIG_FB=y ··· 233 234 CONFIG_CRYPTO_HMAC=y 234 235 CONFIG_CRYPTO_MICHAEL_MIC=m 235 236 CONFIG_CRYPTO_SHA512=m 236 - CONFIG_CRYPTO_TGR192=m 237 237 CONFIG_CRYPTO_WP512=m 238 238 CONFIG_CRYPTO_ANUBIS=m 239 239 CONFIG_CRYPTO_BLOWFISH=m 240 240 CONFIG_CRYPTO_CAST6=m 241 241 CONFIG_CRYPTO_KHAZAD=m 242 - CONFIG_CRYPTO_SALSA20=m 243 242 CONFIG_CRYPTO_SERPENT=m 244 243 CONFIG_CRYPTO_TEA=m 245 244 CONFIG_CRYPTO_TWOFISH=m

-7

arch/powerpc/configs/ppc6xx_defconfig

··· 321 321 CONFIG_ISAPNP=y 322 322 CONFIG_MAC_FLOPPY=m 323 323 CONFIG_BLK_DEV_LOOP=m 324 - CONFIG_BLK_DEV_CRYPTOLOOP=m 325 324 CONFIG_BLK_DEV_NBD=m 326 325 CONFIG_BLK_DEV_RAM=y 327 326 CONFIG_BLK_DEV_RAM_SIZE=16384 ··· 589 590 CONFIG_GAMEPORT_FM801=m 590 591 # CONFIG_LEGACY_PTYS is not set 591 592 CONFIG_SERIAL_NONSTANDARD=y 592 - CONFIG_ROCKETPORT=m 593 593 CONFIG_SYNCLINK_GT=m 594 594 CONFIG_NOZOMI=m 595 595 CONFIG_N_HDLC=m ··· 1105 1107 CONFIG_CRYPTO_HMAC=y 1106 1108 CONFIG_CRYPTO_XCBC=m 1107 1109 CONFIG_CRYPTO_MICHAEL_MIC=m 1108 - CONFIG_CRYPTO_RMD128=m 1109 1110 CONFIG_CRYPTO_RMD160=m 1110 - CONFIG_CRYPTO_RMD256=m 1111 - CONFIG_CRYPTO_RMD320=m 1112 1111 CONFIG_CRYPTO_SHA1=y 1113 1112 CONFIG_CRYPTO_SHA512=m 1114 - CONFIG_CRYPTO_TGR192=m 1115 1113 CONFIG_CRYPTO_WP512=m 1116 1114 CONFIG_CRYPTO_ANUBIS=m 1117 1115 CONFIG_CRYPTO_BLOWFISH=m ··· 1115 1121 CONFIG_CRYPTO_CAST6=m 1116 1122 CONFIG_CRYPTO_FCRYPT=m 1117 1123 CONFIG_CRYPTO_KHAZAD=m 1118 - CONFIG_CRYPTO_SALSA20=m 1119 1124 CONFIG_CRYPTO_SEED=m 1120 1125 CONFIG_CRYPTO_SERPENT=m 1121 1126 CONFIG_CRYPTO_TEA=m

-1

arch/powerpc/configs/ps3_defconfig

··· 165 165 # CONFIG_FTRACE is not set 166 166 CONFIG_CRYPTO_PCBC=m 167 167 CONFIG_CRYPTO_MICHAEL_MIC=m 168 - CONFIG_CRYPTO_SALSA20=m 169 168 CONFIG_CRYPTO_LZO=m 170 169 CONFIG_PRINTK_TIME=y

+3 -3

arch/powerpc/configs/pseries_defconfig

··· 3 3 CONFIG_SYSVIPC=y 4 4 CONFIG_POSIX_MQUEUE=y 5 5 CONFIG_AUDIT=y 6 + # CONFIG_CONTEXT_TRACKING_USER_FORCE is not set 6 7 CONFIG_NO_HZ=y 7 8 CONFIG_HIGH_RES_TIMERS=y 9 + CONFIG_VIRT_CPU_ACCOUNTING_GEN=y 8 10 CONFIG_TASKSTATS=y 9 11 CONFIG_TASK_DELAY_ACCT=y 10 12 CONFIG_TASK_XACCT=y ··· 42 40 CONFIG_DTL=y 43 41 CONFIG_PPC_SMLPAR=y 44 42 CONFIG_IBMEBUS=y 43 + CONFIG_LIBNVDIMM=m 45 44 CONFIG_PAPR_SCM=m 46 45 CONFIG_PPC_SVM=y 47 46 # CONFIG_PPC_PMAC is not set ··· 190 187 CONFIG_HVCS=m 191 188 CONFIG_VIRTIO_CONSOLE=m 192 189 CONFIG_IBM_BSR=m 193 - CONFIG_RAW_DRIVER=y 194 190 CONFIG_I2C_CHARDEV=y 195 191 CONFIG_FB=y 196 192 CONFIG_FIRMWARE_EDID=y ··· 304 302 CONFIG_CRYPTO_MICHAEL_MIC=m 305 303 CONFIG_CRYPTO_SHA1_PPC=m 306 304 CONFIG_CRYPTO_SHA256=y 307 - CONFIG_CRYPTO_TGR192=m 308 305 CONFIG_CRYPTO_WP512=m 309 306 CONFIG_CRYPTO_ANUBIS=m 310 307 CONFIG_CRYPTO_BLOWFISH=m 311 308 CONFIG_CRYPTO_CAST6=m 312 309 CONFIG_CRYPTO_KHAZAD=m 313 - CONFIG_CRYPTO_SALSA20=m 314 310 CONFIG_CRYPTO_SERPENT=m 315 311 CONFIG_CRYPTO_TEA=m 316 312 CONFIG_CRYPTO_TWOFISH=m

-2

arch/powerpc/configs/skiroot_defconfig

··· 133 133 # CONFIG_NET_VENDOR_AQUANTIA is not set 134 134 # CONFIG_NET_VENDOR_ARC is not set 135 135 # CONFIG_NET_VENDOR_ATHEROS is not set 136 - # CONFIG_NET_VENDOR_AURORA is not set 137 136 CONFIG_TIGON3=m 138 137 CONFIG_BNX2X=m 139 138 # CONFIG_NET_VENDOR_BROCADE is not set ··· 273 274 CONFIG_ENCRYPTED_KEYS=y 274 275 CONFIG_SECURITY=y 275 276 CONFIG_HARDENED_USERCOPY=y 276 - CONFIG_HARDENED_USERCOPY_PAGESPAN=y 277 277 CONFIG_FORTIFY_SOURCE=y 278 278 CONFIG_SECURITY_LOCKDOWN_LSM=y 279 279 CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y

-1

arch/powerpc/configs/storcenter_defconfig

··· 76 76 CONFIG_NLS_ISO8859_1=y 77 77 CONFIG_NLS_UTF8=y 78 78 CONFIG_CRC_T10DIF=y 79 - # CONFIG_ENABLE_MUST_CHECK is not set

+1 -13

arch/powerpc/include/asm/asm-prototypes.h

··· 36 36 int64_t opcode, uint64_t msr); 37 37 38 38 /* misc runtime */ 39 + void enable_machine_check(void); 39 40 extern u64 __bswapdi2(u64); 40 41 extern s64 __lshrdi3(s64, int); 41 42 extern s64 __ashldi3(s64, int); ··· 55 54 struct kvm_vcpu; 56 55 void _kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr); 57 56 void _kvmppc_save_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr); 58 - 59 - /* Patch sites */ 60 - extern s32 patch__call_flush_branch_caches1; 61 - extern s32 patch__call_flush_branch_caches2; 62 - extern s32 patch__call_flush_branch_caches3; 63 - extern s32 patch__flush_count_cache_return; 64 - extern s32 patch__flush_link_stack_return; 65 - extern s32 patch__call_kvm_flush_link_stack; 66 - extern s32 patch__call_kvm_flush_link_stack_p9; 67 - extern s32 patch__memset_nocache, patch__memcpy_nocache; 68 - 69 - extern long flush_branch_caches; 70 - extern long kvm_flush_link_stack; 71 57 72 58 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 73 59 void kvmppc_save_tm_hv(struct kvm_vcpu *vcpu, u64 msr, bool preserve_nv);

+1 -1

arch/powerpc/include/asm/barrier.h

··· 86 86 87 87 #ifdef CONFIG_PPC_BOOK3S_64 88 88 #define NOSPEC_BARRIER_SLOT nop 89 - #elif defined(CONFIG_PPC_FSL_BOOK3E) 89 + #elif defined(CONFIG_PPC_E500) 90 90 #define NOSPEC_BARRIER_SLOT nop; nop 91 91 #endif 92 92

+1 -21

arch/powerpc/include/asm/book3s/32/pgtable.h

··· 112 112 /* Permission masks used for kernel mappings */ 113 113 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 114 114 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE) 115 - #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 116 - _PAGE_NO_CACHE | _PAGE_GUARDED) 115 + #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE | _PAGE_GUARDED) 117 116 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 118 117 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 119 118 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 120 - 121 - /* 122 - * Protection used for kernel text. We want the debuggers to be able to 123 - * set breakpoints anywhere, so don't write protect the kernel text 124 - * on platforms where such control is possible. 125 - */ 126 - #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ 127 - defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 128 - #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 129 - #else 130 - #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 131 - #endif 132 - 133 - /* Make modules code happy. We don't set RO yet */ 134 - #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 135 - 136 - /* Advertise special mapping type for AGP */ 137 - #define PAGE_AGP (PAGE_KERNEL_NC) 138 - #define HAVE_PAGE_AGP 139 119 140 120 #define PTE_INDEX_SIZE PTE_SHIFT 141 121 #define PMD_INDEX_SIZE 0

+4 -2

arch/powerpc/include/asm/book3s/64/pgalloc.h

··· 113 113 114 114 /* 115 115 * Early pud pages allocated via memblock allocator 116 - * can't be directly freed to slab 116 + * can't be directly freed to slab. KFENCE pages have 117 + * both reserved and slab flags set so need to be freed 118 + * kmem_cache_free. 117 119 */ 118 - if (PageReserved(page)) 120 + if (PageReserved(page) && !PageSlab(page)) 119 121 free_reserved_page(page); 120 122 else 121 123 kmem_cache_free(PGT_CACHE(PUD_CACHE_INDEX), pud);

-10

arch/powerpc/include/asm/book3s/64/pgtable-4k.h

··· 26 26 return 0; 27 27 } 28 28 29 - static inline int pgd_huge(pgd_t pgd) 30 - { 31 - /* 32 - * leaf pte for huge page 33 - */ 34 - if (radix_enabled()) 35 - return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PTE)); 36 - return 0; 37 - } 38 - #define pgd_huge pgd_huge 39 29 /* 40 30 * With radix , we have hugepage ptes in the pud and pmd entries. We don't 41 31 * need to setup hugepage directory for them. Our pte and page directory format

-9

arch/powerpc/include/asm/book3s/64/pgtable-64k.h

··· 30 30 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 31 31 } 32 32 33 - static inline int pgd_huge(pgd_t pgd) 34 - { 35 - /* 36 - * leaf pte for huge page 37 - */ 38 - return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PTE)); 39 - } 40 - #define pgd_huge pgd_huge 41 - 42 33 /* 43 34 * With 64k page size, we have hugepage ptes in the pgd and pmd entries. We don't 44 35 * need to setup hugepage directory for them. Our pte and page directory format

+9 -33

arch/powerpc/include/asm/book3s/64/pgtable.h

··· 117 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 119 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 120 - #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 121 - _PAGE_RW | _PAGE_EXEC) 120 + #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 122 121 /* 123 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 124 123 * pgprot changes ··· 150 151 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 151 152 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 152 153 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 + /* Radix only, Hash uses PAGE_READONLY_X + execute-only pkey instead */ 155 + #define PAGE_EXECONLY __pgprot(_PAGE_BASE | _PAGE_EXEC) 153 156 154 157 /* Permission masks used for kernel mappings */ 155 158 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 156 - #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 157 - _PAGE_TOLERANT) 158 - #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 - _PAGE_NON_IDEMPOTENT) 159 + #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) 160 + #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) 160 161 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 161 162 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 162 163 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 163 - 164 - /* 165 - * Protection used for kernel text. We want the debuggers to be able to 166 - * set breakpoints anywhere, so don't write protect the kernel text 167 - * on platforms where such control is possible. 168 - */ 169 - #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 170 - defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 171 - #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 172 - #else 173 - #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 174 - #endif 175 - 176 - /* Make modules code happy. We don't set RO yet */ 177 - #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 178 - #define PAGE_AGP (PAGE_KERNEL_NC) 179 164 180 165 #ifndef __ASSEMBLY__ 181 166 /* ··· 316 333 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 317 334 #define FIXADDR_SIZE SZ_32M 318 335 319 - /* Advertise special mapping type for AGP */ 320 - #define HAVE_PAGE_AGP 321 - 322 336 #ifndef __ASSEMBLY__ 323 337 324 338 /* ··· 391 411 * event of it not getting flushed for a long time the delay 392 412 * shouldn't really matter because there's no real memory 393 413 * pressure for swapout to react to. ] 414 + * 415 + * Note: this optimisation also exists in pte_needs_flush() and 416 + * huge_pmd_needs_flush(). 394 417 */ 395 418 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 396 419 #define ptep_clear_flush_young ptep_test_and_clear_young ··· 1106 1123 } 1107 1124 #endif 1108 1125 1109 - #ifdef CONFIG_DEBUG_PAGEALLOC 1126 + #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE) 1110 1127 static inline void __kernel_map_pages(struct page *page, int numpages, int enable) 1111 1128 { 1112 1129 if (radix_enabled()) ··· 1438 1455 static inline bool pud_is_leaf(pud_t pud) 1439 1456 { 1440 1457 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1441 - } 1442 - 1443 - #define p4d_is_leaf p4d_is_leaf 1444 - #define p4d_leaf p4d_is_leaf 1445 - static inline bool p4d_is_leaf(p4d_t p4d) 1446 - { 1447 - return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1448 1458 } 1449 1459 1450 1460 #endif /* __ASSEMBLY__ */

+1 -3

arch/powerpc/include/asm/book3s/64/tlbflush-hash.h

··· 112 112 113 113 struct mmu_gather; 114 114 extern void hash__tlb_flush(struct mmu_gather *tlb); 115 - void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr); 116 115 117 116 #ifdef CONFIG_PPC_64S_HASH_MMU 118 117 /* Private function for use by PCI IO mapping code */ 119 118 extern void __flush_hash_table_range(unsigned long start, unsigned long end); 120 - extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd, 121 - unsigned long addr); 119 + void flush_hash_table_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr); 122 120 #else 123 121 static inline void __flush_hash_table_range(unsigned long start, unsigned long end) { } 124 122 #endif

+56

arch/powerpc/include/asm/book3s/64/tlbflush.h

··· 163 163 */ 164 164 } 165 165 166 + static inline bool __pte_flags_need_flush(unsigned long oldval, 167 + unsigned long newval) 168 + { 169 + unsigned long delta = oldval ^ newval; 170 + 171 + /* 172 + * The return value of this function doesn't matter for hash, 173 + * ptep_modify_prot_start() does a pte_update() which does or schedules 174 + * any necessary hash table update and flush. 175 + */ 176 + if (!radix_enabled()) 177 + return true; 178 + 179 + /* 180 + * We do not expect kernel mappings or non-PTEs or not-present PTEs. 181 + */ 182 + VM_WARN_ON_ONCE(oldval & _PAGE_PRIVILEGED); 183 + VM_WARN_ON_ONCE(newval & _PAGE_PRIVILEGED); 184 + VM_WARN_ON_ONCE(!(oldval & _PAGE_PTE)); 185 + VM_WARN_ON_ONCE(!(newval & _PAGE_PTE)); 186 + VM_WARN_ON_ONCE(!(oldval & _PAGE_PRESENT)); 187 + VM_WARN_ON_ONCE(!(newval & _PAGE_PRESENT)); 188 + 189 + /* 190 + * Must flush on any change except READ, WRITE, EXEC, DIRTY, ACCESSED. 191 + * 192 + * In theory, some changed software bits could be tolerated, in 193 + * practice those should rarely if ever matter. 194 + */ 195 + 196 + if (delta & ~(_PAGE_RWX | _PAGE_DIRTY | _PAGE_ACCESSED)) 197 + return true; 198 + 199 + /* 200 + * If any of the above was present in old but cleared in new, flush. 201 + * With the exception of _PAGE_ACCESSED, don't worry about flushing 202 + * if that was cleared (see the comment in ptep_clear_flush_young()). 203 + */ 204 + if ((delta & ~_PAGE_ACCESSED) & oldval) 205 + return true; 206 + 207 + return false; 208 + } 209 + 210 + static inline bool pte_needs_flush(pte_t oldpte, pte_t newpte) 211 + { 212 + return __pte_flags_need_flush(pte_val(oldpte), pte_val(newpte)); 213 + } 214 + #define pte_needs_flush pte_needs_flush 215 + 216 + static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd) 217 + { 218 + return __pte_flags_need_flush(pmd_val(oldpmd), pmd_val(newpmd)); 219 + } 220 + #define huge_pmd_needs_flush huge_pmd_needs_flush 221 + 166 222 extern bool tlbie_capable; 167 223 extern bool tlbie_enabled; 168 224

+10 -5

arch/powerpc/include/asm/book3s/pgtable.h

··· 25 25 unsigned long size, pgprot_t vma_prot); 26 26 #define __HAVE_PHYS_MEM_ACCESS_PROT 27 27 28 - #if defined(CONFIG_PPC32) || defined(CONFIG_PPC_64S_HASH_MMU) 28 + void __update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep); 29 + 29 30 /* 30 31 * This gets called at the end of handling a page fault, when 31 32 * the kernel has put a new PTE into the page table for the process. ··· 36 35 * corresponding HPTE into the hash table ahead of time, instead of 37 36 * waiting for the inevitable extra hash-table miss exception. 38 37 */ 39 - void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep); 40 - #else 41 - static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) {} 42 - #endif 38 + static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) 39 + { 40 + if (IS_ENABLED(CONFIG_PPC32) && !mmu_has_feature(MMU_FTR_HPTE_TABLE)) 41 + return; 42 + if (radix_enabled()) 43 + return; 44 + __update_mmu_cache(vma, address, ptep); 45 + } 43 46 44 47 #endif /* __ASSEMBLY__ */ 45 48 #endif

+49

arch/powerpc/include/asm/cpu_setup.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2020 IBM Corporation 4 + */ 5 + 6 + #ifndef _ASM_POWERPC_CPU_SETUP_H 7 + #define _ASM_POWERPC_CPU_SETUP_H 8 + void __setup_cpu_power7(unsigned long offset, struct cpu_spec *spec); 9 + void __setup_cpu_power8(unsigned long offset, struct cpu_spec *spec); 10 + void __setup_cpu_power9(unsigned long offset, struct cpu_spec *spec); 11 + void __setup_cpu_power10(unsigned long offset, struct cpu_spec *spec); 12 + void __restore_cpu_power7(void); 13 + void __restore_cpu_power8(void); 14 + void __restore_cpu_power9(void); 15 + void __restore_cpu_power10(void); 16 + 17 + void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec *spec); 18 + void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec *spec); 19 + void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec *spec); 20 + void __setup_cpu_440ep(unsigned long offset, struct cpu_spec *spec); 21 + void __setup_cpu_440epx(unsigned long offset, struct cpu_spec *spec); 22 + void __setup_cpu_440gx(unsigned long offset, struct cpu_spec *spec); 23 + void __setup_cpu_440grx(unsigned long offset, struct cpu_spec *spec); 24 + void __setup_cpu_440spe(unsigned long offset, struct cpu_spec *spec); 25 + void __setup_cpu_440x5(unsigned long offset, struct cpu_spec *spec); 26 + void __setup_cpu_460ex(unsigned long offset, struct cpu_spec *spec); 27 + void __setup_cpu_460gt(unsigned long offset, struct cpu_spec *spec); 28 + void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec); 29 + void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec); 30 + void __setup_cpu_603(unsigned long offset, struct cpu_spec *spec); 31 + void __setup_cpu_604(unsigned long offset, struct cpu_spec *spec); 32 + void __setup_cpu_750(unsigned long offset, struct cpu_spec *spec); 33 + void __setup_cpu_750cx(unsigned long offset, struct cpu_spec *spec); 34 + void __setup_cpu_750fx(unsigned long offset, struct cpu_spec *spec); 35 + void __setup_cpu_7400(unsigned long offset, struct cpu_spec *spec); 36 + void __setup_cpu_7410(unsigned long offset, struct cpu_spec *spec); 37 + void __setup_cpu_745x(unsigned long offset, struct cpu_spec *spec); 38 + 39 + void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec *spec); 40 + void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec *spec); 41 + void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec *spec); 42 + void __restore_cpu_pa6t(void); 43 + void __restore_cpu_ppc970(void); 44 + 45 + void __setup_cpu_e5500(unsigned long offset, struct cpu_spec *spec); 46 + void __setup_cpu_e6500(unsigned long offset, struct cpu_spec *spec); 47 + void __restore_cpu_e5500(void); 48 + void __restore_cpu_e6500(void); 49 + #endif /* _ASM_POWERPC_CPU_SETUP_H */

-12

arch/powerpc/include/asm/cpu_setup_power.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * Copyright (C) 2020 IBM Corporation 4 - */ 5 - void __setup_cpu_power7(unsigned long offset, struct cpu_spec *spec); 6 - void __restore_cpu_power7(void); 7 - void __setup_cpu_power8(unsigned long offset, struct cpu_spec *spec); 8 - void __restore_cpu_power8(void); 9 - void __setup_cpu_power9(unsigned long offset, struct cpu_spec *spec); 10 - void __restore_cpu_power9(void); 11 - void __setup_cpu_power10(unsigned long offset, struct cpu_spec *spec); 12 - void __restore_cpu_power10(void);

+4 -4

arch/powerpc/include/asm/cputable.h

··· 463 463 #define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2) 464 464 465 465 #ifdef CONFIG_PPC64 466 - #ifdef CONFIG_PPC_BOOK3E 466 + #ifdef CONFIG_PPC_BOOK3E_64 467 467 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) 468 468 #else 469 469 #ifdef CONFIG_CPU_LITTLE_ENDIAN ··· 510 510 #elif defined(CONFIG_44x) 511 511 CPU_FTRS_44X | CPU_FTRS_440x6 | 512 512 #endif 513 - #ifdef CONFIG_E500 513 + #ifdef CONFIG_PPC_E500 514 514 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 515 515 #endif 516 516 #ifdef CONFIG_PPC_E500MC ··· 521 521 #endif /* __powerpc64__ */ 522 522 523 523 #ifdef CONFIG_PPC64 524 - #ifdef CONFIG_PPC_BOOK3E 524 + #ifdef CONFIG_PPC_BOOK3E_64 525 525 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) 526 526 #else 527 527 ··· 584 584 #elif defined(CONFIG_44x) 585 585 CPU_FTRS_44X & CPU_FTRS_440x6 & 586 586 #endif 587 - #ifdef CONFIG_E500 587 + #ifdef CONFIG_PPC_E500 588 588 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 589 589 #endif 590 590 #ifdef CONFIG_PPC_E500MC

+1 -1

arch/powerpc/include/asm/cputime.h

··· 95 95 struct lppaca *lp = local_paca->lppaca_ptr; 96 96 97 97 if (unlikely(local_paca->dtl_ridx != be64_to_cpu(lp->dtl_idx))) 98 - accumulate_stolen_time(); 98 + pseries_accumulate_stolen_time(); 99 99 } 100 100 #endif 101 101 }

-8

arch/powerpc/include/asm/dtl.h

··· 37 37 extern struct kmem_cache *dtl_cache; 38 38 extern rwlock_t dtl_access_lock; 39 39 40 - /* 41 - * When CONFIG_VIRT_CPU_ACCOUNTING_NATIVE = y, the cpu accounting code controls 42 - * reading from the dispatch trace log. If other code wants to consume 43 - * DTL entries, it can set this pointer to a function that will get 44 - * called once for each DTL entry that gets processed. 45 - */ 46 - extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index); 47 - 48 40 extern void register_dtl_buffer(int cpu); 49 41 extern void alloc_dtl_buffers(unsigned long *time_limit); 50 42 extern long hcall_vphn(unsigned long cpu, u64 flags, __be32 *associativity);

+2 -2

arch/powerpc/include/asm/hugetlb.h

··· 7 7 8 8 #ifdef CONFIG_PPC_BOOK3S_64 9 9 #include <asm/book3s/64/hugetlb.h> 10 - #elif defined(CONFIG_PPC_FSL_BOOK3E) 11 - #include <asm/nohash/hugetlb-book3e.h> 10 + #elif defined(CONFIG_PPC_E500) 11 + #include <asm/nohash/hugetlb-e500.h> 12 12 #elif defined(CONFIG_PPC_8xx) 13 13 #include <asm/nohash/32/hugetlb-8xx.h> 14 14 #endif /* CONFIG_PPC_BOOK3S_64 */

+28 -22

arch/powerpc/include/asm/hw_irq.h

··· 157 157 158 158 static inline notrace unsigned long irq_soft_mask_set_return(unsigned long mask) 159 159 { 160 - unsigned long flags; 160 + unsigned long flags = irq_soft_mask_return(); 161 161 162 - #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG 163 - WARN_ON(mask && !(mask & IRQS_DISABLED)); 164 - #endif 165 - 166 - asm volatile( 167 - "lbz %0,%1(13); stb %2,%1(13)" 168 - : "=&r" (flags) 169 - : "i" (offsetof(struct paca_struct, irq_soft_mask)), 170 - "r" (mask) 171 - : "memory"); 162 + irq_soft_mask_set(mask); 172 163 173 164 return flags; 174 165 } 175 166 176 167 static inline notrace unsigned long irq_soft_mask_or_return(unsigned long mask) 177 168 { 178 - unsigned long flags, tmp; 169 + unsigned long flags = irq_soft_mask_return(); 179 170 180 - asm volatile( 181 - "lbz %0,%2(13); or %1,%0,%3; stb %1,%2(13)" 182 - : "=&r" (flags), "=r" (tmp) 183 - : "i" (offsetof(struct paca_struct, irq_soft_mask)), 184 - "r" (mask) 185 - : "memory"); 186 - 187 - #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG 188 - WARN_ON((mask | flags) && !((mask | flags) & IRQS_DISABLED)); 189 - #endif 171 + irq_soft_mask_set(flags | mask); 190 172 191 173 return flags; 192 174 } ··· 470 488 { 471 489 } 472 490 #endif /* CONFIG_PPC64 */ 491 + 492 + static inline unsigned long mtmsr_isync_irqsafe(unsigned long msr) 493 + { 494 + #ifdef CONFIG_PPC64 495 + if (arch_irqs_disabled()) { 496 + /* 497 + * With soft-masking, MSR[EE] can change from 1 to 0 498 + * asynchronously when irqs are disabled, and we don't want to 499 + * set MSR[EE] back to 1 here if that has happened. A race-free 500 + * way to do this is ensure EE is already 0. Another way it 501 + * could be done is with a RESTART_TABLE handler, but that's 502 + * probably overkill here. 503 + */ 504 + msr &= ~MSR_EE; 505 + mtmsr_isync(msr); 506 + irq_soft_mask_set(IRQS_ALL_DISABLED); 507 + local_paca->irq_happened |= PACA_IRQ_HARD_DIS; 508 + } else 509 + #endif 510 + mtmsr_isync(msr); 511 + 512 + return msr; 513 + } 514 + 473 515 474 516 #define ARCH_IRQ_INIT_FLAGS IRQ_NOREQUEST 475 517

+24 -17

arch/powerpc/include/asm/interrupt.h

··· 74 74 #include <asm/kprobes.h> 75 75 #include <asm/runlatch.h> 76 76 77 + #ifdef CONFIG_PPC64 78 + /* 79 + * WARN/BUG is handled with a program interrupt so minimise checks here to 80 + * avoid recursion and maximise the chance of getting the first oops handled. 81 + */ 82 + #define INT_SOFT_MASK_BUG_ON(regs, cond) \ 83 + do { \ 84 + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && \ 85 + (user_mode(regs) || (TRAP(regs) != INTERRUPT_PROGRAM))) \ 86 + BUG_ON(cond); \ 87 + } while (0) 88 + #endif 89 + 77 90 #ifdef CONFIG_PPC_BOOK3S_64 78 91 extern char __end_soft_masked[]; 79 92 bool search_kernel_soft_mask_table(unsigned long addr); ··· 183 170 * context. 184 171 */ 185 172 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) { 186 - if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) 187 - BUG_ON(!(regs->msr & MSR_EE)); 173 + INT_SOFT_MASK_BUG_ON(regs, !(regs->msr & MSR_EE)); 188 174 __hard_irq_enable(); 189 175 } else { 190 176 __hard_RI_enable(); ··· 206 194 * CT_WARN_ON comes here via program_check_exception, 207 195 * so avoid recursion. 208 196 */ 209 - if (TRAP(regs) != INTERRUPT_PROGRAM) { 210 - CT_WARN_ON(ct_state() != CONTEXT_KERNEL); 211 - if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) 212 - BUG_ON(is_implicit_soft_masked(regs)); 213 - } 214 - 215 - /* Move this under a debugging check */ 216 - if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && 217 - arch_irq_disabled_regs(regs)) 218 - BUG_ON(search_kernel_restart_table(regs->nip)); 197 + if (TRAP(regs) != INTERRUPT_PROGRAM) 198 + CT_WARN_ON(ct_state() != CONTEXT_KERNEL && 199 + ct_state() != CONTEXT_IDLE); 200 + INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs)); 201 + INT_SOFT_MASK_BUG_ON(regs, arch_irq_disabled_regs(regs) && 202 + search_kernel_restart_table(regs->nip)); 219 203 } 220 - if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) 221 - BUG_ON(!arch_irq_disabled_regs(regs) && !(regs->msr & MSR_EE)); 204 + INT_SOFT_MASK_BUG_ON(regs, !arch_irq_disabled_regs(regs) && 205 + !(regs->msr & MSR_EE)); 222 206 #endif 223 207 224 208 booke_restore_dbcr0(); ··· 289 281 if (TRAP(regs) == INTERRUPT_PERFMON) 290 282 return false; 291 283 } 292 - if (IS_ENABLED(CONFIG_PPC_BOOK3E)) { 284 + if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) { 293 285 if (TRAP(regs) == INTERRUPT_PERFMON) 294 286 return false; 295 287 } ··· 673 665 local_irq_enable(); 674 666 } 675 667 676 - long system_call_exception(long r3, long r4, long r5, long r6, long r7, long r8, 677 - unsigned long r0, struct pt_regs *regs); 668 + long system_call_exception(struct pt_regs *regs, unsigned long r0); 678 669 notrace unsigned long syscall_exit_prepare(unsigned long r3, struct pt_regs *regs, long scv); 679 670 notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs); 680 671 notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs);

+1 -1

arch/powerpc/include/asm/kexec.h

··· 3 3 #define _ASM_POWERPC_KEXEC_H 4 4 #ifdef __KERNEL__ 5 5 6 - #if defined(CONFIG_FSL_BOOKE) || defined(CONFIG_44x) 6 + #if defined(CONFIG_PPC_85xx) || defined(CONFIG_44x) 7 7 8 8 /* 9 9 * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory

+15

arch/powerpc/include/asm/kfence.h

··· 11 11 #include <linux/mm.h> 12 12 #include <asm/pgtable.h> 13 13 14 + #ifdef CONFIG_PPC64_ELF_ABI_V1 15 + #define ARCH_FUNC_PREFIX "." 16 + #endif 17 + 14 18 static inline bool arch_kfence_init_pool(void) 15 19 { 16 20 return true; 17 21 } 18 22 23 + #ifdef CONFIG_PPC64 24 + static inline bool kfence_protect_page(unsigned long addr, bool protect) 25 + { 26 + struct page *page = virt_to_page(addr); 27 + 28 + __kernel_map_pages(page, 1, !protect); 29 + 30 + return true; 31 + } 32 + #else 19 33 static inline bool kfence_protect_page(unsigned long addr, bool protect) 20 34 { 21 35 pte_t *kpte = virt_to_kpte(addr); ··· 43 29 44 30 return true; 45 31 } 32 + #endif 46 33 47 34 #endif /* __ASM_POWERPC_KFENCE_H */

+1 -1

arch/powerpc/include/asm/kgdb.h

··· 52 52 /* On non-E500 family PPC32 we determine the size by picking the last 53 53 * register we need, but on E500 we skip sections so we list what we 54 54 * need to store, and add it up. */ 55 - #ifndef CONFIG_E500 55 + #ifndef CONFIG_PPC_E500 56 56 #define MAXREG (PT_FPSCR+1) 57 57 #else 58 58 /* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/

+1 -1

arch/powerpc/include/asm/kvm_host.h

··· 443 443 }; 444 444 #endif 445 445 446 - # ifdef CONFIG_PPC_FSL_BOOK3E 446 + # ifdef CONFIG_PPC_E500 447 447 #define KVMPPC_BOOKE_IAC_NUM 2 448 448 #define KVMPPC_BOOKE_DAC_NUM 2 449 449 # else

-4

arch/powerpc/include/asm/kvm_ppc.h

··· 104 104 105 105 extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gpa_t gpaddr, 106 106 unsigned int gtlb_idx); 107 - extern void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode); 108 107 extern void kvmppc_mmu_switch_pid(struct kvm_vcpu *vcpu, u32 pid); 109 108 extern int kvmppc_mmu_dtlb_index(struct kvm_vcpu *vcpu, gva_t eaddr); 110 109 extern int kvmppc_mmu_itlb_index(struct kvm_vcpu *vcpu, gva_t eaddr); ··· 152 153 extern int kvmppc_booke_init(void); 153 154 extern void kvmppc_booke_exit(void); 154 155 155 - extern void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu); 156 156 extern int kvmppc_kvm_pv(struct kvm_vcpu *vcpu); 157 157 extern void kvmppc_map_magic(struct kvm_vcpu *vcpu); 158 158 ··· 160 162 extern long kvmppc_alloc_reset_hpt(struct kvm *kvm, int order); 161 163 extern void kvmppc_free_hpt(struct kvm_hpt_info *info); 162 164 extern void kvmppc_rmap_reset(struct kvm *kvm); 163 - extern long kvmppc_prepare_vrma(struct kvm *kvm, 164 - struct kvm_userspace_memory_region *mem); 165 165 extern void kvmppc_map_vrma(struct kvm_vcpu *vcpu, 166 166 struct kvm_memory_slot *memslot, unsigned long porder); 167 167 extern int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu);

+7 -3

arch/powerpc/include/asm/lppaca.h

··· 104 104 volatile __be32 dispersion_count; /* dispatch changed physical cpu */ 105 105 volatile __be64 cmo_faults; /* CMO page fault count */ 106 106 volatile __be64 cmo_fault_time; /* CMO page fault time */ 107 - u8 reserved10[104]; 107 + u8 reserved10[64]; /* [S]PURR expropriated/donated */ 108 + volatile __be64 enqueue_dispatch_tb; /* Total TB enqueue->dispatch */ 109 + volatile __be64 ready_enqueue_tb; /* Total TB ready->enqueue */ 110 + volatile __be64 wait_ready_tb; /* Total TB wait->ready */ 111 + u8 reserved11[16]; 108 112 109 113 /* cacheline 4-5 */ 110 114 111 115 __be32 page_ins; /* CMO Hint - # page ins by OS */ 112 - u8 reserved11[148]; 116 + u8 reserved12[148]; 113 117 volatile __be64 dtl_idx; /* Dispatch Trace Log head index */ 114 - u8 reserved12[96]; 118 + u8 reserved13[96]; 115 119 } ____cacheline_aligned; 116 120 117 121 #define lppaca_of(cpu) (*paca_ptrs[cpu]->lppaca_ptr)

-1

arch/powerpc/include/asm/machdep.h

··· 204 204 extern void e500_idle(void); 205 205 extern void power4_idle(void); 206 206 extern void ppc6xx_idle(void); 207 - extern void book3e_idle(void); 208 207 209 208 /* 210 209 * ppc_md contains a copy of the machine description structure for the

+7 -4

arch/powerpc/include/asm/mmu.h

··· 120 120 */ 121 121 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) 122 122 123 + // NX paste RMA reject in DSI 124 + #define MMU_FTR_NX_DSI ASM_CONST(0x80000000) 125 + 123 126 /* MMU feature bit sets for various CPUs */ 124 127 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 (MMU_FTR_HPTE_TABLE | MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) 125 128 #define MMU_FTRS_POWER MMU_FTRS_DEFAULT_HPTE_ARCH_V2 ··· 144 141 145 142 typedef pte_t *pgtable_t; 146 143 147 - #ifdef CONFIG_PPC_FSL_BOOK3E 144 + #ifdef CONFIG_PPC_E500 148 145 #include <asm/percpu.h> 149 146 DECLARE_PER_CPU(int, next_tlbcam_idx); 150 147 #endif ··· 165 162 #elif defined(CONFIG_44x) 166 163 MMU_FTR_TYPE_44x | 167 164 #endif 168 - #ifdef CONFIG_E500 165 + #ifdef CONFIG_PPC_E500 169 166 MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX | 170 167 #endif 171 168 #ifdef CONFIG_PPC_BOOK3S_32 ··· 184 181 #endif 185 182 #ifdef CONFIG_PPC_RADIX_MMU 186 183 MMU_FTR_TYPE_RADIX | 187 - MMU_FTR_GTSE | 184 + MMU_FTR_GTSE | MMU_FTR_NX_DSI | 188 185 #endif /* CONFIG_PPC_RADIX_MMU */ 189 186 #endif 190 187 #ifdef CONFIG_PPC_KUAP ··· 214 211 #elif defined(CONFIG_44x) 215 212 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_44x 216 213 #endif 217 - #ifdef CONFIG_E500 214 + #ifdef CONFIG_PPC_E500 218 215 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_FSL_E 219 216 #endif 220 217

-2

arch/powerpc/include/asm/mmu_context.h

··· 31 31 extern long mm_iommu_put(struct mm_struct *mm, 32 32 struct mm_iommu_table_group_mem_t *mem); 33 33 extern void mm_iommu_init(struct mm_struct *mm); 34 - extern void mm_iommu_cleanup(struct mm_struct *mm); 35 34 extern struct mm_iommu_table_group_mem_t *mm_iommu_lookup(struct mm_struct *mm, 36 35 unsigned long ua, unsigned long size); 37 36 extern struct mm_iommu_table_group_mem_t *mm_iommu_get(struct mm_struct *mm, ··· 116 117 } 117 118 #endif 118 119 119 - extern void switch_cop(struct mm_struct *next); 120 120 extern int use_cop(unsigned long acop, struct mm_struct *mm); 121 121 extern void drop_cop(unsigned long acop, struct mm_struct *mm); 122 122

+4 -4

arch/powerpc/include/asm/nohash/32/pgtable.h

··· 130 130 #include <asm/nohash/32/pte-40x.h> 131 131 #elif defined(CONFIG_44x) 132 132 #include <asm/nohash/32/pte-44x.h> 133 - #elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT) 134 - #include <asm/nohash/pte-book3e.h> 135 - #elif defined(CONFIG_FSL_BOOKE) 136 - #include <asm/nohash/32/pte-fsl-booke.h> 133 + #elif defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT) 134 + #include <asm/nohash/pte-e500.h> 135 + #elif defined(CONFIG_PPC_85xx) 136 + #include <asm/nohash/32/pte-85xx.h> 137 137 #elif defined(CONFIG_PPC_8xx) 138 138 #include <asm/nohash/32/pte-8xx.h> 139 139 #endif

+3 -3

arch/powerpc/include/asm/nohash/32/pte-fsl-booke.h arch/powerpc/include/asm/nohash/32/pte-85xx.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 - #ifndef _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H 3 - #define _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H 2 + #ifndef _ASM_POWERPC_NOHASH_32_PTE_85xx_H 3 + #define _ASM_POWERPC_NOHASH_32_PTE_85xx_H 4 4 #ifdef __KERNEL__ 5 5 6 6 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based ··· 71 71 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 72 72 73 73 #endif /* __KERNEL__ */ 74 - #endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */ 74 + #endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_85xx_H */

+1 -1

arch/powerpc/include/asm/nohash/64/pgtable.h

··· 70 70 /* 71 71 * Include the PTE bits definitions 72 72 */ 73 - #include <asm/nohash/pte-book3e.h> 73 + #include <asm/nohash/pte-e500.h> 74 74 75 75 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1)) 76 76

+4 -4

arch/powerpc/include/asm/nohash/hugetlb-book3e.h arch/powerpc/include/asm/nohash/hugetlb-e500.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 - #ifndef _ASM_POWERPC_NOHASH_HUGETLB_BOOK3E_H 3 - #define _ASM_POWERPC_NOHASH_HUGETLB_BOOK3E_H 2 + #ifndef _ASM_POWERPC_NOHASH_HUGETLB_E500_H 3 + #define _ASM_POWERPC_NOHASH_HUGETLB_E500_H 4 4 5 5 static inline pte_t *hugepd_page(hugepd_t hpd) 6 6 { ··· 30 30 31 31 static inline void hugepd_populate(hugepd_t *hpdp, pte_t *new, unsigned int pshift) 32 32 { 33 - /* We use the old format for PPC_FSL_BOOK3E */ 33 + /* We use the old format for PPC_E500 */ 34 34 *hpdp = __hugepd(((unsigned long)new & ~PD_HUGE) | pshift); 35 35 } 36 36 ··· 42 42 return shift_to_mmu_psize(shift); 43 43 } 44 44 45 - #endif /* _ASM_POWERPC_NOHASH_HUGETLB_BOOK3E_H */ 45 + #endif /* _ASM_POWERPC_NOHASH_HUGETLB_E500_H */

arch/powerpc/include/asm/nohash/mmu-book3e.h arch/powerpc/include/asm/nohash/mmu-e500.h

+2 -2

arch/powerpc/include/asm/nohash/mmu.h

··· 8 8 #elif defined(CONFIG_44x) 9 9 /* 44x-style software loaded TLB */ 10 10 #include <asm/nohash/32/mmu-44x.h> 11 - #elif defined(CONFIG_PPC_BOOK3E_MMU) 11 + #elif defined(CONFIG_PPC_E500) 12 12 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ 13 - #include <asm/nohash/mmu-book3e.h> 13 + #include <asm/nohash/mmu-e500.h> 14 14 #elif defined (CONFIG_PPC_8xx) 15 15 /* Motorola/Freescale 8xx software loaded TLB */ 16 16 #include <asm/nohash/32/mmu-8xx.h>

+1 -1

arch/powerpc/include/asm/nohash/pgalloc.h

··· 15 15 { 16 16 17 17 } 18 - #endif /* !CONFIG_PPC_BOOK3E */ 18 + #endif /* !CONFIG_PPC_BOOK3E_64 */ 19 19 20 20 static inline pgd_t *pgd_alloc(struct mm_struct *mm) 21 21 {

+2 -28

arch/powerpc/include/asm/nohash/pgtable.h

··· 11 11 /* Permission masks used for kernel mappings */ 12 12 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 13 13 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE) 14 - #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 15 - _PAGE_NO_CACHE | _PAGE_GUARDED) 14 + #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE | _PAGE_GUARDED) 16 15 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 17 16 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 18 17 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 19 - 20 - /* 21 - * Protection used for kernel text. We want the debuggers to be able to 22 - * set breakpoints anywhere, so don't write protect the kernel text 23 - * on platforms where such control is possible. 24 - */ 25 - #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ 26 - defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 27 - #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 28 - #else 29 - #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 30 - #endif 31 - 32 - /* Make modules code happy. We don't set RO yet */ 33 - #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 34 - 35 - /* Advertise special mapping type for AGP */ 36 - #define PAGE_AGP (PAGE_KERNEL_NC) 37 - #define HAVE_PAGE_AGP 38 18 39 19 #ifndef __ASSEMBLY__ 40 20 ··· 257 277 return 0; 258 278 } 259 279 260 - static inline int pgd_huge(pgd_t pgd) 261 - { 262 - return 0; 263 - } 264 - #define pgd_huge pgd_huge 265 - 266 280 #define is_hugepd(hpd) (hugepd_ok(hpd)) 267 281 #endif 268 282 ··· 266 292 * We use it to ensure coherency between the i-cache and d-cache 267 293 * for the page which has just been mapped in. 268 294 */ 269 - #if defined(CONFIG_PPC_FSL_BOOK3E) && defined(CONFIG_HUGETLB_PAGE) 295 + #if defined(CONFIG_PPC_E500) && defined(CONFIG_HUGETLB_PAGE) 270 296 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep); 271 297 #else 272 298 static inline

+3 -3

arch/powerpc/include/asm/nohash/pte-book3e.h arch/powerpc/include/asm/nohash/pte-e500.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 - #ifndef _ASM_POWERPC_NOHASH_PTE_BOOK3E_H 3 - #define _ASM_POWERPC_NOHASH_PTE_BOOK3E_H 2 + #ifndef _ASM_POWERPC_NOHASH_PTE_E500_H 3 + #define _ASM_POWERPC_NOHASH_PTE_E500_H 4 4 #ifdef __KERNEL__ 5 5 6 6 /* PTE bit definitions for processors compliant to the Book3E ··· 126 126 #endif /* __ASSEMBLY__ */ 127 127 128 128 #endif /* __KERNEL__ */ 129 - #endif /* _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */ 129 + #endif /* _ASM_POWERPC_NOHASH_PTE_E500_H */

+1 -1

arch/powerpc/include/asm/nohash/tlbflush.h

··· 18 18 /* 19 19 * TLB flushing for software loaded TLB chips 20 20 * 21 - * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range & 21 + * TODO: (CONFIG_PPC_85xx) determine if flush_tlb_range & 22 22 * flush_tlb_kernel_range are best implemented as tlbia vs 23 23 * specific tlbie's 24 24 */

-6

arch/powerpc/include/asm/opal.h

··· 324 324 325 325 extern void hvc_opal_init_early(void); 326 326 327 - extern int opal_notifier_register(struct notifier_block *nb); 328 - extern int opal_notifier_unregister(struct notifier_block *nb); 329 - 330 327 extern int opal_message_notifier_register(enum opal_msg_type msg_type, 331 328 struct notifier_block *nb); 332 329 extern int opal_message_notifier_unregister(enum opal_msg_type msg_type, 333 330 struct notifier_block *nb); 334 - extern void opal_notifier_enable(void); 335 - extern void opal_notifier_disable(void); 336 - extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 337 331 338 332 extern int opal_async_get_token_interruptible(void); 339 333 extern int opal_async_release_token(int token);

+4 -5

arch/powerpc/include/asm/paca.h

··· 18 18 #include <asm/lppaca.h> 19 19 #include <asm/mmu.h> 20 20 #include <asm/page.h> 21 - #ifdef CONFIG_PPC_BOOK3E 21 + #ifdef CONFIG_PPC_BOOK3E_64 22 22 #include <asm/exception-64e.h> 23 23 #else 24 24 #include <asm/exception-64s.h> ··· 127 127 #endif 128 128 #endif /* CONFIG_PPC_BOOK3S_64 */ 129 129 130 - #ifdef CONFIG_PPC_BOOK3E 130 + #ifdef CONFIG_PPC_BOOK3E_64 131 131 u64 exgen[8] __aligned(0x40); 132 132 /* Keep pgd in the same cacheline as the start of extlb */ 133 133 pgd_t *pgd __aligned(0x40); /* Current PGD */ ··· 151 151 void *dbg_kstack; 152 152 153 153 struct tlb_core_data tcd; 154 - #endif /* CONFIG_PPC_BOOK3E */ 154 + #endif /* CONFIG_PPC_BOOK3E_64 */ 155 155 156 156 #ifdef CONFIG_PPC_64S_HASH_MMU 157 157 unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE]; ··· 168 168 #ifdef CONFIG_PPC64 169 169 u64 exit_save_r1; /* Syscall/interrupt R1 save */ 170 170 #endif 171 - #ifdef CONFIG_PPC_BOOK3E 171 + #ifdef CONFIG_PPC_BOOK3E_64 172 172 u16 trap_save; /* Used when bad stack is encountered */ 173 173 #endif 174 174 #ifdef CONFIG_PPC_BOOK3S_64 ··· 263 263 u64 l1d_flush_size; 264 264 #endif 265 265 #ifdef CONFIG_PPC_PSERIES 266 - struct rtas_args *rtas_args_reentrant; 267 266 u8 *mce_data_buf; /* buffer to hold per cpu rtas errlog */ 268 267 #endif /* CONFIG_PPC_PSERIES */ 269 268

+1 -7

arch/powerpc/include/asm/page.h

··· 31 31 #define HPAGE_SHIFT hpage_shift 32 32 #elif defined(CONFIG_PPC_8xx) 33 33 #define HPAGE_SHIFT 19 /* 512k pages */ 34 - #elif defined(CONFIG_PPC_FSL_BOOK3E) 34 + #elif defined(CONFIG_PPC_E500) 35 35 #define HPAGE_SHIFT 22 /* 4M pages */ 36 36 #endif 37 37 #define HPAGE_SIZE ((1UL) << HPAGE_SHIFT) ··· 307 307 #else 308 308 #include <asm/pgtable-types.h> 309 309 #endif 310 - 311 - 312 - #ifndef CONFIG_HUGETLB_PAGE 313 - #define is_hugepd(pdep) (0) 314 - #define pgd_huge(pgd) (0) 315 - #endif /* CONFIG_HUGETLB_PAGE */ 316 310 317 311 struct page; 318 312 extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);

+12

arch/powerpc/include/asm/paravirt.h

··· 21 21 return static_branch_unlikely(&shared_processor); 22 22 } 23 23 24 + #ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING 25 + extern struct static_key paravirt_steal_enabled; 26 + extern struct static_key paravirt_steal_rq_enabled; 27 + 28 + u64 pseries_paravirt_steal_clock(int cpu); 29 + 30 + static inline u64 paravirt_steal_clock(int cpu) 31 + { 32 + return pseries_paravirt_steal_clock(cpu); 33 + } 34 + #endif 35 + 24 36 /* If bit 0 is set, the cpu has been ceded, conferred, or preempted */ 25 37 static inline u32 yield_count_of(int cpu) 26 38 {

+2

arch/powerpc/include/asm/paravirt_api_clock.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + #include <asm/paravirt.h>

+2

arch/powerpc/include/asm/pgtable-be-types.h

··· 101 101 return pmd_raw(old) == prev; 102 102 } 103 103 104 + #ifdef CONFIG_ARCH_HAS_HUGEPD 104 105 typedef struct { __be64 pdbe; } hugepd_t; 105 106 #define __hugepd(x) ((hugepd_t) { cpu_to_be64(x) }) 106 107 ··· 109 108 { 110 109 return be64_to_cpu(x.pdbe); 111 110 } 111 + #endif 112 112 113 113 #endif /* _ASM_POWERPC_PGTABLE_BE_TYPES_H */

+2

arch/powerpc/include/asm/pgtable-types.h

··· 83 83 } 84 84 #endif 85 85 86 + #ifdef CONFIG_ARCH_HAS_HUGEPD 86 87 typedef struct { unsigned long pd; } hugepd_t; 87 88 #define __hugepd(x) ((hugepd_t) { (x) }) 88 89 static inline unsigned long hpd_val(hugepd_t x) 89 90 { 90 91 return x.pd; 91 92 } 93 + #endif 92 94 93 95 #endif /* _ASM_POWERPC_PGTABLE_TYPES_H */

+19

arch/powerpc/include/asm/pgtable.h

··· 20 20 #include <asm/nohash/pgtable.h> 21 21 #endif /* !CONFIG_PPC_BOOK3S */ 22 22 23 + /* 24 + * Protection used for kernel text. We want the debuggers to be able to 25 + * set breakpoints anywhere, so don't write protect the kernel text 26 + * on platforms where such control is possible. 27 + */ 28 + #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 29 + defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 30 + #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 31 + #else 32 + #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 33 + #endif 34 + 35 + /* Make modules code happy. We don't set RO yet */ 36 + #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 37 + 38 + /* Advertise special mapping type for AGP */ 39 + #define PAGE_AGP (PAGE_KERNEL_NC) 40 + #define HAVE_PAGE_AGP 41 + 23 42 #ifndef __ASSEMBLY__ 24 43 25 44 #ifndef MAX_PTRS_PER_PGD

+5 -2

arch/powerpc/include/asm/ppc-opcode.h

··· 330 330 #define __PPC_XSP(s) ((((s) & 0x1e) | (((s) >> 5) & 0x1)) << 21) 331 331 #define __PPC_XTP(s) __PPC_XSP(s) 332 332 #define __PPC_T_TLB(t) (((t) & 0x3) << 21) 333 + #define __PPC_PL(p) (((p) & 0x3) << 16) 333 334 #define __PPC_WC(w) (((w) & 0x3) << 21) 334 335 #define __PPC_WS(w) (((w) & 0x1f) << 11) 335 336 #define __PPC_SH(s) __PPC_WS(s) ··· 389 388 #define PPC_RAW_RFDI (0x4c00004e) 390 389 #define PPC_RAW_RFMCI (0x4c00004c) 391 390 #define PPC_RAW_TLBILX(t, a, b) (0x7c000024 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) 392 - #define PPC_RAW_WAIT(w) (0x7c00007c | __PPC_WC(w)) 391 + #define PPC_RAW_WAIT_v203 (0x7c00007c) 392 + #define PPC_RAW_WAIT(w, p) (0x7c00003c | __PPC_WC(w) | __PPC_PL(p)) 393 393 #define PPC_RAW_TLBIE(lp, a) (0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp)) 394 394 #define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \ 395 395 (0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r)) ··· 608 606 #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) 609 607 #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) 610 608 #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) 611 - #define PPC_WAIT(w) stringify_in_c(.long PPC_RAW_WAIT(w)) 609 + #define PPC_WAIT_v203 stringify_in_c(.long PPC_RAW_WAIT_v203) 610 + #define PPC_WAIT(w, p) stringify_in_c(.long PPC_RAW_WAIT(w, p)) 612 611 #define PPC_TLBIE(lp, a) stringify_in_c(.long PPC_RAW_TLBIE(lp, a)) 613 612 #define PPC_TLBIE_5(rb, rs, ric, prs, r) \ 614 613 stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))

+46 -6

arch/powerpc/include/asm/ppc_asm.h

··· 34 34 .endm 35 35 36 36 /* 37 + * This expands to a sequence of register clears for regs start to end 38 + * inclusive, of the form: 39 + * 40 + * li rN, 0 41 + */ 42 + .macro ZEROIZE_REGS start, end 43 + .Lreg=\start 44 + .rept (\end - \start + 1) 45 + li .Lreg, 0 46 + .Lreg=.Lreg+1 47 + .endr 48 + .endm 49 + 50 + /* 37 51 * Macros for storing registers into and loading registers from 38 52 * exception frames. 39 53 */ ··· 62 48 #define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base) 63 49 #define REST_NVGPRS(base) REST_GPRS(13, 31, base) 64 50 #endif 51 + 52 + #define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end 53 + #ifdef __powerpc64__ 54 + #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31) 55 + #else 56 + #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31) 57 + #endif 58 + #define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n) 65 59 66 60 #define SAVE_GPR(n, base) SAVE_GPRS(n, n, base) 67 61 #define REST_GPR(n, base) REST_GPRS(n, n, base) ··· 327 305 328 306 #ifdef __powerpc64__ 329 307 308 + #define __LOAD_PACA_TOC(reg) \ 309 + ld reg,PACATOC(r13) 310 + 311 + #define LOAD_PACA_TOC() \ 312 + __LOAD_PACA_TOC(r2) 313 + 330 314 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 331 315 332 316 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ ··· 343 315 rldimi reg, tmp, 32, 0 344 316 345 317 #define LOAD_REG_ADDR(reg,name) \ 346 - ld reg,name@got(r2) 318 + addis reg,r2,name@toc@ha; \ 319 + addi reg,reg,name@toc@l 320 + 321 + #ifdef CONFIG_PPC_BOOK3E_64 322 + /* 323 + * This is used in register-constrained interrupt handlers. Not to be used 324 + * by BOOK3S. ld complains with "got/toc optimization is not supported" if r2 325 + * is not used for the TOC offset, so use @got(tocreg). If the interrupt 326 + * handlers saved r2 instead, LOAD_REG_ADDR could be used. 327 + */ 328 + #define LOAD_REG_ADDR_ALTTOC(reg,tocreg,name) \ 329 + ld reg,name@got(tocreg) 330 + #endif 347 331 348 332 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 349 333 #define ADDROFF(name) 0 ··· 382 342 #endif 383 343 384 344 /* various errata or part fixups */ 385 - #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 345 + #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500) 386 346 #define MFTB(dest) \ 387 347 90: mfspr dest, SPRN_TBRL; \ 388 348 BEGIN_FTR_SECTION_NESTED(96); \ ··· 749 709 * kernel is built for. 750 710 */ 751 711 752 - #ifdef CONFIG_PPC_BOOK3E 712 + #ifdef CONFIG_PPC_BOOK3E_64 753 713 #define FIXUP_ENDIAN 754 714 #else 755 715 /* ··· 789 749 .long 0x2402004c; /* hrfid */ \ 790 750 191: 791 751 792 - #endif /* !CONFIG_PPC_BOOK3E */ 752 + #endif /* !CONFIG_PPC_BOOK3E_64 */ 793 753 794 754 #endif /* __ASSEMBLY__ */ 795 755 ··· 808 768 stringify_in_c(.llong (_target);) \ 809 769 stringify_in_c(.previous) 810 770 811 - #ifdef CONFIG_PPC_FSL_BOOK3E 771 + #ifdef CONFIG_PPC_E500 812 772 #define BTB_FLUSH(reg) \ 813 773 lis reg,BUCSR_INIT@h; \ 814 774 ori reg,reg,BUCSR_INIT@l; \ ··· 816 776 isync; 817 777 #else 818 778 #define BTB_FLUSH(reg) 819 - #endif /* CONFIG_PPC_FSL_BOOK3E */ 779 + #endif /* CONFIG_PPC_E500 */ 820 780 821 781 #endif /* _ASM_POWERPC_PPC_ASM_H */

+17 -3

arch/powerpc/include/asm/processor.h

··· 355 355 356 356 #ifdef CONFIG_PPC64 357 357 358 - #define spin_begin() HMT_low() 358 + #define spin_begin() \ 359 + asm volatile(ASM_FTR_IFCLR( \ 360 + "or 1,1,1", /* HMT_LOW */ \ 361 + "nop", /* v3.1 uses pause_short in cpu_relax instead */ \ 362 + %0) :: "i" (CPU_FTR_ARCH_31) : "memory") 359 363 360 - #define spin_cpu_relax() barrier() 364 + #define spin_cpu_relax() \ 365 + asm volatile(ASM_FTR_IFCLR( \ 366 + "nop", /* Before v3.1 use priority nops in spin_begin/end */ \ 367 + PPC_WAIT(2, 0), /* aka pause_short */ \ 368 + %0) :: "i" (CPU_FTR_ARCH_31) : "memory") 361 369 362 - #define spin_end() HMT_medium() 370 + #define spin_end() \ 371 + asm volatile(ASM_FTR_IFCLR( \ 372 + "or 2,2,2", /* HMT_MEDIUM */ \ 373 + "nop", \ 374 + %0) :: "i" (CPU_FTR_ARCH_31) : "memory") 363 375 364 376 #endif 365 377 ··· 438 426 #endif 439 427 440 428 int do_mathemu(struct pt_regs *regs); 429 + int do_spe_mathemu(struct pt_regs *regs); 430 + int speround_handler(struct pt_regs *regs); 441 431 442 432 /* VMX copying */ 443 433 int enter_vmx_usercopy(void);

-2

arch/powerpc/include/asm/ps3av.h

··· 726 726 extern int ps3av_video_mute(int); 727 727 extern int ps3av_audio_mute(int); 728 728 extern int ps3av_audio_mute_analog(int); 729 - extern int ps3av_dev_open(void); 730 - extern int ps3av_dev_close(void); 731 729 #endif /* _ASM_POWERPC_PS3AV_H_ */

+7 -2

arch/powerpc/include/asm/ptrace.h

··· 99 99 100 100 #define STACK_FRAME_WITH_PT_REGS (STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)) 101 101 102 + // Always displays as "REGS" in memory dumps 103 + #ifdef CONFIG_CPU_BIG_ENDIAN 104 + #define STACK_FRAME_REGS_MARKER ASM_CONST(0x52454753) 105 + #else 106 + #define STACK_FRAME_REGS_MARKER ASM_CONST(0x53474552) 107 + #endif 108 + 102 109 #ifdef __powerpc64__ 103 110 104 111 /* ··· 122 115 123 116 #define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ 124 117 #define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */ 125 - #define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265) 126 118 #define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \ 127 119 STACK_FRAME_OVERHEAD + KERNEL_REDZONE_SIZE) 128 120 #define STACK_FRAME_MARKER 12 ··· 142 136 #define KERNEL_REDZONE_SIZE 0 143 137 #define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ 144 138 #define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */ 145 - #define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773) 146 139 #define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD) 147 140 #define STACK_FRAME_MARKER 2 148 141 #define STACK_FRAME_MIN_SIZE STACK_FRAME_OVERHEAD

+3 -3

arch/powerpc/include/asm/reg_booke.h

··· 246 246 #define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */ 247 247 #define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */ 248 248 249 - #ifdef CONFIG_E500 249 + #ifdef CONFIG_PPC_E500 250 250 /* All e500 */ 251 251 #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 252 252 #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ ··· 282 282 #endif 283 283 284 284 /* Bit definitions for the HID1 */ 285 - #ifdef CONFIG_E500 285 + #ifdef CONFIG_PPC_E500 286 286 /* e500v1/v2 */ 287 287 #define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */ 288 288 #define HID1_RFXE 0x00020000 /* Read fault exception enable */ ··· 545 545 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 546 546 #define TCR_ARE 0x00400000 /* Auto Reload Enable */ 547 547 548 - #ifdef CONFIG_E500 548 + #ifdef CONFIG_PPC_E500 549 549 #define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \ 550 550 (((tcr) & 0x1E0000) >> 15)) 551 551 #else

-1

arch/powerpc/include/asm/rtas.h

··· 240 240 extern int rtas_token(const char *service); 241 241 extern int rtas_service_present(const char *service); 242 242 extern int rtas_call(int token, int, int, int *, ...); 243 - int rtas_call_reentrant(int token, int nargs, int nret, int *outputs, ...); 244 243 void rtas_call_unlocked(struct rtas_args *args, int token, int nargs, 245 244 int nret, ...); 246 245 extern void __noreturn rtas_restart(char *cmd);

+2 -4

arch/powerpc/include/asm/runlatch.h

··· 19 19 do { \ 20 20 if (cpu_has_feature(CPU_FTR_CTRL) && \ 21 21 test_thread_local_flags(_TLF_RUNLATCH)) { \ 22 - unsigned long msr = mfmsr(); \ 23 22 __hard_irq_disable(); \ 24 23 __ppc64_runlatch_off(); \ 25 - if (msr & MSR_EE) \ 24 + if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) \ 26 25 __hard_irq_enable(); \ 27 26 } \ 28 27 } while (0) ··· 30 31 do { \ 31 32 if (cpu_has_feature(CPU_FTR_CTRL) && \ 32 33 !test_thread_local_flags(_TLF_RUNLATCH)) { \ 33 - unsigned long msr = mfmsr(); \ 34 34 __hard_irq_disable(); \ 35 35 __ppc64_runlatch_on(); \ 36 - if (msr & MSR_EE) \ 36 + if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) \ 37 37 __hard_irq_enable(); \ 38 38 } \ 39 39 } while (0)

+14 -3

arch/powerpc/include/asm/sections.h

··· 13 13 #include <asm-generic/sections.h> 14 14 15 15 extern char __head_end[]; 16 + extern char __srwx_boundary[]; 17 + 18 + /* Patch sites */ 19 + extern s32 patch__call_flush_branch_caches1; 20 + extern s32 patch__call_flush_branch_caches2; 21 + extern s32 patch__call_flush_branch_caches3; 22 + extern s32 patch__flush_count_cache_return; 23 + extern s32 patch__flush_link_stack_return; 24 + extern s32 patch__call_kvm_flush_link_stack; 25 + extern s32 patch__call_kvm_flush_link_stack_p9; 26 + extern s32 patch__memset_nocache, patch__memcpy_nocache; 27 + 28 + extern long flush_branch_caches; 29 + extern long kvm_flush_link_stack; 16 30 17 31 #ifdef __powerpc64__ 18 32 19 33 extern char __start_interrupts[]; 20 34 extern char __end_interrupts[]; 21 - 22 - extern char __prom_init_toc_start[]; 23 - extern char __prom_init_toc_end[]; 24 35 25 36 #ifdef CONFIG_PPC_POWERNV 26 37 extern char start_real_trampolines[];

+3 -2

arch/powerpc/include/asm/setup.h

··· 7 7 #ifndef __ASSEMBLY__ 8 8 extern void ppc_printk_progress(char *s, unsigned short hex); 9 9 10 - extern unsigned int rtas_data; 11 10 extern unsigned long long memory_limit; 12 11 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); 13 12 ··· 69 70 static inline void do_barrier_nospec_fixups_range(bool enable, void *start, void *end) { } 70 71 #endif 71 72 72 - #ifdef CONFIG_PPC_FSL_BOOK3E 73 + #ifdef CONFIG_PPC_E500 73 74 void __init setup_spectre_v2(void); 74 75 #else 75 76 static inline void setup_spectre_v2(void) {} ··· 87 88 unsigned long __init prom_init(unsigned long r3, unsigned long r4, 88 89 unsigned long pp, unsigned long r6, 89 90 unsigned long r7, unsigned long kbase); 91 + 92 + extern struct seq_buf ppc_hw_desc; 90 93 91 94 #endif /* !__ASSEMBLY__ */ 92 95

+1 -1

arch/powerpc/include/asm/synch.h

··· 44 44 45 45 #if defined(__powerpc64__) 46 46 # define LWSYNC lwsync 47 - #elif defined(CONFIG_E500) 47 + #elif defined(CONFIG_PPC_E500) 48 48 # define LWSYNC \ 49 49 START_LWSYNC_SECTION(96); \ 50 50 sync; \

+9 -2

arch/powerpc/include/asm/syscall.h

··· 14 14 #include <linux/sched.h> 15 15 #include <linux/thread_info.h> 16 16 17 + #ifdef CONFIG_ARCH_HAS_SYSCALL_WRAPPER 18 + typedef long (*syscall_fn)(const struct pt_regs *); 19 + #else 20 + typedef long (*syscall_fn)(unsigned long, unsigned long, unsigned long, 21 + unsigned long, unsigned long, unsigned long); 22 + #endif 23 + 17 24 /* ftrace syscalls requires exporting the sys_call_table */ 18 - extern const unsigned long sys_call_table[]; 19 - extern const unsigned long compat_sys_call_table[]; 25 + extern const syscall_fn sys_call_table[]; 26 + extern const syscall_fn compat_sys_call_table[]; 20 27 21 28 static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs) 22 29 {

+49

arch/powerpc/include/asm/syscall_wrapper.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * syscall_wrapper.h - powerpc specific wrappers to syscall definitions 4 + * 5 + * Based on arch/{x86,arm64}/include/asm/syscall_wrapper.h 6 + */ 7 + 8 + #ifndef __ASM_POWERPC_SYSCALL_WRAPPER_H 9 + #define __ASM_POWERPC_SYSCALL_WRAPPER_H 10 + 11 + struct pt_regs; 12 + 13 + #define SC_POWERPC_REGS_TO_ARGS(x, ...) \ 14 + __MAP(x,__SC_ARGS \ 15 + ,,regs->gpr[3],,regs->gpr[4],,regs->gpr[5] \ 16 + ,,regs->gpr[6],,regs->gpr[7],,regs->gpr[8]) 17 + 18 + #define __SYSCALL_DEFINEx(x, name, ...) \ 19 + long sys##name(const struct pt_regs *regs); \ 20 + ALLOW_ERROR_INJECTION(sys##name, ERRNO); \ 21 + static long __se_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)); \ 22 + static inline long __do_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__)); \ 23 + long sys##name(const struct pt_regs *regs) \ 24 + { \ 25 + return __se_sys##name(SC_POWERPC_REGS_TO_ARGS(x,__VA_ARGS__)); \ 26 + } \ 27 + static long __se_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)) \ 28 + { \ 29 + long ret = __do_sys##name(__MAP(x,__SC_CAST,__VA_ARGS__)); \ 30 + __MAP(x,__SC_TEST,__VA_ARGS__); \ 31 + __PROTECT(x, ret,__MAP(x,__SC_ARGS,__VA_ARGS__)); \ 32 + return ret; \ 33 + } \ 34 + static inline long __do_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__)) 35 + 36 + #define SYSCALL_DEFINE0(sname) \ 37 + SYSCALL_METADATA(_##sname, 0); \ 38 + long sys_##sname(const struct pt_regs *__unused); \ 39 + ALLOW_ERROR_INJECTION(sys_##sname, ERRNO); \ 40 + long sys_##sname(const struct pt_regs *__unused) 41 + 42 + #define COND_SYSCALL(name) \ 43 + long sys_##name(const struct pt_regs *regs); \ 44 + long __weak sys_##name(const struct pt_regs *regs) \ 45 + { \ 46 + return sys_ni_syscall(); \ 47 + } 48 + 49 + #endif // __ASM_POWERPC_SYSCALL_WRAPPER_H

+117 -35

arch/powerpc/include/asm/syscalls.h

··· 8 8 #include <linux/types.h> 9 9 #include <linux/compat.h> 10 10 11 + #include <asm/syscall.h> 12 + #ifdef CONFIG_PPC64 13 + #include <asm/syscalls_32.h> 14 + #endif 15 + #include <asm/unistd.h> 16 + #include <asm/ucontext.h> 17 + 18 + #ifndef CONFIG_ARCH_HAS_SYSCALL_WRAPPER 19 + long sys_ni_syscall(void); 20 + #else 21 + long sys_ni_syscall(const struct pt_regs *regs); 22 + #endif 23 + 11 24 struct rtas_args; 12 25 13 - asmlinkage long sys_mmap(unsigned long addr, size_t len, 14 - unsigned long prot, unsigned long flags, 15 - unsigned long fd, off_t offset); 16 - asmlinkage long sys_mmap2(unsigned long addr, size_t len, 17 - unsigned long prot, unsigned long flags, 18 - unsigned long fd, unsigned long pgoff); 19 - asmlinkage long ppc64_personality(unsigned long personality); 20 - asmlinkage long sys_rtas(struct rtas_args __user *uargs); 21 - int ppc_select(int n, fd_set __user *inp, fd_set __user *outp, 22 - fd_set __user *exp, struct __kernel_old_timeval __user *tvp); 23 - long ppc_fadvise64_64(int fd, int advice, u32 offset_high, u32 offset_low, 24 - u32 len_high, u32 len_low); 26 + /* 27 + * long long munging: 28 + * The 32 bit ABI passes long longs in an odd even register pair. 29 + * High and low parts are swapped depending on endian mode, 30 + * so define a macro (similar to mips linux32) to handle that. 31 + */ 32 + #ifdef __LITTLE_ENDIAN__ 33 + #define merge_64(low, high) (((u64)high << 32) | low) 34 + #else 35 + #define merge_64(high, low) (((u64)high << 32) | low) 36 + #endif 37 + 38 + /* 39 + * PowerPC architecture-specific syscalls 40 + */ 41 + 42 + #ifndef CONFIG_ARCH_HAS_SYSCALL_WRAPPER 43 + 44 + long sys_rtas(struct rtas_args __user *uargs); 45 + 46 + #ifdef CONFIG_PPC64 47 + long sys_ppc64_personality(unsigned long personality); 48 + #ifdef CONFIG_COMPAT 49 + long compat_sys_ppc64_personality(unsigned long personality); 50 + #endif /* CONFIG_COMPAT */ 51 + #endif /* CONFIG_PPC64 */ 52 + 53 + long sys_swapcontext(struct ucontext __user *old_ctx, 54 + struct ucontext __user *new_ctx, long ctx_size); 55 + long sys_mmap(unsigned long addr, size_t len, 56 + unsigned long prot, unsigned long flags, 57 + unsigned long fd, off_t offset); 58 + long sys_mmap2(unsigned long addr, size_t len, 59 + unsigned long prot, unsigned long flags, 60 + unsigned long fd, unsigned long pgoff); 61 + long sys_switch_endian(void); 62 + 63 + #ifdef CONFIG_PPC32 64 + long sys_sigreturn(void); 65 + long sys_debug_setcontext(struct ucontext __user *ctx, int ndbg, 66 + struct sig_dbg_op __user *dbg); 67 + #endif 68 + 69 + long sys_rt_sigreturn(void); 70 + 71 + long sys_subpage_prot(unsigned long addr, 72 + unsigned long len, u32 __user *map); 25 73 26 74 #ifdef CONFIG_COMPAT 27 - unsigned long compat_sys_mmap2(unsigned long addr, size_t len, 28 - unsigned long prot, unsigned long flags, 29 - unsigned long fd, unsigned long pgoff); 75 + long compat_sys_swapcontext(struct ucontext32 __user *old_ctx, 76 + struct ucontext32 __user *new_ctx, 77 + int ctx_size); 78 + long compat_sys_old_getrlimit(unsigned int resource, 79 + struct compat_rlimit __user *rlim); 80 + long compat_sys_sigreturn(void); 81 + long compat_sys_rt_sigreturn(void); 82 + #endif /* CONFIG_COMPAT */ 30 83 31 - compat_ssize_t compat_sys_pread64(unsigned int fd, char __user *ubuf, compat_size_t count, 32 - u32 reg6, u32 pos1, u32 pos2); 84 + /* 85 + * Architecture specific signatures required by long long munging: 86 + * The 32 bit ABI passes long longs in an odd even register pair. 87 + * The following signatures provide a machine long parameter for 88 + * each register that will be supplied. The implementation is 89 + * responsible for combining parameter pairs. 90 + */ 33 91 34 - compat_ssize_t compat_sys_pwrite64(unsigned int fd, const char __user *ubuf, compat_size_t count, 35 - u32 reg6, u32 pos1, u32 pos2); 92 + #ifdef CONFIG_COMPAT 93 + long compat_sys_mmap2(unsigned long addr, size_t len, 94 + unsigned long prot, unsigned long flags, 95 + unsigned long fd, unsigned long pgoff); 96 + long compat_sys_ppc_pread64(unsigned int fd, 97 + char __user *ubuf, compat_size_t count, 98 + u32 reg6, u32 pos1, u32 pos2); 99 + long compat_sys_ppc_pwrite64(unsigned int fd, 100 + const char __user *ubuf, compat_size_t count, 101 + u32 reg6, u32 pos1, u32 pos2); 102 + long compat_sys_ppc_readahead(int fd, u32 r4, 103 + u32 offset1, u32 offset2, u32 count); 104 + long compat_sys_ppc_truncate64(const char __user *path, u32 reg4, 105 + unsigned long len1, unsigned long len2); 106 + long compat_sys_ppc_ftruncate64(unsigned int fd, u32 reg4, 107 + unsigned long len1, unsigned long len2); 108 + long compat_sys_ppc32_fadvise64(int fd, u32 unused, u32 offset1, u32 offset2, 109 + size_t len, int advice); 110 + long compat_sys_ppc_sync_file_range2(int fd, unsigned int flags, 111 + unsigned int offset1, 112 + unsigned int offset2, 113 + unsigned int nbytes1, 114 + unsigned int nbytes2); 115 + #endif /* CONFIG_COMPAT */ 36 116 37 - compat_ssize_t compat_sys_readahead(int fd, u32 r4, u32 offset1, u32 offset2, u32 count); 38 - 39 - int compat_sys_truncate64(const char __user *path, u32 reg4, 40 - unsigned long len1, unsigned long len2); 41 - 42 - long compat_sys_fallocate(int fd, int mode, u32 offset1, u32 offset2, u32 len1, u32 len2); 43 - 44 - int compat_sys_ftruncate64(unsigned int fd, u32 reg4, unsigned long len1, 45 - unsigned long len2); 46 - 47 - long ppc32_fadvise64(int fd, u32 unused, u32 offset1, u32 offset2, 48 - size_t len, int advice); 49 - 50 - long compat_sys_sync_file_range2(int fd, unsigned int flags, 51 - unsigned int offset1, unsigned int offset2, 52 - unsigned int nbytes1, unsigned int nbytes2); 117 + #if defined(CONFIG_PPC32) || defined(CONFIG_COMPAT) 118 + long sys_ppc_fadvise64_64(int fd, int advice, 119 + u32 offset_high, u32 offset_low, 120 + u32 len_high, u32 len_low); 53 121 #endif 122 + 123 + #else 124 + 125 + #define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, native) 126 + #define __SYSCALL(nr, entry) \ 127 + long entry(const struct pt_regs *regs); 128 + 129 + #ifdef CONFIG_PPC64 130 + #include <asm/syscall_table_64.h> 131 + #else 132 + #include <asm/syscall_table_32.h> 133 + #endif /* CONFIG_PPC64 */ 134 + 135 + #endif /* CONFIG_ARCH_HAS_SYSCALL_WRAPPER */ 54 136 55 137 #endif /* __KERNEL__ */ 56 138 #endif /* __ASM_POWERPC_SYSCALLS_H */

+3 -2

arch/powerpc/include/asm/time.h

··· 116 116 117 117 void timer_broadcast_interrupt(void); 118 118 119 - /* SPLPAR */ 120 - void accumulate_stolen_time(void); 119 + /* SPLPAR and VIRT_CPU_ACCOUNTING_NATIVE */ 120 + void pseries_accumulate_stolen_time(void); 121 + u64 pseries_calculate_stolen_time(u64 stop_tb); 121 122 122 123 #endif /* __KERNEL__ */ 123 124 #endif /* __POWERPC_TIME_H */

+26 -26

arch/powerpc/include/asm/udbg.h

··· 15 15 extern int (*udbg_getc)(void); 16 16 extern int (*udbg_getc_poll)(void); 17 17 18 - extern void udbg_puts(const char *s); 19 - extern int udbg_write(const char *s, int n); 18 + void udbg_puts(const char *s); 19 + int udbg_write(const char *s, int n); 20 20 21 - extern void register_early_udbg_console(void); 22 - extern void udbg_printf(const char *fmt, ...) 21 + void register_early_udbg_console(void); 22 + void udbg_printf(const char *fmt, ...) 23 23 __attribute__ ((format (printf, 1, 2))); 24 - extern void udbg_progress(char *s, unsigned short hex); 24 + void udbg_progress(char *s, unsigned short hex); 25 25 26 26 void __init udbg_uart_init_mmio(void __iomem *addr, unsigned int stride); 27 27 void __init udbg_uart_init_pio(unsigned long port, unsigned int stride); ··· 31 31 32 32 struct device_node; 33 33 void __init udbg_scc_init(int force_scc); 34 - extern int udbg_adb_init(int force_btext); 35 - extern void udbg_adb_init_early(void); 34 + int udbg_adb_init(int force_btext); 35 + void udbg_adb_init_early(void); 36 36 37 - extern void __init udbg_early_init(void); 38 - extern void __init udbg_init_debug_lpar(void); 39 - extern void __init udbg_init_debug_lpar_hvsi(void); 40 - extern void __init udbg_init_pmac_realmode(void); 41 - extern void __init udbg_init_maple_realmode(void); 42 - extern void __init udbg_init_pas_realmode(void); 43 - extern void __init udbg_init_rtas_panel(void); 44 - extern void __init udbg_init_rtas_console(void); 45 - extern void __init udbg_init_debug_beat(void); 46 - extern void __init udbg_init_btext(void); 47 - extern void __init udbg_init_44x_as1(void); 48 - extern void __init udbg_init_40x_realmode(void); 49 - extern void __init udbg_init_cpm(void); 50 - extern void __init udbg_init_usbgecko(void); 51 - extern void __init udbg_init_memcons(void); 52 - extern void __init udbg_init_ehv_bc(void); 53 - extern void __init udbg_init_ps3gelic(void); 54 - extern void __init udbg_init_debug_opal_raw(void); 55 - extern void __init udbg_init_debug_opal_hvsi(void); 37 + void __init udbg_early_init(void); 38 + void __init udbg_init_debug_lpar(void); 39 + void __init udbg_init_debug_lpar_hvsi(void); 40 + void __init udbg_init_pmac_realmode(void); 41 + void __init udbg_init_maple_realmode(void); 42 + void __init udbg_init_pas_realmode(void); 43 + void __init udbg_init_rtas_panel(void); 44 + void __init udbg_init_rtas_console(void); 45 + void __init udbg_init_btext(void); 46 + void __init udbg_init_44x_as1(void); 47 + void __init udbg_init_40x_realmode(void); 48 + void __init udbg_init_cpm(void); 49 + void __init udbg_init_usbgecko(void); 50 + void __init udbg_init_memcons(void); 51 + void __init udbg_init_ehv_bc(void); 52 + void __init udbg_init_ps3gelic(void); 53 + void __init udbg_init_debug_opal_raw(void); 54 + void __init udbg_init_debug_opal_hvsi(void); 55 + void __init udbg_init_debug_16550(void); 56 56 57 57 #endif /* __KERNEL__ */ 58 58 #endif /* _ASM_POWERPC_UDBG_H */

+1

arch/powerpc/include/asm/unistd.h

··· 45 45 #define __ARCH_WANT_SYS_UTIME 46 46 #define __ARCH_WANT_SYS_NEWFSTATAT 47 47 #define __ARCH_WANT_COMPAT_STAT 48 + #define __ARCH_WANT_COMPAT_FALLOCATE 48 49 #define __ARCH_WANT_COMPAT_SYS_SENDFILE 49 50 #endif 50 51 #define __ARCH_WANT_SYS_FORK

-3

arch/powerpc/include/asm/vdso.h

··· 2 2 #ifndef _ASM_POWERPC_VDSO_H 3 3 #define _ASM_POWERPC_VDSO_H 4 4 5 - /* Default map addresses for 32bit vDSO */ 6 - #define VDSO32_MBASE 0x100000 7 - 8 5 #define VDSO_VERSION_STRING LINUX_2.6.15 9 6 10 7 #ifndef __ASSEMBLY__

+7 -1

arch/powerpc/include/asm/vdso/processor.h

··· 22 22 #endif 23 23 24 24 #ifdef CONFIG_PPC64 25 - #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) 25 + #define cpu_relax() \ 26 + asm volatile(ASM_FTR_IFCLR( \ 27 + /* Pre-POWER10 uses low ; medium priority nops */ \ 28 + "or 1,1,1 ; or 2,2,2", \ 29 + /* POWER10 onward uses pause_short (wait 2,0) */ \ 30 + PPC_WAIT(2, 0), \ 31 + %0) :: "i" (CPU_FTR_ARCH_31) : "memory") 26 32 #else 27 33 #define cpu_relax() barrier() 28 34 #endif

+1 -1

arch/powerpc/include/asm/vdso/timebase.h

··· 12 12 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit 13 13 * version below in the else case of the ifdef. 14 14 */ 15 - #if defined(__powerpc64__) && (defined(CONFIG_PPC_CELL) || defined(CONFIG_E500)) 15 + #if defined(__powerpc64__) && (defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500)) 16 16 #define mftb() ({unsigned long rval; \ 17 17 asm volatile( \ 18 18 "90: mfspr %0, %2;\n" \

-1

arch/powerpc/include/asm/xics.h

··· 159 159 extern void xics_update_irq_servers(void); 160 160 extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join); 161 161 extern void xics_mask_unknown_vec(unsigned int vec); 162 - extern irqreturn_t xics_ipi_dispatch(int cpu); 163 162 extern void xics_smp_probe(void); 164 163 extern void xics_register_ics(struct ics *ics); 165 164 extern void xics_teardown_cpu(void);

+6 -8

arch/powerpc/kernel/Makefile

··· 81 81 obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o 82 82 obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o 83 83 obj-$(CONFIG_PPC_BOOK3S_64) += mce.o mce_power.o 84 - obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o 84 + obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_64e.o 85 85 obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o 86 86 obj-$(CONFIG_PPC64) += vdso64_wrapper.o 87 87 obj-$(CONFIG_ALTIVEC) += vecemu.o ··· 100 100 obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 101 101 obj-$(CONFIG_FA_DUMP) += fadump.o 102 102 obj-$(CONFIG_PRESERVE_FA_DUMP) += fadump.o 103 - ifdef CONFIG_PPC32 104 - obj-$(CONFIG_E500) += idle_e500.o 105 - endif 103 + obj-$(CONFIG_PPC_85xx) += idle_85xx.o 106 104 obj-$(CONFIG_PPC_BOOK3S_32) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o 107 105 obj-$(CONFIG_TAU) += tau_6xx.o 108 106 obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o 109 - ifdef CONFIG_FSL_BOOKE 110 - obj-$(CONFIG_HIBERNATION) += swsusp_booke.o 107 + ifdef CONFIG_PPC_85xx 108 + obj-$(CONFIG_HIBERNATION) += swsusp_85xx.o 111 109 else 112 110 obj-$(CONFIG_HIBERNATION) += swsusp_$(BITS).o 113 111 endif 114 112 obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o 115 113 obj-$(CONFIG_MODULES) += module.o module_$(BITS).o 116 114 obj-$(CONFIG_44x) += cpu_setup_44x.o 117 - obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o 115 + obj-$(CONFIG_PPC_E500) += cpu_setup_e500.o 118 116 obj-$(CONFIG_PPC_DOORBELL) += dbell.o 119 117 obj-$(CONFIG_JUMP_LABEL) += jump_label.o 120 118 ··· 120 122 extra-$(CONFIG_PPC_BOOK3S_32) := head_book3s_32.o 121 123 extra-$(CONFIG_40x) := head_40x.o 122 124 extra-$(CONFIG_44x) := head_44x.o 123 - extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o 125 + extra-$(CONFIG_PPC_85xx) := head_85xx.o 124 126 extra-$(CONFIG_PPC_8xx) := head_8xx.o 125 127 extra-y += vmlinux.lds 126 128

+5 -5

arch/powerpc/kernel/asm-offsets.c

··· 59 59 #endif 60 60 #endif 61 61 62 - #if defined(CONFIG_PPC_FSL_BOOK3E) 62 + #if defined(CONFIG_PPC_E500) 63 63 #include "../mm/mmu_decl.h" 64 64 #endif 65 65 ··· 197 197 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened); 198 198 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled); 199 199 200 - #ifdef CONFIG_PPC_BOOK3E 200 + #ifdef CONFIG_PPC_BOOK3E_64 201 201 OFFSET(PACAPGD, paca_struct, pgd); 202 202 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd); 203 203 OFFSET(PACA_EXGEN, paca_struct, exgen); ··· 213 213 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next); 214 214 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max); 215 215 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first); 216 - #endif /* CONFIG_PPC_BOOK3E */ 216 + #endif /* CONFIG_PPC_BOOK3E_64 */ 217 217 218 218 #ifdef CONFIG_PPC_BOOK3S_64 219 219 OFFSET(PACA_EXGEN, paca_struct, exgen); ··· 248 248 #ifdef CONFIG_PPC64 249 249 OFFSET(PACA_EXIT_SAVE_R1, paca_struct, exit_save_r1); 250 250 #endif 251 - #ifdef CONFIG_PPC_BOOK3E 251 + #ifdef CONFIG_PPC_BOOK3E_64 252 252 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save); 253 253 #endif 254 254 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso); ··· 651 651 DEFINE(PGD_T_LOG2, PGD_T_LOG2); 652 652 DEFINE(PTE_T_LOG2, PTE_T_LOG2); 653 653 #endif 654 - #ifdef CONFIG_PPC_FSL_BOOK3E 654 + #ifdef CONFIG_PPC_E500 655 655 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); 656 656 OFFSET(TLBCAM_MAS0, tlbcam, MAS0); 657 657 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);

+3 -3

arch/powerpc/kernel/cpu_setup_fsl_booke.S arch/powerpc/kernel/cpu_setup_e500.S

··· 12 12 #include <asm/processor.h> 13 13 #include <asm/cputable.h> 14 14 #include <asm/ppc_asm.h> 15 - #include <asm/nohash/mmu-book3e.h> 15 + #include <asm/nohash/mmu-e500.h> 16 16 #include <asm/asm-offsets.h> 17 17 #include <asm/mpc85xx.h> 18 18 ··· 108 108 #endif /* CONFIG_PPC_E500MC */ 109 109 110 110 #ifdef CONFIG_PPC32 111 - #ifdef CONFIG_E500 111 + #ifdef CONFIG_PPC_E500 112 112 #ifndef CONFIG_PPC_E500MC 113 113 _GLOBAL(__setup_cpu_e500v1) 114 114 _GLOBAL(__setup_cpu_e500v2) ··· 156 156 mtlr r5 157 157 blr 158 158 #endif /* CONFIG_PPC_E500MC */ 159 - #endif /* CONFIG_E500 */ 159 + #endif /* CONFIG_PPC_E500 */ 160 160 #endif /* CONFIG_PPC32 */ 161 161 162 162 #ifdef CONFIG_PPC_BOOK3E_64

+1 -1

arch/powerpc/kernel/cpu_setup_power.c

··· 11 11 #include <asm/synch.h> 12 12 #include <linux/bitops.h> 13 13 #include <asm/cputable.h> 14 - #include <asm/cpu_setup_power.h> 14 + #include <asm/cpu_setup.h> 15 15 16 16 /* Disable CPU_FTR_HVMODE and return false if MSR:HV is not set */ 17 17 static bool init_hvmode_206(struct cpu_spec *t)

+29

arch/powerpc/kernel/cpu_specs.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + 3 + #ifdef CONFIG_40x 4 + #include "cpu_specs_40x.h" 5 + #endif 6 + 7 + #ifdef CONFIG_PPC_47x 8 + #include "cpu_specs_47x.h" 9 + #elif defined(CONFIG_44x) 10 + #include "cpu_specs_44x.h" 11 + #endif 12 + 13 + #ifdef CONFIG_PPC_8xx 14 + #include "cpu_specs_8xx.h" 15 + #endif 16 + 17 + #ifdef CONFIG_PPC_E500MC 18 + #include "cpu_specs_e500mc.h" 19 + #elif defined(CONFIG_PPC_85xx) 20 + #include "cpu_specs_85xx.h" 21 + #endif 22 + 23 + #ifdef CONFIG_PPC_BOOK3S_32 24 + #include "cpu_specs_book3s_32.h" 25 + #endif 26 + 27 + #ifdef CONFIG_PPC_BOOK3S_64 28 + #include "cpu_specs_book3s_64.h" 29 + #endif

+280

arch/powerpc/kernel/cpu_specs_40x.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 + */ 5 + 6 + static struct cpu_spec cpu_specs[] __initdata = { 7 + { /* STB 04xxx */ 8 + .pvr_mask = 0xffff0000, 9 + .pvr_value = 0x41810000, 10 + .cpu_name = "STB04xxx", 11 + .cpu_features = CPU_FTRS_40X, 12 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 13 + PPC_FEATURE_HAS_4xxMAC, 14 + .mmu_features = MMU_FTR_TYPE_40x, 15 + .icache_bsize = 32, 16 + .dcache_bsize = 32, 17 + .machine_check = machine_check_4xx, 18 + .platform = "ppc405", 19 + }, 20 + { /* NP405L */ 21 + .pvr_mask = 0xffff0000, 22 + .pvr_value = 0x41610000, 23 + .cpu_name = "NP405L", 24 + .cpu_features = CPU_FTRS_40X, 25 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 26 + PPC_FEATURE_HAS_4xxMAC, 27 + .mmu_features = MMU_FTR_TYPE_40x, 28 + .icache_bsize = 32, 29 + .dcache_bsize = 32, 30 + .machine_check = machine_check_4xx, 31 + .platform = "ppc405", 32 + }, 33 + { /* NP4GS3 */ 34 + .pvr_mask = 0xffff0000, 35 + .pvr_value = 0x40B10000, 36 + .cpu_name = "NP4GS3", 37 + .cpu_features = CPU_FTRS_40X, 38 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 39 + PPC_FEATURE_HAS_4xxMAC, 40 + .mmu_features = MMU_FTR_TYPE_40x, 41 + .icache_bsize = 32, 42 + .dcache_bsize = 32, 43 + .machine_check = machine_check_4xx, 44 + .platform = "ppc405", 45 + }, 46 + { /* NP405H */ 47 + .pvr_mask = 0xffff0000, 48 + .pvr_value = 0x41410000, 49 + .cpu_name = "NP405H", 50 + .cpu_features = CPU_FTRS_40X, 51 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 52 + PPC_FEATURE_HAS_4xxMAC, 53 + .mmu_features = MMU_FTR_TYPE_40x, 54 + .icache_bsize = 32, 55 + .dcache_bsize = 32, 56 + .machine_check = machine_check_4xx, 57 + .platform = "ppc405", 58 + }, 59 + { /* 405GPr */ 60 + .pvr_mask = 0xffff0000, 61 + .pvr_value = 0x50910000, 62 + .cpu_name = "405GPr", 63 + .cpu_features = CPU_FTRS_40X, 64 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 65 + PPC_FEATURE_HAS_4xxMAC, 66 + .mmu_features = MMU_FTR_TYPE_40x, 67 + .icache_bsize = 32, 68 + .dcache_bsize = 32, 69 + .machine_check = machine_check_4xx, 70 + .platform = "ppc405", 71 + }, 72 + { /* STBx25xx */ 73 + .pvr_mask = 0xffff0000, 74 + .pvr_value = 0x51510000, 75 + .cpu_name = "STBx25xx", 76 + .cpu_features = CPU_FTRS_40X, 77 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 78 + PPC_FEATURE_HAS_4xxMAC, 79 + .mmu_features = MMU_FTR_TYPE_40x, 80 + .icache_bsize = 32, 81 + .dcache_bsize = 32, 82 + .machine_check = machine_check_4xx, 83 + .platform = "ppc405", 84 + }, 85 + { /* 405LP */ 86 + .pvr_mask = 0xffff0000, 87 + .pvr_value = 0x41F10000, 88 + .cpu_name = "405LP", 89 + .cpu_features = CPU_FTRS_40X, 90 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 91 + .mmu_features = MMU_FTR_TYPE_40x, 92 + .icache_bsize = 32, 93 + .dcache_bsize = 32, 94 + .machine_check = machine_check_4xx, 95 + .platform = "ppc405", 96 + }, 97 + { /* 405EP */ 98 + .pvr_mask = 0xffff0000, 99 + .pvr_value = 0x51210000, 100 + .cpu_name = "405EP", 101 + .cpu_features = CPU_FTRS_40X, 102 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 103 + PPC_FEATURE_HAS_4xxMAC, 104 + .mmu_features = MMU_FTR_TYPE_40x, 105 + .icache_bsize = 32, 106 + .dcache_bsize = 32, 107 + .machine_check = machine_check_4xx, 108 + .platform = "ppc405", 109 + }, 110 + { /* 405EX Rev. A/B with Security */ 111 + .pvr_mask = 0xffff000f, 112 + .pvr_value = 0x12910007, 113 + .cpu_name = "405EX Rev. A/B", 114 + .cpu_features = CPU_FTRS_40X, 115 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 116 + PPC_FEATURE_HAS_4xxMAC, 117 + .mmu_features = MMU_FTR_TYPE_40x, 118 + .icache_bsize = 32, 119 + .dcache_bsize = 32, 120 + .machine_check = machine_check_4xx, 121 + .platform = "ppc405", 122 + }, 123 + { /* 405EX Rev. C without Security */ 124 + .pvr_mask = 0xffff000f, 125 + .pvr_value = 0x1291000d, 126 + .cpu_name = "405EX Rev. C", 127 + .cpu_features = CPU_FTRS_40X, 128 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 129 + PPC_FEATURE_HAS_4xxMAC, 130 + .mmu_features = MMU_FTR_TYPE_40x, 131 + .icache_bsize = 32, 132 + .dcache_bsize = 32, 133 + .machine_check = machine_check_4xx, 134 + .platform = "ppc405", 135 + }, 136 + { /* 405EX Rev. C with Security */ 137 + .pvr_mask = 0xffff000f, 138 + .pvr_value = 0x1291000f, 139 + .cpu_name = "405EX Rev. C", 140 + .cpu_features = CPU_FTRS_40X, 141 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 142 + PPC_FEATURE_HAS_4xxMAC, 143 + .mmu_features = MMU_FTR_TYPE_40x, 144 + .icache_bsize = 32, 145 + .dcache_bsize = 32, 146 + .machine_check = machine_check_4xx, 147 + .platform = "ppc405", 148 + }, 149 + { /* 405EX Rev. D without Security */ 150 + .pvr_mask = 0xffff000f, 151 + .pvr_value = 0x12910003, 152 + .cpu_name = "405EX Rev. D", 153 + .cpu_features = CPU_FTRS_40X, 154 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 155 + PPC_FEATURE_HAS_4xxMAC, 156 + .mmu_features = MMU_FTR_TYPE_40x, 157 + .icache_bsize = 32, 158 + .dcache_bsize = 32, 159 + .machine_check = machine_check_4xx, 160 + .platform = "ppc405", 161 + }, 162 + { /* 405EX Rev. D with Security */ 163 + .pvr_mask = 0xffff000f, 164 + .pvr_value = 0x12910005, 165 + .cpu_name = "405EX Rev. D", 166 + .cpu_features = CPU_FTRS_40X, 167 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 168 + PPC_FEATURE_HAS_4xxMAC, 169 + .mmu_features = MMU_FTR_TYPE_40x, 170 + .icache_bsize = 32, 171 + .dcache_bsize = 32, 172 + .machine_check = machine_check_4xx, 173 + .platform = "ppc405", 174 + }, 175 + { /* 405EXr Rev. A/B without Security */ 176 + .pvr_mask = 0xffff000f, 177 + .pvr_value = 0x12910001, 178 + .cpu_name = "405EXr Rev. A/B", 179 + .cpu_features = CPU_FTRS_40X, 180 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 181 + PPC_FEATURE_HAS_4xxMAC, 182 + .mmu_features = MMU_FTR_TYPE_40x, 183 + .icache_bsize = 32, 184 + .dcache_bsize = 32, 185 + .machine_check = machine_check_4xx, 186 + .platform = "ppc405", 187 + }, 188 + { /* 405EXr Rev. C without Security */ 189 + .pvr_mask = 0xffff000f, 190 + .pvr_value = 0x12910009, 191 + .cpu_name = "405EXr Rev. C", 192 + .cpu_features = CPU_FTRS_40X, 193 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 194 + PPC_FEATURE_HAS_4xxMAC, 195 + .mmu_features = MMU_FTR_TYPE_40x, 196 + .icache_bsize = 32, 197 + .dcache_bsize = 32, 198 + .machine_check = machine_check_4xx, 199 + .platform = "ppc405", 200 + }, 201 + { /* 405EXr Rev. C with Security */ 202 + .pvr_mask = 0xffff000f, 203 + .pvr_value = 0x1291000b, 204 + .cpu_name = "405EXr Rev. C", 205 + .cpu_features = CPU_FTRS_40X, 206 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 207 + PPC_FEATURE_HAS_4xxMAC, 208 + .mmu_features = MMU_FTR_TYPE_40x, 209 + .icache_bsize = 32, 210 + .dcache_bsize = 32, 211 + .machine_check = machine_check_4xx, 212 + .platform = "ppc405", 213 + }, 214 + { /* 405EXr Rev. D without Security */ 215 + .pvr_mask = 0xffff000f, 216 + .pvr_value = 0x12910000, 217 + .cpu_name = "405EXr Rev. D", 218 + .cpu_features = CPU_FTRS_40X, 219 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 220 + PPC_FEATURE_HAS_4xxMAC, 221 + .mmu_features = MMU_FTR_TYPE_40x, 222 + .icache_bsize = 32, 223 + .dcache_bsize = 32, 224 + .machine_check = machine_check_4xx, 225 + .platform = "ppc405", 226 + }, 227 + { /* 405EXr Rev. D with Security */ 228 + .pvr_mask = 0xffff000f, 229 + .pvr_value = 0x12910002, 230 + .cpu_name = "405EXr Rev. D", 231 + .cpu_features = CPU_FTRS_40X, 232 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 233 + PPC_FEATURE_HAS_4xxMAC, 234 + .mmu_features = MMU_FTR_TYPE_40x, 235 + .icache_bsize = 32, 236 + .dcache_bsize = 32, 237 + .machine_check = machine_check_4xx, 238 + .platform = "ppc405", 239 + }, 240 + { 241 + /* 405EZ */ 242 + .pvr_mask = 0xffff0000, 243 + .pvr_value = 0x41510000, 244 + .cpu_name = "405EZ", 245 + .cpu_features = CPU_FTRS_40X, 246 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 247 + PPC_FEATURE_HAS_4xxMAC, 248 + .mmu_features = MMU_FTR_TYPE_40x, 249 + .icache_bsize = 32, 250 + .dcache_bsize = 32, 251 + .machine_check = machine_check_4xx, 252 + .platform = "ppc405", 253 + }, 254 + { /* APM8018X */ 255 + .pvr_mask = 0xffff0000, 256 + .pvr_value = 0x7ff11432, 257 + .cpu_name = "APM8018X", 258 + .cpu_features = CPU_FTRS_40X, 259 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 260 + PPC_FEATURE_HAS_4xxMAC, 261 + .mmu_features = MMU_FTR_TYPE_40x, 262 + .icache_bsize = 32, 263 + .dcache_bsize = 32, 264 + .machine_check = machine_check_4xx, 265 + .platform = "ppc405", 266 + }, 267 + { /* default match */ 268 + .pvr_mask = 0x00000000, 269 + .pvr_value = 0x00000000, 270 + .cpu_name = "(generic 40x PPC)", 271 + .cpu_features = CPU_FTRS_40X, 272 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | 273 + PPC_FEATURE_HAS_4xxMAC, 274 + .mmu_features = MMU_FTR_TYPE_40x, 275 + .icache_bsize = 32, 276 + .dcache_bsize = 32, 277 + .machine_check = machine_check_4xx, 278 + .platform = "ppc405", 279 + } 280 + };

+304

arch/powerpc/kernel/cpu_specs_44x.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 + */ 5 + 6 + #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 7 + PPC_FEATURE_BOOKE) 8 + 9 + static struct cpu_spec cpu_specs[] __initdata = { 10 + { 11 + .pvr_mask = 0xf0000fff, 12 + .pvr_value = 0x40000850, 13 + .cpu_name = "440GR Rev. A", 14 + .cpu_features = CPU_FTRS_44X, 15 + .cpu_user_features = COMMON_USER_BOOKE, 16 + .mmu_features = MMU_FTR_TYPE_44x, 17 + .icache_bsize = 32, 18 + .dcache_bsize = 32, 19 + .machine_check = machine_check_4xx, 20 + .platform = "ppc440", 21 + }, 22 + { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */ 23 + .pvr_mask = 0xf0000fff, 24 + .pvr_value = 0x40000858, 25 + .cpu_name = "440EP Rev. A", 26 + .cpu_features = CPU_FTRS_44X, 27 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 28 + .mmu_features = MMU_FTR_TYPE_44x, 29 + .icache_bsize = 32, 30 + .dcache_bsize = 32, 31 + .cpu_setup = __setup_cpu_440ep, 32 + .machine_check = machine_check_4xx, 33 + .platform = "ppc440", 34 + }, 35 + { 36 + .pvr_mask = 0xf0000fff, 37 + .pvr_value = 0x400008d3, 38 + .cpu_name = "440GR Rev. B", 39 + .cpu_features = CPU_FTRS_44X, 40 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 41 + .mmu_features = MMU_FTR_TYPE_44x, 42 + .icache_bsize = 32, 43 + .dcache_bsize = 32, 44 + .machine_check = machine_check_4xx, 45 + .platform = "ppc440", 46 + }, 47 + { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */ 48 + .pvr_mask = 0xf0000ff7, 49 + .pvr_value = 0x400008d4, 50 + .cpu_name = "440EP Rev. C", 51 + .cpu_features = CPU_FTRS_44X, 52 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 53 + .mmu_features = MMU_FTR_TYPE_44x, 54 + .icache_bsize = 32, 55 + .dcache_bsize = 32, 56 + .cpu_setup = __setup_cpu_440ep, 57 + .machine_check = machine_check_4xx, 58 + .platform = "ppc440", 59 + }, 60 + { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */ 61 + .pvr_mask = 0xf0000fff, 62 + .pvr_value = 0x400008db, 63 + .cpu_name = "440EP Rev. B", 64 + .cpu_features = CPU_FTRS_44X, 65 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 66 + .mmu_features = MMU_FTR_TYPE_44x, 67 + .icache_bsize = 32, 68 + .dcache_bsize = 32, 69 + .cpu_setup = __setup_cpu_440ep, 70 + .machine_check = machine_check_4xx, 71 + .platform = "ppc440", 72 + }, 73 + { /* 440GRX */ 74 + .pvr_mask = 0xf0000ffb, 75 + .pvr_value = 0x200008D0, 76 + .cpu_name = "440GRX", 77 + .cpu_features = CPU_FTRS_44X, 78 + .cpu_user_features = COMMON_USER_BOOKE, 79 + .mmu_features = MMU_FTR_TYPE_44x, 80 + .icache_bsize = 32, 81 + .dcache_bsize = 32, 82 + .cpu_setup = __setup_cpu_440grx, 83 + .machine_check = machine_check_440A, 84 + .platform = "ppc440", 85 + }, 86 + { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */ 87 + .pvr_mask = 0xf0000ffb, 88 + .pvr_value = 0x200008D8, 89 + .cpu_name = "440EPX", 90 + .cpu_features = CPU_FTRS_44X, 91 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 92 + .mmu_features = MMU_FTR_TYPE_44x, 93 + .icache_bsize = 32, 94 + .dcache_bsize = 32, 95 + .cpu_setup = __setup_cpu_440epx, 96 + .machine_check = machine_check_440A, 97 + .platform = "ppc440", 98 + }, 99 + { /* 440GP Rev. B */ 100 + .pvr_mask = 0xf0000fff, 101 + .pvr_value = 0x40000440, 102 + .cpu_name = "440GP Rev. B", 103 + .cpu_features = CPU_FTRS_44X, 104 + .cpu_user_features = COMMON_USER_BOOKE, 105 + .mmu_features = MMU_FTR_TYPE_44x, 106 + .icache_bsize = 32, 107 + .dcache_bsize = 32, 108 + .machine_check = machine_check_4xx, 109 + .platform = "ppc440gp", 110 + }, 111 + { /* 440GP Rev. C */ 112 + .pvr_mask = 0xf0000fff, 113 + .pvr_value = 0x40000481, 114 + .cpu_name = "440GP Rev. C", 115 + .cpu_features = CPU_FTRS_44X, 116 + .cpu_user_features = COMMON_USER_BOOKE, 117 + .mmu_features = MMU_FTR_TYPE_44x, 118 + .icache_bsize = 32, 119 + .dcache_bsize = 32, 120 + .machine_check = machine_check_4xx, 121 + .platform = "ppc440gp", 122 + }, 123 + { /* 440GX Rev. A */ 124 + .pvr_mask = 0xf0000fff, 125 + .pvr_value = 0x50000850, 126 + .cpu_name = "440GX Rev. A", 127 + .cpu_features = CPU_FTRS_44X, 128 + .cpu_user_features = COMMON_USER_BOOKE, 129 + .mmu_features = MMU_FTR_TYPE_44x, 130 + .icache_bsize = 32, 131 + .dcache_bsize = 32, 132 + .cpu_setup = __setup_cpu_440gx, 133 + .machine_check = machine_check_440A, 134 + .platform = "ppc440", 135 + }, 136 + { /* 440GX Rev. B */ 137 + .pvr_mask = 0xf0000fff, 138 + .pvr_value = 0x50000851, 139 + .cpu_name = "440GX Rev. B", 140 + .cpu_features = CPU_FTRS_44X, 141 + .cpu_user_features = COMMON_USER_BOOKE, 142 + .mmu_features = MMU_FTR_TYPE_44x, 143 + .icache_bsize = 32, 144 + .dcache_bsize = 32, 145 + .cpu_setup = __setup_cpu_440gx, 146 + .machine_check = machine_check_440A, 147 + .platform = "ppc440", 148 + }, 149 + { /* 440GX Rev. C */ 150 + .pvr_mask = 0xf0000fff, 151 + .pvr_value = 0x50000892, 152 + .cpu_name = "440GX Rev. C", 153 + .cpu_features = CPU_FTRS_44X, 154 + .cpu_user_features = COMMON_USER_BOOKE, 155 + .mmu_features = MMU_FTR_TYPE_44x, 156 + .icache_bsize = 32, 157 + .dcache_bsize = 32, 158 + .cpu_setup = __setup_cpu_440gx, 159 + .machine_check = machine_check_440A, 160 + .platform = "ppc440", 161 + }, 162 + { /* 440GX Rev. F */ 163 + .pvr_mask = 0xf0000fff, 164 + .pvr_value = 0x50000894, 165 + .cpu_name = "440GX Rev. F", 166 + .cpu_features = CPU_FTRS_44X, 167 + .cpu_user_features = COMMON_USER_BOOKE, 168 + .mmu_features = MMU_FTR_TYPE_44x, 169 + .icache_bsize = 32, 170 + .dcache_bsize = 32, 171 + .cpu_setup = __setup_cpu_440gx, 172 + .machine_check = machine_check_440A, 173 + .platform = "ppc440", 174 + }, 175 + { /* 440SP Rev. A */ 176 + .pvr_mask = 0xfff00fff, 177 + .pvr_value = 0x53200891, 178 + .cpu_name = "440SP Rev. A", 179 + .cpu_features = CPU_FTRS_44X, 180 + .cpu_user_features = COMMON_USER_BOOKE, 181 + .mmu_features = MMU_FTR_TYPE_44x, 182 + .icache_bsize = 32, 183 + .dcache_bsize = 32, 184 + .machine_check = machine_check_4xx, 185 + .platform = "ppc440", 186 + }, 187 + { /* 440SPe Rev. A */ 188 + .pvr_mask = 0xfff00fff, 189 + .pvr_value = 0x53400890, 190 + .cpu_name = "440SPe Rev. A", 191 + .cpu_features = CPU_FTRS_44X, 192 + .cpu_user_features = COMMON_USER_BOOKE, 193 + .mmu_features = MMU_FTR_TYPE_44x, 194 + .icache_bsize = 32, 195 + .dcache_bsize = 32, 196 + .cpu_setup = __setup_cpu_440spe, 197 + .machine_check = machine_check_440A, 198 + .platform = "ppc440", 199 + }, 200 + { /* 440SPe Rev. B */ 201 + .pvr_mask = 0xfff00fff, 202 + .pvr_value = 0x53400891, 203 + .cpu_name = "440SPe Rev. B", 204 + .cpu_features = CPU_FTRS_44X, 205 + .cpu_user_features = COMMON_USER_BOOKE, 206 + .mmu_features = MMU_FTR_TYPE_44x, 207 + .icache_bsize = 32, 208 + .dcache_bsize = 32, 209 + .cpu_setup = __setup_cpu_440spe, 210 + .machine_check = machine_check_440A, 211 + .platform = "ppc440", 212 + }, 213 + { /* 460EX */ 214 + .pvr_mask = 0xffff0006, 215 + .pvr_value = 0x13020002, 216 + .cpu_name = "460EX", 217 + .cpu_features = CPU_FTRS_440x6, 218 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 219 + .mmu_features = MMU_FTR_TYPE_44x, 220 + .icache_bsize = 32, 221 + .dcache_bsize = 32, 222 + .cpu_setup = __setup_cpu_460ex, 223 + .machine_check = machine_check_440A, 224 + .platform = "ppc440", 225 + }, 226 + { /* 460EX Rev B */ 227 + .pvr_mask = 0xffff0007, 228 + .pvr_value = 0x13020004, 229 + .cpu_name = "460EX Rev. B", 230 + .cpu_features = CPU_FTRS_440x6, 231 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 232 + .mmu_features = MMU_FTR_TYPE_44x, 233 + .icache_bsize = 32, 234 + .dcache_bsize = 32, 235 + .cpu_setup = __setup_cpu_460ex, 236 + .machine_check = machine_check_440A, 237 + .platform = "ppc440", 238 + }, 239 + { /* 460GT */ 240 + .pvr_mask = 0xffff0006, 241 + .pvr_value = 0x13020000, 242 + .cpu_name = "460GT", 243 + .cpu_features = CPU_FTRS_440x6, 244 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 245 + .mmu_features = MMU_FTR_TYPE_44x, 246 + .icache_bsize = 32, 247 + .dcache_bsize = 32, 248 + .cpu_setup = __setup_cpu_460gt, 249 + .machine_check = machine_check_440A, 250 + .platform = "ppc440", 251 + }, 252 + { /* 460GT Rev B */ 253 + .pvr_mask = 0xffff0007, 254 + .pvr_value = 0x13020005, 255 + .cpu_name = "460GT Rev. B", 256 + .cpu_features = CPU_FTRS_440x6, 257 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 258 + .mmu_features = MMU_FTR_TYPE_44x, 259 + .icache_bsize = 32, 260 + .dcache_bsize = 32, 261 + .cpu_setup = __setup_cpu_460gt, 262 + .machine_check = machine_check_440A, 263 + .platform = "ppc440", 264 + }, 265 + { /* 460SX */ 266 + .pvr_mask = 0xffffff00, 267 + .pvr_value = 0x13541800, 268 + .cpu_name = "460SX", 269 + .cpu_features = CPU_FTRS_44X, 270 + .cpu_user_features = COMMON_USER_BOOKE, 271 + .mmu_features = MMU_FTR_TYPE_44x, 272 + .icache_bsize = 32, 273 + .dcache_bsize = 32, 274 + .cpu_setup = __setup_cpu_460sx, 275 + .machine_check = machine_check_440A, 276 + .platform = "ppc440", 277 + }, 278 + { /* 464 in APM821xx */ 279 + .pvr_mask = 0xfffffff0, 280 + .pvr_value = 0x12C41C80, 281 + .cpu_name = "APM821XX", 282 + .cpu_features = CPU_FTRS_44X, 283 + .cpu_user_features = COMMON_USER_BOOKE | 284 + PPC_FEATURE_HAS_FPU, 285 + .mmu_features = MMU_FTR_TYPE_44x, 286 + .icache_bsize = 32, 287 + .dcache_bsize = 32, 288 + .cpu_setup = __setup_cpu_apm821xx, 289 + .machine_check = machine_check_440A, 290 + .platform = "ppc440", 291 + }, 292 + { /* default match */ 293 + .pvr_mask = 0x00000000, 294 + .pvr_value = 0x00000000, 295 + .cpu_name = "(generic 44x PPC)", 296 + .cpu_features = CPU_FTRS_44X, 297 + .cpu_user_features = COMMON_USER_BOOKE, 298 + .mmu_features = MMU_FTR_TYPE_44x, 299 + .icache_bsize = 32, 300 + .dcache_bsize = 32, 301 + .machine_check = machine_check_4xx, 302 + .platform = "ppc440", 303 + } 304 + };

+74

arch/powerpc/kernel/cpu_specs_47x.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 + */ 5 + 6 + #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 7 + PPC_FEATURE_BOOKE) 8 + 9 + static struct cpu_spec cpu_specs[] __initdata = { 10 + { /* 476 DD2 core */ 11 + .pvr_mask = 0xffffffff, 12 + .pvr_value = 0x11a52080, 13 + .cpu_name = "476", 14 + .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, 15 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 16 + .mmu_features = MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | 17 + MMU_FTR_LOCK_BCAST_INVAL, 18 + .icache_bsize = 32, 19 + .dcache_bsize = 128, 20 + .machine_check = machine_check_47x, 21 + .platform = "ppc470", 22 + }, 23 + { /* 476fpe */ 24 + .pvr_mask = 0xffff0000, 25 + .pvr_value = 0x7ff50000, 26 + .cpu_name = "476fpe", 27 + .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, 28 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 29 + .mmu_features = MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | 30 + MMU_FTR_LOCK_BCAST_INVAL, 31 + .icache_bsize = 32, 32 + .dcache_bsize = 128, 33 + .machine_check = machine_check_47x, 34 + .platform = "ppc470", 35 + }, 36 + { /* 476 iss */ 37 + .pvr_mask = 0xffff0000, 38 + .pvr_value = 0x00050000, 39 + .cpu_name = "476", 40 + .cpu_features = CPU_FTRS_47X, 41 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 42 + .mmu_features = MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | 43 + MMU_FTR_LOCK_BCAST_INVAL, 44 + .icache_bsize = 32, 45 + .dcache_bsize = 128, 46 + .machine_check = machine_check_47x, 47 + .platform = "ppc470", 48 + }, 49 + { /* 476 others */ 50 + .pvr_mask = 0xffff0000, 51 + .pvr_value = 0x11a50000, 52 + .cpu_name = "476", 53 + .cpu_features = CPU_FTRS_47X, 54 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 55 + .mmu_features = MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | 56 + MMU_FTR_LOCK_BCAST_INVAL, 57 + .icache_bsize = 32, 58 + .dcache_bsize = 128, 59 + .machine_check = machine_check_47x, 60 + .platform = "ppc470", 61 + }, 62 + { /* default match */ 63 + .pvr_mask = 0x00000000, 64 + .pvr_value = 0x00000000, 65 + .cpu_name = "(generic 47x PPC)", 66 + .cpu_features = CPU_FTRS_47X, 67 + .cpu_user_features = COMMON_USER_BOOKE, 68 + .mmu_features = MMU_FTR_TYPE_47x, 69 + .icache_bsize = 32, 70 + .dcache_bsize = 128, 71 + .machine_check = machine_check_47x, 72 + .platform = "ppc470", 73 + } 74 + };

+57

arch/powerpc/kernel/cpu_specs_85xx.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 + */ 5 + 6 + #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 7 + PPC_FEATURE_BOOKE) 8 + 9 + static struct cpu_spec cpu_specs[] __initdata = { 10 + { /* e500 */ 11 + .pvr_mask = 0xffff0000, 12 + .pvr_value = 0x80200000, 13 + .cpu_name = "e500", 14 + .cpu_features = CPU_FTRS_E500, 15 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_SPE_COMP | 16 + PPC_FEATURE_HAS_EFP_SINGLE_COMP, 17 + .cpu_user_features2 = PPC_FEATURE2_ISEL, 18 + .mmu_features = MMU_FTR_TYPE_FSL_E, 19 + .icache_bsize = 32, 20 + .dcache_bsize = 32, 21 + .num_pmcs = 4, 22 + .cpu_setup = __setup_cpu_e500v1, 23 + .machine_check = machine_check_e500, 24 + .platform = "ppc8540", 25 + }, 26 + { /* e500v2 */ 27 + .pvr_mask = 0xffff0000, 28 + .pvr_value = 0x80210000, 29 + .cpu_name = "e500v2", 30 + .cpu_features = CPU_FTRS_E500_2, 31 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_SPE_COMP | 32 + PPC_FEATURE_HAS_EFP_SINGLE_COMP | 33 + PPC_FEATURE_HAS_EFP_DOUBLE_COMP, 34 + .cpu_user_features2 = PPC_FEATURE2_ISEL, 35 + .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS, 36 + .icache_bsize = 32, 37 + .dcache_bsize = 32, 38 + .num_pmcs = 4, 39 + .cpu_setup = __setup_cpu_e500v2, 40 + .machine_check = machine_check_e500, 41 + .platform = "ppc8548", 42 + .cpu_down_flush = cpu_down_flush_e500v2, 43 + }, 44 + { /* default match */ 45 + .pvr_mask = 0x00000000, 46 + .pvr_value = 0x00000000, 47 + .cpu_name = "(generic E500 PPC)", 48 + .cpu_features = CPU_FTRS_E500, 49 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_SPE_COMP | 50 + PPC_FEATURE_HAS_EFP_SINGLE_COMP, 51 + .mmu_features = MMU_FTR_TYPE_FSL_E, 52 + .icache_bsize = 32, 53 + .dcache_bsize = 32, 54 + .machine_check = machine_check_e500, 55 + .platform = "powerpc", 56 + } 57 + };

+23

arch/powerpc/kernel/cpu_specs_8xx.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 + */ 5 + 6 + static struct cpu_spec cpu_specs[] __initdata = { 7 + { /* 8xx */ 8 + .pvr_mask = 0xffff0000, 9 + .pvr_value = PVR_8xx, 10 + .cpu_name = "8xx", 11 + /* 12 + * CPU_FTR_MAYBE_CAN_DOZE is possible, 13 + * if the 8xx code is there.... 14 + */ 15 + .cpu_features = CPU_FTRS_8XX, 16 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 17 + .mmu_features = MMU_FTR_TYPE_8xx, 18 + .icache_bsize = 16, 19 + .dcache_bsize = 16, 20 + .machine_check = machine_check_8xx, 21 + .platform = "ppc823", 22 + }, 23 + };

+605

arch/powerpc/kernel/cpu_specs_book3s_32.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 + */ 5 + 6 + #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 7 + PPC_FEATURE_HAS_MMU) 8 + 9 + static struct cpu_spec cpu_specs[] __initdata = { 10 + #ifdef CONFIG_PPC_BOOK3S_603 11 + { /* 603 */ 12 + .pvr_mask = 0xffff0000, 13 + .pvr_value = 0x00030000, 14 + .cpu_name = "603", 15 + .cpu_features = CPU_FTRS_603, 16 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 17 + .mmu_features = 0, 18 + .icache_bsize = 32, 19 + .dcache_bsize = 32, 20 + .cpu_setup = __setup_cpu_603, 21 + .machine_check = machine_check_generic, 22 + .platform = "ppc603", 23 + }, 24 + { /* 603e */ 25 + .pvr_mask = 0xffff0000, 26 + .pvr_value = 0x00060000, 27 + .cpu_name = "603e", 28 + .cpu_features = CPU_FTRS_603, 29 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 30 + .mmu_features = 0, 31 + .icache_bsize = 32, 32 + .dcache_bsize = 32, 33 + .cpu_setup = __setup_cpu_603, 34 + .machine_check = machine_check_generic, 35 + .platform = "ppc603", 36 + }, 37 + { /* 603ev */ 38 + .pvr_mask = 0xffff0000, 39 + .pvr_value = 0x00070000, 40 + .cpu_name = "603ev", 41 + .cpu_features = CPU_FTRS_603, 42 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 43 + .mmu_features = 0, 44 + .icache_bsize = 32, 45 + .dcache_bsize = 32, 46 + .cpu_setup = __setup_cpu_603, 47 + .machine_check = machine_check_generic, 48 + .platform = "ppc603", 49 + }, 50 + { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 51 + .pvr_mask = 0x7fff0000, 52 + .pvr_value = 0x00810000, 53 + .cpu_name = "82xx", 54 + .cpu_features = CPU_FTRS_82XX, 55 + .cpu_user_features = COMMON_USER, 56 + .mmu_features = 0, 57 + .icache_bsize = 32, 58 + .dcache_bsize = 32, 59 + .cpu_setup = __setup_cpu_603, 60 + .machine_check = machine_check_generic, 61 + .platform = "ppc603", 62 + }, 63 + { /* All G2_LE (603e core, plus some) have the same pvr */ 64 + .pvr_mask = 0x7fff0000, 65 + .pvr_value = 0x00820000, 66 + .cpu_name = "G2_LE", 67 + .cpu_features = CPU_FTRS_G2_LE, 68 + .cpu_user_features = COMMON_USER, 69 + .mmu_features = MMU_FTR_USE_HIGH_BATS, 70 + .icache_bsize = 32, 71 + .dcache_bsize = 32, 72 + .cpu_setup = __setup_cpu_603, 73 + .machine_check = machine_check_generic, 74 + .platform = "ppc603", 75 + }, 76 + #ifdef CONFIG_PPC_83xx 77 + { /* e300c1 (a 603e core, plus some) on 83xx */ 78 + .pvr_mask = 0x7fff0000, 79 + .pvr_value = 0x00830000, 80 + .cpu_name = "e300c1", 81 + .cpu_features = CPU_FTRS_E300, 82 + .cpu_user_features = COMMON_USER, 83 + .mmu_features = MMU_FTR_USE_HIGH_BATS, 84 + .icache_bsize = 32, 85 + .dcache_bsize = 32, 86 + .cpu_setup = __setup_cpu_603, 87 + .machine_check = machine_check_83xx, 88 + .platform = "ppc603", 89 + }, 90 + { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */ 91 + .pvr_mask = 0x7fff0000, 92 + .pvr_value = 0x00840000, 93 + .cpu_name = "e300c2", 94 + .cpu_features = CPU_FTRS_E300C2, 95 + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 96 + .mmu_features = MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU, 97 + .icache_bsize = 32, 98 + .dcache_bsize = 32, 99 + .cpu_setup = __setup_cpu_603, 100 + .machine_check = machine_check_83xx, 101 + .platform = "ppc603", 102 + }, 103 + { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */ 104 + .pvr_mask = 0x7fff0000, 105 + .pvr_value = 0x00850000, 106 + .cpu_name = "e300c3", 107 + .cpu_features = CPU_FTRS_E300, 108 + .cpu_user_features = COMMON_USER, 109 + .mmu_features = MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU, 110 + .icache_bsize = 32, 111 + .dcache_bsize = 32, 112 + .cpu_setup = __setup_cpu_603, 113 + .machine_check = machine_check_83xx, 114 + .num_pmcs = 4, 115 + .platform = "ppc603", 116 + }, 117 + { /* e300c4 (e300c1, plus one IU) */ 118 + .pvr_mask = 0x7fff0000, 119 + .pvr_value = 0x00860000, 120 + .cpu_name = "e300c4", 121 + .cpu_features = CPU_FTRS_E300, 122 + .cpu_user_features = COMMON_USER, 123 + .mmu_features = MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU, 124 + .icache_bsize = 32, 125 + .dcache_bsize = 32, 126 + .cpu_setup = __setup_cpu_603, 127 + .machine_check = machine_check_83xx, 128 + .num_pmcs = 4, 129 + .platform = "ppc603", 130 + }, 131 + #endif 132 + #endif /* CONFIG_PPC_BOOK3S_603 */ 133 + #ifdef CONFIG_PPC_BOOK3S_604 134 + { /* 604 */ 135 + .pvr_mask = 0xffff0000, 136 + .pvr_value = 0x00040000, 137 + .cpu_name = "604", 138 + .cpu_features = CPU_FTRS_604, 139 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 140 + .mmu_features = MMU_FTR_HPTE_TABLE, 141 + .icache_bsize = 32, 142 + .dcache_bsize = 32, 143 + .num_pmcs = 2, 144 + .cpu_setup = __setup_cpu_604, 145 + .machine_check = machine_check_generic, 146 + .platform = "ppc604", 147 + }, 148 + { /* 604e */ 149 + .pvr_mask = 0xfffff000, 150 + .pvr_value = 0x00090000, 151 + .cpu_name = "604e", 152 + .cpu_features = CPU_FTRS_604, 153 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 154 + .mmu_features = MMU_FTR_HPTE_TABLE, 155 + .icache_bsize = 32, 156 + .dcache_bsize = 32, 157 + .num_pmcs = 4, 158 + .cpu_setup = __setup_cpu_604, 159 + .machine_check = machine_check_generic, 160 + .platform = "ppc604", 161 + }, 162 + { /* 604r */ 163 + .pvr_mask = 0xffff0000, 164 + .pvr_value = 0x00090000, 165 + .cpu_name = "604r", 166 + .cpu_features = CPU_FTRS_604, 167 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 168 + .mmu_features = MMU_FTR_HPTE_TABLE, 169 + .icache_bsize = 32, 170 + .dcache_bsize = 32, 171 + .num_pmcs = 4, 172 + .cpu_setup = __setup_cpu_604, 173 + .machine_check = machine_check_generic, 174 + .platform = "ppc604", 175 + }, 176 + { /* 604ev */ 177 + .pvr_mask = 0xffff0000, 178 + .pvr_value = 0x000a0000, 179 + .cpu_name = "604ev", 180 + .cpu_features = CPU_FTRS_604, 181 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 182 + .mmu_features = MMU_FTR_HPTE_TABLE, 183 + .icache_bsize = 32, 184 + .dcache_bsize = 32, 185 + .num_pmcs = 4, 186 + .cpu_setup = __setup_cpu_604, 187 + .machine_check = machine_check_generic, 188 + .platform = "ppc604", 189 + }, 190 + { /* 740/750 (0x4202, don't support TAU ?) */ 191 + .pvr_mask = 0xffffffff, 192 + .pvr_value = 0x00084202, 193 + .cpu_name = "740/750", 194 + .cpu_features = CPU_FTRS_740_NOTAU, 195 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 196 + .mmu_features = MMU_FTR_HPTE_TABLE, 197 + .icache_bsize = 32, 198 + .dcache_bsize = 32, 199 + .num_pmcs = 4, 200 + .cpu_setup = __setup_cpu_750, 201 + .machine_check = machine_check_generic, 202 + .platform = "ppc750", 203 + }, 204 + { /* 750CX (80100 and 8010x?) */ 205 + .pvr_mask = 0xfffffff0, 206 + .pvr_value = 0x00080100, 207 + .cpu_name = "750CX", 208 + .cpu_features = CPU_FTRS_750, 209 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 210 + .mmu_features = MMU_FTR_HPTE_TABLE, 211 + .icache_bsize = 32, 212 + .dcache_bsize = 32, 213 + .num_pmcs = 4, 214 + .cpu_setup = __setup_cpu_750cx, 215 + .machine_check = machine_check_generic, 216 + .platform = "ppc750", 217 + }, 218 + { /* 750CX (82201 and 82202) */ 219 + .pvr_mask = 0xfffffff0, 220 + .pvr_value = 0x00082200, 221 + .cpu_name = "750CX", 222 + .cpu_features = CPU_FTRS_750, 223 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 224 + .mmu_features = MMU_FTR_HPTE_TABLE, 225 + .icache_bsize = 32, 226 + .dcache_bsize = 32, 227 + .num_pmcs = 4, 228 + .pmc_type = PPC_PMC_IBM, 229 + .cpu_setup = __setup_cpu_750cx, 230 + .machine_check = machine_check_generic, 231 + .platform = "ppc750", 232 + }, 233 + { /* 750CXe (82214) */ 234 + .pvr_mask = 0xfffffff0, 235 + .pvr_value = 0x00082210, 236 + .cpu_name = "750CXe", 237 + .cpu_features = CPU_FTRS_750, 238 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 239 + .mmu_features = MMU_FTR_HPTE_TABLE, 240 + .icache_bsize = 32, 241 + .dcache_bsize = 32, 242 + .num_pmcs = 4, 243 + .pmc_type = PPC_PMC_IBM, 244 + .cpu_setup = __setup_cpu_750cx, 245 + .machine_check = machine_check_generic, 246 + .platform = "ppc750", 247 + }, 248 + { /* 750CXe "Gekko" (83214) */ 249 + .pvr_mask = 0xffffffff, 250 + .pvr_value = 0x00083214, 251 + .cpu_name = "750CXe", 252 + .cpu_features = CPU_FTRS_750, 253 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 254 + .mmu_features = MMU_FTR_HPTE_TABLE, 255 + .icache_bsize = 32, 256 + .dcache_bsize = 32, 257 + .num_pmcs = 4, 258 + .pmc_type = PPC_PMC_IBM, 259 + .cpu_setup = __setup_cpu_750cx, 260 + .machine_check = machine_check_generic, 261 + .platform = "ppc750", 262 + }, 263 + { /* 750CL (and "Broadway") */ 264 + .pvr_mask = 0xfffff0e0, 265 + .pvr_value = 0x00087000, 266 + .cpu_name = "750CL", 267 + .cpu_features = CPU_FTRS_750CL, 268 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 269 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 270 + .icache_bsize = 32, 271 + .dcache_bsize = 32, 272 + .num_pmcs = 4, 273 + .pmc_type = PPC_PMC_IBM, 274 + .cpu_setup = __setup_cpu_750, 275 + .machine_check = machine_check_generic, 276 + .platform = "ppc750", 277 + }, 278 + { /* 745/755 */ 279 + .pvr_mask = 0xfffff000, 280 + .pvr_value = 0x00083000, 281 + .cpu_name = "745/755", 282 + .cpu_features = CPU_FTRS_750, 283 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 284 + .mmu_features = MMU_FTR_HPTE_TABLE, 285 + .icache_bsize = 32, 286 + .dcache_bsize = 32, 287 + .num_pmcs = 4, 288 + .pmc_type = PPC_PMC_IBM, 289 + .cpu_setup = __setup_cpu_750, 290 + .machine_check = machine_check_generic, 291 + .platform = "ppc750", 292 + }, 293 + { /* 750FX rev 1.x */ 294 + .pvr_mask = 0xffffff00, 295 + .pvr_value = 0x70000100, 296 + .cpu_name = "750FX", 297 + .cpu_features = CPU_FTRS_750FX1, 298 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 299 + .mmu_features = MMU_FTR_HPTE_TABLE, 300 + .icache_bsize = 32, 301 + .dcache_bsize = 32, 302 + .num_pmcs = 4, 303 + .pmc_type = PPC_PMC_IBM, 304 + .cpu_setup = __setup_cpu_750, 305 + .machine_check = machine_check_generic, 306 + .platform = "ppc750", 307 + }, 308 + { /* 750FX rev 2.0 must disable HID0[DPM] */ 309 + .pvr_mask = 0xffffffff, 310 + .pvr_value = 0x70000200, 311 + .cpu_name = "750FX", 312 + .cpu_features = CPU_FTRS_750FX2, 313 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 314 + .mmu_features = MMU_FTR_HPTE_TABLE, 315 + .icache_bsize = 32, 316 + .dcache_bsize = 32, 317 + .num_pmcs = 4, 318 + .pmc_type = PPC_PMC_IBM, 319 + .cpu_setup = __setup_cpu_750, 320 + .machine_check = machine_check_generic, 321 + .platform = "ppc750", 322 + }, 323 + { /* 750FX (All revs except 2.0) */ 324 + .pvr_mask = 0xffff0000, 325 + .pvr_value = 0x70000000, 326 + .cpu_name = "750FX", 327 + .cpu_features = CPU_FTRS_750FX, 328 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 329 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 330 + .icache_bsize = 32, 331 + .dcache_bsize = 32, 332 + .num_pmcs = 4, 333 + .pmc_type = PPC_PMC_IBM, 334 + .cpu_setup = __setup_cpu_750fx, 335 + .machine_check = machine_check_generic, 336 + .platform = "ppc750", 337 + }, 338 + { /* 750GX */ 339 + .pvr_mask = 0xffff0000, 340 + .pvr_value = 0x70020000, 341 + .cpu_name = "750GX", 342 + .cpu_features = CPU_FTRS_750GX, 343 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 344 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 345 + .icache_bsize = 32, 346 + .dcache_bsize = 32, 347 + .num_pmcs = 4, 348 + .pmc_type = PPC_PMC_IBM, 349 + .cpu_setup = __setup_cpu_750fx, 350 + .machine_check = machine_check_generic, 351 + .platform = "ppc750", 352 + }, 353 + { /* 740/750 (L2CR bit need fixup for 740) */ 354 + .pvr_mask = 0xffff0000, 355 + .pvr_value = 0x00080000, 356 + .cpu_name = "740/750", 357 + .cpu_features = CPU_FTRS_740, 358 + .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 359 + .mmu_features = MMU_FTR_HPTE_TABLE, 360 + .icache_bsize = 32, 361 + .dcache_bsize = 32, 362 + .num_pmcs = 4, 363 + .pmc_type = PPC_PMC_IBM, 364 + .cpu_setup = __setup_cpu_750, 365 + .machine_check = machine_check_generic, 366 + .platform = "ppc750", 367 + }, 368 + { /* 7400 rev 1.1 ? (no TAU) */ 369 + .pvr_mask = 0xffffffff, 370 + .pvr_value = 0x000c1101, 371 + .cpu_name = "7400 (1.1)", 372 + .cpu_features = CPU_FTRS_7400_NOTAU, 373 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 374 + PPC_FEATURE_PPC_LE, 375 + .mmu_features = MMU_FTR_HPTE_TABLE, 376 + .icache_bsize = 32, 377 + .dcache_bsize = 32, 378 + .num_pmcs = 4, 379 + .pmc_type = PPC_PMC_G4, 380 + .cpu_setup = __setup_cpu_7400, 381 + .machine_check = machine_check_generic, 382 + .platform = "ppc7400", 383 + }, 384 + { /* 7400 */ 385 + .pvr_mask = 0xffff0000, 386 + .pvr_value = 0x000c0000, 387 + .cpu_name = "7400", 388 + .cpu_features = CPU_FTRS_7400, 389 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 390 + PPC_FEATURE_PPC_LE, 391 + .mmu_features = MMU_FTR_HPTE_TABLE, 392 + .icache_bsize = 32, 393 + .dcache_bsize = 32, 394 + .num_pmcs = 4, 395 + .pmc_type = PPC_PMC_G4, 396 + .cpu_setup = __setup_cpu_7400, 397 + .machine_check = machine_check_generic, 398 + .platform = "ppc7400", 399 + }, 400 + { /* 7410 */ 401 + .pvr_mask = 0xffff0000, 402 + .pvr_value = 0x800c0000, 403 + .cpu_name = "7410", 404 + .cpu_features = CPU_FTRS_7400, 405 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 406 + PPC_FEATURE_PPC_LE, 407 + .mmu_features = MMU_FTR_HPTE_TABLE, 408 + .icache_bsize = 32, 409 + .dcache_bsize = 32, 410 + .num_pmcs = 4, 411 + .pmc_type = PPC_PMC_G4, 412 + .cpu_setup = __setup_cpu_7410, 413 + .machine_check = machine_check_generic, 414 + .platform = "ppc7400", 415 + }, 416 + { /* 7450 2.0 - no doze/nap */ 417 + .pvr_mask = 0xffffffff, 418 + .pvr_value = 0x80000200, 419 + .cpu_name = "7450", 420 + .cpu_features = CPU_FTRS_7450_20, 421 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 422 + PPC_FEATURE_PPC_LE, 423 + .mmu_features = MMU_FTR_HPTE_TABLE, 424 + .icache_bsize = 32, 425 + .dcache_bsize = 32, 426 + .num_pmcs = 6, 427 + .pmc_type = PPC_PMC_G4, 428 + .cpu_setup = __setup_cpu_745x, 429 + .machine_check = machine_check_generic, 430 + .platform = "ppc7450", 431 + }, 432 + { /* 7450 2.1 */ 433 + .pvr_mask = 0xffffffff, 434 + .pvr_value = 0x80000201, 435 + .cpu_name = "7450", 436 + .cpu_features = CPU_FTRS_7450_21, 437 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 438 + PPC_FEATURE_PPC_LE, 439 + .mmu_features = MMU_FTR_HPTE_TABLE, 440 + .icache_bsize = 32, 441 + .dcache_bsize = 32, 442 + .num_pmcs = 6, 443 + .pmc_type = PPC_PMC_G4, 444 + .cpu_setup = __setup_cpu_745x, 445 + .machine_check = machine_check_generic, 446 + .platform = "ppc7450", 447 + }, 448 + { /* 7450 2.3 and newer */ 449 + .pvr_mask = 0xffff0000, 450 + .pvr_value = 0x80000000, 451 + .cpu_name = "7450", 452 + .cpu_features = CPU_FTRS_7450_23, 453 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 454 + PPC_FEATURE_PPC_LE, 455 + .mmu_features = MMU_FTR_HPTE_TABLE, 456 + .icache_bsize = 32, 457 + .dcache_bsize = 32, 458 + .num_pmcs = 6, 459 + .pmc_type = PPC_PMC_G4, 460 + .cpu_setup = __setup_cpu_745x, 461 + .machine_check = machine_check_generic, 462 + .platform = "ppc7450", 463 + }, 464 + { /* 7455 rev 1.x */ 465 + .pvr_mask = 0xffffff00, 466 + .pvr_value = 0x80010100, 467 + .cpu_name = "7455", 468 + .cpu_features = CPU_FTRS_7455_1, 469 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 470 + PPC_FEATURE_PPC_LE, 471 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 472 + .icache_bsize = 32, 473 + .dcache_bsize = 32, 474 + .num_pmcs = 6, 475 + .pmc_type = PPC_PMC_G4, 476 + .cpu_setup = __setup_cpu_745x, 477 + .machine_check = machine_check_generic, 478 + .platform = "ppc7450", 479 + }, 480 + { /* 7455 rev 2.0 */ 481 + .pvr_mask = 0xffffffff, 482 + .pvr_value = 0x80010200, 483 + .cpu_name = "7455", 484 + .cpu_features = CPU_FTRS_7455_20, 485 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 486 + PPC_FEATURE_PPC_LE, 487 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 488 + .icache_bsize = 32, 489 + .dcache_bsize = 32, 490 + .num_pmcs = 6, 491 + .pmc_type = PPC_PMC_G4, 492 + .cpu_setup = __setup_cpu_745x, 493 + .machine_check = machine_check_generic, 494 + .platform = "ppc7450", 495 + }, 496 + { /* 7455 others */ 497 + .pvr_mask = 0xffff0000, 498 + .pvr_value = 0x80010000, 499 + .cpu_name = "7455", 500 + .cpu_features = CPU_FTRS_7455, 501 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 502 + PPC_FEATURE_PPC_LE, 503 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 504 + .icache_bsize = 32, 505 + .dcache_bsize = 32, 506 + .num_pmcs = 6, 507 + .pmc_type = PPC_PMC_G4, 508 + .cpu_setup = __setup_cpu_745x, 509 + .machine_check = machine_check_generic, 510 + .platform = "ppc7450", 511 + }, 512 + { /* 7447/7457 Rev 1.0 */ 513 + .pvr_mask = 0xffffffff, 514 + .pvr_value = 0x80020100, 515 + .cpu_name = "7447/7457", 516 + .cpu_features = CPU_FTRS_7447_10, 517 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 518 + PPC_FEATURE_PPC_LE, 519 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 520 + .icache_bsize = 32, 521 + .dcache_bsize = 32, 522 + .num_pmcs = 6, 523 + .pmc_type = PPC_PMC_G4, 524 + .cpu_setup = __setup_cpu_745x, 525 + .machine_check = machine_check_generic, 526 + .platform = "ppc7450", 527 + }, 528 + { /* 7447/7457 Rev 1.1 */ 529 + .pvr_mask = 0xffffffff, 530 + .pvr_value = 0x80020101, 531 + .cpu_name = "7447/7457", 532 + .cpu_features = CPU_FTRS_7447_10, 533 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 534 + PPC_FEATURE_PPC_LE, 535 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 536 + .icache_bsize = 32, 537 + .dcache_bsize = 32, 538 + .num_pmcs = 6, 539 + .pmc_type = PPC_PMC_G4, 540 + .cpu_setup = __setup_cpu_745x, 541 + .machine_check = machine_check_generic, 542 + .platform = "ppc7450", 543 + }, 544 + { /* 7447/7457 Rev 1.2 and later */ 545 + .pvr_mask = 0xffff0000, 546 + .pvr_value = 0x80020000, 547 + .cpu_name = "7447/7457", 548 + .cpu_features = CPU_FTRS_7447, 549 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 550 + PPC_FEATURE_PPC_LE, 551 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 552 + .icache_bsize = 32, 553 + .dcache_bsize = 32, 554 + .num_pmcs = 6, 555 + .pmc_type = PPC_PMC_G4, 556 + .cpu_setup = __setup_cpu_745x, 557 + .machine_check = machine_check_generic, 558 + .platform = "ppc7450", 559 + }, 560 + { /* 7447A */ 561 + .pvr_mask = 0xffff0000, 562 + .pvr_value = 0x80030000, 563 + .cpu_name = "7447A", 564 + .cpu_features = CPU_FTRS_7447A, 565 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 566 + PPC_FEATURE_PPC_LE, 567 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 568 + .icache_bsize = 32, 569 + .dcache_bsize = 32, 570 + .num_pmcs = 6, 571 + .pmc_type = PPC_PMC_G4, 572 + .cpu_setup = __setup_cpu_745x, 573 + .machine_check = machine_check_generic, 574 + .platform = "ppc7450", 575 + }, 576 + { /* 7448 */ 577 + .pvr_mask = 0xffff0000, 578 + .pvr_value = 0x80040000, 579 + .cpu_name = "7448", 580 + .cpu_features = CPU_FTRS_7448, 581 + .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | 582 + PPC_FEATURE_PPC_LE, 583 + .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 584 + .icache_bsize = 32, 585 + .dcache_bsize = 32, 586 + .num_pmcs = 6, 587 + .pmc_type = PPC_PMC_G4, 588 + .cpu_setup = __setup_cpu_745x, 589 + .machine_check = machine_check_generic, 590 + .platform = "ppc7450", 591 + }, 592 + { /* default match, we assume split I/D cache & TB (non-601)... */ 593 + .pvr_mask = 0x00000000, 594 + .pvr_value = 0x00000000, 595 + .cpu_name = "(generic PPC)", 596 + .cpu_features = CPU_FTRS_CLASSIC32, 597 + .cpu_user_features = COMMON_USER, 598 + .mmu_features = MMU_FTR_HPTE_TABLE, 599 + .icache_bsize = 32, 600 + .dcache_bsize = 32, 601 + .machine_check = machine_check_generic, 602 + .platform = "ppc603", 603 + }, 604 + #endif /* CONFIG_PPC_BOOK3S_604 */ 605 + };

+481

arch/powerpc/kernel/cpu_specs_book3s_64.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 + * 5 + * Modifications for ppc64: 6 + * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> 7 + */ 8 + 9 + /* NOTE: 10 + * Unlike ppc32, ppc64 will only call cpu_setup() for the boot CPU, it's 11 + * the responsibility of the appropriate CPU save/restore functions to 12 + * eventually copy these settings over. Those save/restore aren't yet 13 + * part of the cputable though. That has to be fixed for both ppc32 14 + * and ppc64 15 + */ 16 + #define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 17 + PPC_FEATURE_HAS_MMU | PPC_FEATURE_64) 18 + #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4) 19 + #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\ 20 + PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) 21 + #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\ 22 + PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) 23 + #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\ 24 + PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 25 + PPC_FEATURE_TRUE_LE | \ 26 + PPC_FEATURE_PSERIES_PERFMON_COMPAT) 27 + #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ 28 + PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 29 + PPC_FEATURE_TRUE_LE | \ 30 + PPC_FEATURE_PSERIES_PERFMON_COMPAT) 31 + #define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR) 32 + #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ 33 + PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 34 + PPC_FEATURE_TRUE_LE | \ 35 + PPC_FEATURE_PSERIES_PERFMON_COMPAT) 36 + #define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \ 37 + PPC_FEATURE2_HTM_COMP | \ 38 + PPC_FEATURE2_HTM_NOSC_COMP | \ 39 + PPC_FEATURE2_DSCR | \ 40 + PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \ 41 + PPC_FEATURE2_VEC_CRYPTO) 42 + #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\ 43 + PPC_FEATURE_TRUE_LE | \ 44 + PPC_FEATURE_HAS_ALTIVEC_COMP) 45 + #define COMMON_USER_POWER9 COMMON_USER_POWER8 46 + #define COMMON_USER2_POWER9 (COMMON_USER2_POWER8 | \ 47 + PPC_FEATURE2_ARCH_3_00 | \ 48 + PPC_FEATURE2_HAS_IEEE128 | \ 49 + PPC_FEATURE2_DARN | \ 50 + PPC_FEATURE2_SCV) 51 + #define COMMON_USER_POWER10 COMMON_USER_POWER9 52 + #define COMMON_USER2_POWER10 (PPC_FEATURE2_ARCH_3_1 | \ 53 + PPC_FEATURE2_MMA | \ 54 + PPC_FEATURE2_ARCH_3_00 | \ 55 + PPC_FEATURE2_HAS_IEEE128 | \ 56 + PPC_FEATURE2_DARN | \ 57 + PPC_FEATURE2_SCV | \ 58 + PPC_FEATURE2_ARCH_2_07 | \ 59 + PPC_FEATURE2_DSCR | \ 60 + PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \ 61 + PPC_FEATURE2_VEC_CRYPTO) 62 + 63 + static struct cpu_spec cpu_specs[] __initdata = { 64 + { /* PPC970 */ 65 + .pvr_mask = 0xffff0000, 66 + .pvr_value = 0x00390000, 67 + .cpu_name = "PPC970", 68 + .cpu_features = CPU_FTRS_PPC970, 69 + .cpu_user_features = COMMON_USER_POWER4 | PPC_FEATURE_HAS_ALTIVEC_COMP, 70 + .mmu_features = MMU_FTRS_PPC970, 71 + .icache_bsize = 128, 72 + .dcache_bsize = 128, 73 + .num_pmcs = 8, 74 + .pmc_type = PPC_PMC_IBM, 75 + .cpu_setup = __setup_cpu_ppc970, 76 + .cpu_restore = __restore_cpu_ppc970, 77 + .platform = "ppc970", 78 + }, 79 + { /* PPC970FX */ 80 + .pvr_mask = 0xffff0000, 81 + .pvr_value = 0x003c0000, 82 + .cpu_name = "PPC970FX", 83 + .cpu_features = CPU_FTRS_PPC970, 84 + .cpu_user_features = COMMON_USER_POWER4 | PPC_FEATURE_HAS_ALTIVEC_COMP, 85 + .mmu_features = MMU_FTRS_PPC970, 86 + .icache_bsize = 128, 87 + .dcache_bsize = 128, 88 + .num_pmcs = 8, 89 + .pmc_type = PPC_PMC_IBM, 90 + .cpu_setup = __setup_cpu_ppc970, 91 + .cpu_restore = __restore_cpu_ppc970, 92 + .platform = "ppc970", 93 + }, 94 + { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */ 95 + .pvr_mask = 0xffffffff, 96 + .pvr_value = 0x00440100, 97 + .cpu_name = "PPC970MP", 98 + .cpu_features = CPU_FTRS_PPC970, 99 + .cpu_user_features = COMMON_USER_POWER4 | PPC_FEATURE_HAS_ALTIVEC_COMP, 100 + .mmu_features = MMU_FTRS_PPC970, 101 + .icache_bsize = 128, 102 + .dcache_bsize = 128, 103 + .num_pmcs = 8, 104 + .pmc_type = PPC_PMC_IBM, 105 + .cpu_setup = __setup_cpu_ppc970, 106 + .cpu_restore = __restore_cpu_ppc970, 107 + .platform = "ppc970", 108 + }, 109 + { /* PPC970MP */ 110 + .pvr_mask = 0xffff0000, 111 + .pvr_value = 0x00440000, 112 + .cpu_name = "PPC970MP", 113 + .cpu_features = CPU_FTRS_PPC970, 114 + .cpu_user_features = COMMON_USER_POWER4 | PPC_FEATURE_HAS_ALTIVEC_COMP, 115 + .mmu_features = MMU_FTRS_PPC970, 116 + .icache_bsize = 128, 117 + .dcache_bsize = 128, 118 + .num_pmcs = 8, 119 + .pmc_type = PPC_PMC_IBM, 120 + .cpu_setup = __setup_cpu_ppc970MP, 121 + .cpu_restore = __restore_cpu_ppc970, 122 + .platform = "ppc970", 123 + }, 124 + { /* PPC970GX */ 125 + .pvr_mask = 0xffff0000, 126 + .pvr_value = 0x00450000, 127 + .cpu_name = "PPC970GX", 128 + .cpu_features = CPU_FTRS_PPC970, 129 + .cpu_user_features = COMMON_USER_POWER4 | PPC_FEATURE_HAS_ALTIVEC_COMP, 130 + .mmu_features = MMU_FTRS_PPC970, 131 + .icache_bsize = 128, 132 + .dcache_bsize = 128, 133 + .num_pmcs = 8, 134 + .pmc_type = PPC_PMC_IBM, 135 + .cpu_setup = __setup_cpu_ppc970, 136 + .platform = "ppc970", 137 + }, 138 + { /* Power5 GR */ 139 + .pvr_mask = 0xffff0000, 140 + .pvr_value = 0x003a0000, 141 + .cpu_name = "POWER5 (gr)", 142 + .cpu_features = CPU_FTRS_POWER5, 143 + .cpu_user_features = COMMON_USER_POWER5, 144 + .mmu_features = MMU_FTRS_POWER5, 145 + .icache_bsize = 128, 146 + .dcache_bsize = 128, 147 + .num_pmcs = 6, 148 + .pmc_type = PPC_PMC_IBM, 149 + .platform = "power5", 150 + }, 151 + { /* Power5++ */ 152 + .pvr_mask = 0xffffff00, 153 + .pvr_value = 0x003b0300, 154 + .cpu_name = "POWER5+ (gs)", 155 + .cpu_features = CPU_FTRS_POWER5, 156 + .cpu_user_features = COMMON_USER_POWER5_PLUS, 157 + .mmu_features = MMU_FTRS_POWER5, 158 + .icache_bsize = 128, 159 + .dcache_bsize = 128, 160 + .num_pmcs = 6, 161 + .platform = "power5+", 162 + }, 163 + { /* Power5 GS */ 164 + .pvr_mask = 0xffff0000, 165 + .pvr_value = 0x003b0000, 166 + .cpu_name = "POWER5+ (gs)", 167 + .cpu_features = CPU_FTRS_POWER5, 168 + .cpu_user_features = COMMON_USER_POWER5_PLUS, 169 + .mmu_features = MMU_FTRS_POWER5, 170 + .icache_bsize = 128, 171 + .dcache_bsize = 128, 172 + .num_pmcs = 6, 173 + .pmc_type = PPC_PMC_IBM, 174 + .platform = "power5+", 175 + }, 176 + { /* POWER6 in P5+ mode; 2.04-compliant processor */ 177 + .pvr_mask = 0xffffffff, 178 + .pvr_value = 0x0f000001, 179 + .cpu_name = "POWER5+", 180 + .cpu_features = CPU_FTRS_POWER5, 181 + .cpu_user_features = COMMON_USER_POWER5_PLUS, 182 + .mmu_features = MMU_FTRS_POWER5, 183 + .icache_bsize = 128, 184 + .dcache_bsize = 128, 185 + .platform = "power5+", 186 + }, 187 + { /* Power6 */ 188 + .pvr_mask = 0xffff0000, 189 + .pvr_value = 0x003e0000, 190 + .cpu_name = "POWER6 (raw)", 191 + .cpu_features = CPU_FTRS_POWER6, 192 + .cpu_user_features = COMMON_USER_POWER6 | PPC_FEATURE_POWER6_EXT, 193 + .mmu_features = MMU_FTRS_POWER6, 194 + .icache_bsize = 128, 195 + .dcache_bsize = 128, 196 + .num_pmcs = 6, 197 + .pmc_type = PPC_PMC_IBM, 198 + .platform = "power6x", 199 + }, 200 + { /* 2.05-compliant processor, i.e. Power6 "architected" mode */ 201 + .pvr_mask = 0xffffffff, 202 + .pvr_value = 0x0f000002, 203 + .cpu_name = "POWER6 (architected)", 204 + .cpu_features = CPU_FTRS_POWER6, 205 + .cpu_user_features = COMMON_USER_POWER6, 206 + .mmu_features = MMU_FTRS_POWER6, 207 + .icache_bsize = 128, 208 + .dcache_bsize = 128, 209 + .platform = "power6", 210 + }, 211 + { /* 2.06-compliant processor, i.e. Power7 "architected" mode */ 212 + .pvr_mask = 0xffffffff, 213 + .pvr_value = 0x0f000003, 214 + .cpu_name = "POWER7 (architected)", 215 + .cpu_features = CPU_FTRS_POWER7, 216 + .cpu_user_features = COMMON_USER_POWER7, 217 + .cpu_user_features2 = COMMON_USER2_POWER7, 218 + .mmu_features = MMU_FTRS_POWER7, 219 + .icache_bsize = 128, 220 + .dcache_bsize = 128, 221 + .cpu_setup = __setup_cpu_power7, 222 + .cpu_restore = __restore_cpu_power7, 223 + .machine_check_early = __machine_check_early_realmode_p7, 224 + .platform = "power7", 225 + }, 226 + { /* 2.07-compliant processor, i.e. Power8 "architected" mode */ 227 + .pvr_mask = 0xffffffff, 228 + .pvr_value = 0x0f000004, 229 + .cpu_name = "POWER8 (architected)", 230 + .cpu_features = CPU_FTRS_POWER8, 231 + .cpu_user_features = COMMON_USER_POWER8, 232 + .cpu_user_features2 = COMMON_USER2_POWER8, 233 + .mmu_features = MMU_FTRS_POWER8, 234 + .icache_bsize = 128, 235 + .dcache_bsize = 128, 236 + .cpu_setup = __setup_cpu_power8, 237 + .cpu_restore = __restore_cpu_power8, 238 + .machine_check_early = __machine_check_early_realmode_p8, 239 + .platform = "power8", 240 + }, 241 + { /* 3.00-compliant processor, i.e. Power9 "architected" mode */ 242 + .pvr_mask = 0xffffffff, 243 + .pvr_value = 0x0f000005, 244 + .cpu_name = "POWER9 (architected)", 245 + .cpu_features = CPU_FTRS_POWER9, 246 + .cpu_user_features = COMMON_USER_POWER9, 247 + .cpu_user_features2 = COMMON_USER2_POWER9, 248 + .mmu_features = MMU_FTRS_POWER9, 249 + .icache_bsize = 128, 250 + .dcache_bsize = 128, 251 + .cpu_setup = __setup_cpu_power9, 252 + .cpu_restore = __restore_cpu_power9, 253 + .platform = "power9", 254 + }, 255 + { /* 3.1-compliant processor, i.e. Power10 "architected" mode */ 256 + .pvr_mask = 0xffffffff, 257 + .pvr_value = 0x0f000006, 258 + .cpu_name = "POWER10 (architected)", 259 + .cpu_features = CPU_FTRS_POWER10, 260 + .cpu_user_features = COMMON_USER_POWER10, 261 + .cpu_user_features2 = COMMON_USER2_POWER10, 262 + .mmu_features = MMU_FTRS_POWER10, 263 + .icache_bsize = 128, 264 + .dcache_bsize = 128, 265 + .cpu_setup = __setup_cpu_power10, 266 + .cpu_restore = __restore_cpu_power10, 267 + .platform = "power10", 268 + }, 269 + { /* Power7 */ 270 + .pvr_mask = 0xffff0000, 271 + .pvr_value = 0x003f0000, 272 + .cpu_name = "POWER7 (raw)", 273 + .cpu_features = CPU_FTRS_POWER7, 274 + .cpu_user_features = COMMON_USER_POWER7, 275 + .cpu_user_features2 = COMMON_USER2_POWER7, 276 + .mmu_features = MMU_FTRS_POWER7, 277 + .icache_bsize = 128, 278 + .dcache_bsize = 128, 279 + .num_pmcs = 6, 280 + .pmc_type = PPC_PMC_IBM, 281 + .cpu_setup = __setup_cpu_power7, 282 + .cpu_restore = __restore_cpu_power7, 283 + .machine_check_early = __machine_check_early_realmode_p7, 284 + .platform = "power7", 285 + }, 286 + { /* Power7+ */ 287 + .pvr_mask = 0xffff0000, 288 + .pvr_value = 0x004A0000, 289 + .cpu_name = "POWER7+ (raw)", 290 + .cpu_features = CPU_FTRS_POWER7, 291 + .cpu_user_features = COMMON_USER_POWER7, 292 + .cpu_user_features2 = COMMON_USER2_POWER7, 293 + .mmu_features = MMU_FTRS_POWER7, 294 + .icache_bsize = 128, 295 + .dcache_bsize = 128, 296 + .num_pmcs = 6, 297 + .pmc_type = PPC_PMC_IBM, 298 + .cpu_setup = __setup_cpu_power7, 299 + .cpu_restore = __restore_cpu_power7, 300 + .machine_check_early = __machine_check_early_realmode_p7, 301 + .platform = "power7+", 302 + }, 303 + { /* Power8E */ 304 + .pvr_mask = 0xffff0000, 305 + .pvr_value = 0x004b0000, 306 + .cpu_name = "POWER8E (raw)", 307 + .cpu_features = CPU_FTRS_POWER8E, 308 + .cpu_user_features = COMMON_USER_POWER8, 309 + .cpu_user_features2 = COMMON_USER2_POWER8, 310 + .mmu_features = MMU_FTRS_POWER8, 311 + .icache_bsize = 128, 312 + .dcache_bsize = 128, 313 + .num_pmcs = 6, 314 + .pmc_type = PPC_PMC_IBM, 315 + .cpu_setup = __setup_cpu_power8, 316 + .cpu_restore = __restore_cpu_power8, 317 + .machine_check_early = __machine_check_early_realmode_p8, 318 + .platform = "power8", 319 + }, 320 + { /* Power8NVL */ 321 + .pvr_mask = 0xffff0000, 322 + .pvr_value = 0x004c0000, 323 + .cpu_name = "POWER8NVL (raw)", 324 + .cpu_features = CPU_FTRS_POWER8, 325 + .cpu_user_features = COMMON_USER_POWER8, 326 + .cpu_user_features2 = COMMON_USER2_POWER8, 327 + .mmu_features = MMU_FTRS_POWER8, 328 + .icache_bsize = 128, 329 + .dcache_bsize = 128, 330 + .num_pmcs = 6, 331 + .pmc_type = PPC_PMC_IBM, 332 + .cpu_setup = __setup_cpu_power8, 333 + .cpu_restore = __restore_cpu_power8, 334 + .machine_check_early = __machine_check_early_realmode_p8, 335 + .platform = "power8", 336 + }, 337 + { /* Power8 */ 338 + .pvr_mask = 0xffff0000, 339 + .pvr_value = 0x004d0000, 340 + .cpu_name = "POWER8 (raw)", 341 + .cpu_features = CPU_FTRS_POWER8, 342 + .cpu_user_features = COMMON_USER_POWER8, 343 + .cpu_user_features2 = COMMON_USER2_POWER8, 344 + .mmu_features = MMU_FTRS_POWER8, 345 + .icache_bsize = 128, 346 + .dcache_bsize = 128, 347 + .num_pmcs = 6, 348 + .pmc_type = PPC_PMC_IBM, 349 + .cpu_setup = __setup_cpu_power8, 350 + .cpu_restore = __restore_cpu_power8, 351 + .machine_check_early = __machine_check_early_realmode_p8, 352 + .platform = "power8", 353 + }, 354 + { /* Power9 DD2.0 */ 355 + .pvr_mask = 0xffffefff, 356 + .pvr_value = 0x004e0200, 357 + .cpu_name = "POWER9 (raw)", 358 + .cpu_features = CPU_FTRS_POWER9_DD2_0, 359 + .cpu_user_features = COMMON_USER_POWER9, 360 + .cpu_user_features2 = COMMON_USER2_POWER9, 361 + .mmu_features = MMU_FTRS_POWER9, 362 + .icache_bsize = 128, 363 + .dcache_bsize = 128, 364 + .num_pmcs = 6, 365 + .pmc_type = PPC_PMC_IBM, 366 + .cpu_setup = __setup_cpu_power9, 367 + .cpu_restore = __restore_cpu_power9, 368 + .machine_check_early = __machine_check_early_realmode_p9, 369 + .platform = "power9", 370 + }, 371 + { /* Power9 DD 2.1 */ 372 + .pvr_mask = 0xffffefff, 373 + .pvr_value = 0x004e0201, 374 + .cpu_name = "POWER9 (raw)", 375 + .cpu_features = CPU_FTRS_POWER9_DD2_1, 376 + .cpu_user_features = COMMON_USER_POWER9, 377 + .cpu_user_features2 = COMMON_USER2_POWER9, 378 + .mmu_features = MMU_FTRS_POWER9, 379 + .icache_bsize = 128, 380 + .dcache_bsize = 128, 381 + .num_pmcs = 6, 382 + .pmc_type = PPC_PMC_IBM, 383 + .cpu_setup = __setup_cpu_power9, 384 + .cpu_restore = __restore_cpu_power9, 385 + .machine_check_early = __machine_check_early_realmode_p9, 386 + .platform = "power9", 387 + }, 388 + { /* Power9 DD2.2 */ 389 + .pvr_mask = 0xffffefff, 390 + .pvr_value = 0x004e0202, 391 + .cpu_name = "POWER9 (raw)", 392 + .cpu_features = CPU_FTRS_POWER9_DD2_2, 393 + .cpu_user_features = COMMON_USER_POWER9, 394 + .cpu_user_features2 = COMMON_USER2_POWER9, 395 + .mmu_features = MMU_FTRS_POWER9, 396 + .icache_bsize = 128, 397 + .dcache_bsize = 128, 398 + .num_pmcs = 6, 399 + .pmc_type = PPC_PMC_IBM, 400 + .cpu_setup = __setup_cpu_power9, 401 + .cpu_restore = __restore_cpu_power9, 402 + .machine_check_early = __machine_check_early_realmode_p9, 403 + .platform = "power9", 404 + }, 405 + { /* Power9 DD2.3 or later */ 406 + .pvr_mask = 0xffff0000, 407 + .pvr_value = 0x004e0000, 408 + .cpu_name = "POWER9 (raw)", 409 + .cpu_features = CPU_FTRS_POWER9_DD2_3, 410 + .cpu_user_features = COMMON_USER_POWER9, 411 + .cpu_user_features2 = COMMON_USER2_POWER9, 412 + .mmu_features = MMU_FTRS_POWER9, 413 + .icache_bsize = 128, 414 + .dcache_bsize = 128, 415 + .num_pmcs = 6, 416 + .pmc_type = PPC_PMC_IBM, 417 + .cpu_setup = __setup_cpu_power9, 418 + .cpu_restore = __restore_cpu_power9, 419 + .machine_check_early = __machine_check_early_realmode_p9, 420 + .platform = "power9", 421 + }, 422 + { /* Power10 */ 423 + .pvr_mask = 0xffff0000, 424 + .pvr_value = 0x00800000, 425 + .cpu_name = "POWER10 (raw)", 426 + .cpu_features = CPU_FTRS_POWER10, 427 + .cpu_user_features = COMMON_USER_POWER10, 428 + .cpu_user_features2 = COMMON_USER2_POWER10, 429 + .mmu_features = MMU_FTRS_POWER10, 430 + .icache_bsize = 128, 431 + .dcache_bsize = 128, 432 + .num_pmcs = 6, 433 + .pmc_type = PPC_PMC_IBM, 434 + .cpu_setup = __setup_cpu_power10, 435 + .cpu_restore = __restore_cpu_power10, 436 + .machine_check_early = __machine_check_early_realmode_p10, 437 + .platform = "power10", 438 + }, 439 + { /* Cell Broadband Engine */ 440 + .pvr_mask = 0xffff0000, 441 + .pvr_value = 0x00700000, 442 + .cpu_name = "Cell Broadband Engine", 443 + .cpu_features = CPU_FTRS_CELL, 444 + .cpu_user_features = COMMON_USER_PPC64 | PPC_FEATURE_CELL | 445 + PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_SMT, 446 + .mmu_features = MMU_FTRS_CELL, 447 + .icache_bsize = 128, 448 + .dcache_bsize = 128, 449 + .num_pmcs = 4, 450 + .pmc_type = PPC_PMC_IBM, 451 + .platform = "ppc-cell-be", 452 + }, 453 + { /* PA Semi PA6T */ 454 + .pvr_mask = 0x7fff0000, 455 + .pvr_value = 0x00900000, 456 + .cpu_name = "PA6T", 457 + .cpu_features = CPU_FTRS_PA6T, 458 + .cpu_user_features = COMMON_USER_PA6T, 459 + .mmu_features = MMU_FTRS_PA6T, 460 + .icache_bsize = 64, 461 + .dcache_bsize = 64, 462 + .num_pmcs = 6, 463 + .pmc_type = PPC_PMC_PA6T, 464 + .cpu_setup = __setup_cpu_pa6t, 465 + .cpu_restore = __restore_cpu_pa6t, 466 + .platform = "pa6t", 467 + }, 468 + { /* default match */ 469 + .pvr_mask = 0x00000000, 470 + .pvr_value = 0x00000000, 471 + .cpu_name = "POWER5 (compatible)", 472 + .cpu_features = CPU_FTRS_COMPATIBLE, 473 + .cpu_user_features = COMMON_USER_PPC64, 474 + .mmu_features = MMU_FTRS_POWER, 475 + .icache_bsize = 128, 476 + .dcache_bsize = 128, 477 + .num_pmcs = 6, 478 + .pmc_type = PPC_PMC_IBM, 479 + .platform = "power5", 480 + } 481 + };

+75

arch/powerpc/kernel/cpu_specs_e500mc.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 4 + * 5 + * Modifications for ppc64: 6 + * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> 7 + */ 8 + 9 + #ifdef CONFIG_PPC64 10 + #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 11 + PPC_FEATURE_HAS_FPU | PPC_FEATURE_64) 12 + #else 13 + #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 14 + PPC_FEATURE_BOOKE) 15 + #endif 16 + 17 + static struct cpu_spec cpu_specs[] __initdata = { 18 + #ifdef CONFIG_PPC32 19 + { /* e500mc */ 20 + .pvr_mask = 0xffff0000, 21 + .pvr_value = 0x80230000, 22 + .cpu_name = "e500mc", 23 + .cpu_features = CPU_FTRS_E500MC, 24 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 25 + .cpu_user_features2 = PPC_FEATURE2_ISEL, 26 + .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX, 27 + .icache_bsize = 64, 28 + .dcache_bsize = 64, 29 + .num_pmcs = 4, 30 + .cpu_setup = __setup_cpu_e500mc, 31 + .machine_check = machine_check_e500mc, 32 + .platform = "ppce500mc", 33 + .cpu_down_flush = cpu_down_flush_e500mc, 34 + }, 35 + #endif /* CONFIG_PPC32 */ 36 + { /* e5500 */ 37 + .pvr_mask = 0xffff0000, 38 + .pvr_value = 0x80240000, 39 + .cpu_name = "e5500", 40 + .cpu_features = CPU_FTRS_E5500, 41 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 42 + .cpu_user_features2 = PPC_FEATURE2_ISEL, 43 + .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX, 44 + .icache_bsize = 64, 45 + .dcache_bsize = 64, 46 + .num_pmcs = 4, 47 + .cpu_setup = __setup_cpu_e5500, 48 + #ifndef CONFIG_PPC32 49 + .cpu_restore = __restore_cpu_e5500, 50 + #endif 51 + .machine_check = machine_check_e500mc, 52 + .platform = "ppce5500", 53 + .cpu_down_flush = cpu_down_flush_e5500, 54 + }, 55 + { /* e6500 */ 56 + .pvr_mask = 0xffff0000, 57 + .pvr_value = 0x80400000, 58 + .cpu_name = "e6500", 59 + .cpu_features = CPU_FTRS_E6500, 60 + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU | 61 + PPC_FEATURE_HAS_ALTIVEC_COMP, 62 + .cpu_user_features2 = PPC_FEATURE2_ISEL, 63 + .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX, 64 + .icache_bsize = 64, 65 + .dcache_bsize = 64, 66 + .num_pmcs = 6, 67 + .cpu_setup = __setup_cpu_e6500, 68 + #ifndef CONFIG_PPC32 69 + .cpu_restore = __restore_cpu_e6500, 70 + #endif 71 + .machine_check = machine_check_e500mc, 72 + .platform = "ppce6500", 73 + .cpu_down_flush = cpu_down_flush_e6500, 74 + }, 75 + };

+4 -1916

arch/powerpc/kernel/cputable.c

··· 18 18 #include <asm/mce.h> 19 19 #include <asm/mmu.h> 20 20 #include <asm/setup.h> 21 + #include <asm/cpu_setup.h> 21 22 22 23 static struct cpu_spec the_cpu_spec __read_mostly; 23 24 ··· 28 27 /* The platform string corresponding to the real PVR */ 29 28 const char *powerpc_base_platform; 30 29 31 - /* NOTE: 32 - * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's 33 - * the responsibility of the appropriate CPU save/restore functions to 34 - * eventually copy these settings over. Those save/restore aren't yet 35 - * part of the cputable though. That has to be fixed for both ppc32 36 - * and ppc64 37 - */ 38 - #ifdef CONFIG_PPC32 39 - extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec); 40 - extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec); 41 - extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec); 42 - extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec); 43 - extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec); 44 - extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec); 45 - extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec); 46 - extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec); 47 - extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec); 48 - extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec); 49 - extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec); 50 - extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec); 51 - extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec); 52 - extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec); 53 - extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec); 54 - extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec); 55 - extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec); 56 - extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec); 57 - extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec); 58 - extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec); 59 - extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec); 60 - #endif /* CONFIG_PPC32 */ 61 - #ifdef CONFIG_PPC64 62 - #include <asm/cpu_setup_power.h> 63 - extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); 64 - extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec); 65 - extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec); 66 - extern void __restore_cpu_pa6t(void); 67 - extern void __restore_cpu_ppc970(void); 68 - extern long __machine_check_early_realmode_p7(struct pt_regs *regs); 69 - extern long __machine_check_early_realmode_p8(struct pt_regs *regs); 70 - extern long __machine_check_early_realmode_p9(struct pt_regs *regs); 71 - #endif /* CONFIG_PPC64 */ 72 - #if defined(CONFIG_E500) 73 - extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec); 74 - extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec); 75 - extern void __restore_cpu_e5500(void); 76 - extern void __restore_cpu_e6500(void); 77 - #endif /* CONFIG_E500 */ 78 - 79 - /* This table only contains "desktop" CPUs, it need to be filled with embedded 80 - * ones as well... 81 - */ 82 - #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 83 - PPC_FEATURE_HAS_MMU) 84 - #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64) 85 - #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4) 86 - #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\ 87 - PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) 88 - #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\ 89 - PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP) 90 - #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\ 91 - PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 92 - PPC_FEATURE_TRUE_LE | \ 93 - PPC_FEATURE_PSERIES_PERFMON_COMPAT) 94 - #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ 95 - PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 96 - PPC_FEATURE_TRUE_LE | \ 97 - PPC_FEATURE_PSERIES_PERFMON_COMPAT) 98 - #define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR) 99 - #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ 100 - PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ 101 - PPC_FEATURE_TRUE_LE | \ 102 - PPC_FEATURE_PSERIES_PERFMON_COMPAT) 103 - #define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \ 104 - PPC_FEATURE2_HTM_COMP | \ 105 - PPC_FEATURE2_HTM_NOSC_COMP | \ 106 - PPC_FEATURE2_DSCR | \ 107 - PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \ 108 - PPC_FEATURE2_VEC_CRYPTO) 109 - #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\ 110 - PPC_FEATURE_TRUE_LE | \ 111 - PPC_FEATURE_HAS_ALTIVEC_COMP) 112 - #define COMMON_USER_POWER9 COMMON_USER_POWER8 113 - #define COMMON_USER2_POWER9 (COMMON_USER2_POWER8 | \ 114 - PPC_FEATURE2_ARCH_3_00 | \ 115 - PPC_FEATURE2_HAS_IEEE128 | \ 116 - PPC_FEATURE2_DARN | \ 117 - PPC_FEATURE2_SCV) 118 - #define COMMON_USER_POWER10 COMMON_USER_POWER9 119 - #define COMMON_USER2_POWER10 (PPC_FEATURE2_ARCH_3_1 | \ 120 - PPC_FEATURE2_MMA | \ 121 - PPC_FEATURE2_ARCH_3_00 | \ 122 - PPC_FEATURE2_HAS_IEEE128 | \ 123 - PPC_FEATURE2_DARN | \ 124 - PPC_FEATURE2_SCV | \ 125 - PPC_FEATURE2_ARCH_2_07 | \ 126 - PPC_FEATURE2_DSCR | \ 127 - PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \ 128 - PPC_FEATURE2_VEC_CRYPTO) 129 - 130 - #ifdef CONFIG_PPC_BOOK3E_64 131 - #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE) 132 - #else 133 - #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \ 134 - PPC_FEATURE_BOOKE) 135 - #endif 136 - 137 - static struct cpu_spec __initdata cpu_specs[] = { 138 - #ifdef CONFIG_PPC_BOOK3S_64 139 - { /* PPC970 */ 140 - .pvr_mask = 0xffff0000, 141 - .pvr_value = 0x00390000, 142 - .cpu_name = "PPC970", 143 - .cpu_features = CPU_FTRS_PPC970, 144 - .cpu_user_features = COMMON_USER_POWER4 | 145 - PPC_FEATURE_HAS_ALTIVEC_COMP, 146 - .mmu_features = MMU_FTRS_PPC970, 147 - .icache_bsize = 128, 148 - .dcache_bsize = 128, 149 - .num_pmcs = 8, 150 - .pmc_type = PPC_PMC_IBM, 151 - .cpu_setup = __setup_cpu_ppc970, 152 - .cpu_restore = __restore_cpu_ppc970, 153 - .platform = "ppc970", 154 - }, 155 - { /* PPC970FX */ 156 - .pvr_mask = 0xffff0000, 157 - .pvr_value = 0x003c0000, 158 - .cpu_name = "PPC970FX", 159 - .cpu_features = CPU_FTRS_PPC970, 160 - .cpu_user_features = COMMON_USER_POWER4 | 161 - PPC_FEATURE_HAS_ALTIVEC_COMP, 162 - .mmu_features = MMU_FTRS_PPC970, 163 - .icache_bsize = 128, 164 - .dcache_bsize = 128, 165 - .num_pmcs = 8, 166 - .pmc_type = PPC_PMC_IBM, 167 - .cpu_setup = __setup_cpu_ppc970, 168 - .cpu_restore = __restore_cpu_ppc970, 169 - .platform = "ppc970", 170 - }, 171 - { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */ 172 - .pvr_mask = 0xffffffff, 173 - .pvr_value = 0x00440100, 174 - .cpu_name = "PPC970MP", 175 - .cpu_features = CPU_FTRS_PPC970, 176 - .cpu_user_features = COMMON_USER_POWER4 | 177 - PPC_FEATURE_HAS_ALTIVEC_COMP, 178 - .mmu_features = MMU_FTRS_PPC970, 179 - .icache_bsize = 128, 180 - .dcache_bsize = 128, 181 - .num_pmcs = 8, 182 - .pmc_type = PPC_PMC_IBM, 183 - .cpu_setup = __setup_cpu_ppc970, 184 - .cpu_restore = __restore_cpu_ppc970, 185 - .platform = "ppc970", 186 - }, 187 - { /* PPC970MP */ 188 - .pvr_mask = 0xffff0000, 189 - .pvr_value = 0x00440000, 190 - .cpu_name = "PPC970MP", 191 - .cpu_features = CPU_FTRS_PPC970, 192 - .cpu_user_features = COMMON_USER_POWER4 | 193 - PPC_FEATURE_HAS_ALTIVEC_COMP, 194 - .mmu_features = MMU_FTRS_PPC970, 195 - .icache_bsize = 128, 196 - .dcache_bsize = 128, 197 - .num_pmcs = 8, 198 - .pmc_type = PPC_PMC_IBM, 199 - .cpu_setup = __setup_cpu_ppc970MP, 200 - .cpu_restore = __restore_cpu_ppc970, 201 - .platform = "ppc970", 202 - }, 203 - { /* PPC970GX */ 204 - .pvr_mask = 0xffff0000, 205 - .pvr_value = 0x00450000, 206 - .cpu_name = "PPC970GX", 207 - .cpu_features = CPU_FTRS_PPC970, 208 - .cpu_user_features = COMMON_USER_POWER4 | 209 - PPC_FEATURE_HAS_ALTIVEC_COMP, 210 - .mmu_features = MMU_FTRS_PPC970, 211 - .icache_bsize = 128, 212 - .dcache_bsize = 128, 213 - .num_pmcs = 8, 214 - .pmc_type = PPC_PMC_IBM, 215 - .cpu_setup = __setup_cpu_ppc970, 216 - .platform = "ppc970", 217 - }, 218 - { /* Power5 GR */ 219 - .pvr_mask = 0xffff0000, 220 - .pvr_value = 0x003a0000, 221 - .cpu_name = "POWER5 (gr)", 222 - .cpu_features = CPU_FTRS_POWER5, 223 - .cpu_user_features = COMMON_USER_POWER5, 224 - .mmu_features = MMU_FTRS_POWER5, 225 - .icache_bsize = 128, 226 - .dcache_bsize = 128, 227 - .num_pmcs = 6, 228 - .pmc_type = PPC_PMC_IBM, 229 - .platform = "power5", 230 - }, 231 - { /* Power5++ */ 232 - .pvr_mask = 0xffffff00, 233 - .pvr_value = 0x003b0300, 234 - .cpu_name = "POWER5+ (gs)", 235 - .cpu_features = CPU_FTRS_POWER5, 236 - .cpu_user_features = COMMON_USER_POWER5_PLUS, 237 - .mmu_features = MMU_FTRS_POWER5, 238 - .icache_bsize = 128, 239 - .dcache_bsize = 128, 240 - .num_pmcs = 6, 241 - .platform = "power5+", 242 - }, 243 - { /* Power5 GS */ 244 - .pvr_mask = 0xffff0000, 245 - .pvr_value = 0x003b0000, 246 - .cpu_name = "POWER5+ (gs)", 247 - .cpu_features = CPU_FTRS_POWER5, 248 - .cpu_user_features = COMMON_USER_POWER5_PLUS, 249 - .mmu_features = MMU_FTRS_POWER5, 250 - .icache_bsize = 128, 251 - .dcache_bsize = 128, 252 - .num_pmcs = 6, 253 - .pmc_type = PPC_PMC_IBM, 254 - .platform = "power5+", 255 - }, 256 - { /* POWER6 in P5+ mode; 2.04-compliant processor */ 257 - .pvr_mask = 0xffffffff, 258 - .pvr_value = 0x0f000001, 259 - .cpu_name = "POWER5+", 260 - .cpu_features = CPU_FTRS_POWER5, 261 - .cpu_user_features = COMMON_USER_POWER5_PLUS, 262 - .mmu_features = MMU_FTRS_POWER5, 263 - .icache_bsize = 128, 264 - .dcache_bsize = 128, 265 - .platform = "power5+", 266 - }, 267 - { /* Power6 */ 268 - .pvr_mask = 0xffff0000, 269 - .pvr_value = 0x003e0000, 270 - .cpu_name = "POWER6 (raw)", 271 - .cpu_features = CPU_FTRS_POWER6, 272 - .cpu_user_features = COMMON_USER_POWER6 | 273 - PPC_FEATURE_POWER6_EXT, 274 - .mmu_features = MMU_FTRS_POWER6, 275 - .icache_bsize = 128, 276 - .dcache_bsize = 128, 277 - .num_pmcs = 6, 278 - .pmc_type = PPC_PMC_IBM, 279 - .platform = "power6x", 280 - }, 281 - { /* 2.05-compliant processor, i.e. Power6 "architected" mode */ 282 - .pvr_mask = 0xffffffff, 283 - .pvr_value = 0x0f000002, 284 - .cpu_name = "POWER6 (architected)", 285 - .cpu_features = CPU_FTRS_POWER6, 286 - .cpu_user_features = COMMON_USER_POWER6, 287 - .mmu_features = MMU_FTRS_POWER6, 288 - .icache_bsize = 128, 289 - .dcache_bsize = 128, 290 - .platform = "power6", 291 - }, 292 - { /* 2.06-compliant processor, i.e. Power7 "architected" mode */ 293 - .pvr_mask = 0xffffffff, 294 - .pvr_value = 0x0f000003, 295 - .cpu_name = "POWER7 (architected)", 296 - .cpu_features = CPU_FTRS_POWER7, 297 - .cpu_user_features = COMMON_USER_POWER7, 298 - .cpu_user_features2 = COMMON_USER2_POWER7, 299 - .mmu_features = MMU_FTRS_POWER7, 300 - .icache_bsize = 128, 301 - .dcache_bsize = 128, 302 - .cpu_setup = __setup_cpu_power7, 303 - .cpu_restore = __restore_cpu_power7, 304 - .machine_check_early = __machine_check_early_realmode_p7, 305 - .platform = "power7", 306 - }, 307 - { /* 2.07-compliant processor, i.e. Power8 "architected" mode */ 308 - .pvr_mask = 0xffffffff, 309 - .pvr_value = 0x0f000004, 310 - .cpu_name = "POWER8 (architected)", 311 - .cpu_features = CPU_FTRS_POWER8, 312 - .cpu_user_features = COMMON_USER_POWER8, 313 - .cpu_user_features2 = COMMON_USER2_POWER8, 314 - .mmu_features = MMU_FTRS_POWER8, 315 - .icache_bsize = 128, 316 - .dcache_bsize = 128, 317 - .cpu_setup = __setup_cpu_power8, 318 - .cpu_restore = __restore_cpu_power8, 319 - .machine_check_early = __machine_check_early_realmode_p8, 320 - .platform = "power8", 321 - }, 322 - { /* 3.00-compliant processor, i.e. Power9 "architected" mode */ 323 - .pvr_mask = 0xffffffff, 324 - .pvr_value = 0x0f000005, 325 - .cpu_name = "POWER9 (architected)", 326 - .cpu_features = CPU_FTRS_POWER9, 327 - .cpu_user_features = COMMON_USER_POWER9, 328 - .cpu_user_features2 = COMMON_USER2_POWER9, 329 - .mmu_features = MMU_FTRS_POWER9, 330 - .icache_bsize = 128, 331 - .dcache_bsize = 128, 332 - .cpu_setup = __setup_cpu_power9, 333 - .cpu_restore = __restore_cpu_power9, 334 - .platform = "power9", 335 - }, 336 - { /* 3.1-compliant processor, i.e. Power10 "architected" mode */ 337 - .pvr_mask = 0xffffffff, 338 - .pvr_value = 0x0f000006, 339 - .cpu_name = "POWER10 (architected)", 340 - .cpu_features = CPU_FTRS_POWER10, 341 - .cpu_user_features = COMMON_USER_POWER10, 342 - .cpu_user_features2 = COMMON_USER2_POWER10, 343 - .mmu_features = MMU_FTRS_POWER10, 344 - .icache_bsize = 128, 345 - .dcache_bsize = 128, 346 - .cpu_setup = __setup_cpu_power10, 347 - .cpu_restore = __restore_cpu_power10, 348 - .platform = "power10", 349 - }, 350 - { /* Power7 */ 351 - .pvr_mask = 0xffff0000, 352 - .pvr_value = 0x003f0000, 353 - .cpu_name = "POWER7 (raw)", 354 - .cpu_features = CPU_FTRS_POWER7, 355 - .cpu_user_features = COMMON_USER_POWER7, 356 - .cpu_user_features2 = COMMON_USER2_POWER7, 357 - .mmu_features = MMU_FTRS_POWER7, 358 - .icache_bsize = 128, 359 - .dcache_bsize = 128, 360 - .num_pmcs = 6, 361 - .pmc_type = PPC_PMC_IBM, 362 - .cpu_setup = __setup_cpu_power7, 363 - .cpu_restore = __restore_cpu_power7, 364 - .machine_check_early = __machine_check_early_realmode_p7, 365 - .platform = "power7", 366 - }, 367 - { /* Power7+ */ 368 - .pvr_mask = 0xffff0000, 369 - .pvr_value = 0x004A0000, 370 - .cpu_name = "POWER7+ (raw)", 371 - .cpu_features = CPU_FTRS_POWER7, 372 - .cpu_user_features = COMMON_USER_POWER7, 373 - .cpu_user_features2 = COMMON_USER2_POWER7, 374 - .mmu_features = MMU_FTRS_POWER7, 375 - .icache_bsize = 128, 376 - .dcache_bsize = 128, 377 - .num_pmcs = 6, 378 - .pmc_type = PPC_PMC_IBM, 379 - .cpu_setup = __setup_cpu_power7, 380 - .cpu_restore = __restore_cpu_power7, 381 - .machine_check_early = __machine_check_early_realmode_p7, 382 - .platform = "power7+", 383 - }, 384 - { /* Power8E */ 385 - .pvr_mask = 0xffff0000, 386 - .pvr_value = 0x004b0000, 387 - .cpu_name = "POWER8E (raw)", 388 - .cpu_features = CPU_FTRS_POWER8E, 389 - .cpu_user_features = COMMON_USER_POWER8, 390 - .cpu_user_features2 = COMMON_USER2_POWER8, 391 - .mmu_features = MMU_FTRS_POWER8, 392 - .icache_bsize = 128, 393 - .dcache_bsize = 128, 394 - .num_pmcs = 6, 395 - .pmc_type = PPC_PMC_IBM, 396 - .cpu_setup = __setup_cpu_power8, 397 - .cpu_restore = __restore_cpu_power8, 398 - .machine_check_early = __machine_check_early_realmode_p8, 399 - .platform = "power8", 400 - }, 401 - { /* Power8NVL */ 402 - .pvr_mask = 0xffff0000, 403 - .pvr_value = 0x004c0000, 404 - .cpu_name = "POWER8NVL (raw)", 405 - .cpu_features = CPU_FTRS_POWER8, 406 - .cpu_user_features = COMMON_USER_POWER8, 407 - .cpu_user_features2 = COMMON_USER2_POWER8, 408 - .mmu_features = MMU_FTRS_POWER8, 409 - .icache_bsize = 128, 410 - .dcache_bsize = 128, 411 - .num_pmcs = 6, 412 - .pmc_type = PPC_PMC_IBM, 413 - .cpu_setup = __setup_cpu_power8, 414 - .cpu_restore = __restore_cpu_power8, 415 - .machine_check_early = __machine_check_early_realmode_p8, 416 - .platform = "power8", 417 - }, 418 - { /* Power8 */ 419 - .pvr_mask = 0xffff0000, 420 - .pvr_value = 0x004d0000, 421 - .cpu_name = "POWER8 (raw)", 422 - .cpu_features = CPU_FTRS_POWER8, 423 - .cpu_user_features = COMMON_USER_POWER8, 424 - .cpu_user_features2 = COMMON_USER2_POWER8, 425 - .mmu_features = MMU_FTRS_POWER8, 426 - .icache_bsize = 128, 427 - .dcache_bsize = 128, 428 - .num_pmcs = 6, 429 - .pmc_type = PPC_PMC_IBM, 430 - .cpu_setup = __setup_cpu_power8, 431 - .cpu_restore = __restore_cpu_power8, 432 - .machine_check_early = __machine_check_early_realmode_p8, 433 - .platform = "power8", 434 - }, 435 - { /* Power9 DD2.0 */ 436 - .pvr_mask = 0xffffefff, 437 - .pvr_value = 0x004e0200, 438 - .cpu_name = "POWER9 (raw)", 439 - .cpu_features = CPU_FTRS_POWER9_DD2_0, 440 - .cpu_user_features = COMMON_USER_POWER9, 441 - .cpu_user_features2 = COMMON_USER2_POWER9, 442 - .mmu_features = MMU_FTRS_POWER9, 443 - .icache_bsize = 128, 444 - .dcache_bsize = 128, 445 - .num_pmcs = 6, 446 - .pmc_type = PPC_PMC_IBM, 447 - .cpu_setup = __setup_cpu_power9, 448 - .cpu_restore = __restore_cpu_power9, 449 - .machine_check_early = __machine_check_early_realmode_p9, 450 - .platform = "power9", 451 - }, 452 - { /* Power9 DD 2.1 */ 453 - .pvr_mask = 0xffffefff, 454 - .pvr_value = 0x004e0201, 455 - .cpu_name = "POWER9 (raw)", 456 - .cpu_features = CPU_FTRS_POWER9_DD2_1, 457 - .cpu_user_features = COMMON_USER_POWER9, 458 - .cpu_user_features2 = COMMON_USER2_POWER9, 459 - .mmu_features = MMU_FTRS_POWER9, 460 - .icache_bsize = 128, 461 - .dcache_bsize = 128, 462 - .num_pmcs = 6, 463 - .pmc_type = PPC_PMC_IBM, 464 - .cpu_setup = __setup_cpu_power9, 465 - .cpu_restore = __restore_cpu_power9, 466 - .machine_check_early = __machine_check_early_realmode_p9, 467 - .platform = "power9", 468 - }, 469 - { /* Power9 DD2.2 */ 470 - .pvr_mask = 0xffffefff, 471 - .pvr_value = 0x004e0202, 472 - .cpu_name = "POWER9 (raw)", 473 - .cpu_features = CPU_FTRS_POWER9_DD2_2, 474 - .cpu_user_features = COMMON_USER_POWER9, 475 - .cpu_user_features2 = COMMON_USER2_POWER9, 476 - .mmu_features = MMU_FTRS_POWER9, 477 - .icache_bsize = 128, 478 - .dcache_bsize = 128, 479 - .num_pmcs = 6, 480 - .pmc_type = PPC_PMC_IBM, 481 - .cpu_setup = __setup_cpu_power9, 482 - .cpu_restore = __restore_cpu_power9, 483 - .machine_check_early = __machine_check_early_realmode_p9, 484 - .platform = "power9", 485 - }, 486 - { /* Power9 DD2.3 or later */ 487 - .pvr_mask = 0xffff0000, 488 - .pvr_value = 0x004e0000, 489 - .cpu_name = "POWER9 (raw)", 490 - .cpu_features = CPU_FTRS_POWER9_DD2_3, 491 - .cpu_user_features = COMMON_USER_POWER9, 492 - .cpu_user_features2 = COMMON_USER2_POWER9, 493 - .mmu_features = MMU_FTRS_POWER9, 494 - .icache_bsize = 128, 495 - .dcache_bsize = 128, 496 - .num_pmcs = 6, 497 - .pmc_type = PPC_PMC_IBM, 498 - .cpu_setup = __setup_cpu_power9, 499 - .cpu_restore = __restore_cpu_power9, 500 - .machine_check_early = __machine_check_early_realmode_p9, 501 - .platform = "power9", 502 - }, 503 - { /* Power10 */ 504 - .pvr_mask = 0xffff0000, 505 - .pvr_value = 0x00800000, 506 - .cpu_name = "POWER10 (raw)", 507 - .cpu_features = CPU_FTRS_POWER10, 508 - .cpu_user_features = COMMON_USER_POWER10, 509 - .cpu_user_features2 = COMMON_USER2_POWER10, 510 - .mmu_features = MMU_FTRS_POWER10, 511 - .icache_bsize = 128, 512 - .dcache_bsize = 128, 513 - .num_pmcs = 6, 514 - .pmc_type = PPC_PMC_IBM, 515 - .cpu_setup = __setup_cpu_power10, 516 - .cpu_restore = __restore_cpu_power10, 517 - .machine_check_early = __machine_check_early_realmode_p10, 518 - .platform = "power10", 519 - }, 520 - { /* Cell Broadband Engine */ 521 - .pvr_mask = 0xffff0000, 522 - .pvr_value = 0x00700000, 523 - .cpu_name = "Cell Broadband Engine", 524 - .cpu_features = CPU_FTRS_CELL, 525 - .cpu_user_features = COMMON_USER_PPC64 | 526 - PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP | 527 - PPC_FEATURE_SMT, 528 - .mmu_features = MMU_FTRS_CELL, 529 - .icache_bsize = 128, 530 - .dcache_bsize = 128, 531 - .num_pmcs = 4, 532 - .pmc_type = PPC_PMC_IBM, 533 - .platform = "ppc-cell-be", 534 - }, 535 - { /* PA Semi PA6T */ 536 - .pvr_mask = 0x7fff0000, 537 - .pvr_value = 0x00900000, 538 - .cpu_name = "PA6T", 539 - .cpu_features = CPU_FTRS_PA6T, 540 - .cpu_user_features = COMMON_USER_PA6T, 541 - .mmu_features = MMU_FTRS_PA6T, 542 - .icache_bsize = 64, 543 - .dcache_bsize = 64, 544 - .num_pmcs = 6, 545 - .pmc_type = PPC_PMC_PA6T, 546 - .cpu_setup = __setup_cpu_pa6t, 547 - .cpu_restore = __restore_cpu_pa6t, 548 - .platform = "pa6t", 549 - }, 550 - { /* default match */ 551 - .pvr_mask = 0x00000000, 552 - .pvr_value = 0x00000000, 553 - .cpu_name = "POWER5 (compatible)", 554 - .cpu_features = CPU_FTRS_COMPATIBLE, 555 - .cpu_user_features = COMMON_USER_PPC64, 556 - .mmu_features = MMU_FTRS_POWER, 557 - .icache_bsize = 128, 558 - .dcache_bsize = 128, 559 - .num_pmcs = 6, 560 - .pmc_type = PPC_PMC_IBM, 561 - .platform = "power5", 562 - } 563 - #endif /* CONFIG_PPC_BOOK3S_64 */ 564 - 565 - #ifdef CONFIG_PPC32 566 - #ifdef CONFIG_PPC_BOOK3S_32 567 - #ifdef CONFIG_PPC_BOOK3S_604 568 - { /* 604 */ 569 - .pvr_mask = 0xffff0000, 570 - .pvr_value = 0x00040000, 571 - .cpu_name = "604", 572 - .cpu_features = CPU_FTRS_604, 573 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 574 - .mmu_features = MMU_FTR_HPTE_TABLE, 575 - .icache_bsize = 32, 576 - .dcache_bsize = 32, 577 - .num_pmcs = 2, 578 - .cpu_setup = __setup_cpu_604, 579 - .machine_check = machine_check_generic, 580 - .platform = "ppc604", 581 - }, 582 - { /* 604e */ 583 - .pvr_mask = 0xfffff000, 584 - .pvr_value = 0x00090000, 585 - .cpu_name = "604e", 586 - .cpu_features = CPU_FTRS_604, 587 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 588 - .mmu_features = MMU_FTR_HPTE_TABLE, 589 - .icache_bsize = 32, 590 - .dcache_bsize = 32, 591 - .num_pmcs = 4, 592 - .cpu_setup = __setup_cpu_604, 593 - .machine_check = machine_check_generic, 594 - .platform = "ppc604", 595 - }, 596 - { /* 604r */ 597 - .pvr_mask = 0xffff0000, 598 - .pvr_value = 0x00090000, 599 - .cpu_name = "604r", 600 - .cpu_features = CPU_FTRS_604, 601 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 602 - .mmu_features = MMU_FTR_HPTE_TABLE, 603 - .icache_bsize = 32, 604 - .dcache_bsize = 32, 605 - .num_pmcs = 4, 606 - .cpu_setup = __setup_cpu_604, 607 - .machine_check = machine_check_generic, 608 - .platform = "ppc604", 609 - }, 610 - { /* 604ev */ 611 - .pvr_mask = 0xffff0000, 612 - .pvr_value = 0x000a0000, 613 - .cpu_name = "604ev", 614 - .cpu_features = CPU_FTRS_604, 615 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 616 - .mmu_features = MMU_FTR_HPTE_TABLE, 617 - .icache_bsize = 32, 618 - .dcache_bsize = 32, 619 - .num_pmcs = 4, 620 - .cpu_setup = __setup_cpu_604, 621 - .machine_check = machine_check_generic, 622 - .platform = "ppc604", 623 - }, 624 - { /* 740/750 (0x4202, don't support TAU ?) */ 625 - .pvr_mask = 0xffffffff, 626 - .pvr_value = 0x00084202, 627 - .cpu_name = "740/750", 628 - .cpu_features = CPU_FTRS_740_NOTAU, 629 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 630 - .mmu_features = MMU_FTR_HPTE_TABLE, 631 - .icache_bsize = 32, 632 - .dcache_bsize = 32, 633 - .num_pmcs = 4, 634 - .cpu_setup = __setup_cpu_750, 635 - .machine_check = machine_check_generic, 636 - .platform = "ppc750", 637 - }, 638 - { /* 750CX (80100 and 8010x?) */ 639 - .pvr_mask = 0xfffffff0, 640 - .pvr_value = 0x00080100, 641 - .cpu_name = "750CX", 642 - .cpu_features = CPU_FTRS_750, 643 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 644 - .mmu_features = MMU_FTR_HPTE_TABLE, 645 - .icache_bsize = 32, 646 - .dcache_bsize = 32, 647 - .num_pmcs = 4, 648 - .cpu_setup = __setup_cpu_750cx, 649 - .machine_check = machine_check_generic, 650 - .platform = "ppc750", 651 - }, 652 - { /* 750CX (82201 and 82202) */ 653 - .pvr_mask = 0xfffffff0, 654 - .pvr_value = 0x00082200, 655 - .cpu_name = "750CX", 656 - .cpu_features = CPU_FTRS_750, 657 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 658 - .mmu_features = MMU_FTR_HPTE_TABLE, 659 - .icache_bsize = 32, 660 - .dcache_bsize = 32, 661 - .num_pmcs = 4, 662 - .pmc_type = PPC_PMC_IBM, 663 - .cpu_setup = __setup_cpu_750cx, 664 - .machine_check = machine_check_generic, 665 - .platform = "ppc750", 666 - }, 667 - { /* 750CXe (82214) */ 668 - .pvr_mask = 0xfffffff0, 669 - .pvr_value = 0x00082210, 670 - .cpu_name = "750CXe", 671 - .cpu_features = CPU_FTRS_750, 672 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 673 - .mmu_features = MMU_FTR_HPTE_TABLE, 674 - .icache_bsize = 32, 675 - .dcache_bsize = 32, 676 - .num_pmcs = 4, 677 - .pmc_type = PPC_PMC_IBM, 678 - .cpu_setup = __setup_cpu_750cx, 679 - .machine_check = machine_check_generic, 680 - .platform = "ppc750", 681 - }, 682 - { /* 750CXe "Gekko" (83214) */ 683 - .pvr_mask = 0xffffffff, 684 - .pvr_value = 0x00083214, 685 - .cpu_name = "750CXe", 686 - .cpu_features = CPU_FTRS_750, 687 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 688 - .mmu_features = MMU_FTR_HPTE_TABLE, 689 - .icache_bsize = 32, 690 - .dcache_bsize = 32, 691 - .num_pmcs = 4, 692 - .pmc_type = PPC_PMC_IBM, 693 - .cpu_setup = __setup_cpu_750cx, 694 - .machine_check = machine_check_generic, 695 - .platform = "ppc750", 696 - }, 697 - { /* 750CL (and "Broadway") */ 698 - .pvr_mask = 0xfffff0e0, 699 - .pvr_value = 0x00087000, 700 - .cpu_name = "750CL", 701 - .cpu_features = CPU_FTRS_750CL, 702 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 703 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 704 - .icache_bsize = 32, 705 - .dcache_bsize = 32, 706 - .num_pmcs = 4, 707 - .pmc_type = PPC_PMC_IBM, 708 - .cpu_setup = __setup_cpu_750, 709 - .machine_check = machine_check_generic, 710 - .platform = "ppc750", 711 - }, 712 - { /* 745/755 */ 713 - .pvr_mask = 0xfffff000, 714 - .pvr_value = 0x00083000, 715 - .cpu_name = "745/755", 716 - .cpu_features = CPU_FTRS_750, 717 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 718 - .mmu_features = MMU_FTR_HPTE_TABLE, 719 - .icache_bsize = 32, 720 - .dcache_bsize = 32, 721 - .num_pmcs = 4, 722 - .pmc_type = PPC_PMC_IBM, 723 - .cpu_setup = __setup_cpu_750, 724 - .machine_check = machine_check_generic, 725 - .platform = "ppc750", 726 - }, 727 - { /* 750FX rev 1.x */ 728 - .pvr_mask = 0xffffff00, 729 - .pvr_value = 0x70000100, 730 - .cpu_name = "750FX", 731 - .cpu_features = CPU_FTRS_750FX1, 732 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 733 - .mmu_features = MMU_FTR_HPTE_TABLE, 734 - .icache_bsize = 32, 735 - .dcache_bsize = 32, 736 - .num_pmcs = 4, 737 - .pmc_type = PPC_PMC_IBM, 738 - .cpu_setup = __setup_cpu_750, 739 - .machine_check = machine_check_generic, 740 - .platform = "ppc750", 741 - }, 742 - { /* 750FX rev 2.0 must disable HID0[DPM] */ 743 - .pvr_mask = 0xffffffff, 744 - .pvr_value = 0x70000200, 745 - .cpu_name = "750FX", 746 - .cpu_features = CPU_FTRS_750FX2, 747 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 748 - .mmu_features = MMU_FTR_HPTE_TABLE, 749 - .icache_bsize = 32, 750 - .dcache_bsize = 32, 751 - .num_pmcs = 4, 752 - .pmc_type = PPC_PMC_IBM, 753 - .cpu_setup = __setup_cpu_750, 754 - .machine_check = machine_check_generic, 755 - .platform = "ppc750", 756 - }, 757 - { /* 750FX (All revs except 2.0) */ 758 - .pvr_mask = 0xffff0000, 759 - .pvr_value = 0x70000000, 760 - .cpu_name = "750FX", 761 - .cpu_features = CPU_FTRS_750FX, 762 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 763 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 764 - .icache_bsize = 32, 765 - .dcache_bsize = 32, 766 - .num_pmcs = 4, 767 - .pmc_type = PPC_PMC_IBM, 768 - .cpu_setup = __setup_cpu_750fx, 769 - .machine_check = machine_check_generic, 770 - .platform = "ppc750", 771 - }, 772 - { /* 750GX */ 773 - .pvr_mask = 0xffff0000, 774 - .pvr_value = 0x70020000, 775 - .cpu_name = "750GX", 776 - .cpu_features = CPU_FTRS_750GX, 777 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 778 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 779 - .icache_bsize = 32, 780 - .dcache_bsize = 32, 781 - .num_pmcs = 4, 782 - .pmc_type = PPC_PMC_IBM, 783 - .cpu_setup = __setup_cpu_750fx, 784 - .machine_check = machine_check_generic, 785 - .platform = "ppc750", 786 - }, 787 - { /* 740/750 (L2CR bit need fixup for 740) */ 788 - .pvr_mask = 0xffff0000, 789 - .pvr_value = 0x00080000, 790 - .cpu_name = "740/750", 791 - .cpu_features = CPU_FTRS_740, 792 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 793 - .mmu_features = MMU_FTR_HPTE_TABLE, 794 - .icache_bsize = 32, 795 - .dcache_bsize = 32, 796 - .num_pmcs = 4, 797 - .pmc_type = PPC_PMC_IBM, 798 - .cpu_setup = __setup_cpu_750, 799 - .machine_check = machine_check_generic, 800 - .platform = "ppc750", 801 - }, 802 - { /* 7400 rev 1.1 ? (no TAU) */ 803 - .pvr_mask = 0xffffffff, 804 - .pvr_value = 0x000c1101, 805 - .cpu_name = "7400 (1.1)", 806 - .cpu_features = CPU_FTRS_7400_NOTAU, 807 - .cpu_user_features = COMMON_USER | 808 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 809 - .mmu_features = MMU_FTR_HPTE_TABLE, 810 - .icache_bsize = 32, 811 - .dcache_bsize = 32, 812 - .num_pmcs = 4, 813 - .pmc_type = PPC_PMC_G4, 814 - .cpu_setup = __setup_cpu_7400, 815 - .machine_check = machine_check_generic, 816 - .platform = "ppc7400", 817 - }, 818 - { /* 7400 */ 819 - .pvr_mask = 0xffff0000, 820 - .pvr_value = 0x000c0000, 821 - .cpu_name = "7400", 822 - .cpu_features = CPU_FTRS_7400, 823 - .cpu_user_features = COMMON_USER | 824 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 825 - .mmu_features = MMU_FTR_HPTE_TABLE, 826 - .icache_bsize = 32, 827 - .dcache_bsize = 32, 828 - .num_pmcs = 4, 829 - .pmc_type = PPC_PMC_G4, 830 - .cpu_setup = __setup_cpu_7400, 831 - .machine_check = machine_check_generic, 832 - .platform = "ppc7400", 833 - }, 834 - { /* 7410 */ 835 - .pvr_mask = 0xffff0000, 836 - .pvr_value = 0x800c0000, 837 - .cpu_name = "7410", 838 - .cpu_features = CPU_FTRS_7400, 839 - .cpu_user_features = COMMON_USER | 840 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 841 - .mmu_features = MMU_FTR_HPTE_TABLE, 842 - .icache_bsize = 32, 843 - .dcache_bsize = 32, 844 - .num_pmcs = 4, 845 - .pmc_type = PPC_PMC_G4, 846 - .cpu_setup = __setup_cpu_7410, 847 - .machine_check = machine_check_generic, 848 - .platform = "ppc7400", 849 - }, 850 - { /* 7450 2.0 - no doze/nap */ 851 - .pvr_mask = 0xffffffff, 852 - .pvr_value = 0x80000200, 853 - .cpu_name = "7450", 854 - .cpu_features = CPU_FTRS_7450_20, 855 - .cpu_user_features = COMMON_USER | 856 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 857 - .mmu_features = MMU_FTR_HPTE_TABLE, 858 - .icache_bsize = 32, 859 - .dcache_bsize = 32, 860 - .num_pmcs = 6, 861 - .pmc_type = PPC_PMC_G4, 862 - .cpu_setup = __setup_cpu_745x, 863 - .machine_check = machine_check_generic, 864 - .platform = "ppc7450", 865 - }, 866 - { /* 7450 2.1 */ 867 - .pvr_mask = 0xffffffff, 868 - .pvr_value = 0x80000201, 869 - .cpu_name = "7450", 870 - .cpu_features = CPU_FTRS_7450_21, 871 - .cpu_user_features = COMMON_USER | 872 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 873 - .mmu_features = MMU_FTR_HPTE_TABLE, 874 - .icache_bsize = 32, 875 - .dcache_bsize = 32, 876 - .num_pmcs = 6, 877 - .pmc_type = PPC_PMC_G4, 878 - .cpu_setup = __setup_cpu_745x, 879 - .machine_check = machine_check_generic, 880 - .platform = "ppc7450", 881 - }, 882 - { /* 7450 2.3 and newer */ 883 - .pvr_mask = 0xffff0000, 884 - .pvr_value = 0x80000000, 885 - .cpu_name = "7450", 886 - .cpu_features = CPU_FTRS_7450_23, 887 - .cpu_user_features = COMMON_USER | 888 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 889 - .mmu_features = MMU_FTR_HPTE_TABLE, 890 - .icache_bsize = 32, 891 - .dcache_bsize = 32, 892 - .num_pmcs = 6, 893 - .pmc_type = PPC_PMC_G4, 894 - .cpu_setup = __setup_cpu_745x, 895 - .machine_check = machine_check_generic, 896 - .platform = "ppc7450", 897 - }, 898 - { /* 7455 rev 1.x */ 899 - .pvr_mask = 0xffffff00, 900 - .pvr_value = 0x80010100, 901 - .cpu_name = "7455", 902 - .cpu_features = CPU_FTRS_7455_1, 903 - .cpu_user_features = COMMON_USER | 904 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 905 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 906 - .icache_bsize = 32, 907 - .dcache_bsize = 32, 908 - .num_pmcs = 6, 909 - .pmc_type = PPC_PMC_G4, 910 - .cpu_setup = __setup_cpu_745x, 911 - .machine_check = machine_check_generic, 912 - .platform = "ppc7450", 913 - }, 914 - { /* 7455 rev 2.0 */ 915 - .pvr_mask = 0xffffffff, 916 - .pvr_value = 0x80010200, 917 - .cpu_name = "7455", 918 - .cpu_features = CPU_FTRS_7455_20, 919 - .cpu_user_features = COMMON_USER | 920 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 921 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 922 - .icache_bsize = 32, 923 - .dcache_bsize = 32, 924 - .num_pmcs = 6, 925 - .pmc_type = PPC_PMC_G4, 926 - .cpu_setup = __setup_cpu_745x, 927 - .machine_check = machine_check_generic, 928 - .platform = "ppc7450", 929 - }, 930 - { /* 7455 others */ 931 - .pvr_mask = 0xffff0000, 932 - .pvr_value = 0x80010000, 933 - .cpu_name = "7455", 934 - .cpu_features = CPU_FTRS_7455, 935 - .cpu_user_features = COMMON_USER | 936 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 937 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 938 - .icache_bsize = 32, 939 - .dcache_bsize = 32, 940 - .num_pmcs = 6, 941 - .pmc_type = PPC_PMC_G4, 942 - .cpu_setup = __setup_cpu_745x, 943 - .machine_check = machine_check_generic, 944 - .platform = "ppc7450", 945 - }, 946 - { /* 7447/7457 Rev 1.0 */ 947 - .pvr_mask = 0xffffffff, 948 - .pvr_value = 0x80020100, 949 - .cpu_name = "7447/7457", 950 - .cpu_features = CPU_FTRS_7447_10, 951 - .cpu_user_features = COMMON_USER | 952 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 953 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 954 - .icache_bsize = 32, 955 - .dcache_bsize = 32, 956 - .num_pmcs = 6, 957 - .pmc_type = PPC_PMC_G4, 958 - .cpu_setup = __setup_cpu_745x, 959 - .machine_check = machine_check_generic, 960 - .platform = "ppc7450", 961 - }, 962 - { /* 7447/7457 Rev 1.1 */ 963 - .pvr_mask = 0xffffffff, 964 - .pvr_value = 0x80020101, 965 - .cpu_name = "7447/7457", 966 - .cpu_features = CPU_FTRS_7447_10, 967 - .cpu_user_features = COMMON_USER | 968 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 969 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 970 - .icache_bsize = 32, 971 - .dcache_bsize = 32, 972 - .num_pmcs = 6, 973 - .pmc_type = PPC_PMC_G4, 974 - .cpu_setup = __setup_cpu_745x, 975 - .machine_check = machine_check_generic, 976 - .platform = "ppc7450", 977 - }, 978 - { /* 7447/7457 Rev 1.2 and later */ 979 - .pvr_mask = 0xffff0000, 980 - .pvr_value = 0x80020000, 981 - .cpu_name = "7447/7457", 982 - .cpu_features = CPU_FTRS_7447, 983 - .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 984 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 985 - .icache_bsize = 32, 986 - .dcache_bsize = 32, 987 - .num_pmcs = 6, 988 - .pmc_type = PPC_PMC_G4, 989 - .cpu_setup = __setup_cpu_745x, 990 - .machine_check = machine_check_generic, 991 - .platform = "ppc7450", 992 - }, 993 - { /* 7447A */ 994 - .pvr_mask = 0xffff0000, 995 - .pvr_value = 0x80030000, 996 - .cpu_name = "7447A", 997 - .cpu_features = CPU_FTRS_7447A, 998 - .cpu_user_features = COMMON_USER | 999 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 1000 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 1001 - .icache_bsize = 32, 1002 - .dcache_bsize = 32, 1003 - .num_pmcs = 6, 1004 - .pmc_type = PPC_PMC_G4, 1005 - .cpu_setup = __setup_cpu_745x, 1006 - .machine_check = machine_check_generic, 1007 - .platform = "ppc7450", 1008 - }, 1009 - { /* 7448 */ 1010 - .pvr_mask = 0xffff0000, 1011 - .pvr_value = 0x80040000, 1012 - .cpu_name = "7448", 1013 - .cpu_features = CPU_FTRS_7448, 1014 - .cpu_user_features = COMMON_USER | 1015 - PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, 1016 - .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, 1017 - .icache_bsize = 32, 1018 - .dcache_bsize = 32, 1019 - .num_pmcs = 6, 1020 - .pmc_type = PPC_PMC_G4, 1021 - .cpu_setup = __setup_cpu_745x, 1022 - .machine_check = machine_check_generic, 1023 - .platform = "ppc7450", 1024 - }, 1025 - #endif /* CONFIG_PPC_BOOK3S_604 */ 1026 - #ifdef CONFIG_PPC_BOOK3S_603 1027 - { /* 603 */ 1028 - .pvr_mask = 0xffff0000, 1029 - .pvr_value = 0x00030000, 1030 - .cpu_name = "603", 1031 - .cpu_features = CPU_FTRS_603, 1032 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 1033 - .mmu_features = 0, 1034 - .icache_bsize = 32, 1035 - .dcache_bsize = 32, 1036 - .cpu_setup = __setup_cpu_603, 1037 - .machine_check = machine_check_generic, 1038 - .platform = "ppc603", 1039 - }, 1040 - { /* 603e */ 1041 - .pvr_mask = 0xffff0000, 1042 - .pvr_value = 0x00060000, 1043 - .cpu_name = "603e", 1044 - .cpu_features = CPU_FTRS_603, 1045 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 1046 - .mmu_features = 0, 1047 - .icache_bsize = 32, 1048 - .dcache_bsize = 32, 1049 - .cpu_setup = __setup_cpu_603, 1050 - .machine_check = machine_check_generic, 1051 - .platform = "ppc603", 1052 - }, 1053 - { /* 603ev */ 1054 - .pvr_mask = 0xffff0000, 1055 - .pvr_value = 0x00070000, 1056 - .cpu_name = "603ev", 1057 - .cpu_features = CPU_FTRS_603, 1058 - .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, 1059 - .mmu_features = 0, 1060 - .icache_bsize = 32, 1061 - .dcache_bsize = 32, 1062 - .cpu_setup = __setup_cpu_603, 1063 - .machine_check = machine_check_generic, 1064 - .platform = "ppc603", 1065 - }, 1066 - { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 1067 - .pvr_mask = 0x7fff0000, 1068 - .pvr_value = 0x00810000, 1069 - .cpu_name = "82xx", 1070 - .cpu_features = CPU_FTRS_82XX, 1071 - .cpu_user_features = COMMON_USER, 1072 - .mmu_features = 0, 1073 - .icache_bsize = 32, 1074 - .dcache_bsize = 32, 1075 - .cpu_setup = __setup_cpu_603, 1076 - .machine_check = machine_check_generic, 1077 - .platform = "ppc603", 1078 - }, 1079 - { /* All G2_LE (603e core, plus some) have the same pvr */ 1080 - .pvr_mask = 0x7fff0000, 1081 - .pvr_value = 0x00820000, 1082 - .cpu_name = "G2_LE", 1083 - .cpu_features = CPU_FTRS_G2_LE, 1084 - .cpu_user_features = COMMON_USER, 1085 - .mmu_features = MMU_FTR_USE_HIGH_BATS, 1086 - .icache_bsize = 32, 1087 - .dcache_bsize = 32, 1088 - .cpu_setup = __setup_cpu_603, 1089 - .machine_check = machine_check_generic, 1090 - .platform = "ppc603", 1091 - }, 1092 - #ifdef CONFIG_PPC_83xx 1093 - { /* e300c1 (a 603e core, plus some) on 83xx */ 1094 - .pvr_mask = 0x7fff0000, 1095 - .pvr_value = 0x00830000, 1096 - .cpu_name = "e300c1", 1097 - .cpu_features = CPU_FTRS_E300, 1098 - .cpu_user_features = COMMON_USER, 1099 - .mmu_features = MMU_FTR_USE_HIGH_BATS, 1100 - .icache_bsize = 32, 1101 - .dcache_bsize = 32, 1102 - .cpu_setup = __setup_cpu_603, 1103 - .machine_check = machine_check_83xx, 1104 - .platform = "ppc603", 1105 - }, 1106 - { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */ 1107 - .pvr_mask = 0x7fff0000, 1108 - .pvr_value = 0x00840000, 1109 - .cpu_name = "e300c2", 1110 - .cpu_features = CPU_FTRS_E300C2, 1111 - .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1112 - .mmu_features = MMU_FTR_USE_HIGH_BATS | 1113 - MMU_FTR_NEED_DTLB_SW_LRU, 1114 - .icache_bsize = 32, 1115 - .dcache_bsize = 32, 1116 - .cpu_setup = __setup_cpu_603, 1117 - .machine_check = machine_check_83xx, 1118 - .platform = "ppc603", 1119 - }, 1120 - { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */ 1121 - .pvr_mask = 0x7fff0000, 1122 - .pvr_value = 0x00850000, 1123 - .cpu_name = "e300c3", 1124 - .cpu_features = CPU_FTRS_E300, 1125 - .cpu_user_features = COMMON_USER, 1126 - .mmu_features = MMU_FTR_USE_HIGH_BATS | 1127 - MMU_FTR_NEED_DTLB_SW_LRU, 1128 - .icache_bsize = 32, 1129 - .dcache_bsize = 32, 1130 - .cpu_setup = __setup_cpu_603, 1131 - .machine_check = machine_check_83xx, 1132 - .num_pmcs = 4, 1133 - .platform = "ppc603", 1134 - }, 1135 - { /* e300c4 (e300c1, plus one IU) */ 1136 - .pvr_mask = 0x7fff0000, 1137 - .pvr_value = 0x00860000, 1138 - .cpu_name = "e300c4", 1139 - .cpu_features = CPU_FTRS_E300, 1140 - .cpu_user_features = COMMON_USER, 1141 - .mmu_features = MMU_FTR_USE_HIGH_BATS | 1142 - MMU_FTR_NEED_DTLB_SW_LRU, 1143 - .icache_bsize = 32, 1144 - .dcache_bsize = 32, 1145 - .cpu_setup = __setup_cpu_603, 1146 - .machine_check = machine_check_83xx, 1147 - .num_pmcs = 4, 1148 - .platform = "ppc603", 1149 - }, 1150 - #endif 1151 - #endif /* CONFIG_PPC_BOOK3S_603 */ 1152 - #ifdef CONFIG_PPC_BOOK3S_604 1153 - { /* default match, we assume split I/D cache & TB (non-601)... */ 1154 - .pvr_mask = 0x00000000, 1155 - .pvr_value = 0x00000000, 1156 - .cpu_name = "(generic PPC)", 1157 - .cpu_features = CPU_FTRS_CLASSIC32, 1158 - .cpu_user_features = COMMON_USER, 1159 - .mmu_features = MMU_FTR_HPTE_TABLE, 1160 - .icache_bsize = 32, 1161 - .dcache_bsize = 32, 1162 - .machine_check = machine_check_generic, 1163 - .platform = "ppc603", 1164 - }, 1165 - #endif /* CONFIG_PPC_BOOK3S_604 */ 1166 - #endif /* CONFIG_PPC_BOOK3S_32 */ 1167 - #ifdef CONFIG_PPC_8xx 1168 - { /* 8xx */ 1169 - .pvr_mask = 0xffff0000, 1170 - .pvr_value = PVR_8xx, 1171 - .cpu_name = "8xx", 1172 - /* CPU_FTR_MAYBE_CAN_DOZE is possible, 1173 - * if the 8xx code is there.... */ 1174 - .cpu_features = CPU_FTRS_8XX, 1175 - .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1176 - .mmu_features = MMU_FTR_TYPE_8xx, 1177 - .icache_bsize = 16, 1178 - .dcache_bsize = 16, 1179 - .machine_check = machine_check_8xx, 1180 - .platform = "ppc823", 1181 - }, 1182 - #endif /* CONFIG_PPC_8xx */ 1183 - #ifdef CONFIG_40x 1184 - { /* STB 04xxx */ 1185 - .pvr_mask = 0xffff0000, 1186 - .pvr_value = 0x41810000, 1187 - .cpu_name = "STB04xxx", 1188 - .cpu_features = CPU_FTRS_40X, 1189 - .cpu_user_features = PPC_FEATURE_32 | 1190 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1191 - .mmu_features = MMU_FTR_TYPE_40x, 1192 - .icache_bsize = 32, 1193 - .dcache_bsize = 32, 1194 - .machine_check = machine_check_4xx, 1195 - .platform = "ppc405", 1196 - }, 1197 - { /* NP405L */ 1198 - .pvr_mask = 0xffff0000, 1199 - .pvr_value = 0x41610000, 1200 - .cpu_name = "NP405L", 1201 - .cpu_features = CPU_FTRS_40X, 1202 - .cpu_user_features = PPC_FEATURE_32 | 1203 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1204 - .mmu_features = MMU_FTR_TYPE_40x, 1205 - .icache_bsize = 32, 1206 - .dcache_bsize = 32, 1207 - .machine_check = machine_check_4xx, 1208 - .platform = "ppc405", 1209 - }, 1210 - { /* NP4GS3 */ 1211 - .pvr_mask = 0xffff0000, 1212 - .pvr_value = 0x40B10000, 1213 - .cpu_name = "NP4GS3", 1214 - .cpu_features = CPU_FTRS_40X, 1215 - .cpu_user_features = PPC_FEATURE_32 | 1216 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1217 - .mmu_features = MMU_FTR_TYPE_40x, 1218 - .icache_bsize = 32, 1219 - .dcache_bsize = 32, 1220 - .machine_check = machine_check_4xx, 1221 - .platform = "ppc405", 1222 - }, 1223 - { /* NP405H */ 1224 - .pvr_mask = 0xffff0000, 1225 - .pvr_value = 0x41410000, 1226 - .cpu_name = "NP405H", 1227 - .cpu_features = CPU_FTRS_40X, 1228 - .cpu_user_features = PPC_FEATURE_32 | 1229 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1230 - .mmu_features = MMU_FTR_TYPE_40x, 1231 - .icache_bsize = 32, 1232 - .dcache_bsize = 32, 1233 - .machine_check = machine_check_4xx, 1234 - .platform = "ppc405", 1235 - }, 1236 - { /* 405GPr */ 1237 - .pvr_mask = 0xffff0000, 1238 - .pvr_value = 0x50910000, 1239 - .cpu_name = "405GPr", 1240 - .cpu_features = CPU_FTRS_40X, 1241 - .cpu_user_features = PPC_FEATURE_32 | 1242 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1243 - .mmu_features = MMU_FTR_TYPE_40x, 1244 - .icache_bsize = 32, 1245 - .dcache_bsize = 32, 1246 - .machine_check = machine_check_4xx, 1247 - .platform = "ppc405", 1248 - }, 1249 - { /* STBx25xx */ 1250 - .pvr_mask = 0xffff0000, 1251 - .pvr_value = 0x51510000, 1252 - .cpu_name = "STBx25xx", 1253 - .cpu_features = CPU_FTRS_40X, 1254 - .cpu_user_features = PPC_FEATURE_32 | 1255 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1256 - .mmu_features = MMU_FTR_TYPE_40x, 1257 - .icache_bsize = 32, 1258 - .dcache_bsize = 32, 1259 - .machine_check = machine_check_4xx, 1260 - .platform = "ppc405", 1261 - }, 1262 - { /* 405LP */ 1263 - .pvr_mask = 0xffff0000, 1264 - .pvr_value = 0x41F10000, 1265 - .cpu_name = "405LP", 1266 - .cpu_features = CPU_FTRS_40X, 1267 - .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 1268 - .mmu_features = MMU_FTR_TYPE_40x, 1269 - .icache_bsize = 32, 1270 - .dcache_bsize = 32, 1271 - .machine_check = machine_check_4xx, 1272 - .platform = "ppc405", 1273 - }, 1274 - { /* 405EP */ 1275 - .pvr_mask = 0xffff0000, 1276 - .pvr_value = 0x51210000, 1277 - .cpu_name = "405EP", 1278 - .cpu_features = CPU_FTRS_40X, 1279 - .cpu_user_features = PPC_FEATURE_32 | 1280 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1281 - .mmu_features = MMU_FTR_TYPE_40x, 1282 - .icache_bsize = 32, 1283 - .dcache_bsize = 32, 1284 - .machine_check = machine_check_4xx, 1285 - .platform = "ppc405", 1286 - }, 1287 - { /* 405EX Rev. A/B with Security */ 1288 - .pvr_mask = 0xffff000f, 1289 - .pvr_value = 0x12910007, 1290 - .cpu_name = "405EX Rev. A/B", 1291 - .cpu_features = CPU_FTRS_40X, 1292 - .cpu_user_features = PPC_FEATURE_32 | 1293 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1294 - .mmu_features = MMU_FTR_TYPE_40x, 1295 - .icache_bsize = 32, 1296 - .dcache_bsize = 32, 1297 - .machine_check = machine_check_4xx, 1298 - .platform = "ppc405", 1299 - }, 1300 - { /* 405EX Rev. C without Security */ 1301 - .pvr_mask = 0xffff000f, 1302 - .pvr_value = 0x1291000d, 1303 - .cpu_name = "405EX Rev. C", 1304 - .cpu_features = CPU_FTRS_40X, 1305 - .cpu_user_features = PPC_FEATURE_32 | 1306 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1307 - .mmu_features = MMU_FTR_TYPE_40x, 1308 - .icache_bsize = 32, 1309 - .dcache_bsize = 32, 1310 - .machine_check = machine_check_4xx, 1311 - .platform = "ppc405", 1312 - }, 1313 - { /* 405EX Rev. C with Security */ 1314 - .pvr_mask = 0xffff000f, 1315 - .pvr_value = 0x1291000f, 1316 - .cpu_name = "405EX Rev. C", 1317 - .cpu_features = CPU_FTRS_40X, 1318 - .cpu_user_features = PPC_FEATURE_32 | 1319 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1320 - .mmu_features = MMU_FTR_TYPE_40x, 1321 - .icache_bsize = 32, 1322 - .dcache_bsize = 32, 1323 - .machine_check = machine_check_4xx, 1324 - .platform = "ppc405", 1325 - }, 1326 - { /* 405EX Rev. D without Security */ 1327 - .pvr_mask = 0xffff000f, 1328 - .pvr_value = 0x12910003, 1329 - .cpu_name = "405EX Rev. D", 1330 - .cpu_features = CPU_FTRS_40X, 1331 - .cpu_user_features = PPC_FEATURE_32 | 1332 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1333 - .mmu_features = MMU_FTR_TYPE_40x, 1334 - .icache_bsize = 32, 1335 - .dcache_bsize = 32, 1336 - .machine_check = machine_check_4xx, 1337 - .platform = "ppc405", 1338 - }, 1339 - { /* 405EX Rev. D with Security */ 1340 - .pvr_mask = 0xffff000f, 1341 - .pvr_value = 0x12910005, 1342 - .cpu_name = "405EX Rev. D", 1343 - .cpu_features = CPU_FTRS_40X, 1344 - .cpu_user_features = PPC_FEATURE_32 | 1345 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1346 - .mmu_features = MMU_FTR_TYPE_40x, 1347 - .icache_bsize = 32, 1348 - .dcache_bsize = 32, 1349 - .machine_check = machine_check_4xx, 1350 - .platform = "ppc405", 1351 - }, 1352 - { /* 405EXr Rev. A/B without Security */ 1353 - .pvr_mask = 0xffff000f, 1354 - .pvr_value = 0x12910001, 1355 - .cpu_name = "405EXr Rev. A/B", 1356 - .cpu_features = CPU_FTRS_40X, 1357 - .cpu_user_features = PPC_FEATURE_32 | 1358 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1359 - .mmu_features = MMU_FTR_TYPE_40x, 1360 - .icache_bsize = 32, 1361 - .dcache_bsize = 32, 1362 - .machine_check = machine_check_4xx, 1363 - .platform = "ppc405", 1364 - }, 1365 - { /* 405EXr Rev. C without Security */ 1366 - .pvr_mask = 0xffff000f, 1367 - .pvr_value = 0x12910009, 1368 - .cpu_name = "405EXr Rev. C", 1369 - .cpu_features = CPU_FTRS_40X, 1370 - .cpu_user_features = PPC_FEATURE_32 | 1371 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1372 - .mmu_features = MMU_FTR_TYPE_40x, 1373 - .icache_bsize = 32, 1374 - .dcache_bsize = 32, 1375 - .machine_check = machine_check_4xx, 1376 - .platform = "ppc405", 1377 - }, 1378 - { /* 405EXr Rev. C with Security */ 1379 - .pvr_mask = 0xffff000f, 1380 - .pvr_value = 0x1291000b, 1381 - .cpu_name = "405EXr Rev. C", 1382 - .cpu_features = CPU_FTRS_40X, 1383 - .cpu_user_features = PPC_FEATURE_32 | 1384 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1385 - .mmu_features = MMU_FTR_TYPE_40x, 1386 - .icache_bsize = 32, 1387 - .dcache_bsize = 32, 1388 - .machine_check = machine_check_4xx, 1389 - .platform = "ppc405", 1390 - }, 1391 - { /* 405EXr Rev. D without Security */ 1392 - .pvr_mask = 0xffff000f, 1393 - .pvr_value = 0x12910000, 1394 - .cpu_name = "405EXr Rev. D", 1395 - .cpu_features = CPU_FTRS_40X, 1396 - .cpu_user_features = PPC_FEATURE_32 | 1397 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1398 - .mmu_features = MMU_FTR_TYPE_40x, 1399 - .icache_bsize = 32, 1400 - .dcache_bsize = 32, 1401 - .machine_check = machine_check_4xx, 1402 - .platform = "ppc405", 1403 - }, 1404 - { /* 405EXr Rev. D with Security */ 1405 - .pvr_mask = 0xffff000f, 1406 - .pvr_value = 0x12910002, 1407 - .cpu_name = "405EXr Rev. D", 1408 - .cpu_features = CPU_FTRS_40X, 1409 - .cpu_user_features = PPC_FEATURE_32 | 1410 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1411 - .mmu_features = MMU_FTR_TYPE_40x, 1412 - .icache_bsize = 32, 1413 - .dcache_bsize = 32, 1414 - .machine_check = machine_check_4xx, 1415 - .platform = "ppc405", 1416 - }, 1417 - { 1418 - /* 405EZ */ 1419 - .pvr_mask = 0xffff0000, 1420 - .pvr_value = 0x41510000, 1421 - .cpu_name = "405EZ", 1422 - .cpu_features = CPU_FTRS_40X, 1423 - .cpu_user_features = PPC_FEATURE_32 | 1424 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1425 - .mmu_features = MMU_FTR_TYPE_40x, 1426 - .icache_bsize = 32, 1427 - .dcache_bsize = 32, 1428 - .machine_check = machine_check_4xx, 1429 - .platform = "ppc405", 1430 - }, 1431 - { /* APM8018X */ 1432 - .pvr_mask = 0xffff0000, 1433 - .pvr_value = 0x7ff11432, 1434 - .cpu_name = "APM8018X", 1435 - .cpu_features = CPU_FTRS_40X, 1436 - .cpu_user_features = PPC_FEATURE_32 | 1437 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1438 - .mmu_features = MMU_FTR_TYPE_40x, 1439 - .icache_bsize = 32, 1440 - .dcache_bsize = 32, 1441 - .machine_check = machine_check_4xx, 1442 - .platform = "ppc405", 1443 - }, 1444 - { /* default match */ 1445 - .pvr_mask = 0x00000000, 1446 - .pvr_value = 0x00000000, 1447 - .cpu_name = "(generic 40x PPC)", 1448 - .cpu_features = CPU_FTRS_40X, 1449 - .cpu_user_features = PPC_FEATURE_32 | 1450 - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 1451 - .mmu_features = MMU_FTR_TYPE_40x, 1452 - .icache_bsize = 32, 1453 - .dcache_bsize = 32, 1454 - .machine_check = machine_check_4xx, 1455 - .platform = "ppc405", 1456 - } 1457 - 1458 - #endif /* CONFIG_40x */ 1459 - #ifdef CONFIG_44x 1460 - #ifndef CONFIG_PPC_47x 1461 - { 1462 - .pvr_mask = 0xf0000fff, 1463 - .pvr_value = 0x40000850, 1464 - .cpu_name = "440GR Rev. A", 1465 - .cpu_features = CPU_FTRS_44X, 1466 - .cpu_user_features = COMMON_USER_BOOKE, 1467 - .mmu_features = MMU_FTR_TYPE_44x, 1468 - .icache_bsize = 32, 1469 - .dcache_bsize = 32, 1470 - .machine_check = machine_check_4xx, 1471 - .platform = "ppc440", 1472 - }, 1473 - { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1474 - .pvr_mask = 0xf0000fff, 1475 - .pvr_value = 0x40000858, 1476 - .cpu_name = "440EP Rev. A", 1477 - .cpu_features = CPU_FTRS_44X, 1478 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1479 - .mmu_features = MMU_FTR_TYPE_44x, 1480 - .icache_bsize = 32, 1481 - .dcache_bsize = 32, 1482 - .cpu_setup = __setup_cpu_440ep, 1483 - .machine_check = machine_check_4xx, 1484 - .platform = "ppc440", 1485 - }, 1486 - { 1487 - .pvr_mask = 0xf0000fff, 1488 - .pvr_value = 0x400008d3, 1489 - .cpu_name = "440GR Rev. B", 1490 - .cpu_features = CPU_FTRS_44X, 1491 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1492 - .mmu_features = MMU_FTR_TYPE_44x, 1493 - .icache_bsize = 32, 1494 - .dcache_bsize = 32, 1495 - .machine_check = machine_check_4xx, 1496 - .platform = "ppc440", 1497 - }, 1498 - { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1499 - .pvr_mask = 0xf0000ff7, 1500 - .pvr_value = 0x400008d4, 1501 - .cpu_name = "440EP Rev. C", 1502 - .cpu_features = CPU_FTRS_44X, 1503 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1504 - .mmu_features = MMU_FTR_TYPE_44x, 1505 - .icache_bsize = 32, 1506 - .dcache_bsize = 32, 1507 - .cpu_setup = __setup_cpu_440ep, 1508 - .machine_check = machine_check_4xx, 1509 - .platform = "ppc440", 1510 - }, 1511 - { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */ 1512 - .pvr_mask = 0xf0000fff, 1513 - .pvr_value = 0x400008db, 1514 - .cpu_name = "440EP Rev. B", 1515 - .cpu_features = CPU_FTRS_44X, 1516 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1517 - .mmu_features = MMU_FTR_TYPE_44x, 1518 - .icache_bsize = 32, 1519 - .dcache_bsize = 32, 1520 - .cpu_setup = __setup_cpu_440ep, 1521 - .machine_check = machine_check_4xx, 1522 - .platform = "ppc440", 1523 - }, 1524 - { /* 440GRX */ 1525 - .pvr_mask = 0xf0000ffb, 1526 - .pvr_value = 0x200008D0, 1527 - .cpu_name = "440GRX", 1528 - .cpu_features = CPU_FTRS_44X, 1529 - .cpu_user_features = COMMON_USER_BOOKE, 1530 - .mmu_features = MMU_FTR_TYPE_44x, 1531 - .icache_bsize = 32, 1532 - .dcache_bsize = 32, 1533 - .cpu_setup = __setup_cpu_440grx, 1534 - .machine_check = machine_check_440A, 1535 - .platform = "ppc440", 1536 - }, 1537 - { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */ 1538 - .pvr_mask = 0xf0000ffb, 1539 - .pvr_value = 0x200008D8, 1540 - .cpu_name = "440EPX", 1541 - .cpu_features = CPU_FTRS_44X, 1542 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1543 - .mmu_features = MMU_FTR_TYPE_44x, 1544 - .icache_bsize = 32, 1545 - .dcache_bsize = 32, 1546 - .cpu_setup = __setup_cpu_440epx, 1547 - .machine_check = machine_check_440A, 1548 - .platform = "ppc440", 1549 - }, 1550 - { /* 440GP Rev. B */ 1551 - .pvr_mask = 0xf0000fff, 1552 - .pvr_value = 0x40000440, 1553 - .cpu_name = "440GP Rev. B", 1554 - .cpu_features = CPU_FTRS_44X, 1555 - .cpu_user_features = COMMON_USER_BOOKE, 1556 - .mmu_features = MMU_FTR_TYPE_44x, 1557 - .icache_bsize = 32, 1558 - .dcache_bsize = 32, 1559 - .machine_check = machine_check_4xx, 1560 - .platform = "ppc440gp", 1561 - }, 1562 - { /* 440GP Rev. C */ 1563 - .pvr_mask = 0xf0000fff, 1564 - .pvr_value = 0x40000481, 1565 - .cpu_name = "440GP Rev. C", 1566 - .cpu_features = CPU_FTRS_44X, 1567 - .cpu_user_features = COMMON_USER_BOOKE, 1568 - .mmu_features = MMU_FTR_TYPE_44x, 1569 - .icache_bsize = 32, 1570 - .dcache_bsize = 32, 1571 - .machine_check = machine_check_4xx, 1572 - .platform = "ppc440gp", 1573 - }, 1574 - { /* 440GX Rev. A */ 1575 - .pvr_mask = 0xf0000fff, 1576 - .pvr_value = 0x50000850, 1577 - .cpu_name = "440GX Rev. A", 1578 - .cpu_features = CPU_FTRS_44X, 1579 - .cpu_user_features = COMMON_USER_BOOKE, 1580 - .mmu_features = MMU_FTR_TYPE_44x, 1581 - .icache_bsize = 32, 1582 - .dcache_bsize = 32, 1583 - .cpu_setup = __setup_cpu_440gx, 1584 - .machine_check = machine_check_440A, 1585 - .platform = "ppc440", 1586 - }, 1587 - { /* 440GX Rev. B */ 1588 - .pvr_mask = 0xf0000fff, 1589 - .pvr_value = 0x50000851, 1590 - .cpu_name = "440GX Rev. B", 1591 - .cpu_features = CPU_FTRS_44X, 1592 - .cpu_user_features = COMMON_USER_BOOKE, 1593 - .mmu_features = MMU_FTR_TYPE_44x, 1594 - .icache_bsize = 32, 1595 - .dcache_bsize = 32, 1596 - .cpu_setup = __setup_cpu_440gx, 1597 - .machine_check = machine_check_440A, 1598 - .platform = "ppc440", 1599 - }, 1600 - { /* 440GX Rev. C */ 1601 - .pvr_mask = 0xf0000fff, 1602 - .pvr_value = 0x50000892, 1603 - .cpu_name = "440GX Rev. C", 1604 - .cpu_features = CPU_FTRS_44X, 1605 - .cpu_user_features = COMMON_USER_BOOKE, 1606 - .mmu_features = MMU_FTR_TYPE_44x, 1607 - .icache_bsize = 32, 1608 - .dcache_bsize = 32, 1609 - .cpu_setup = __setup_cpu_440gx, 1610 - .machine_check = machine_check_440A, 1611 - .platform = "ppc440", 1612 - }, 1613 - { /* 440GX Rev. F */ 1614 - .pvr_mask = 0xf0000fff, 1615 - .pvr_value = 0x50000894, 1616 - .cpu_name = "440GX Rev. F", 1617 - .cpu_features = CPU_FTRS_44X, 1618 - .cpu_user_features = COMMON_USER_BOOKE, 1619 - .mmu_features = MMU_FTR_TYPE_44x, 1620 - .icache_bsize = 32, 1621 - .dcache_bsize = 32, 1622 - .cpu_setup = __setup_cpu_440gx, 1623 - .machine_check = machine_check_440A, 1624 - .platform = "ppc440", 1625 - }, 1626 - { /* 440SP Rev. A */ 1627 - .pvr_mask = 0xfff00fff, 1628 - .pvr_value = 0x53200891, 1629 - .cpu_name = "440SP Rev. A", 1630 - .cpu_features = CPU_FTRS_44X, 1631 - .cpu_user_features = COMMON_USER_BOOKE, 1632 - .mmu_features = MMU_FTR_TYPE_44x, 1633 - .icache_bsize = 32, 1634 - .dcache_bsize = 32, 1635 - .machine_check = machine_check_4xx, 1636 - .platform = "ppc440", 1637 - }, 1638 - { /* 440SPe Rev. A */ 1639 - .pvr_mask = 0xfff00fff, 1640 - .pvr_value = 0x53400890, 1641 - .cpu_name = "440SPe Rev. A", 1642 - .cpu_features = CPU_FTRS_44X, 1643 - .cpu_user_features = COMMON_USER_BOOKE, 1644 - .mmu_features = MMU_FTR_TYPE_44x, 1645 - .icache_bsize = 32, 1646 - .dcache_bsize = 32, 1647 - .cpu_setup = __setup_cpu_440spe, 1648 - .machine_check = machine_check_440A, 1649 - .platform = "ppc440", 1650 - }, 1651 - { /* 440SPe Rev. B */ 1652 - .pvr_mask = 0xfff00fff, 1653 - .pvr_value = 0x53400891, 1654 - .cpu_name = "440SPe Rev. B", 1655 - .cpu_features = CPU_FTRS_44X, 1656 - .cpu_user_features = COMMON_USER_BOOKE, 1657 - .mmu_features = MMU_FTR_TYPE_44x, 1658 - .icache_bsize = 32, 1659 - .dcache_bsize = 32, 1660 - .cpu_setup = __setup_cpu_440spe, 1661 - .machine_check = machine_check_440A, 1662 - .platform = "ppc440", 1663 - }, 1664 - { /* 460EX */ 1665 - .pvr_mask = 0xffff0006, 1666 - .pvr_value = 0x13020002, 1667 - .cpu_name = "460EX", 1668 - .cpu_features = CPU_FTRS_440x6, 1669 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1670 - .mmu_features = MMU_FTR_TYPE_44x, 1671 - .icache_bsize = 32, 1672 - .dcache_bsize = 32, 1673 - .cpu_setup = __setup_cpu_460ex, 1674 - .machine_check = machine_check_440A, 1675 - .platform = "ppc440", 1676 - }, 1677 - { /* 460EX Rev B */ 1678 - .pvr_mask = 0xffff0007, 1679 - .pvr_value = 0x13020004, 1680 - .cpu_name = "460EX Rev. B", 1681 - .cpu_features = CPU_FTRS_440x6, 1682 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1683 - .mmu_features = MMU_FTR_TYPE_44x, 1684 - .icache_bsize = 32, 1685 - .dcache_bsize = 32, 1686 - .cpu_setup = __setup_cpu_460ex, 1687 - .machine_check = machine_check_440A, 1688 - .platform = "ppc440", 1689 - }, 1690 - { /* 460GT */ 1691 - .pvr_mask = 0xffff0006, 1692 - .pvr_value = 0x13020000, 1693 - .cpu_name = "460GT", 1694 - .cpu_features = CPU_FTRS_440x6, 1695 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1696 - .mmu_features = MMU_FTR_TYPE_44x, 1697 - .icache_bsize = 32, 1698 - .dcache_bsize = 32, 1699 - .cpu_setup = __setup_cpu_460gt, 1700 - .machine_check = machine_check_440A, 1701 - .platform = "ppc440", 1702 - }, 1703 - { /* 460GT Rev B */ 1704 - .pvr_mask = 0xffff0007, 1705 - .pvr_value = 0x13020005, 1706 - .cpu_name = "460GT Rev. B", 1707 - .cpu_features = CPU_FTRS_440x6, 1708 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1709 - .mmu_features = MMU_FTR_TYPE_44x, 1710 - .icache_bsize = 32, 1711 - .dcache_bsize = 32, 1712 - .cpu_setup = __setup_cpu_460gt, 1713 - .machine_check = machine_check_440A, 1714 - .platform = "ppc440", 1715 - }, 1716 - { /* 460SX */ 1717 - .pvr_mask = 0xffffff00, 1718 - .pvr_value = 0x13541800, 1719 - .cpu_name = "460SX", 1720 - .cpu_features = CPU_FTRS_44X, 1721 - .cpu_user_features = COMMON_USER_BOOKE, 1722 - .mmu_features = MMU_FTR_TYPE_44x, 1723 - .icache_bsize = 32, 1724 - .dcache_bsize = 32, 1725 - .cpu_setup = __setup_cpu_460sx, 1726 - .machine_check = machine_check_440A, 1727 - .platform = "ppc440", 1728 - }, 1729 - { /* 464 in APM821xx */ 1730 - .pvr_mask = 0xfffffff0, 1731 - .pvr_value = 0x12C41C80, 1732 - .cpu_name = "APM821XX", 1733 - .cpu_features = CPU_FTRS_44X, 1734 - .cpu_user_features = COMMON_USER_BOOKE | 1735 - PPC_FEATURE_HAS_FPU, 1736 - .mmu_features = MMU_FTR_TYPE_44x, 1737 - .icache_bsize = 32, 1738 - .dcache_bsize = 32, 1739 - .cpu_setup = __setup_cpu_apm821xx, 1740 - .machine_check = machine_check_440A, 1741 - .platform = "ppc440", 1742 - }, 1743 - { /* default match */ 1744 - .pvr_mask = 0x00000000, 1745 - .pvr_value = 0x00000000, 1746 - .cpu_name = "(generic 44x PPC)", 1747 - .cpu_features = CPU_FTRS_44X, 1748 - .cpu_user_features = COMMON_USER_BOOKE, 1749 - .mmu_features = MMU_FTR_TYPE_44x, 1750 - .icache_bsize = 32, 1751 - .dcache_bsize = 32, 1752 - .machine_check = machine_check_4xx, 1753 - .platform = "ppc440", 1754 - } 1755 - #else /* CONFIG_PPC_47x */ 1756 - { /* 476 DD2 core */ 1757 - .pvr_mask = 0xffffffff, 1758 - .pvr_value = 0x11a52080, 1759 - .cpu_name = "476", 1760 - .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, 1761 - .cpu_user_features = COMMON_USER_BOOKE | 1762 - PPC_FEATURE_HAS_FPU, 1763 - .mmu_features = MMU_FTR_TYPE_47x | 1764 - MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1765 - .icache_bsize = 32, 1766 - .dcache_bsize = 128, 1767 - .machine_check = machine_check_47x, 1768 - .platform = "ppc470", 1769 - }, 1770 - { /* 476fpe */ 1771 - .pvr_mask = 0xffff0000, 1772 - .pvr_value = 0x7ff50000, 1773 - .cpu_name = "476fpe", 1774 - .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, 1775 - .cpu_user_features = COMMON_USER_BOOKE | 1776 - PPC_FEATURE_HAS_FPU, 1777 - .mmu_features = MMU_FTR_TYPE_47x | 1778 - MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1779 - .icache_bsize = 32, 1780 - .dcache_bsize = 128, 1781 - .machine_check = machine_check_47x, 1782 - .platform = "ppc470", 1783 - }, 1784 - { /* 476 iss */ 1785 - .pvr_mask = 0xffff0000, 1786 - .pvr_value = 0x00050000, 1787 - .cpu_name = "476", 1788 - .cpu_features = CPU_FTRS_47X, 1789 - .cpu_user_features = COMMON_USER_BOOKE | 1790 - PPC_FEATURE_HAS_FPU, 1791 - .mmu_features = MMU_FTR_TYPE_47x | 1792 - MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1793 - .icache_bsize = 32, 1794 - .dcache_bsize = 128, 1795 - .machine_check = machine_check_47x, 1796 - .platform = "ppc470", 1797 - }, 1798 - { /* 476 others */ 1799 - .pvr_mask = 0xffff0000, 1800 - .pvr_value = 0x11a50000, 1801 - .cpu_name = "476", 1802 - .cpu_features = CPU_FTRS_47X, 1803 - .cpu_user_features = COMMON_USER_BOOKE | 1804 - PPC_FEATURE_HAS_FPU, 1805 - .mmu_features = MMU_FTR_TYPE_47x | 1806 - MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, 1807 - .icache_bsize = 32, 1808 - .dcache_bsize = 128, 1809 - .machine_check = machine_check_47x, 1810 - .platform = "ppc470", 1811 - }, 1812 - { /* default match */ 1813 - .pvr_mask = 0x00000000, 1814 - .pvr_value = 0x00000000, 1815 - .cpu_name = "(generic 47x PPC)", 1816 - .cpu_features = CPU_FTRS_47X, 1817 - .cpu_user_features = COMMON_USER_BOOKE, 1818 - .mmu_features = MMU_FTR_TYPE_47x, 1819 - .icache_bsize = 32, 1820 - .dcache_bsize = 128, 1821 - .machine_check = machine_check_47x, 1822 - .platform = "ppc470", 1823 - } 1824 - #endif /* CONFIG_PPC_47x */ 1825 - #endif /* CONFIG_44x */ 1826 - #endif /* CONFIG_PPC32 */ 1827 - #ifdef CONFIG_E500 1828 - #ifdef CONFIG_PPC32 1829 - #ifndef CONFIG_PPC_E500MC 1830 - { /* e500 */ 1831 - .pvr_mask = 0xffff0000, 1832 - .pvr_value = 0x80200000, 1833 - .cpu_name = "e500", 1834 - .cpu_features = CPU_FTRS_E500, 1835 - .cpu_user_features = COMMON_USER_BOOKE | 1836 - PPC_FEATURE_HAS_SPE_COMP | 1837 - PPC_FEATURE_HAS_EFP_SINGLE_COMP, 1838 - .cpu_user_features2 = PPC_FEATURE2_ISEL, 1839 - .mmu_features = MMU_FTR_TYPE_FSL_E, 1840 - .icache_bsize = 32, 1841 - .dcache_bsize = 32, 1842 - .num_pmcs = 4, 1843 - .cpu_setup = __setup_cpu_e500v1, 1844 - .machine_check = machine_check_e500, 1845 - .platform = "ppc8540", 1846 - }, 1847 - { /* e500v2 */ 1848 - .pvr_mask = 0xffff0000, 1849 - .pvr_value = 0x80210000, 1850 - .cpu_name = "e500v2", 1851 - .cpu_features = CPU_FTRS_E500_2, 1852 - .cpu_user_features = COMMON_USER_BOOKE | 1853 - PPC_FEATURE_HAS_SPE_COMP | 1854 - PPC_FEATURE_HAS_EFP_SINGLE_COMP | 1855 - PPC_FEATURE_HAS_EFP_DOUBLE_COMP, 1856 - .cpu_user_features2 = PPC_FEATURE2_ISEL, 1857 - .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS, 1858 - .icache_bsize = 32, 1859 - .dcache_bsize = 32, 1860 - .num_pmcs = 4, 1861 - .cpu_setup = __setup_cpu_e500v2, 1862 - .machine_check = machine_check_e500, 1863 - .platform = "ppc8548", 1864 - .cpu_down_flush = cpu_down_flush_e500v2, 1865 - }, 1866 - #else 1867 - { /* e500mc */ 1868 - .pvr_mask = 0xffff0000, 1869 - .pvr_value = 0x80230000, 1870 - .cpu_name = "e500mc", 1871 - .cpu_features = CPU_FTRS_E500MC, 1872 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1873 - .cpu_user_features2 = PPC_FEATURE2_ISEL, 1874 - .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 1875 - MMU_FTR_USE_TLBILX, 1876 - .icache_bsize = 64, 1877 - .dcache_bsize = 64, 1878 - .num_pmcs = 4, 1879 - .cpu_setup = __setup_cpu_e500mc, 1880 - .machine_check = machine_check_e500mc, 1881 - .platform = "ppce500mc", 1882 - .cpu_down_flush = cpu_down_flush_e500mc, 1883 - }, 1884 - #endif /* CONFIG_PPC_E500MC */ 1885 - #endif /* CONFIG_PPC32 */ 1886 - #ifdef CONFIG_PPC_E500MC 1887 - { /* e5500 */ 1888 - .pvr_mask = 0xffff0000, 1889 - .pvr_value = 0x80240000, 1890 - .cpu_name = "e5500", 1891 - .cpu_features = CPU_FTRS_E5500, 1892 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 1893 - .cpu_user_features2 = PPC_FEATURE2_ISEL, 1894 - .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 1895 - MMU_FTR_USE_TLBILX, 1896 - .icache_bsize = 64, 1897 - .dcache_bsize = 64, 1898 - .num_pmcs = 4, 1899 - .cpu_setup = __setup_cpu_e5500, 1900 - #ifndef CONFIG_PPC32 1901 - .cpu_restore = __restore_cpu_e5500, 1902 - #endif 1903 - .machine_check = machine_check_e500mc, 1904 - .platform = "ppce5500", 1905 - .cpu_down_flush = cpu_down_flush_e5500, 1906 - }, 1907 - { /* e6500 */ 1908 - .pvr_mask = 0xffff0000, 1909 - .pvr_value = 0x80400000, 1910 - .cpu_name = "e6500", 1911 - .cpu_features = CPU_FTRS_E6500, 1912 - .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU | 1913 - PPC_FEATURE_HAS_ALTIVEC_COMP, 1914 - .cpu_user_features2 = PPC_FEATURE2_ISEL, 1915 - .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 1916 - MMU_FTR_USE_TLBILX, 1917 - .icache_bsize = 64, 1918 - .dcache_bsize = 64, 1919 - .num_pmcs = 6, 1920 - .cpu_setup = __setup_cpu_e6500, 1921 - #ifndef CONFIG_PPC32 1922 - .cpu_restore = __restore_cpu_e6500, 1923 - #endif 1924 - .machine_check = machine_check_e500mc, 1925 - .platform = "ppce6500", 1926 - .cpu_down_flush = cpu_down_flush_e6500, 1927 - }, 1928 - #endif /* CONFIG_PPC_E500MC */ 1929 - #ifdef CONFIG_PPC32 1930 - { /* default match */ 1931 - .pvr_mask = 0x00000000, 1932 - .pvr_value = 0x00000000, 1933 - .cpu_name = "(generic E500 PPC)", 1934 - .cpu_features = CPU_FTRS_E500, 1935 - .cpu_user_features = COMMON_USER_BOOKE | 1936 - PPC_FEATURE_HAS_SPE_COMP | 1937 - PPC_FEATURE_HAS_EFP_SINGLE_COMP, 1938 - .mmu_features = MMU_FTR_TYPE_FSL_E, 1939 - .icache_bsize = 32, 1940 - .dcache_bsize = 32, 1941 - .machine_check = machine_check_e500, 1942 - .platform = "powerpc", 1943 - } 1944 - #endif /* CONFIG_PPC32 */ 1945 - #endif /* CONFIG_E500 */ 1946 - }; 30 + #include "cpu_specs.h" 1947 31 1948 32 void __init set_cur_cpu_spec(struct cpu_spec *s) 1949 33 { ··· 103 2017 { 104 2018 struct cpu_spec *s = cpu_specs; 105 2019 int i; 2020 + 2021 + BUILD_BUG_ON(!ARRAY_SIZE(cpu_specs)); 106 2022 107 2023 s = PTRRELOC(s); 108 2024

+1 -1

arch/powerpc/kernel/dt_cpu_ftrs.c

··· 1099 1099 1100 1100 prop = of_get_flat_dt_prop(node, "display-name", NULL); 1101 1101 if (prop && strlen((char *)prop) != 0) { 1102 - strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name)); 1102 + strscpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name)); 1103 1103 cur_cpu_spec->cpu_name = dt_cpu_name; 1104 1104 } 1105 1105

+23 -29

arch/powerpc/kernel/entry_32.S

··· 49 49 */ 50 50 .align 12 51 51 52 - #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500) 52 + #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_E500) 53 53 .globl prepare_transfer_to_handler 54 54 prepare_transfer_to_handler: 55 55 /* if from kernel, check interrupted DOZE/NAP mode */ ··· 68 68 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */ 69 69 rlwinm r9,r9,0,~MSR_EE 70 70 lwz r12,_LINK(r11) /* and return to address in LR */ 71 - lwz r2, GPR2(r11) 71 + REST_GPR(2, r11) 72 72 b fast_exception_return 73 73 _ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler) 74 - #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */ 74 + #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_PPC_E500 */ 75 75 76 76 #if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32) 77 77 .globl __kuep_lock ··· 101 101 102 102 .globl transfer_to_syscall 103 103 transfer_to_syscall: 104 + stw r3, ORIG_GPR3(r1) 104 105 stw r11, GPR1(r1) 105 106 stw r11, 0(r1) 106 107 mflr r12 ··· 122 121 SAVE_NVGPRS(r1) 123 122 kuep_lock 124 123 125 - /* Calling convention has r9 = orig r0, r10 = regs */ 126 - addi r10,r1,STACK_FRAME_OVERHEAD 127 - mr r9,r0 124 + /* Calling convention has r3 = regs, r4 = orig r0 */ 125 + addi r3,r1,STACK_FRAME_OVERHEAD 126 + mr r4,r0 128 127 bl system_call_exception 129 128 130 129 ret_from_syscall: ··· 144 143 lwz r7,_NIP(r1) 145 144 lwz r8,_MSR(r1) 146 145 cmpwi r3,0 147 - lwz r3,GPR3(r1) 146 + REST_GPR(3, r1) 148 147 syscall_exit_finish: 149 148 mtspr SPRN_SRR0,r7 150 149 mtspr SPRN_SRR1,r8 ··· 152 151 bne 3f 153 152 mtcr r5 154 153 155 - 1: lwz r2,GPR2(r1) 156 - lwz r1,GPR1(r1) 154 + 1: REST_GPR(2, r1) 155 + REST_GPR(1, r1) 157 156 rfi 158 157 #ifdef CONFIG_40x 159 158 b . /* Prevent prefetch past rfi */ ··· 165 164 REST_NVGPRS(r1) 166 165 mtctr r4 167 166 mtxer r5 168 - lwz r0,GPR0(r1) 169 - lwz r3,GPR3(r1) 170 - REST_GPRS(4, 11, r1) 171 - lwz r12,GPR12(r1) 167 + REST_GPR(0, r1) 168 + REST_GPRS(3, 12, r1) 172 169 b 1b 173 170 174 171 #ifdef CONFIG_44x ··· 258 259 beq 3f /* if not, we've got problems */ 259 260 #endif 260 261 261 - 2: REST_GPRS(3, 6, r11) 262 - lwz r10,_CCR(r11) 263 - REST_GPRS(1, 2, r11) 262 + 2: lwz r10,_CCR(r11) 263 + REST_GPRS(1, 6, r11) 264 264 mtcr r10 265 265 lwz r10,_LINK(r11) 266 266 mtlr r10 267 - /* Clear the exception_marker on the stack to avoid confusing stacktrace */ 267 + /* Clear the exception marker on the stack to avoid confusing stacktrace */ 268 268 li r10, 0 269 269 stw r10, 8(r11) 270 270 REST_GPR(10, r11) ··· 274 276 mtspr SPRN_SRR0,r12 275 277 REST_GPR(9, r11) 276 278 REST_GPR(12, r11) 277 - lwz r11,GPR11(r11) 279 + REST_GPR(11, r11) 278 280 rfi 279 281 #ifdef CONFIG_40x 280 282 b . /* Prevent prefetch past rfi */ ··· 320 322 li r0,0 321 323 322 324 /* 323 - * Leaving a stale exception_marker on the stack can confuse 325 + * Leaving a stale exception marker on the stack can confuse 324 326 * the reliable stack unwinder later on. Clear it. 325 327 */ 326 328 stw r0,8(r1) ··· 372 374 mtspr SPRN_XER,r5 373 375 374 376 /* 375 - * Leaving a stale exception_marker on the stack can confuse 377 + * Leaving a stale exception marker on the stack can confuse 376 378 * the reliable stack unwinder later on. Clear it. 377 379 */ 378 380 stw r0,8(r1) ··· 451 453 lwz r3,_MSR(r1); \ 452 454 andi. r3,r3,MSR_PR; \ 453 455 bne interrupt_return; \ 454 - lwz r0,GPR0(r1); \ 455 - lwz r2,GPR2(r1); \ 456 - REST_GPRS(3, 8, r1); \ 456 + REST_GPR(0, r1); \ 457 + REST_GPRS(2, 8, r1); \ 457 458 lwz r10,_XER(r1); \ 458 459 lwz r11,_CTR(r1); \ 459 460 mtspr SPRN_XER,r10; \ ··· 471 474 lwz r12,_MSR(r1); \ 472 475 mtspr exc_lvl_srr0,r11; \ 473 476 mtspr exc_lvl_srr1,r12; \ 474 - lwz r9,GPR9(r1); \ 475 - lwz r12,GPR12(r1); \ 476 - lwz r10,GPR10(r1); \ 477 - lwz r11,GPR11(r1); \ 478 - lwz r1,GPR1(r1); \ 477 + REST_GPRS(9, 12, r1); \ 478 + REST_GPR(1, r1); \ 479 479 exc_lvl_rfi; \ 480 480 b .; /* prevent prefetch past exc_lvl_rfi */ 481 481 ··· 482 488 mtspr SPRN_##exc_lvl_srr0,r9; \ 483 489 mtspr SPRN_##exc_lvl_srr1,r10; 484 490 485 - #if defined(CONFIG_PPC_BOOK3E_MMU) 491 + #if defined(CONFIG_PPC_E500) 486 492 #ifdef CONFIG_PHYS_64BIT 487 493 #define RESTORE_MAS7 \ 488 494 lwz r11,MAS7(r1); \

+3 -3

arch/powerpc/kernel/entry_64.S

··· 292 292 293 293 /* Prepare a 32-bit mode big endian MSR 294 294 */ 295 - #ifdef CONFIG_PPC_BOOK3E 295 + #ifdef CONFIG_PPC_BOOK3E_64 296 296 rlwinm r11,r11,0,1,31 297 297 mtsrr1 r11 298 298 rfi 299 - #else /* CONFIG_PPC_BOOK3E */ 299 + #else /* CONFIG_PPC_BOOK3E_64 */ 300 300 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_LE) 301 301 andc r11,r11,r12 302 302 mtsrr1 r11 303 303 RFI_TO_KERNEL 304 - #endif /* CONFIG_PPC_BOOK3E */ 304 + #endif /* CONFIG_PPC_BOOK3E_64 */ 305 305 306 306 1: /* Return from OF */ 307 307 FIXUP_ENDIAN

+26 -44

arch/powerpc/kernel/exceptions-64e.S

··· 216 216 mtlr r10 217 217 mtcr r11 218 218 219 - ld r10,GPR10(r1) 220 - ld r11,GPR11(r1) 221 - ld r12,GPR12(r1) 219 + REST_GPRS(10, 12, r1) 222 220 mtspr \scratch,r0 223 221 224 222 std r10,\paca_ex+EX_R10(r13); 225 223 std r11,\paca_ex+EX_R11(r13); 226 224 ld r10,_NIP(r1) 227 225 ld r11,_MSR(r1) 228 - ld r0,GPR0(r1) 229 - ld r1,GPR1(r1) 226 + REST_GPR(0, r1) 227 + REST_GPR(1, r1) 230 228 mtspr \srr0,r10 231 229 mtspr \srr1,r11 232 230 ld r10,\paca_ex+EX_R10(r13) ··· 289 291 #define SPRN_MC_SRR0 SPRN_MCSRR0 290 292 #define SPRN_MC_SRR1 SPRN_MCSRR1 291 293 292 - #ifdef CONFIG_PPC_FSL_BOOK3E 293 294 #define GEN_BTB_FLUSH \ 294 295 START_BTB_FLUSH_SECTION \ 295 296 beq 1f; \ ··· 304 307 #define DBG_BTB_FLUSH CRIT_BTB_FLUSH 305 308 #define MC_BTB_FLUSH CRIT_BTB_FLUSH 306 309 #define GDBELL_BTB_FLUSH GEN_BTB_FLUSH 307 - #else 308 - #define GEN_BTB_FLUSH 309 - #define CRIT_BTB_FLUSH 310 - #define DBG_BTB_FLUSH 311 - #define MC_BTB_FLUSH 312 - #define GDBELL_BTB_FLUSH 313 - #endif 314 310 315 311 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ 316 312 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) ··· 362 372 /* Core exception code for all exceptions except TLB misses. */ 363 373 #define EXCEPTION_COMMON_LVL(n, scratch, excf) \ 364 374 exc_##n##_common: \ 365 - std r0,GPR0(r1); /* save r0 in stackframe */ \ 366 - std r2,GPR2(r1); /* save r2 in stackframe */ \ 367 - SAVE_GPRS(3, 9, r1); /* save r3 - r9 in stackframe */ \ 375 + SAVE_GPR(0, r1); /* save r0 in stackframe */ \ 376 + SAVE_GPRS(2, 9, r1); /* save r2 - r9 in stackframe */ \ 368 377 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 369 378 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 370 379 beq 2f; /* if from kernel mode */ \ 371 380 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \ 372 381 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 373 382 mfspr r5,scratch; /* get back r13 */ \ 374 - std r12,GPR12(r1); /* save r12 in stackframe */ \ 375 - ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 383 + SAVE_GPR(12, r1); /* save r12 in stackframe */ \ 384 + LOAD_PACA_TOC(); /* get kernel TOC into r2 */ \ 376 385 mflr r6; /* save LR in stackframe */ \ 377 386 mfctr r7; /* save CTR in stackframe */ \ 378 387 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 379 388 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 380 389 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 381 390 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \ 382 - ld r12,exception_marker@toc(r2); \ 383 - li r0,0; \ 391 + LOAD_REG_IMMEDIATE(r12, STACK_FRAME_REGS_MARKER); \ 392 + ZEROIZE_GPR(0); \ 384 393 std r3,GPR10(r1); /* save r10 to stackframe */ \ 385 394 std r4,GPR11(r1); /* save r11 to stackframe */ \ 386 395 std r5,GPR13(r1); /* save it to stackframe */ \ ··· 458 469 addi r3,r1,STACK_FRAME_OVERHEAD; \ 459 470 bl hdlr; \ 460 471 b interrupt_return 461 - 462 - /* This value is used to mark exception frames on the stack. */ 463 - .section ".toc","aw" 464 - exception_marker: 465 - .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 466 - 467 472 468 473 /* 469 474 * And here we have the exception vectors ! ··· 687 704 beq+ 1f 688 705 689 706 #ifdef CONFIG_RELOCATABLE 690 - ld r15,PACATOC(r13) 691 - ld r14,interrupt_base_book3e@got(r15) 692 - ld r15,__end_interrupts@got(r15) 707 + __LOAD_PACA_TOC(r15) 708 + LOAD_REG_ADDR_ALTTOC(r14, r15, interrupt_base_book3e) 709 + LOAD_REG_ADDR_ALTTOC(r15, r15, __end_interrupts) 693 710 cmpld cr0,r10,r14 694 711 cmpld cr1,r10,r15 695 712 #else ··· 758 775 beq+ 1f 759 776 760 777 #ifdef CONFIG_RELOCATABLE 761 - ld r15,PACATOC(r13) 762 - ld r14,interrupt_base_book3e@got(r15) 763 - ld r15,__end_interrupts@got(r15) 778 + __LOAD_PACA_TOC(r15) 779 + LOAD_REG_ADDR_ALTTOC(r14, r15, interrupt_base_book3e) 780 + LOAD_REG_ADDR_ALTTOC(r15, r15, __end_interrupts) 764 781 cmpld cr0,r10,r14 765 782 cmpld cr1,r10,r15 766 783 #else ··· 883 900 884 901 .macro SEARCH_RESTART_TABLE 885 902 #ifdef CONFIG_RELOCATABLE 886 - ld r11,PACATOC(r13) 887 - ld r14,__start___restart_table@got(r11) 888 - ld r15,__stop___restart_table@got(r11) 903 + __LOAD_PACA_TOC(r11) 904 + LOAD_REG_ADDR_ALTTOC(r14, r11, __start___restart_table) 905 + LOAD_REG_ADDR_ALTTOC(r15, r11, __stop___restart_table) 889 906 #else 890 907 LOAD_REG_IMMEDIATE_SYM(r14, r11, __start___restart_table) 891 908 LOAD_REG_IMMEDIATE_SYM(r15, r11, __stop___restart_table) ··· 1039 1056 mfspr r11,SPRN_ESR 1040 1057 std r10,_DEAR(r1) 1041 1058 std r11,_ESR(r1) 1042 - std r0,GPR0(r1); /* save r0 in stackframe */ \ 1043 - std r2,GPR2(r1); /* save r2 in stackframe */ \ 1044 - SAVE_GPRS(3, 9, r1); /* save r3 - r9 in stackframe */ \ 1059 + SAVE_GPR(0, r1); /* save r0 in stackframe */ \ 1060 + SAVE_GPRS(2, 9, r1); /* save r2 - r9 in stackframe */ \ 1045 1061 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 1046 1062 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 1047 1063 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 1048 1064 std r3,GPR10(r1); /* save r10 to stackframe */ \ 1049 1065 std r4,GPR11(r1); /* save r11 to stackframe */ \ 1050 - std r12,GPR12(r1); /* save r12 in stackframe */ \ 1066 + SAVE_GPR(12, r1); /* save r12 in stackframe */ \ 1051 1067 std r5,GPR13(r1); /* save it to stackframe */ \ 1052 1068 mflr r10 1053 1069 mfctr r11 ··· 1054 1072 std r10,_LINK(r1) 1055 1073 std r11,_CTR(r1) 1056 1074 std r12,_XER(r1) 1057 - SAVE_GPRS(14, 31, r1) 1075 + SAVE_NVGPRS(r1) 1058 1076 lhz r12,PACA_TRAP_SAVE(r13) 1059 1077 std r12,_TRAP(r1) 1060 1078 addi r11,r1,INT_FRAME_SIZE 1061 1079 std r11,0(r1) 1062 - li r12,0 1080 + ZEROIZE_GPR(12) 1063 1081 std r12,0(r11) 1064 - ld r2,PACATOC(r13) 1082 + LOAD_PACA_TOC() 1065 1083 1: addi r3,r1,STACK_FRAME_OVERHEAD 1066 1084 bl kernel_bad_stack 1067 1085 b 1b ··· 1302 1320 1303 1321 /* Now we branch the new virtual address mapped by this entry */ 1304 1322 #ifdef CONFIG_RELOCATABLE 1305 - ld r5,PACATOC(r13) 1306 - ld r3,1f@got(r5) 1323 + __LOAD_PACA_TOC(r5) 1324 + LOAD_REG_ADDR_ALTTOC(r3, r5, 1f) 1307 1325 #else 1308 1326 LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f) 1309 1327 #endif

+91 -68

arch/powerpc/kernel/exceptions-64s.S

··· 281 281 mfspr r9,SPRN_PPR 282 282 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) 283 283 HMT_MEDIUM 284 - std r10,IAREA+EX_R10(r13) /* save r10 - r12 */ 284 + std r10,IAREA+EX_R10(r13) /* save r10 */ 285 285 .if ICFAR 286 286 BEGIN_FTR_SECTION 287 287 mfspr r10,SPRN_CFAR ··· 321 321 mfctr r10 322 322 std r10,IAREA+EX_CTR(r13) 323 323 mfcr r9 324 - std r11,IAREA+EX_R11(r13) 324 + std r11,IAREA+EX_R11(r13) /* save r11 - r12 */ 325 325 std r12,IAREA+EX_R12(r13) 326 326 327 327 /* ··· 580 580 std r2,GPR2(r1) /* save r2 in stackframe */ 581 581 SAVE_GPRS(3, 8, r1) /* save r3 - r8 in stackframe */ 582 582 mflr r9 /* Get LR, later save to stack */ 583 - ld r2,PACATOC(r13) /* get kernel TOC into r2 */ 583 + LOAD_PACA_TOC() /* get kernel TOC into r2 */ 584 584 std r9,_LINK(r1) 585 585 lbz r10,PACAIRQSOFTMASK(r13) 586 586 mfspr r11,SPRN_XER /* save XER in stackframe */ ··· 589 589 li r9,IVEC 590 590 std r9,_TRAP(r1) /* set trap number */ 591 591 li r10,0 592 - ld r11,exception_marker@toc(r2) 592 + LOAD_REG_IMMEDIATE(r11, STACK_FRAME_REGS_MARKER) 593 593 std r10,RESULT(r1) /* clear regs->result */ 594 594 std r11,STACK_FRAME_OVERHEAD-16(r1) /* mark the frame */ 595 595 .endm ··· 610 610 .macro SEARCH_RESTART_TABLE 611 611 #ifdef CONFIG_RELOCATABLE 612 612 mr r12,r2 613 - ld r2,PACATOC(r13) 613 + LOAD_PACA_TOC() 614 614 LOAD_REG_ADDR(r9, __start___restart_table) 615 615 LOAD_REG_ADDR(r10, __stop___restart_table) 616 616 mr r2,r12 ··· 640 640 .macro SEARCH_SOFT_MASK_TABLE 641 641 #ifdef CONFIG_RELOCATABLE 642 642 mr r12,r2 643 - ld r2,PACATOC(r13) 643 + LOAD_PACA_TOC() 644 644 LOAD_REG_ADDR(r9, __start___soft_mask_table) 645 645 LOAD_REG_ADDR(r10, __stop___soft_mask_table) 646 646 mr r2,r12 ··· 700 700 REST_GPR(0, r1) 701 701 /* restore original r1. */ 702 702 ld r1,GPR1(r1) 703 + .endm 704 + 705 + /* 706 + * EARLY_BOOT_FIXUP - Fix real-mode interrupt with wrong endian in early boot. 707 + * 708 + * There's a short window during boot where although the kernel is running 709 + * little endian, any exceptions will cause the CPU to switch back to big 710 + * endian. For example a WARN() boils down to a trap instruction, which will 711 + * cause a program check, and we end up here but with the CPU in big endian 712 + * mode. The first instruction of the program check handler (in GEN_INT_ENTRY 713 + * below) is an mtsprg, which when executed in the wrong endian is an lhzu with 714 + * a ~3GB displacement from r3. The content of r3 is random, so that is a load 715 + * from some random location, and depending on the system can easily lead to a 716 + * checkstop, or an infinitely recursive page fault. 717 + * 718 + * So to handle that case we have a trampoline here that can detect we are in 719 + * the wrong endian and flip us back to the correct endian. We can't flip 720 + * MSR[LE] using mtmsr, so we have to use rfid. That requires backing up SRR0/1 721 + * as well as a GPR. To do that we use SPRG0/2/3, as SPRG1 is already used for 722 + * the paca. SPRG3 is user readable, but this trampoline is only active very 723 + * early in boot, and SPRG3 will be reinitialised in vdso_getcpu_init() before 724 + * userspace starts. 725 + */ 726 + .macro EARLY_BOOT_FIXUP 727 + BEGIN_FTR_SECTION 728 + #ifdef CONFIG_CPU_LITTLE_ENDIAN 729 + tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8 730 + b 2f // Skip trampoline if endian is correct 731 + .long 0xa643707d // mtsprg 0, r11 Backup r11 732 + .long 0xa6027a7d // mfsrr0 r11 733 + .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2 734 + .long 0xa6027b7d // mfsrr1 r11 735 + .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3 736 + .long 0xa600607d // mfmsr r11 737 + .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE] 738 + .long 0xa6037b7d // mtsrr1 r11 739 + /* 740 + * This is 'li r11,1f' where 1f is the absolute address of that 741 + * label, byteswapped into the SI field of the instruction. 742 + */ 743 + .long 0x00006039 | \ 744 + ((ABS_ADDR(1f, real_vectors) & 0x00ff) << 24) | \ 745 + ((ABS_ADDR(1f, real_vectors) & 0xff00) << 8) 746 + .long 0xa6037a7d // mtsrr0 r11 747 + .long 0x2400004c // rfid 748 + 1: 749 + mfsprg r11, 3 750 + mtsrr1 r11 // Restore SRR1 751 + mfsprg r11, 2 752 + mtsrr0 r11 // Restore SRR0 753 + mfsprg r11, 0 // Restore r11 754 + 2: 755 + #endif 756 + /* 757 + * program check could hit at any time, and pseries can not block 758 + * MSR[ME] in early boot. So check if there is anything useful in r13 759 + * yet, and spin forever if not. 760 + */ 761 + mtsprg 0, r11 762 + mfcr r11 763 + cmpdi r13, 0 764 + beq . 765 + mtcr r11 766 + mfsprg r11, 0 767 + END_FTR_SECTION(0, 1) // nop out after boot 703 768 .endm 704 769 705 770 /* ··· 1144 1079 INT_DEFINE_END(machine_check) 1145 1080 1146 1081 EXC_REAL_BEGIN(machine_check, 0x200, 0x100) 1082 + EARLY_BOOT_FIXUP 1147 1083 GEN_INT_ENTRY machine_check_early, virt=0 1148 1084 EXC_REAL_END(machine_check, 0x200, 0x100) 1149 1085 EXC_VIRT_NONE(0x4200, 0x100) ··· 1209 1143 bl enable_machine_check 1210 1144 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1211 1145 addi r3,r1,STACK_FRAME_OVERHEAD 1146 + BEGIN_FTR_SECTION 1147 + bl machine_check_early_boot 1148 + END_FTR_SECTION(0, 1) // nop out after boot 1212 1149 bl machine_check_early 1213 1150 std r3,RESULT(r1) /* Save result */ 1214 1151 ld r12,_MSR(r1) ··· 1688 1619 INT_DEFINE_END(program_check) 1689 1620 1690 1621 EXC_REAL_BEGIN(program_check, 0x700, 0x100) 1691 - 1692 - #ifdef CONFIG_CPU_LITTLE_ENDIAN 1693 - /* 1694 - * There's a short window during boot where although the kernel is 1695 - * running little endian, any exceptions will cause the CPU to switch 1696 - * back to big endian. For example a WARN() boils down to a trap 1697 - * instruction, which will cause a program check, and we end up here but 1698 - * with the CPU in big endian mode. The first instruction of the program 1699 - * check handler (in GEN_INT_ENTRY below) is an mtsprg, which when 1700 - * executed in the wrong endian is an lhzu with a ~3GB displacement from 1701 - * r3. The content of r3 is random, so that is a load from some random 1702 - * location, and depending on the system can easily lead to a checkstop, 1703 - * or an infinitely recursive page fault. 1704 - * 1705 - * So to handle that case we have a trampoline here that can detect we 1706 - * are in the wrong endian and flip us back to the correct endian. We 1707 - * can't flip MSR[LE] using mtmsr, so we have to use rfid. That requires 1708 - * backing up SRR0/1 as well as a GPR. To do that we use SPRG0/2/3, as 1709 - * SPRG1 is already used for the paca. SPRG3 is user readable, but this 1710 - * trampoline is only active very early in boot, and SPRG3 will be 1711 - * reinitialised in vdso_getcpu_init() before userspace starts. 1712 - */ 1713 - BEGIN_FTR_SECTION 1714 - tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8 1715 - b 1f // Skip trampoline if endian is correct 1716 - .long 0xa643707d // mtsprg 0, r11 Backup r11 1717 - .long 0xa6027a7d // mfsrr0 r11 1718 - .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2 1719 - .long 0xa6027b7d // mfsrr1 r11 1720 - .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3 1721 - .long 0xa600607d // mfmsr r11 1722 - .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE] 1723 - .long 0xa6037b7d // mtsrr1 r11 1724 - .long 0x34076039 // li r11, 0x734 1725 - .long 0xa6037a7d // mtsrr0 r11 1726 - .long 0x2400004c // rfid 1727 - mfsprg r11, 3 1728 - mtsrr1 r11 // Restore SRR1 1729 - mfsprg r11, 2 1730 - mtsrr0 r11 // Restore SRR0 1731 - mfsprg r11, 0 // Restore r11 1732 - 1: 1733 - END_FTR_SECTION(0, 1) // nop out after boot 1734 - #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1735 - 1622 + EARLY_BOOT_FIXUP 1736 1623 GEN_INT_ENTRY program_check, virt=0 1737 1624 EXC_REAL_END(program_check, 0x700, 0x100) 1738 1625 EXC_VIRT_BEGIN(program_check, 0x4700, 0x100) ··· 2819 2794 masked_interrupt: 2820 2795 .endif 2821 2796 stw r9,PACA_EXGEN+EX_CCR(r13) 2797 + #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG 2798 + /* 2799 + * Ensure there was no previous MUST_HARD_MASK interrupt or 2800 + * HARD_DIS setting. If this does fire, the interrupt is still 2801 + * masked and MSR[EE] will be cleared on return, so no need to 2802 + * panic, but somebody probably enabled MSR[EE] under 2803 + * PACA_IRQ_HARD_DIS, mtmsr(mfmsr() | MSR_x) being a common 2804 + * cause. 2805 + */ 2806 + lbz r9,PACAIRQHAPPENED(r13) 2807 + andi. r9,r9,(PACA_IRQ_MUST_HARD_MASK|PACA_IRQ_HARD_DIS) 2808 + 0: tdnei r9,0 2809 + EMIT_WARN_ENTRY 0b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE) 2810 + #endif 2822 2811 lbz r9,PACAIRQHAPPENED(r13) 2823 2812 or r9,r9,r10 2824 2813 stb r9,PACAIRQHAPPENED(r13) ··· 3073 3034 MASKED_INTERRUPT 3074 3035 MASKED_INTERRUPT hsrr=1 3075 3036 3076 - /* 3077 - * Relocation-on interrupts: A subset of the interrupts can be delivered 3078 - * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 3079 - * it. Addresses are the same as the original interrupt addresses, but 3080 - * offset by 0xc000000000004000. 3081 - * It's impossible to receive interrupts below 0x300 via this mechanism. 3082 - * KVM: None of these traps are from the guest ; anything that escalated 3083 - * to HV=1 from HV=0 is delivered via real mode handlers. 3084 - */ 3085 - 3086 - /* 3087 - * This uses the standard macro, since the original 0x300 vector 3088 - * only has extra guff for STAB-based processors -- which never 3089 - * come here. 3090 - */ 3091 - 3092 3037 USE_FIXED_SECTION(virt_trampolines) 3093 3038 /* 3094 3039 * All code below __end_soft_masked is treated as soft-masked. If ··· 3098 3075 USE_TEXT_SECTION() 3099 3076 3100 3077 /* MSR[RI] should be clear because this uses SRR[01] */ 3101 - enable_machine_check: 3078 + _GLOBAL(enable_machine_check) 3102 3079 mflr r0 3103 3080 bcl 20,31,$+4 3104 3081 0: mflr r3

arch/powerpc/kernel/fsl_booke_entry_mapping.S arch/powerpc/kernel/85xx_entry_mapping.S

+25 -29

arch/powerpc/kernel/head_64.S

··· 143 143 .globl __secondary_hold 144 144 __secondary_hold: 145 145 FIXUP_ENDIAN 146 - #ifndef CONFIG_PPC_BOOK3E 146 + #ifndef CONFIG_PPC_BOOK3E_64 147 147 mfmsr r24 148 148 ori r24,r24,MSR_RI 149 149 mtmsrd r24 /* RI on */ ··· 160 160 sync 161 161 162 162 li r26,0 163 - #ifdef CONFIG_PPC_BOOK3E 163 + #ifdef CONFIG_PPC_BOOK3E_64 164 164 tovirt(r26,r26) 165 165 #endif 166 166 /* All secondary cpus wait here until told to start. */ ··· 169 169 beq 100b 170 170 171 171 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 172 - #ifdef CONFIG_PPC_BOOK3E 172 + #ifdef CONFIG_PPC_BOOK3E_64 173 173 tovirt(r12,r12) 174 174 #endif 175 175 mtctr r12 ··· 178 178 * it may be the case that other platforms have r4 right to 179 179 * begin with, this gives us some safety in case it is not 180 180 */ 181 - #ifdef CONFIG_PPC_BOOK3E 181 + #ifdef CONFIG_PPC_BOOK3E_64 182 182 mr r4,r25 183 183 #else 184 184 li r4,0 ··· 191 191 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 192 192 #endif 193 193 CLOSE_FIXED_SECTION(first_256B) 194 - 195 - /* This value is used to mark exception frames on the stack. */ 196 - .section ".toc","aw" 197 - /* This value is used to mark exception frames on the stack. */ 198 - exception_marker: 199 - .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 200 - .previous 201 194 202 195 /* 203 196 * On server, we include the exception vectors code here as it ··· 207 214 208 215 #include "interrupt_64.S" 209 216 210 - #ifdef CONFIG_PPC_BOOK3E 217 + #ifdef CONFIG_PPC_BOOK3E_64 211 218 /* 212 219 * The booting_thread_hwid holds the thread id we want to boot in cpu 213 220 * hotplug case. It is set by cpu hotplug code, and is invalid by default. ··· 315 322 bl book3e_secondary_thread_init 316 323 b generic_secondary_common_init 317 324 318 - #endif /* CONFIG_PPC_BOOK3E */ 325 + #endif /* CONFIG_PPC_BOOK3E_64 */ 319 326 320 327 /* 321 328 * On pSeries and most other platforms, secondary processors spin ··· 338 345 bl relative_toc 339 346 tovirt(r2,r2) 340 347 341 - #ifdef CONFIG_PPC_BOOK3E 348 + #ifdef CONFIG_PPC_BOOK3E_64 342 349 /* Book3E initialization */ 343 350 mr r3,r24 344 351 mr r4,r25 ··· 410 417 b kexec_wait /* next kernel might do better */ 411 418 412 419 2: SET_PACA(r13) 413 - #ifdef CONFIG_PPC_BOOK3E 420 + #ifdef CONFIG_PPC_BOOK3E_64 414 421 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 415 422 mtspr SPRN_SPRG_TLB_EXFRAME,r12 416 423 #endif ··· 487 494 /* Make sure we are running in 64 bits mode */ 488 495 bl enable_64b_mode 489 496 497 + /* Zero r13 (paca) so early program check / mce don't use it */ 498 + li r13,0 499 + 490 500 /* Get TOC pointer (current runtime address) */ 491 501 bl relative_toc 492 502 ··· 515 519 mr r29,r9 516 520 #endif 517 521 518 - #ifdef CONFIG_PPC_BOOK3E 522 + #ifdef CONFIG_PPC_BOOK3E_64 519 523 bl start_initialization_book3e 520 524 b __after_prom_start 521 525 #else ··· 536 540 /* Switch off MMU if not already off */ 537 541 bl __mmu_off 538 542 b __after_prom_start 539 - #endif /* CONFIG_PPC_BOOK3E */ 543 + #endif /* CONFIG_PPC_BOOK3E_64 */ 540 544 541 545 __REF 542 546 __boot_from_prom: ··· 583 587 /* process relocations for the final address of the kernel */ 584 588 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 585 589 sldi r25,r25,32 586 - #if defined(CONFIG_PPC_BOOK3E) 590 + #if defined(CONFIG_PPC_BOOK3E_64) 587 591 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 588 592 #endif 589 593 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 590 - #if defined(CONFIG_PPC_BOOK3E) 594 + #if defined(CONFIG_PPC_BOOK3E_64) 591 595 tophys(r26,r26) 592 596 #endif 593 597 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ ··· 595 599 add r25,r25,r26 596 600 1: mr r3,r25 597 601 bl relocate 598 - #if defined(CONFIG_PPC_BOOK3E) 602 + #if defined(CONFIG_PPC_BOOK3E_64) 599 603 /* IVPR needs to be set after relocation. */ 600 604 bl init_core_book3e 601 605 #endif ··· 609 613 * Note: This process overwrites the OF exception vectors. 610 614 */ 611 615 li r3,0 /* target addr */ 612 - #ifdef CONFIG_PPC_BOOK3E 616 + #ifdef CONFIG_PPC_BOOK3E_64 613 617 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 614 618 #endif 615 619 mr. r4,r26 /* In some cases the loader may */ 616 - #if defined(CONFIG_PPC_BOOK3E) 620 + #if defined(CONFIG_PPC_BOOK3E_64) 617 621 tovirt(r4,r4) 618 622 #endif 619 623 beq 9f /* have already put us at zero */ ··· 626 630 * variable __run_at_load, if it is set the kernel is treated as relocatable 627 631 * kernel, otherwise it will be moved to PHYSICAL_START 628 632 */ 629 - #if defined(CONFIG_PPC_BOOK3E) 633 + #if defined(CONFIG_PPC_BOOK3E_64) 630 634 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 631 635 #endif 632 636 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 633 637 cmplwi cr0,r7,1 634 638 bne 3f 635 639 636 - #ifdef CONFIG_PPC_BOOK3E 640 + #ifdef CONFIG_PPC_BOOK3E_64 637 641 LOAD_REG_ADDR(r5, __end_interrupts) 638 642 LOAD_REG_ADDR(r11, _stext) 639 643 sub r5,r5,r11 ··· 844 848 * before going into C code. 845 849 */ 846 850 start_secondary_prolog: 847 - ld r2,PACATOC(r13) 851 + LOAD_PACA_TOC() 848 852 li r3,0 849 853 std r3,0(r1) /* Zero the stack frame pointer */ 850 854 bl start_secondary ··· 867 871 */ 868 872 enable_64b_mode: 869 873 mfmsr r11 /* grab the current MSR */ 870 - #ifdef CONFIG_PPC_BOOK3E 874 + #ifdef CONFIG_PPC_BOOK3E_64 871 875 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 872 876 mtmsr r11 873 - #else /* CONFIG_PPC_BOOK3E */ 877 + #else /* CONFIG_PPC_BOOK3E_64 */ 874 878 LOAD_REG_IMMEDIATE(r12, MSR_64BIT) 875 879 or r11,r11,r12 876 880 mtmsrd r11 ··· 936 940 std r29,8(r11); 937 941 #endif 938 942 939 - #ifndef CONFIG_PPC_BOOK3E 943 + #ifndef CONFIG_PPC_BOOK3E_64 940 944 mfmsr r6 941 945 ori r6,r6,MSR_RI 942 946 mtmsrd r6 /* RI on */ ··· 984 988 std r1,PACAKSAVE(r13) 985 989 986 990 /* Load the TOC (virtual address) */ 987 - ld r2,PACATOC(r13) 991 + LOAD_PACA_TOC() 988 992 989 993 /* Mark interrupts soft and hard disabled (they might be enabled 990 994 * in the PACA when doing hotplug)

+4 -4

arch/powerpc/kernel/head_booke.h

··· 34 34 */ 35 35 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4)) 36 36 37 - #ifdef CONFIG_PPC_FSL_BOOK3E 37 + #ifdef CONFIG_PPC_E500 38 38 #define BOOKE_CLEAR_BTB(reg) \ 39 39 START_BTB_FLUSH_SECTION \ 40 40 BTB_FLUSH(reg) \ ··· 103 103 .endm 104 104 105 105 .macro prepare_transfer_to_handler 106 - #ifdef CONFIG_E500 106 + #ifdef CONFIG_PPC_E500 107 107 andi. r12,r9,MSR_PR 108 108 bne 777f 109 109 bl prepare_transfer_to_handler ··· 242 242 243 243 244 244 .macro SAVE_MMU_REGS 245 - #ifdef CONFIG_PPC_BOOK3E_MMU 245 + #ifdef CONFIG_PPC_E500 246 246 mfspr r0,SPRN_MAS0 247 247 stw r0,MAS0(r1) 248 248 mfspr r0,SPRN_MAS1 ··· 257 257 mfspr r0,SPRN_MAS7 258 258 stw r0,MAS7(r1) 259 259 #endif /* CONFIG_PHYS_64BIT */ 260 - #endif /* CONFIG_PPC_BOOK3E_MMU */ 260 + #endif /* CONFIG_PPC_E500 */ 261 261 #ifdef CONFIG_44x 262 262 mfspr r0,SPRN_MMUCR 263 263 stw r0,MMUCR(r1)

+4 -4

arch/powerpc/kernel/head_fsl_booke.S arch/powerpc/kernel/head_85xx.S

··· 129 129 130 130 /* 131 131 * For the second relocation, we already set the right tlb entries 132 - * for the kernel space, so skip the code in fsl_booke_entry_mapping.S 132 + * for the kernel space, so skip the code in 85xx_entry_mapping.S 133 133 */ 134 134 cmpwi r19,1 135 135 beq set_ivor ··· 159 159 lwz r20,0(r20) 160 160 161 161 #define ENTRY_MAPPING_BOOT_SETUP 162 - #include "fsl_booke_entry_mapping.S" 162 + #include "85xx_entry_mapping.S" 163 163 #undef ENTRY_MAPPING_BOOT_SETUP 164 164 165 165 set_ivor: ··· 912 912 * Global functions 913 913 */ 914 914 915 - #ifdef CONFIG_E500 915 + #ifdef CONFIG_PPC_E500 916 916 #ifndef CONFIG_PPC_E500MC 917 917 /* Adjust or setup IVORs for e500v1/v2 */ 918 918 _GLOBAL(__setup_e500_ivors) ··· 955 955 sync 956 956 blr 957 957 #endif /* CONFIG_PPC_E500MC */ 958 - #endif /* CONFIG_E500 */ 958 + #endif /* CONFIG_PPC_E500 */ 959 959 960 960 #ifdef CONFIG_SPE 961 961 /*

+3 -7

arch/powerpc/kernel/idle_book3e.S arch/powerpc/kernel/idle_64e.S

··· 2 2 /* 3 3 * Copyright 2010 IBM Corp, Benjamin Herrenschmidt <benh@kernel.crashing.org> 4 4 * 5 - * Generic idle routine for Book3E processors 5 + * Generic idle routine for 64 bits e500 processors 6 6 */ 7 7 8 8 #include <linux/threads.h> ··· 16 16 #include <asm/hw_irq.h> 17 17 18 18 /* 64-bit version only for now */ 19 - #ifdef CONFIG_PPC64 20 - 21 19 .macro BOOK3E_IDLE name loop 22 20 _GLOBAL(\name) 23 21 /* Save LR for later */ ··· 75 77 76 78 .macro BOOK3E_IDLE_LOOP 77 79 1: 78 - PPC_WAIT(0) 80 + PPC_WAIT_v203 79 81 b 1b 80 82 .endm 81 83 ··· 96 98 97 99 BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP 98 100 99 - BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP 100 - 101 - #endif /* CONFIG_PPC64 */ 101 + BOOK3E_IDLE e500_idle BOOK3E_IDLE_LOOP

arch/powerpc/kernel/idle_e500.S arch/powerpc/kernel/idle_85xx.S

-10

arch/powerpc/kernel/interrupt.c

··· 431 431 432 432 if (unlikely(stack_store)) 433 433 __hard_EE_RI_disable(); 434 - /* 435 - * Returning to a kernel context with local irqs disabled. 436 - * Here, if EE was enabled in the interrupted context, enable 437 - * it on return as well. A problem exists here where a soft 438 - * masked interrupt may have cleared MSR[EE] and set HARD_DIS 439 - * here, and it will still exist on return to the caller. This 440 - * will be resolved by the masked interrupt firing again. 441 - */ 442 - if (regs->msr & MSR_EE) 443 - local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; 444 434 #endif /* CONFIG_PPC64 */ 445 435 } 446 436

+62 -67

arch/powerpc/kernel/interrupt_64.S

··· 13 13 #include <asm/ppc_asm.h> 14 14 #include <asm/ptrace.h> 15 15 16 - .section ".toc","aw" 17 - SYS_CALL_TABLE: 18 - .tc sys_call_table[TC],sys_call_table 19 - 20 - #ifdef CONFIG_COMPAT 21 - COMPAT_SYS_CALL_TABLE: 22 - .tc compat_sys_call_table[TC],compat_sys_call_table 23 - #endif 24 - .previous 25 - 26 16 .align 7 27 17 28 18 .macro DEBUG_SRR_VALID srr ··· 57 67 std r0,GPR0(r1) 58 68 std r10,GPR1(r1) 59 69 std r2,GPR2(r1) 60 - ld r2,PACATOC(r13) 70 + LOAD_PACA_TOC() 61 71 mfcr r12 62 72 li r11,0 63 - /* Can we avoid saving r3-r8 in common case? */ 64 - std r3,GPR3(r1) 65 - std r4,GPR4(r1) 66 - std r5,GPR5(r1) 67 - std r6,GPR6(r1) 68 - std r7,GPR7(r1) 69 - std r8,GPR8(r1) 73 + /* Save syscall parameters in r3-r8 */ 74 + SAVE_GPRS(3, 8, r1) 70 75 /* Zero r9-r12, this should only be required when restoring all GPRs */ 71 76 std r11,GPR9(r1) 72 77 std r11,GPR10(r1) ··· 76 91 li r11,\trapnr 77 92 std r11,_TRAP(r1) 78 93 std r12,_CCR(r1) 79 - addi r10,r1,STACK_FRAME_OVERHEAD 80 - ld r11,exception_marker@toc(r2) 81 - std r11,-16(r10) /* "regshere" marker */ 94 + std r3,ORIG_GPR3(r1) 95 + /* Calling convention has r3 = regs, r4 = orig r0 */ 96 + addi r3,r1,STACK_FRAME_OVERHEAD 97 + mr r4,r0 98 + LOAD_REG_IMMEDIATE(r11, STACK_FRAME_REGS_MARKER) 99 + std r11,-16(r3) /* "regshere" marker */ 82 100 83 101 BEGIN_FTR_SECTION 84 102 HMT_MEDIUM ··· 96 108 * but this is the best we can do. 97 109 */ 98 110 99 - /* Calling convention has r9 = orig r0, r10 = regs */ 100 - mr r9,r0 101 111 bl system_call_exception 102 112 103 113 .Lsyscall_vectored_\name\()_exit: ··· 134 148 /* Could zero these as per ABI, but we may consider a stricter ABI 135 149 * which preserves these if libc implementations can benefit, so 136 150 * restore them for now until further measurement is done. */ 137 - ld r0,GPR0(r1) 138 - ld r4,GPR4(r1) 139 - ld r5,GPR5(r1) 140 - ld r6,GPR6(r1) 141 - ld r7,GPR7(r1) 142 - ld r8,GPR8(r1) 151 + REST_GPR(0, r1) 152 + REST_GPRS(4, 8, r1) 143 153 /* Zero volatile regs that may contain sensitive kernel data */ 144 - li r9,0 145 - li r10,0 146 - li r11,0 147 - li r12,0 154 + ZEROIZE_GPRS(9, 12) 148 155 mtspr SPRN_XER,r0 149 156 150 157 /* ··· 160 181 ld r5,_XER(r1) 161 182 162 183 REST_NVGPRS(r1) 163 - ld r0,GPR0(r1) 184 + REST_GPR(0, r1) 164 185 mtcr r2 165 186 mtctr r3 166 187 mtlr r4 ··· 174 195 _ASM_NOKPROBE_SYMBOL(syscall_vectored_\name\()_restart) 175 196 GET_PACA(r13) 176 197 ld r1,PACA_EXIT_SAVE_R1(r13) 177 - ld r2,PACATOC(r13) 198 + LOAD_PACA_TOC() 178 199 ld r3,RESULT(r1) 179 200 addi r4,r1,STACK_FRAME_OVERHEAD 180 201 li r11,IRQS_ALL_DISABLED ··· 219 240 std r0,GPR0(r1) 220 241 std r10,GPR1(r1) 221 242 std r2,GPR2(r1) 222 - #ifdef CONFIG_PPC_FSL_BOOK3E 243 + #ifdef CONFIG_PPC_E500 223 244 START_BTB_FLUSH_SECTION 224 245 BTB_FLUSH(r10) 225 246 END_BTB_FLUSH_SECTION 226 247 #endif 227 - ld r2,PACATOC(r13) 248 + LOAD_PACA_TOC() 228 249 mfcr r12 229 250 li r11,0 230 - /* Can we avoid saving r3-r8 in common case? */ 231 - std r3,GPR3(r1) 232 - std r4,GPR4(r1) 233 - std r5,GPR5(r1) 234 - std r6,GPR6(r1) 235 - std r7,GPR7(r1) 236 - std r8,GPR8(r1) 251 + /* Save syscall parameters in r3-r8 */ 252 + SAVE_GPRS(3, 8, r1) 237 253 /* Zero r9-r12, this should only be required when restoring all GPRs */ 238 254 std r11,GPR9(r1) 239 255 std r11,GPR10(r1) ··· 249 275 std r10,_LINK(r1) 250 276 std r11,_TRAP(r1) 251 277 std r12,_CCR(r1) 252 - addi r10,r1,STACK_FRAME_OVERHEAD 253 - ld r11,exception_marker@toc(r2) 254 - std r11,-16(r10) /* "regshere" marker */ 278 + std r3,ORIG_GPR3(r1) 279 + /* Calling convention has r3 = regs, r4 = orig r0 */ 280 + addi r3,r1,STACK_FRAME_OVERHEAD 281 + mr r4,r0 282 + LOAD_REG_IMMEDIATE(r11, STACK_FRAME_REGS_MARKER) 283 + std r11,-16(r3) /* "regshere" marker */ 255 284 256 285 #ifdef CONFIG_PPC_BOOK3S 257 286 li r11,1 ··· 275 298 wrteei 1 276 299 #endif 277 300 278 - /* Calling convention has r9 = orig r0, r10 = regs */ 279 - mr r9,r0 280 301 bl system_call_exception 281 302 282 303 .Lsyscall_exit: ··· 318 343 cmpdi r3,0 319 344 bne .Lsyscall_restore_regs 320 345 /* Zero volatile regs that may contain sensitive kernel data */ 321 - li r0,0 322 - li r4,0 323 - li r5,0 324 - li r6,0 325 - li r7,0 326 - li r8,0 327 - li r9,0 328 - li r10,0 329 - li r11,0 330 - li r12,0 346 + ZEROIZE_GPR(0) 347 + ZEROIZE_GPRS(4, 12) 331 348 mtctr r0 332 349 mtspr SPRN_XER,r0 333 350 .Lsyscall_restore_regs_cont: ··· 345 378 REST_NVGPRS(r1) 346 379 mtctr r3 347 380 mtspr SPRN_XER,r4 348 - ld r0,GPR0(r1) 381 + REST_GPR(0, r1) 349 382 REST_GPRS(4, 12, r1) 350 383 b .Lsyscall_restore_regs_cont 351 384 .Lsyscall_rst_end: ··· 355 388 _ASM_NOKPROBE_SYMBOL(syscall_restart) 356 389 GET_PACA(r13) 357 390 ld r1,PACA_EXIT_SAVE_R1(r13) 358 - ld r2,PACATOC(r13) 391 + LOAD_PACA_TOC() 359 392 ld r3,RESULT(r1) 360 393 addi r4,r1,STACK_FRAME_OVERHEAD 361 394 li r11,IRQS_ALL_DISABLED ··· 502 535 _ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user_restart) 503 536 GET_PACA(r13) 504 537 ld r1,PACA_EXIT_SAVE_R1(r13) 505 - ld r2,PACATOC(r13) 538 + LOAD_PACA_TOC() 506 539 addi r3,r1,STACK_FRAME_OVERHEAD 507 540 li r11,IRQS_ALL_DISABLED 508 541 stb r11,PACAIRQSOFTMASK(r13) ··· 526 559 ld r11,SOFTE(r1) 527 560 cmpwi r11,IRQS_ENABLED 528 561 stb r11,PACAIRQSOFTMASK(r13) 529 - bne 1f 562 + beq .Linterrupt_return_\srr\()_soft_enabled 563 + 564 + /* 565 + * Returning to soft-disabled context. 566 + * Check if a MUST_HARD_MASK interrupt has become pending, in which 567 + * case we need to disable MSR[EE] in the return context. 568 + */ 569 + ld r12,_MSR(r1) 570 + andi. r10,r12,MSR_EE 571 + beq .Lfast_kernel_interrupt_return_\srr\() // EE already disabled 572 + lbz r11,PACAIRQHAPPENED(r13) 573 + andi. r10,r11,PACA_IRQ_MUST_HARD_MASK 574 + beq 1f // No HARD_MASK pending 575 + 576 + /* Must clear MSR_EE from _MSR */ 577 + #ifdef CONFIG_PPC_BOOK3S 578 + li r10,0 579 + /* Clear valid before changing _MSR */ 580 + .ifc \srr,srr 581 + stb r10,PACASRR_VALID(r13) 582 + .else 583 + stb r10,PACAHSRR_VALID(r13) 584 + .endif 585 + #endif 586 + xori r12,r12,MSR_EE 587 + std r12,_MSR(r1) 588 + b .Lfast_kernel_interrupt_return_\srr\() 589 + 590 + .Linterrupt_return_\srr\()_soft_enabled: 530 591 #ifdef CONFIG_PPC_BOOK3S 531 592 lbz r11,PACAIRQHAPPENED(r13) 532 593 andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l 533 594 bne- interrupt_return_\srr\()_kernel_restart 534 595 #endif 535 - li r11,0 536 - stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS 537 596 1: 597 + li r11,0 598 + stb r11,PACAIRQHAPPENED(r13) // clear the possible HARD_DIS 538 599 539 600 .Lfast_kernel_interrupt_return_\srr\(): 540 601 cmpdi cr1,r3,0 ··· 614 619 mtspr SPRN_XER,r5 615 620 616 621 /* 617 - * Leaving a stale exception_marker on the stack can confuse 622 + * Leaving a stale STACK_FRAME_REGS_MARKER on the stack can confuse 618 623 * the reliable stack unwinder later on. Clear it. 619 624 */ 620 625 std r0,STACK_FRAME_OVERHEAD-16(r1) ··· 663 668 _ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_kernel_restart) 664 669 GET_PACA(r13) 665 670 ld r1,PACA_EXIT_SAVE_R1(r13) 666 - ld r2,PACATOC(r13) 671 + LOAD_PACA_TOC() 667 672 addi r3,r1,STACK_FRAME_OVERHEAD 668 673 li r11,IRQS_ALL_DISABLED 669 674 stb r11,PACAIRQSOFTMASK(r13)

+61 -32

arch/powerpc/kernel/irq_64.c

··· 68 68 69 69 int distribute_irqs = 1; 70 70 71 + static inline void next_interrupt(struct pt_regs *regs) 72 + { 73 + /* 74 + * Softirq processing can enable/disable irqs, which will leave 75 + * MSR[EE] enabled and the soft mask set to IRQS_DISABLED. Fix 76 + * this up. 77 + */ 78 + if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) 79 + hard_irq_disable(); 80 + else 81 + irq_soft_mask_set(IRQS_ALL_DISABLED); 82 + 83 + /* 84 + * We are responding to the next interrupt, so interrupt-off 85 + * latencies should be reset here. 86 + */ 87 + trace_hardirqs_on(); 88 + trace_hardirqs_off(); 89 + } 90 + 91 + static inline bool irq_happened_test_and_clear(u8 irq) 92 + { 93 + if (local_paca->irq_happened & irq) { 94 + local_paca->irq_happened &= ~irq; 95 + return true; 96 + } 97 + return false; 98 + } 99 + 71 100 void replay_soft_interrupts(void) 72 101 { 73 102 struct pt_regs regs; ··· 108 79 * recurse into this function. Don't keep any state across 109 80 * interrupt handler calls which may change underneath us. 110 81 * 82 + * Softirqs can not be disabled over replay to stop this recursion 83 + * because interrupts taken in idle code may require RCU softirq 84 + * to run in the irq RCU tracking context. This is a hard problem 85 + * to fix without changes to the softirq or idle layer. 86 + * 111 87 * We use local_paca rather than get_paca() to avoid all the 112 88 * debug_smp_processor_id() business in this low level function. 113 89 */ 90 + 91 + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) { 92 + WARN_ON_ONCE(mfmsr() & MSR_EE); 93 + WARN_ON(!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)); 94 + } 114 95 115 96 ppc_save_regs(&regs); 116 97 regs.softe = IRQS_ENABLED; 117 98 regs.msr |= MSR_EE; 118 99 119 100 again: 120 - if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) 121 - WARN_ON_ONCE(mfmsr() & MSR_EE); 122 - 123 101 /* 124 102 * Force the delivery of pending soft-disabled interrupts on PS3. 125 103 * Any HV call will have this side effect. ··· 141 105 * This is a higher priority interrupt than the others, so 142 106 * replay it first. 143 107 */ 144 - if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_HMI)) { 145 - local_paca->irq_happened &= ~PACA_IRQ_HMI; 108 + if (IS_ENABLED(CONFIG_PPC_BOOK3S) && 109 + irq_happened_test_and_clear(PACA_IRQ_HMI)) { 146 110 regs.trap = INTERRUPT_HMI; 147 111 handle_hmi_exception(&regs); 148 - if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) 149 - hard_irq_disable(); 112 + next_interrupt(&regs); 150 113 } 151 114 152 - if (local_paca->irq_happened & PACA_IRQ_DEC) { 153 - local_paca->irq_happened &= ~PACA_IRQ_DEC; 115 + if (irq_happened_test_and_clear(PACA_IRQ_DEC)) { 154 116 regs.trap = INTERRUPT_DECREMENTER; 155 117 timer_interrupt(&regs); 156 - if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) 157 - hard_irq_disable(); 118 + next_interrupt(&regs); 158 119 } 159 120 160 - if (local_paca->irq_happened & PACA_IRQ_EE) { 161 - local_paca->irq_happened &= ~PACA_IRQ_EE; 121 + if (irq_happened_test_and_clear(PACA_IRQ_EE)) { 162 122 regs.trap = INTERRUPT_EXTERNAL; 163 123 do_IRQ(&regs); 164 - if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) 165 - hard_irq_disable(); 124 + next_interrupt(&regs); 166 125 } 167 126 168 - if (IS_ENABLED(CONFIG_PPC_DOORBELL) && (local_paca->irq_happened & PACA_IRQ_DBELL)) { 169 - local_paca->irq_happened &= ~PACA_IRQ_DBELL; 127 + if (IS_ENABLED(CONFIG_PPC_DOORBELL) && 128 + irq_happened_test_and_clear(PACA_IRQ_DBELL)) { 170 129 regs.trap = INTERRUPT_DOORBELL; 171 130 doorbell_exception(&regs); 172 - if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) 173 - hard_irq_disable(); 131 + next_interrupt(&regs); 174 132 } 175 133 176 134 /* Book3E does not support soft-masking PMI interrupts */ 177 - if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_PMI)) { 178 - local_paca->irq_happened &= ~PACA_IRQ_PMI; 135 + if (IS_ENABLED(CONFIG_PPC_BOOK3S) && 136 + irq_happened_test_and_clear(PACA_IRQ_PMI)) { 179 137 regs.trap = INTERRUPT_PERFMON; 180 138 performance_monitor_exception(&regs); 181 - if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) 182 - hard_irq_disable(); 139 + next_interrupt(&regs); 183 140 } 184 141 185 - if (local_paca->irq_happened & ~PACA_IRQ_HARD_DIS) { 186 - /* 187 - * We are responding to the next interrupt, so interrupt-off 188 - * latencies should be reset here. 189 - */ 190 - trace_hardirqs_on(); 191 - trace_hardirqs_off(); 142 + /* 143 + * Softirq processing can enable and disable interrupts, which can 144 + * result in new irqs becoming pending. Must keep looping until we 145 + * have cleared out all pending interrupts. 146 + */ 147 + if (local_paca->irq_happened & ~PACA_IRQ_HARD_DIS) 192 148 goto again; 193 - } 194 149 } 195 150 196 151 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_KUAP) ··· 297 270 trace_hardirqs_off(); 298 271 299 272 replay_soft_interrupts_irqrestore(); 300 - local_paca->irq_happened = 0; 301 273 302 274 trace_hardirqs_on(); 303 275 irq_soft_mask_set(IRQS_ENABLED); 276 + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) 277 + WARN_ON(local_paca->irq_happened != PACA_IRQ_HARD_DIS); 278 + local_paca->irq_happened = 0; 304 279 __hard_irq_enable(); 305 280 preempt_enable(); 306 281 }

+6 -6

arch/powerpc/kernel/kgdb.c

··· 47 47 { 0x0c00, 0x14 /* SIGCHLD */ }, /* system call */ 48 48 #ifdef CONFIG_BOOKE_OR_40x 49 49 { 0x2002, 0x05 /* SIGTRAP */ }, /* debug */ 50 - #if defined(CONFIG_FSL_BOOKE) 50 + #if defined(CONFIG_PPC_85xx) 51 51 { 0x2010, 0x08 /* SIGFPE */ }, /* spe unavailable */ 52 52 { 0x2020, 0x08 /* SIGFPE */ }, /* spe unavailable */ 53 53 { 0x2030, 0x08 /* SIGFPE */ }, /* spe fp data */ ··· 57 57 { 0x2900, 0x08 /* SIGFPE */ }, /* apu unavailable */ 58 58 { 0x3100, 0x0e /* SIGALRM */ }, /* fixed interval timer */ 59 59 { 0x3200, 0x02 /* SIGINT */ }, /* watchdog */ 60 - #else /* ! CONFIG_FSL_BOOKE */ 60 + #else /* ! CONFIG_PPC_85xx */ 61 61 { 0x1000, 0x0e /* SIGALRM */ }, /* prog interval timer */ 62 62 { 0x1010, 0x0e /* SIGALRM */ }, /* fixed interval timer */ 63 63 { 0x1020, 0x02 /* SIGINT */ }, /* watchdog */ ··· 208 208 for (reg = 14; reg < 32; reg++) 209 209 PACK64(ptr, regs->gpr[reg]); 210 210 211 - #ifdef CONFIG_FSL_BOOKE 211 + #ifdef CONFIG_PPC_85xx 212 212 #ifdef CONFIG_SPE 213 213 for (reg = 0; reg < 32; reg++) 214 214 PACK64(ptr, p->thread.evr[reg]); ··· 234 234 #define GDB_SIZEOF_REG sizeof(unsigned long) 235 235 #define GDB_SIZEOF_REG_U32 sizeof(u32) 236 236 237 - #ifdef CONFIG_FSL_BOOKE 237 + #ifdef CONFIG_PPC_85xx 238 238 #define GDB_SIZEOF_FLOAT_REG sizeof(unsigned long) 239 239 #else 240 240 #define GDB_SIZEOF_FLOAT_REG sizeof(u64) ··· 329 329 330 330 if (regno >= 32 && regno < 64) { 331 331 /* FP registers 32 -> 63 */ 332 - #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_SPE) 332 + #if defined(CONFIG_PPC_85xx) && defined(CONFIG_SPE) 333 333 if (current) 334 334 memcpy(mem, &current->thread.evr[regno-32], 335 335 dbg_reg_def[regno].size); ··· 355 355 356 356 if (regno >= 32 && regno < 64) { 357 357 /* FP registers 32 -> 63 */ 358 - #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_SPE) 358 + #if defined(CONFIG_PPC_85xx) && defined(CONFIG_SPE) 359 359 memcpy(&current->thread.evr[regno-32], mem, 360 360 dbg_reg_def[regno].size); 361 361 #else

+7 -1

arch/powerpc/kernel/kprobes.c

··· 161 161 preempt_disable(); 162 162 prev = get_kprobe(p->addr - 1); 163 163 preempt_enable_no_resched(); 164 - if (prev && ppc_inst_prefixed(ppc_inst_read(prev->ainsn.insn))) { 164 + 165 + /* 166 + * When prev is a ftrace-based kprobe, we don't have an insn, and it 167 + * doesn't probe for prefixed instruction. 168 + */ 169 + if (prev && !kprobe_ftrace(prev) && 170 + ppc_inst_prefixed(ppc_inst_read(prev->ainsn.insn))) { 165 171 printk("Cannot register a kprobe on the second word of prefixed instruction\n"); 166 172 ret = -EINVAL; 167 173 }

+4 -4

arch/powerpc/kernel/kvm.c

··· 455 455 kvm_patch_ins_lwz(inst, magic_var(dsisr), inst_rt); 456 456 break; 457 457 458 - #ifdef CONFIG_PPC_BOOK3E_MMU 458 + #ifdef CONFIG_PPC_E500 459 459 case KVM_INST_MFSPR(SPRN_MAS0): 460 460 if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7) 461 461 kvm_patch_ins_lwz(inst, magic_var(mas0), inst_rt); ··· 484 484 if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7) 485 485 kvm_patch_ins_lwz(inst, magic_var(mas7_3), inst_rt); 486 486 break; 487 - #endif /* CONFIG_PPC_BOOK3E_MMU */ 487 + #endif /* CONFIG_PPC_E500 */ 488 488 489 489 case KVM_INST_MFSPR(SPRN_SPRG4): 490 490 #ifdef CONFIG_BOOKE ··· 557 557 case KVM_INST_MTSPR(SPRN_DSISR): 558 558 kvm_patch_ins_stw(inst, magic_var(dsisr), inst_rt); 559 559 break; 560 - #ifdef CONFIG_PPC_BOOK3E_MMU 560 + #ifdef CONFIG_PPC_E500 561 561 case KVM_INST_MTSPR(SPRN_MAS0): 562 562 if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7) 563 563 kvm_patch_ins_stw(inst, magic_var(mas0), inst_rt); ··· 586 586 if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7) 587 587 kvm_patch_ins_stw(inst, magic_var(mas7_3), inst_rt); 588 588 break; 589 - #endif /* CONFIG_PPC_BOOK3E_MMU */ 589 + #endif /* CONFIG_PPC_E500 */ 590 590 591 591 case KVM_INST_MTSPR(SPRN_SPRG4): 592 592 if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)

+2

arch/powerpc/kernel/legacy_serial.c

··· 471 471 } 472 472 #endif 473 473 474 + of_node_put(stdout); 475 + 474 476 DBG("legacy_serial_console = %d\n", legacy_serial_console); 475 477 if (legacy_serial_console >= 0) 476 478 setup_legacy_serial_console(legacy_serial_console);

+3 -3

arch/powerpc/kernel/misc_64.S

··· 286 286 287 287 288 288 #ifdef CONFIG_KEXEC_CORE 289 - #ifdef CONFIG_PPC_BOOK3E 289 + #ifdef CONFIG_PPC_BOOK3E_64 290 290 /* 291 291 * BOOK3E has no real MMU mode, so we have to setup the initial TLB 292 292 * for a core to identity map v:0 to p:0. This current implementation ··· 354 354 * don't overwrite r3 here, it is live for kexec_wait above. 355 355 */ 356 356 real_mode: /* assume normal blr return */ 357 - #ifdef CONFIG_PPC_BOOK3E 357 + #ifdef CONFIG_PPC_BOOK3E_64 358 358 /* Create an identity mapping. */ 359 359 b kexec_create_tlb 360 360 #else ··· 413 413 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */ 414 414 415 415 /* disable interrupts, we are overwriting kernel data next */ 416 - #ifdef CONFIG_PPC_BOOK3E 416 + #ifdef CONFIG_PPC_BOOK3E_64 417 417 wrteei 0 418 418 #else 419 419 mfmsr r3

+1 -1

arch/powerpc/kernel/optprobes_head.S

··· 73 73 * further below. 74 74 */ 75 75 #ifdef CONFIG_PPC64 76 - ld r2,PACATOC(r13) 76 + LOAD_PACA_TOC() 77 77 #endif 78 78 79 79 .global optprobe_template_op_address

+3 -35

arch/powerpc/kernel/paca.c

··· 16 16 #include <asm/kexec.h> 17 17 #include <asm/svm.h> 18 18 #include <asm/ultravisor.h> 19 - #include <asm/rtas.h> 20 19 21 20 #include "setup.h" 22 21 ··· 169 170 } 170 171 #endif /* CONFIG_PPC_64S_HASH_MMU */ 171 172 172 - #ifdef CONFIG_PPC_PSERIES 173 - /** 174 - * new_rtas_args() - Allocates rtas args 175 - * @cpu: CPU number 176 - * @limit: Memory limit for this allocation 177 - * 178 - * Allocates a struct rtas_args and return it's pointer, 179 - * if not in Hypervisor mode 180 - * 181 - * Return: Pointer to allocated rtas_args 182 - * NULL if CPU in Hypervisor Mode 183 - */ 184 - static struct rtas_args * __init new_rtas_args(int cpu, unsigned long limit) 185 - { 186 - limit = min_t(unsigned long, limit, RTAS_INSTANTIATE_MAX); 187 - 188 - if (early_cpu_has_feature(CPU_FTR_HVMODE)) 189 - return NULL; 190 - 191 - return alloc_paca_data(sizeof(struct rtas_args), L1_CACHE_BYTES, 192 - limit, cpu); 193 - } 194 - #endif /* CONFIG_PPC_PSERIES */ 195 - 196 173 /* The Paca is an array with one entry per processor. Each contains an 197 174 * lppaca, which contains the information shared between the 198 175 * hypervisor and Linux. ··· 186 211 #ifdef CONFIG_PPC_PSERIES 187 212 new_paca->lppaca_ptr = NULL; 188 213 #endif 189 - #ifdef CONFIG_PPC_BOOK3E 214 + #ifdef CONFIG_PPC_BOOK3E_64 190 215 new_paca->kernel_pgd = swapper_pg_dir; 191 216 #endif 192 217 new_paca->lock_token = 0x8000; ··· 203 228 new_paca->slb_shadow_ptr = NULL; 204 229 #endif 205 230 206 - #ifdef CONFIG_PPC_BOOK3E 231 + #ifdef CONFIG_PPC_BOOK3E_64 207 232 /* For now -- if we have threads this will be adjusted later */ 208 233 new_paca->tcd_ptr = &new_paca->tcd; 209 - #endif 210 - 211 - #ifdef CONFIG_PPC_PSERIES 212 - new_paca->rtas_args_reentrant = NULL; 213 234 #endif 214 235 } 215 236 ··· 215 244 /* Setup r13 */ 216 245 local_paca = new_paca; 217 246 218 - #ifdef CONFIG_PPC_BOOK3E 247 + #ifdef CONFIG_PPC_BOOK3E_64 219 248 /* On Book3E, initialize the TLB miss exception frames */ 220 249 mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb); 221 250 #else ··· 278 307 #endif 279 308 #ifdef CONFIG_PPC_64S_HASH_MMU 280 309 paca->slb_shadow_ptr = new_slb_shadow(cpu, limit); 281 - #endif 282 - #ifdef CONFIG_PPC_PSERIES 283 - paca->rtas_args_reentrant = new_rtas_args(cpu, limit); 284 310 #endif 285 311 paca_struct_size += sizeof(struct paca_struct); 286 312 }

+2 -2

arch/powerpc/kernel/pci-common.c

··· 135 135 list_add_tail(&phb->list_node, &hose_list); 136 136 spin_unlock(&hose_spinlock); 137 137 138 - phb->dn = dev; 138 + phb->dn = of_node_get(dev); 139 139 phb->is_dynamic = slab_is_available(); 140 140 #ifdef CONFIG_PPC64 141 141 if (dev) { ··· 158 158 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */ 159 159 if (phb->global_number < MAX_PHBS) 160 160 clear_bit(phb->global_number, phb_bitmap); 161 - 161 + of_node_put(phb->dn); 162 162 list_del(&phb->list_node); 163 163 spin_unlock(&hose_spinlock); 164 164

+1

arch/powerpc/kernel/pci_dn.c

··· 330 330 INIT_LIST_HEAD(&pdn->list); 331 331 parent = of_get_parent(dn); 332 332 pdn->parent = parent ? PCI_DN(parent) : NULL; 333 + of_node_put(parent); 333 334 if (pdn->parent) 334 335 list_add_tail(&pdn->list, &pdn->parent->child_list); 335 336

+3 -3

arch/powerpc/kernel/ppc32.h arch/powerpc/include/asm/syscalls_32.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - #ifndef _PPC64_PPC32_H 3 - #define _PPC64_PPC32_H 2 + #ifndef _ASM_POWERPC_SYSCALLS_32_H 3 + #define _ASM_POWERPC_SYSCALLS_32_H 4 4 5 5 #include <linux/compat.h> 6 6 #include <asm/siginfo.h> ··· 57 57 struct mcontext32 uc_mcontext; 58 58 }; 59 59 60 - #endif /* _PPC64_PPC32_H */ 60 + #endif // _ASM_POWERPC_SYSCALLS_32_H

+2 -2

arch/powerpc/kernel/process.c

··· 127 127 newmsr |= MSR_VSX; 128 128 129 129 if (oldmsr != newmsr) 130 - mtmsr_isync(newmsr); 130 + newmsr = mtmsr_isync_irqsafe(newmsr); 131 131 132 132 return newmsr; 133 133 } ··· 145 145 newmsr &= ~MSR_VSX; 146 146 147 147 if (oldmsr != newmsr) 148 - mtmsr_isync(newmsr); 148 + mtmsr_isync_irqsafe(newmsr); 149 149 } 150 150 EXPORT_SYMBOL(__msr_check_and_clear); 151 151

+52 -11

arch/powerpc/kernel/prom.c

··· 30 30 #include <linux/libfdt.h> 31 31 #include <linux/cpu.h> 32 32 #include <linux/pgtable.h> 33 + #include <linux/seq_buf.h> 33 34 34 35 #include <asm/rtas.h> 35 36 #include <asm/page.h> ··· 138 137 } 139 138 140 139 /* 141 - * ibm,pa-features is a per-cpu property that contains a string of 140 + * ibm,pa/pi-features is a per-cpu property that contains a string of 142 141 * attribute descriptors, each of which has a 2 byte header plus up 143 142 * to 254 bytes worth of processor attribute bits. First header 144 143 * byte specifies the number of bytes following the header. ··· 150 149 * is supported/not supported. Note that the bit numbers are 151 150 * big-endian to match the definition in PAPR. 152 151 */ 153 - static struct ibm_pa_feature { 152 + struct ibm_feature { 154 153 unsigned long cpu_features; /* CPU_FTR_xxx bit */ 155 154 unsigned long mmu_features; /* MMU_FTR_xxx bit */ 156 155 unsigned int cpu_user_ftrs; /* PPC_FEATURE_xxx bit */ 157 156 unsigned int cpu_user_ftrs2; /* PPC_FEATURE2_xxx bit */ 158 - unsigned char pabyte; /* byte number in ibm,pa-features */ 157 + unsigned char pabyte; /* byte number in ibm,pa/pi-features */ 159 158 unsigned char pabit; /* bit number (big-endian) */ 160 159 unsigned char invert; /* if 1, pa bit set => clear feature */ 161 - } ibm_pa_features[] __initdata = { 160 + }; 161 + 162 + static struct ibm_feature ibm_pa_features[] __initdata = { 162 163 { .pabyte = 0, .pabit = 0, .cpu_user_ftrs = PPC_FEATURE_HAS_MMU }, 163 164 { .pabyte = 0, .pabit = 1, .cpu_user_ftrs = PPC_FEATURE_HAS_FPU }, 164 165 { .pabyte = 0, .pabit = 3, .cpu_features = CPU_FTR_CTRL }, ··· 182 179 { .pabyte = 64, .pabit = 0, .cpu_features = CPU_FTR_DAWR1 }, 183 180 }; 184 181 182 + /* 183 + * ibm,pi-features property provides the support of processor specific 184 + * options not described in ibm,pa-features. Right now use byte 0, bit 3 185 + * which indicates the occurrence of DSI interrupt when the paste operation 186 + * on the suspended NX window. 187 + */ 188 + static struct ibm_feature ibm_pi_features[] __initdata = { 189 + { .pabyte = 0, .pabit = 3, .mmu_features = MMU_FTR_NX_DSI }, 190 + }; 191 + 185 192 static void __init scan_features(unsigned long node, const unsigned char *ftrs, 186 193 unsigned long tablelen, 187 - struct ibm_pa_feature *fp, 194 + struct ibm_feature *fp, 188 195 unsigned long ft_size) 189 196 { 190 197 unsigned long i, len, bit; ··· 231 218 } 232 219 } 233 220 234 - static void __init check_cpu_pa_features(unsigned long node) 221 + static void __init check_cpu_features(unsigned long node, char *name, 222 + struct ibm_feature *fp, 223 + unsigned long size) 235 224 { 236 225 const unsigned char *pa_ftrs; 237 226 int tablelen; 238 227 239 - pa_ftrs = of_get_flat_dt_prop(node, "ibm,pa-features", &tablelen); 228 + pa_ftrs = of_get_flat_dt_prop(node, name, &tablelen); 240 229 if (pa_ftrs == NULL) 241 230 return; 242 231 243 - scan_features(node, pa_ftrs, tablelen, 244 - ibm_pa_features, ARRAY_SIZE(ibm_pa_features)); 232 + scan_features(node, pa_ftrs, tablelen, fp, size); 245 233 } 246 234 247 235 #ifdef CONFIG_PPC_64S_HASH_MMU ··· 390 376 */ 391 377 if (!dt_cpu_ftrs_in_use()) { 392 378 prop = of_get_flat_dt_prop(node, "cpu-version", NULL); 393 - if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000) 379 + if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000) { 394 380 identify_cpu(0, be32_to_cpup(prop)); 381 + seq_buf_printf(&ppc_hw_desc, "0x%04x ", be32_to_cpup(prop)); 382 + } 395 383 396 384 check_cpu_feature_properties(node); 397 - check_cpu_pa_features(node); 385 + check_cpu_features(node, "ibm,pa-features", ibm_pa_features, 386 + ARRAY_SIZE(ibm_pa_features)); 387 + check_cpu_features(node, "ibm,pi-features", ibm_pi_features, 388 + ARRAY_SIZE(ibm_pi_features)); 398 389 } 399 390 400 391 identical_pvr_fixup(node); ··· 715 696 static void tm_init(void) { } 716 697 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 717 698 699 + static int __init 700 + early_init_dt_scan_model(unsigned long node, const char *uname, 701 + int depth, void *data) 702 + { 703 + const char *prop; 704 + 705 + if (depth != 0) 706 + return 0; 707 + 708 + prop = of_get_flat_dt_prop(node, "model", NULL); 709 + if (prop) 710 + seq_buf_printf(&ppc_hw_desc, "%s ", prop); 711 + 712 + /* break now */ 713 + return 1; 714 + } 715 + 718 716 #ifdef CONFIG_PPC64 719 717 static void __init save_fscr_to_task(void) 720 718 { ··· 759 723 /* Too early to BUG_ON(), do it by hand */ 760 724 if (!early_init_dt_verify(params)) 761 725 panic("BUG: Failed verifying flat device tree, bad version?"); 726 + 727 + of_scan_flat_dt(early_init_dt_scan_model, NULL); 762 728 763 729 #ifdef CONFIG_PPC_RTAS 764 730 /* Some machines might need RTAS info for debugging, grab it now. */ ··· 840 802 DBG("Scanning CPUs ...\n"); 841 803 842 804 dt_cpu_ftrs_scan(); 805 + 806 + // We can now add the CPU name & PVR to the hardware description 807 + seq_buf_printf(&ppc_hw_desc, "%s 0x%04lx ", cur_cpu_spec->cpu_name, mfspr(SPRN_PVR)); 843 808 844 809 /* Retrieve CPU related informations from the flat tree 845 810 * (altivec support, boot CPU ID, ...)

-6

arch/powerpc/kernel/prom_init.c

··· 96 96 #define OF_WA_CLAIM 1 /* do phys/virt claim separately, then map */ 97 97 #define OF_WA_LONGTRAIL 2 /* work around longtrail bugs */ 98 98 99 - #define PROM_BUG() do { \ 100 - prom_printf("kernel BUG at %s line 0x%x!\n", \ 101 - __FILE__, __LINE__); \ 102 - __builtin_trap(); \ 103 - } while (0) 104 - 105 99 #ifdef DEBUG_PROM 106 100 #define prom_debug(x...) prom_printf(x) 107 101 #else

+1 -2

arch/powerpc/kernel/prom_init_check.sh

··· 26 26 __secondary_hold_acknowledge __secondary_hold_spinloop __start 27 27 logo_linux_clut224 btext_prepare_BAT 28 28 reloc_got2 kernstart_addr memstart_addr linux_banner _stext 29 - __prom_init_toc_start __prom_init_toc_end btext_setup_display TOC. 30 - relocate" 29 + btext_setup_display TOC. relocate" 31 30 32 31 NM="$1" 33 32 OBJ="$2"

+7 -7

arch/powerpc/kernel/reloc_64.S

··· 27 27 add r9,r9,r12 /* r9 has runtime addr of .rela.dyn section */ 28 28 ld r10,(p_st - 0b)(r12) 29 29 add r10,r10,r12 /* r10 has runtime addr of _stext */ 30 - ld r13,(p_sym - 0b)(r12) 31 - add r13,r13,r12 /* r13 has runtime addr of .dynsym */ 30 + ld r4,(p_sym - 0b)(r12) 31 + add r4,r4,r12 /* r4 has runtime addr of .dynsym */ 32 32 33 33 /* 34 34 * Scan the dynamic section for the RELA, RELASZ and RELAENT entries. ··· 84 84 ld r0,16(r9) /* reloc->r_addend */ 85 85 b .Lstore 86 86 .Luaddr64: 87 - srdi r14,r0,32 /* ELF64_R_SYM(reloc->r_info) */ 87 + srdi r5,r0,32 /* ELF64_R_SYM(reloc->r_info) */ 88 88 clrldi r0,r0,32 89 89 cmpdi r0,R_PPC64_UADDR64 90 90 bne .Lnext 91 91 ld r6,0(r9) 92 92 ld r0,16(r9) 93 - mulli r14,r14,24 /* 24 == sizeof(elf64_sym) */ 94 - add r14,r14,r13 /* elf64_sym[ELF64_R_SYM] */ 95 - ld r14,8(r14) 96 - add r0,r0,r14 93 + mulli r5,r5,24 /* 24 == sizeof(elf64_sym) */ 94 + add r5,r5,r4 /* elf64_sym[ELF64_R_SYM] */ 95 + ld r5,8(r5) 96 + add r0,r0,r5 97 97 .Lstore: 98 98 add r0,r0,r3 99 99 stdx r0,r7,r6

+24 -55

arch/powerpc/kernel/rtas.c

··· 23 23 #include <linux/memblock.h> 24 24 #include <linux/slab.h> 25 25 #include <linux/reboot.h> 26 + #include <linux/security.h> 26 27 #include <linux/syscalls.h> 27 28 #include <linux/of.h> 28 29 #include <linux/of_fdt.h> ··· 44 43 #include <asm/time.h> 45 44 #include <asm/mmu.h> 46 45 #include <asm/topology.h> 47 - #include <asm/paca.h> 48 46 49 47 /* This is here deliberately so it's only used in this file */ 50 48 void enter_rtas(unsigned long); ··· 464 464 va_end(list); 465 465 } 466 466 467 + static int ibm_open_errinjct_token; 468 + static int ibm_errinjct_token; 469 + 467 470 int rtas_call(int token, int nargs, int nret, int *outputs, ...) 468 471 { 469 472 va_list list; ··· 478 475 479 476 if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE) 480 477 return -1; 478 + 479 + if (token == ibm_open_errinjct_token || token == ibm_errinjct_token) { 480 + /* 481 + * It would be nicer to not discard the error value 482 + * from security_locked_down(), but callers expect an 483 + * RTAS status, not an errno. 484 + */ 485 + if (security_locked_down(LOCKDOWN_RTAS_ERROR_INJECTION)) 486 + return -1; 487 + } 481 488 482 489 if ((mfmsr() & (MSR_IR|MSR_DR)) != (MSR_IR|MSR_DR)) { 483 490 WARN_ON_ONCE(1); ··· 945 932 pr_err("ibm,activate-firmware failed (%i)\n", fwrc); 946 933 } 947 934 948 - #ifdef CONFIG_PPC_PSERIES 949 - /** 950 - * rtas_call_reentrant() - Used for reentrant rtas calls 951 - * @token: Token for desired reentrant RTAS call 952 - * @nargs: Number of Input Parameters 953 - * @nret: Number of Output Parameters 954 - * @outputs: Array of outputs 955 - * @...: Inputs for desired RTAS call 956 - * 957 - * According to LoPAR documentation, only "ibm,int-on", "ibm,int-off", 958 - * "ibm,get-xive" and "ibm,set-xive" are currently reentrant. 959 - * Reentrant calls need their own rtas_args buffer, so not using rtas.args, but 960 - * PACA one instead. 961 - * 962 - * Return: -1 on error, 963 - * First output value of RTAS call if (nret > 0), 964 - * 0 otherwise, 965 - */ 966 - int rtas_call_reentrant(int token, int nargs, int nret, int *outputs, ...) 967 - { 968 - va_list list; 969 - struct rtas_args *args; 970 - unsigned long flags; 971 - int i, ret = 0; 972 - 973 - if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE) 974 - return -1; 975 - 976 - local_irq_save(flags); 977 - preempt_disable(); 978 - 979 - /* We use the per-cpu (PACA) rtas args buffer */ 980 - args = local_paca->rtas_args_reentrant; 981 - 982 - va_start(list, outputs); 983 - va_rtas_call_unlocked(args, token, nargs, nret, list); 984 - va_end(list); 985 - 986 - if (nret > 1 && outputs) 987 - for (i = 0; i < nret - 1; ++i) 988 - outputs[i] = be32_to_cpu(args->rets[i + 1]); 989 - 990 - if (nret > 0) 991 - ret = be32_to_cpu(args->rets[0]); 992 - 993 - local_irq_restore(flags); 994 - preempt_enable(); 995 - 996 - return ret; 997 - } 998 - 999 - #endif /* CONFIG_PPC_PSERIES */ 1000 - 1001 935 /** 1002 936 * get_pseries_errorlog() - Find a specific pseries error log in an RTAS 1003 937 * extended event log. ··· 1187 1227 if (block_rtas_call(token, nargs, &args)) 1188 1228 return -EINVAL; 1189 1229 1230 + if (token == ibm_open_errinjct_token || token == ibm_errinjct_token) { 1231 + int err; 1232 + 1233 + err = security_locked_down(LOCKDOWN_RTAS_ERROR_INJECTION); 1234 + if (err) 1235 + return err; 1236 + } 1237 + 1190 1238 /* Need to handle ibm,suspend_me call specially */ 1191 1239 if (token == rtas_token("ibm,suspend-me")) { 1192 1240 ··· 1293 1325 #ifdef CONFIG_RTAS_ERROR_LOGGING 1294 1326 rtas_last_error_token = rtas_token("rtas-last-error"); 1295 1327 #endif 1296 - 1328 + ibm_open_errinjct_token = rtas_token("ibm,open-errinjct"); 1329 + ibm_errinjct_token = rtas_token("ibm,errinjct"); 1297 1330 rtas_syscall_filter_init(); 1298 1331 } 1299 1332

+6 -5

arch/powerpc/kernel/security.c

··· 16 16 #include <asm/asm-prototypes.h> 17 17 #include <asm/code-patching.h> 18 18 #include <asm/security_features.h> 19 + #include <asm/sections.h> 19 20 #include <asm/setup.h> 20 21 #include <asm/inst.h> 21 22 ··· 35 34 bool barrier_nospec_enabled; 36 35 static bool no_nospec; 37 36 static bool btb_flush_enabled; 38 - #if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_BOOK3S_64) 37 + #if defined(CONFIG_PPC_E500) || defined(CONFIG_PPC_BOOK3S_64) 39 38 static bool no_spectrev2; 40 39 #endif 41 40 ··· 122 121 device_initcall(security_feature_debugfs_init); 123 122 #endif /* CONFIG_DEBUG_FS */ 124 123 125 - #if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_BOOK3S_64) 124 + #if defined(CONFIG_PPC_E500) || defined(CONFIG_PPC_BOOK3S_64) 126 125 static int __init handle_nospectre_v2(char *p) 127 126 { 128 127 no_spectrev2 = true; ··· 130 129 return 0; 131 130 } 132 131 early_param("nospectre_v2", handle_nospectre_v2); 133 - #endif /* CONFIG_PPC_FSL_BOOK3E || CONFIG_PPC_BOOK3S_64 */ 132 + #endif /* CONFIG_PPC_E500 || CONFIG_PPC_BOOK3S_64 */ 134 133 135 - #ifdef CONFIG_PPC_FSL_BOOK3E 134 + #ifdef CONFIG_PPC_E500 136 135 void __init setup_spectre_v2(void) 137 136 { 138 137 if (no_spectrev2 || cpu_mitigations_off()) ··· 140 139 else 141 140 btb_flush_enabled = true; 142 141 } 143 - #endif /* CONFIG_PPC_FSL_BOOK3E */ 142 + #endif /* CONFIG_PPC_E500 */ 144 143 145 144 #ifdef CONFIG_PPC_BOOK3S_64 146 145 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)

+18 -1

arch/powerpc/kernel/setup-common.c

··· 18 18 #include <linux/delay.h> 19 19 #include <linux/initrd.h> 20 20 #include <linux/platform_device.h> 21 + #include <linux/printk.h> 21 22 #include <linux/seq_file.h> 22 23 #include <linux/ioport.h> 23 24 #include <linux/console.h> ··· 26 25 #include <linux/root_dev.h> 27 26 #include <linux/cpu.h> 28 27 #include <linux/unistd.h> 28 + #include <linux/seq_buf.h> 29 29 #include <linux/serial.h> 30 30 #include <linux/serial_8250.h> 31 31 #include <linux/percpu.h> ··· 590 588 device_initcall(add_pcspkr); 591 589 #endif /* CONFIG_PCSPKR_PLATFORM */ 592 590 591 + static char ppc_hw_desc_buf[128] __initdata; 592 + 593 + struct seq_buf ppc_hw_desc __initdata = { 594 + .buffer = ppc_hw_desc_buf, 595 + .size = sizeof(ppc_hw_desc_buf), 596 + .len = 0, 597 + .readpos = 0, 598 + }; 599 + 593 600 static __init void probe_machine(void) 594 601 { 595 602 extern struct machdep_calls __machine_desc_start; ··· 639 628 for (;;); 640 629 } 641 630 642 - printk(KERN_INFO "Using %s machine description\n", ppc_md.name); 631 + // Append the machine name to other info we've gathered 632 + seq_buf_puts(&ppc_hw_desc, ppc_md.name); 633 + 634 + // Set the generic hardware description shown in oopses 635 + dump_stack_set_arch_desc(ppc_hw_desc.buffer); 636 + 637 + pr_info("Hardware name: %s\n", ppc_hw_desc.buffer); 643 638 } 644 639 645 640 /* Match a class of boards, not a specific device configuration. */

+1 -1

arch/powerpc/kernel/setup.h

··· 23 23 static inline void check_smt_enabled(void) { } 24 24 #endif 25 25 26 - #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 26 + #if defined(CONFIG_PPC_BOOK3E_64) && defined(CONFIG_SMP) 27 27 void setup_tlb_core_data(void); 28 28 #else 29 29 static inline void setup_tlb_core_data(void) { }

+1 -1

arch/powerpc/kernel/setup_32.c

··· 207 207 ppc_md.power_save = ppc6xx_idle; 208 208 #endif 209 209 210 - #ifdef CONFIG_E500 210 + #ifdef CONFIG_PPC_E500 211 211 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 212 212 cpu_has_feature(CPU_FTR_CAN_NAP)) 213 213 ppc_md.power_save = e500_idle;

+30 -13

arch/powerpc/kernel/setup_64.c

··· 34 34 #include <linux/of.h> 35 35 #include <linux/of_fdt.h> 36 36 37 + #include <asm/asm-prototypes.h> 37 38 #include <asm/kvm_guest.h> 38 39 #include <asm/io.h> 39 40 #include <asm/kdump.h> ··· 87 86 }; 88 87 EXPORT_SYMBOL_GPL(ppc64_caches); 89 88 90 - #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 89 + #if defined(CONFIG_PPC_BOOK3E_64) && defined(CONFIG_SMP) 91 90 void __init setup_tlb_core_data(void) 92 91 { 93 92 int cpu; ··· 177 176 #endif /* CONFIG_SMP */ 178 177 179 178 /** Fix up paca fields required for the boot cpu */ 180 - static void __init fixup_boot_paca(void) 179 + static void __init fixup_boot_paca(struct paca_struct *boot_paca) 181 180 { 182 181 /* The boot cpu is started */ 183 - get_paca()->cpu_start = 1; 182 + boot_paca->cpu_start = 1; 183 + #ifdef CONFIG_PPC_BOOK3S_64 184 + /* 185 + * Give the early boot machine check stack somewhere to use, use 186 + * half of the init stack. This is a bit hacky but there should not be 187 + * deep stack usage in early init so shouldn't overflow it or overwrite 188 + * things. 189 + */ 190 + boot_paca->mc_emergency_sp = (void *)&init_thread_union + 191 + (THREAD_SIZE/2); 192 + #endif 184 193 /* Allow percpu accesses to work until we setup percpu data */ 185 - get_paca()->data_offset = 0; 186 - /* Mark interrupts disabled in PACA */ 187 - irq_soft_mask_set(IRQS_DISABLED); 194 + boot_paca->data_offset = 0; 195 + /* Mark interrupts soft and hard disabled in PACA */ 196 + boot_paca->irq_soft_mask = IRQS_DISABLED; 197 + boot_paca->irq_happened = PACA_IRQ_HARD_DIS; 198 + WARN_ON(mfmsr() & MSR_EE); 188 199 } 189 200 190 201 static void __init configure_exceptions(void) ··· 363 350 * what CPU we are on. 364 351 */ 365 352 initialise_paca(&boot_paca, 0); 366 - setup_paca(&boot_paca); 367 - fixup_boot_paca(); 353 + fixup_boot_paca(&boot_paca); 354 + WARN_ON(local_paca != 0); 355 + setup_paca(&boot_paca); /* install the paca into registers */ 368 356 369 357 /* -------- printk is now safe to use ------- */ 358 + 359 + if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && (mfmsr() & MSR_HV)) 360 + enable_machine_check(); 370 361 371 362 /* Try new device tree based feature discovery ... */ 372 363 if (!dt_cpu_ftrs_init(__va(dt_ptr))) ··· 394 377 /* Poison paca_ptrs[0] again if it's not the boot cpu */ 395 378 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0])); 396 379 } 397 - setup_paca(paca_ptrs[boot_cpuid]); 398 - fixup_boot_paca(); 380 + fixup_boot_paca(paca_ptrs[boot_cpuid]); 381 + setup_paca(paca_ptrs[boot_cpuid]); /* install the paca into registers */ 399 382 400 383 /* 401 384 * Configure exception handlers. This include setting up trampolines ··· 690 673 */ 691 674 __init u64 ppc64_bolted_size(void) 692 675 { 693 - #ifdef CONFIG_PPC_BOOK3E 676 + #ifdef CONFIG_PPC_BOOK3E_64 694 677 /* Freescale BookE bolts the entire linear mapping */ 695 678 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */ 696 679 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) ··· 740 723 } 741 724 } 742 725 743 - #ifdef CONFIG_PPC_BOOK3E 726 + #ifdef CONFIG_PPC_BOOK3E_64 744 727 void __init exc_lvl_early_init(void) 745 728 { 746 729 unsigned int i; ··· 842 825 /* 843 826 * BookE and BookS radix are historical values and should be revisited. 844 827 */ 845 - if (IS_ENABLED(CONFIG_PPC_BOOK3E)) { 828 + if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) { 846 829 atom_size = SZ_1M; 847 830 } else if (radix_enabled()) { 848 831 atom_size = PAGE_SIZE;

-3

arch/powerpc/kernel/signal.h

··· 196 196 197 197 #else /* CONFIG_PPC64 */ 198 198 199 - extern long sys_rt_sigreturn(void); 200 - extern long sys_sigreturn(void); 201 - 202 199 static inline int handle_rt_signal64(struct ksignal *ksig, sigset_t *set, 203 200 struct task_struct *tsk) 204 201 {

+1 -1

arch/powerpc/kernel/signal_32.c

··· 43 43 #include <asm/tm.h> 44 44 #include <asm/asm-prototypes.h> 45 45 #ifdef CONFIG_PPC64 46 - #include "ppc32.h" 46 + #include <asm/syscalls_32.h> 47 47 #include <asm/unistd.h> 48 48 #else 49 49 #include <asm/ucontext.h>

+23 -17

arch/powerpc/kernel/smp.c

··· 708 708 static void smp_store_cpu_info(int id) 709 709 { 710 710 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); 711 - #ifdef CONFIG_PPC_FSL_BOOK3E 711 + #ifdef CONFIG_PPC_E500 712 712 per_cpu(next_tlbcam_idx, id) 713 713 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; 714 714 #endif ··· 1257 1257 1258 1258 int __cpu_up(unsigned int cpu, struct task_struct *tidle) 1259 1259 { 1260 - int rc, c; 1260 + const unsigned long boot_spin_ms = 5 * MSEC_PER_SEC; 1261 + const bool booting = system_state < SYSTEM_RUNNING; 1262 + const unsigned long hp_spin_ms = 1; 1263 + unsigned long deadline; 1264 + int rc; 1265 + const unsigned long spin_wait_ms = booting ? boot_spin_ms : hp_spin_ms; 1261 1266 1262 1267 /* 1263 1268 * Don't allow secondary threads to come online if inhibited ··· 1307 1302 } 1308 1303 1309 1304 /* 1310 - * wait to see if the cpu made a callin (is actually up). 1311 - * use this value that I found through experimentation. 1312 - * -- Cort 1305 + * At boot time, simply spin on the callin word until the 1306 + * deadline passes. 1307 + * 1308 + * At run time, spin for an optimistic amount of time to avoid 1309 + * sleeping in the common case. 1313 1310 */ 1314 - if (system_state < SYSTEM_RUNNING) 1315 - for (c = 50000; c && !cpu_callin_map[cpu]; c--) 1316 - udelay(100); 1317 - #ifdef CONFIG_HOTPLUG_CPU 1318 - else 1319 - /* 1320 - * CPUs can take much longer to come up in the 1321 - * hotplug case. Wait five seconds. 1322 - */ 1323 - for (c = 5000; c && !cpu_callin_map[cpu]; c--) 1324 - msleep(1); 1325 - #endif 1311 + deadline = jiffies + msecs_to_jiffies(spin_wait_ms); 1312 + spin_until_cond(cpu_callin_map[cpu] || time_is_before_jiffies(deadline)); 1313 + 1314 + if (!cpu_callin_map[cpu] && system_state >= SYSTEM_RUNNING) { 1315 + const unsigned long sleep_interval_us = 10 * USEC_PER_MSEC; 1316 + const unsigned long sleep_wait_ms = 100 * MSEC_PER_SEC; 1317 + 1318 + deadline = jiffies + msecs_to_jiffies(sleep_wait_ms); 1319 + while (!cpu_callin_map[cpu] && time_is_after_jiffies(deadline)) 1320 + fsleep(sleep_interval_us); 1321 + } 1326 1322 1327 1323 if (!cpu_callin_map[cpu]) { 1328 1324 printk(KERN_ERR "Processor %u is stuck.\n", cpu);

+5 -11

arch/powerpc/kernel/swsusp_asm64.S

··· 76 76 swsusp_save_area: 77 77 .space SL_SIZE 78 78 79 - .section ".toc","aw" 80 - swsusp_save_area_ptr: 81 - .tc swsusp_save_area[TC],swsusp_save_area 82 - restore_pblist_ptr: 83 - .tc restore_pblist[TC],restore_pblist 84 - 85 79 .section .text 86 80 .align 5 87 81 _GLOBAL(swsusp_arch_suspend) 88 - ld r11,swsusp_save_area_ptr@toc(r2) 82 + LOAD_REG_ADDR(r11, swsusp_save_area) 89 83 SAVE_SPECIAL(LR) 90 84 SAVE_REGISTER(r1) 91 85 SAVE_SPECIAL(CR) ··· 125 131 bl swsusp_save 126 132 127 133 /* restore LR */ 128 - ld r11,swsusp_save_area_ptr@toc(r2) 134 + LOAD_REG_ADDR(r11, swsusp_save_area) 129 135 RESTORE_SPECIAL(LR) 130 136 addi r1,r1,128 131 137 ··· 139 145 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 140 146 sync 141 147 142 - ld r12,restore_pblist_ptr@toc(r2) 148 + LOAD_REG_ADDR(r11, restore_pblist) 143 149 ld r12,0(r12) 144 150 145 151 cmpdi r12,0 ··· 181 187 tlbia 182 188 #endif 183 189 184 - ld r11,swsusp_save_area_ptr@toc(r2) 190 + LOAD_REG_ADDR(r11, swsusp_save_area) 185 191 186 192 RESTORE_SPECIAL(CR) 187 193 ··· 259 265 bl do_after_copyback 260 266 addi r1,r1,128 261 267 262 - ld r11,swsusp_save_area_ptr@toc(r2) 268 + LOAD_REG_ADDR(r11, swsusp_save_area) 263 269 RESTORE_SPECIAL(LR) 264 270 265 271 li r3, 0

arch/powerpc/kernel/swsusp_booke.S arch/powerpc/kernel/swsusp_85xx.S

+24 -42

arch/powerpc/kernel/sys_ppc32.c

··· 25 25 #include <linux/poll.h> 26 26 #include <linux/personality.h> 27 27 #include <linux/stat.h> 28 - #include <linux/mman.h> 29 28 #include <linux/in.h> 30 29 #include <linux/syscalls.h> 31 30 #include <linux/unistd.h> ··· 47 48 #include <asm/syscalls.h> 48 49 #include <asm/switch_to.h> 49 50 50 - unsigned long compat_sys_mmap2(unsigned long addr, size_t len, 51 - unsigned long prot, unsigned long flags, 52 - unsigned long fd, unsigned long pgoff) 53 - { 54 - /* This should remain 12 even if PAGE_SIZE changes */ 55 - return sys_mmap(addr, len, prot, flags, fd, pgoff << 12); 56 - } 57 - 58 - /* 59 - * long long munging: 60 - * The 32 bit ABI passes long longs in an odd even register pair. 61 - * High and low parts are swapped depending on endian mode, 62 - * so define a macro (similar to mips linux32) to handle that. 63 - */ 64 - #ifdef __LITTLE_ENDIAN__ 65 - #define merge_64(low, high) ((u64)high << 32) | low 66 - #else 67 - #define merge_64(high, low) ((u64)high << 32) | low 68 - #endif 69 - 70 - compat_ssize_t compat_sys_pread64(unsigned int fd, char __user *ubuf, compat_size_t count, 71 - u32 reg6, u32 pos1, u32 pos2) 51 + COMPAT_SYSCALL_DEFINE6(ppc_pread64, 52 + unsigned int, fd, 53 + char __user *, ubuf, compat_size_t, count, 54 + u32, reg6, u32, pos1, u32, pos2) 72 55 { 73 56 return ksys_pread64(fd, ubuf, count, merge_64(pos1, pos2)); 74 57 } 75 58 76 - compat_ssize_t compat_sys_pwrite64(unsigned int fd, const char __user *ubuf, compat_size_t count, 77 - u32 reg6, u32 pos1, u32 pos2) 59 + COMPAT_SYSCALL_DEFINE6(ppc_pwrite64, 60 + unsigned int, fd, 61 + const char __user *, ubuf, compat_size_t, count, 62 + u32, reg6, u32, pos1, u32, pos2) 78 63 { 79 64 return ksys_pwrite64(fd, ubuf, count, merge_64(pos1, pos2)); 80 65 } 81 66 82 - compat_ssize_t compat_sys_readahead(int fd, u32 r4, u32 offset1, u32 offset2, u32 count) 67 + COMPAT_SYSCALL_DEFINE5(ppc_readahead, 68 + int, fd, u32, r4, 69 + u32, offset1, u32, offset2, u32, count) 83 70 { 84 71 return ksys_readahead(fd, merge_64(offset1, offset2), count); 85 72 } 86 73 87 - asmlinkage int compat_sys_truncate64(const char __user * path, u32 reg4, 88 - unsigned long len1, unsigned long len2) 74 + COMPAT_SYSCALL_DEFINE4(ppc_truncate64, 75 + const char __user *, path, u32, reg4, 76 + unsigned long, len1, unsigned long, len2) 89 77 { 90 78 return ksys_truncate(path, merge_64(len1, len2)); 91 79 } 92 80 93 - asmlinkage long compat_sys_fallocate(int fd, int mode, u32 offset1, u32 offset2, 94 - u32 len1, u32 len2) 95 - { 96 - return ksys_fallocate(fd, mode, ((loff_t)offset1 << 32) | offset2, 97 - merge_64(len1, len2)); 98 - } 99 - 100 - asmlinkage int compat_sys_ftruncate64(unsigned int fd, u32 reg4, unsigned long len1, 101 - unsigned long len2) 81 + COMPAT_SYSCALL_DEFINE4(ppc_ftruncate64, 82 + unsigned int, fd, u32, reg4, 83 + unsigned long, len1, unsigned long, len2) 102 84 { 103 85 return ksys_ftruncate(fd, merge_64(len1, len2)); 104 86 } 105 87 106 - long ppc32_fadvise64(int fd, u32 unused, u32 offset1, u32 offset2, 107 - size_t len, int advice) 88 + COMPAT_SYSCALL_DEFINE6(ppc32_fadvise64, 89 + int, fd, u32, unused, u32, offset1, u32, offset2, 90 + size_t, len, int, advice) 108 91 { 109 92 return ksys_fadvise64_64(fd, merge_64(offset1, offset2), len, 110 93 advice); 111 94 } 112 95 113 - asmlinkage long compat_sys_sync_file_range2(int fd, unsigned int flags, 114 - unsigned offset1, unsigned offset2, 115 - unsigned nbytes1, unsigned nbytes2) 96 + COMPAT_SYSCALL_DEFINE6(ppc_sync_file_range2, 97 + int, fd, unsigned int, flags, 98 + unsigned int, offset1, unsigned int, offset2, 99 + unsigned int, nbytes1, unsigned int, nbytes2) 116 100 { 117 101 loff_t offset = merge_64(offset1, offset2); 118 102 loff_t nbytes = merge_64(nbytes1, nbytes2);

+19 -20

arch/powerpc/kernel/syscall.c

··· 12 12 #include <asm/unistd.h> 13 13 14 14 15 - typedef long (*syscall_fn)(long, long, long, long, long, long); 16 - 17 15 /* Has to run notrace because it is entered not completely "reconciled" */ 18 - notrace long system_call_exception(long r3, long r4, long r5, 19 - long r6, long r7, long r8, 20 - unsigned long r0, struct pt_regs *regs) 16 + notrace long system_call_exception(struct pt_regs *regs, unsigned long r0) 21 17 { 22 18 long ret; 23 19 syscall_fn f; ··· 21 25 kuap_lock(); 22 26 23 27 add_random_kstack_offset(); 24 - regs->orig_gpr3 = r3; 25 28 26 29 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) 27 30 BUG_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED); ··· 134 139 r0 = do_syscall_trace_enter(regs); 135 140 if (unlikely(r0 >= NR_syscalls)) 136 141 return regs->gpr[3]; 137 - r3 = regs->gpr[3]; 138 - r4 = regs->gpr[4]; 139 - r5 = regs->gpr[5]; 140 - r6 = regs->gpr[6]; 141 - r7 = regs->gpr[7]; 142 - r8 = regs->gpr[8]; 143 142 144 143 } else if (unlikely(r0 >= NR_syscalls)) { 145 144 if (unlikely(trap_is_unsupported_scv(regs))) { ··· 147 158 /* May be faster to do array_index_nospec? */ 148 159 barrier_nospec(); 149 160 161 + #ifdef CONFIG_ARCH_HAS_SYSCALL_WRAPPER 162 + // No COMPAT if we have SYSCALL_WRAPPER, see Kconfig 163 + f = (void *)sys_call_table[r0]; 164 + ret = f(regs); 165 + #else 150 166 if (unlikely(is_compat_task())) { 167 + unsigned long r3, r4, r5, r6, r7, r8; 168 + 151 169 f = (void *)compat_sys_call_table[r0]; 152 170 153 - r3 &= 0x00000000ffffffffULL; 154 - r4 &= 0x00000000ffffffffULL; 155 - r5 &= 0x00000000ffffffffULL; 156 - r6 &= 0x00000000ffffffffULL; 157 - r7 &= 0x00000000ffffffffULL; 158 - r8 &= 0x00000000ffffffffULL; 171 + r3 = regs->gpr[3] & 0x00000000ffffffffULL; 172 + r4 = regs->gpr[4] & 0x00000000ffffffffULL; 173 + r5 = regs->gpr[5] & 0x00000000ffffffffULL; 174 + r6 = regs->gpr[6] & 0x00000000ffffffffULL; 175 + r7 = regs->gpr[7] & 0x00000000ffffffffULL; 176 + r8 = regs->gpr[8] & 0x00000000ffffffffULL; 159 177 178 + ret = f(r3, r4, r5, r6, r7, r8); 160 179 } else { 161 180 f = (void *)sys_call_table[r0]; 162 - } 163 181 164 - ret = f(r3, r4, r5, r6, r7, r8); 182 + ret = f(regs->gpr[3], regs->gpr[4], regs->gpr[5], 183 + regs->gpr[6], regs->gpr[7], regs->gpr[8]); 184 + } 185 + #endif 165 186 166 187 /* 167 188 * Ultimately, this value will get limited by KSTACK_OFFSET_MAX(),

+33 -27

arch/powerpc/kernel/syscalls.c

··· 36 36 #include <asm/time.h> 37 37 #include <asm/unistd.h> 38 38 39 - static inline long do_mmap2(unsigned long addr, size_t len, 40 - unsigned long prot, unsigned long flags, 41 - unsigned long fd, unsigned long off, int shift) 39 + static long do_mmap2(unsigned long addr, size_t len, 40 + unsigned long prot, unsigned long flags, 41 + unsigned long fd, unsigned long off, int shift) 42 42 { 43 43 if (!arch_validate_prot(prot, addr)) 44 44 return -EINVAL; ··· 56 56 return do_mmap2(addr, len, prot, flags, fd, pgoff, PAGE_SHIFT-12); 57 57 } 58 58 59 + #ifdef CONFIG_COMPAT 60 + COMPAT_SYSCALL_DEFINE6(mmap2, 61 + unsigned long, addr, size_t, len, 62 + unsigned long, prot, unsigned long, flags, 63 + unsigned long, fd, unsigned long, off_4k) 64 + { 65 + return do_mmap2(addr, len, prot, flags, fd, off_4k, PAGE_SHIFT-12); 66 + } 67 + #endif 68 + 59 69 SYSCALL_DEFINE6(mmap, unsigned long, addr, size_t, len, 60 70 unsigned long, prot, unsigned long, flags, 61 71 unsigned long, fd, off_t, offset) ··· 73 63 return do_mmap2(addr, len, prot, flags, fd, offset, PAGE_SHIFT); 74 64 } 75 65 76 - #ifdef CONFIG_PPC32 77 - /* 78 - * Due to some executables calling the wrong select we sometimes 79 - * get wrong args. This determines how the args are being passed 80 - * (a single ptr to them all args passed) then calls 81 - * sys_select() with the appropriate args. -- Cort 82 - */ 83 - int 84 - ppc_select(int n, fd_set __user *inp, fd_set __user *outp, fd_set __user *exp, struct __kernel_old_timeval __user *tvp) 85 - { 86 - if ((unsigned long)n >= 4096) 87 - return sys_old_select((void __user *)n); 88 - 89 - return sys_select(n, inp, outp, exp, tvp); 90 - } 91 - #endif 92 - 93 66 #ifdef CONFIG_PPC64 94 - long ppc64_personality(unsigned long personality) 67 + static long do_ppc64_personality(unsigned long personality) 95 68 { 96 69 long ret; 97 70 98 71 if (personality(current->personality) == PER_LINUX32 99 72 && personality(personality) == PER_LINUX) 100 73 personality = (personality & ~PER_MASK) | PER_LINUX32; 101 - ret = sys_personality(personality); 74 + ret = ksys_personality(personality); 102 75 if (personality(ret) == PER_LINUX32) 103 76 ret = (ret & ~PER_MASK) | PER_LINUX; 104 77 return ret; 105 78 } 106 - #endif 107 79 108 - long ppc_fadvise64_64(int fd, int advice, u32 offset_high, u32 offset_low, 109 - u32 len_high, u32 len_low) 80 + SYSCALL_DEFINE1(ppc64_personality, unsigned long, personality) 110 81 { 111 - return ksys_fadvise64_64(fd, (u64)offset_high << 32 | offset_low, 112 - (u64)len_high << 32 | len_low, advice); 82 + return do_ppc64_personality(personality); 83 + } 84 + 85 + #ifdef CONFIG_COMPAT 86 + COMPAT_SYSCALL_DEFINE1(ppc64_personality, unsigned long, personality) 87 + { 88 + return do_ppc64_personality(personality); 89 + } 90 + #endif /* CONFIG_COMPAT */ 91 + #endif /* CONFIG_PPC64 */ 92 + 93 + SYSCALL_DEFINE6(ppc_fadvise64_64, 94 + int, fd, int, advice, u32, offset_high, u32, offset_low, 95 + u32, len_high, u32, len_low) 96 + { 97 + return ksys_fadvise64_64(fd, merge_64(offset_high, offset_low), 98 + merge_64(len_high, len_low), advice); 113 99 } 114 100 115 101 SYSCALL_DEFINE0(switch_endian)

+12 -12

arch/powerpc/kernel/syscalls/syscall.tbl

··· 110 110 79 common settimeofday sys_settimeofday compat_sys_settimeofday 111 111 80 common getgroups sys_getgroups 112 112 81 common setgroups sys_setgroups 113 - 82 32 select ppc_select sys_ni_syscall 113 + 82 32 select sys_old_select compat_sys_old_select 114 114 82 64 select sys_ni_syscall 115 115 82 spu select sys_ni_syscall 116 116 83 common symlink sys_symlink ··· 178 178 133 common fchdir sys_fchdir 179 179 134 common bdflush sys_ni_syscall 180 180 135 common sysfs sys_sysfs 181 - 136 32 personality sys_personality ppc64_personality 182 - 136 64 personality ppc64_personality 183 - 136 spu personality ppc64_personality 181 + 136 32 personality sys_personality compat_sys_ppc64_personality 182 + 136 64 personality sys_ppc64_personality 183 + 136 spu personality sys_ppc64_personality 184 184 137 common afs_syscall sys_ni_syscall 185 185 138 common setfsuid sys_setfsuid 186 186 139 common setfsgid sys_setfsgid ··· 228 228 176 64 rt_sigtimedwait sys_rt_sigtimedwait 229 229 177 nospu rt_sigqueueinfo sys_rt_sigqueueinfo compat_sys_rt_sigqueueinfo 230 230 178 nospu rt_sigsuspend sys_rt_sigsuspend compat_sys_rt_sigsuspend 231 - 179 common pread64 sys_pread64 compat_sys_pread64 232 - 180 common pwrite64 sys_pwrite64 compat_sys_pwrite64 231 + 179 common pread64 sys_pread64 compat_sys_ppc_pread64 232 + 180 common pwrite64 sys_pwrite64 compat_sys_ppc_pwrite64 233 233 181 common chown sys_chown 234 234 182 common getcwd sys_getcwd 235 235 183 common capget sys_capget ··· 242 242 188 common putpmsg sys_ni_syscall 243 243 189 nospu vfork sys_vfork 244 244 190 common ugetrlimit sys_getrlimit compat_sys_getrlimit 245 - 191 common readahead sys_readahead compat_sys_readahead 245 + 191 common readahead sys_readahead compat_sys_ppc_readahead 246 246 192 32 mmap2 sys_mmap2 compat_sys_mmap2 247 - 193 32 truncate64 sys_truncate64 compat_sys_truncate64 248 - 194 32 ftruncate64 sys_ftruncate64 compat_sys_ftruncate64 247 + 193 32 truncate64 sys_truncate64 compat_sys_ppc_truncate64 248 + 194 32 ftruncate64 sys_ftruncate64 compat_sys_ppc_ftruncate64 249 249 195 32 stat64 sys_stat64 250 250 196 32 lstat64 sys_lstat64 251 251 197 32 fstat64 sys_fstat64 ··· 288 288 230 common io_submit sys_io_submit compat_sys_io_submit 289 289 231 common io_cancel sys_io_cancel 290 290 232 nospu set_tid_address sys_set_tid_address 291 - 233 common fadvise64 sys_fadvise64 ppc32_fadvise64 291 + 233 common fadvise64 sys_fadvise64 compat_sys_ppc32_fadvise64 292 292 234 nospu exit_group sys_exit_group 293 293 235 nospu lookup_dcookie sys_lookup_dcookie compat_sys_lookup_dcookie 294 294 236 common epoll_create sys_epoll_create ··· 323 323 251 spu utimes sys_utimes 324 324 252 common statfs64 sys_statfs64 compat_sys_statfs64 325 325 253 common fstatfs64 sys_fstatfs64 compat_sys_fstatfs64 326 - 254 32 fadvise64_64 ppc_fadvise64_64 326 + 254 32 fadvise64_64 sys_ppc_fadvise64_64 327 327 254 spu fadvise64_64 sys_ni_syscall 328 328 255 common rtas sys_rtas 329 329 256 32 sys_debug_setcontext sys_debug_setcontext sys_ni_syscall ··· 390 390 305 common signalfd sys_signalfd compat_sys_signalfd 391 391 306 common timerfd_create sys_timerfd_create 392 392 307 common eventfd sys_eventfd 393 - 308 common sync_file_range2 sys_sync_file_range2 compat_sys_sync_file_range2 393 + 308 common sync_file_range2 sys_sync_file_range2 compat_sys_ppc_sync_file_range2 394 394 309 nospu fallocate sys_fallocate compat_sys_fallocate 395 395 310 nospu subpage_prot sys_subpage_prot 396 396 311 32 timerfd_settime sys_timerfd_settime32

+3 -3

arch/powerpc/kernel/sysfs.c

··· 228 228 } 229 229 #endif /* CONFIG_PPC64 */ 230 230 231 - #ifdef CONFIG_PPC_FSL_BOOK3E 231 + #ifdef CONFIG_PPC_E500 232 232 #define MAX_BIT 63 233 233 234 234 static u64 pw20_wt; ··· 907 907 device_create_file(s, &dev_attr_tscr); 908 908 #endif /* CONFIG_PPC64 */ 909 909 910 - #ifdef CONFIG_PPC_FSL_BOOK3E 910 + #ifdef CONFIG_PPC_E500 911 911 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 912 912 device_create_file(s, &dev_attr_pw20_state); 913 913 device_create_file(s, &dev_attr_pw20_wait_time); ··· 1003 1003 device_remove_file(s, &dev_attr_tscr); 1004 1004 #endif /* CONFIG_PPC64 */ 1005 1005 1006 - #ifdef CONFIG_PPC_FSL_BOOK3E 1006 + #ifdef CONFIG_PPC_E500 1007 1007 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) { 1008 1008 device_remove_file(s, &dev_attr_pw20_state); 1009 1009 device_remove_file(s, &dev_attr_pw20_wait_time);

+19 -14

arch/powerpc/kernel/systbl.S arch/powerpc/kernel/systbl.c

··· 10 10 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com) 11 11 */ 12 12 13 - #include <asm/ppc_asm.h> 13 + #include <linux/syscalls.h> 14 + #include <linux/compat.h> 15 + #include <asm/unistd.h> 16 + #include <asm/syscalls.h> 14 17 15 - .section .rodata,"a" 18 + #undef __SYSCALL_WITH_COMPAT 19 + #define __SYSCALL_WITH_COMPAT(nr, entry, compat) __SYSCALL(nr, entry) 16 20 17 - #ifdef CONFIG_PPC64 18 - .p2align 3 19 - #define __SYSCALL(nr, entry) .8byte entry 21 + #undef __SYSCALL 22 + #ifdef CONFIG_ARCH_HAS_SYSCALL_WRAPPER 23 + #define __SYSCALL(nr, entry) [nr] = entry, 20 24 #else 21 - .p2align 2 22 - #define __SYSCALL(nr, entry) .long entry 25 + /* 26 + * Coerce syscall handlers with arbitrary parameters to common type 27 + * requires cast to void* to avoid -Wcast-function-type. 28 + */ 29 + #define __SYSCALL(nr, entry) [nr] = (void *) entry, 23 30 #endif 24 31 25 - #define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, native) 26 - .globl sys_call_table 27 - sys_call_table: 32 + const syscall_fn sys_call_table[] = { 28 33 #ifdef CONFIG_PPC64 29 34 #include <asm/syscall_table_64.h> 30 35 #else 31 36 #include <asm/syscall_table_32.h> 32 37 #endif 38 + }; 33 39 34 40 #ifdef CONFIG_COMPAT 35 41 #undef __SYSCALL_WITH_COMPAT 36 42 #define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, compat) 37 - .globl compat_sys_call_table 38 - compat_sys_call_table: 39 - #define compat_sys_sigsuspend sys_sigsuspend 43 + const syscall_fn compat_sys_call_table[] = { 40 44 #include <asm/syscall_table_32.h> 41 - #endif 45 + }; 46 + #endif /* CONFIG_COMPAT */

-30

arch/powerpc/kernel/systbl_chk.sh

··· 1 - #!/bin/sh 2 - # SPDX-License-Identifier: GPL-2.0-or-later 3 - # 4 - # Just process the CPP output from systbl_chk.c and complain 5 - # if anything is out of order. 6 - # 7 - # Copyright © 2008 IBM Corporation 8 - # 9 - 10 - awk 'BEGIN { num = -1; } # Ignore the beginning of the file 11 - /^#/ { next; } 12 - /^[ \t]*$/ { next; } 13 - /^START_TABLE/ { num = 0; next; } 14 - /^END_TABLE/ { 15 - if (num != $2) { 16 - printf "Error: NR_syscalls (%s) is not one more than the last syscall (%s)\n", 17 - $2, num - 1; 18 - exit(1); 19 - } 20 - num = -1; # Ignore the rest of the file 21 - } 22 - { 23 - if (num == -1) next; 24 - if (($1 != -1) && ($1 != num)) { 25 - printf "Error: Syscall %s out of order (expected %s)\n", 26 - $1, num; 27 - exit(1); 28 - }; 29 - num++; 30 - }' "$1"

+20 -101

arch/powerpc/kernel/time.c

··· 178 178 return tb; 179 179 } 180 180 181 - #ifdef CONFIG_PPC_SPLPAR 182 - 183 - #include <asm/dtl.h> 184 - 185 - void (*dtl_consumer)(struct dtl_entry *, u64); 186 - 187 - /* 188 - * Scan the dispatch trace log and count up the stolen time. 189 - * Should be called with interrupts disabled. 190 - */ 191 - static u64 scan_dispatch_log(u64 stop_tb) 192 - { 193 - u64 i = local_paca->dtl_ridx; 194 - struct dtl_entry *dtl = local_paca->dtl_curr; 195 - struct dtl_entry *dtl_end = local_paca->dispatch_log_end; 196 - struct lppaca *vpa = local_paca->lppaca_ptr; 197 - u64 tb_delta; 198 - u64 stolen = 0; 199 - u64 dtb; 200 - 201 - if (!dtl) 202 - return 0; 203 - 204 - if (i == be64_to_cpu(vpa->dtl_idx)) 205 - return 0; 206 - while (i < be64_to_cpu(vpa->dtl_idx)) { 207 - dtb = be64_to_cpu(dtl->timebase); 208 - tb_delta = be32_to_cpu(dtl->enqueue_to_dispatch_time) + 209 - be32_to_cpu(dtl->ready_to_enqueue_time); 210 - barrier(); 211 - if (i + N_DISPATCH_LOG < be64_to_cpu(vpa->dtl_idx)) { 212 - /* buffer has overflowed */ 213 - i = be64_to_cpu(vpa->dtl_idx) - N_DISPATCH_LOG; 214 - dtl = local_paca->dispatch_log + (i % N_DISPATCH_LOG); 215 - continue; 216 - } 217 - if (dtb > stop_tb) 218 - break; 219 - if (dtl_consumer) 220 - dtl_consumer(dtl, i); 221 - stolen += tb_delta; 222 - ++i; 223 - ++dtl; 224 - if (dtl == dtl_end) 225 - dtl = local_paca->dispatch_log; 226 - } 227 - local_paca->dtl_ridx = i; 228 - local_paca->dtl_curr = dtl; 229 - return stolen; 230 - } 231 - 232 - /* 233 - * Accumulate stolen time by scanning the dispatch trace log. 234 - * Called on entry from user mode. 235 - */ 236 - void notrace accumulate_stolen_time(void) 237 - { 238 - u64 sst, ust; 239 - struct cpu_accounting_data *acct = &local_paca->accounting; 240 - 241 - sst = scan_dispatch_log(acct->starttime_user); 242 - ust = scan_dispatch_log(acct->starttime); 243 - acct->stime -= sst; 244 - acct->utime -= ust; 245 - acct->steal_time += ust + sst; 246 - } 247 - 248 - static inline u64 calculate_stolen_time(u64 stop_tb) 249 - { 250 - if (!firmware_has_feature(FW_FEATURE_SPLPAR)) 251 - return 0; 252 - 253 - if (get_paca()->dtl_ridx != be64_to_cpu(get_lppaca()->dtl_idx)) 254 - return scan_dispatch_log(stop_tb); 255 - 256 - return 0; 257 - } 258 - 259 - #else /* CONFIG_PPC_SPLPAR */ 260 - static inline u64 calculate_stolen_time(u64 stop_tb) 261 - { 262 - return 0; 263 - } 264 - 265 - #endif /* CONFIG_PPC_SPLPAR */ 266 - 267 181 /* 268 182 * Account time for a transition between system, hard irq 269 183 * or soft irq state. ··· 236 322 237 323 *stime_scaled = vtime_delta_scaled(acct, now, stime); 238 324 239 - *steal_time = calculate_stolen_time(now); 325 + if (IS_ENABLED(CONFIG_PPC_SPLPAR) && 326 + firmware_has_feature(FW_FEATURE_SPLPAR)) 327 + *steal_time = pseries_calculate_stolen_time(now); 328 + else 329 + *steal_time = 0; 240 330 241 331 return stime; 242 332 } ··· 532 614 return; 533 615 } 534 616 535 - /* 536 - * Ensure a positive value is written to the decrementer, or 537 - * else some CPUs will continue to take decrementer exceptions. 538 - * When the PPC_WATCHDOG (decrementer based) is configured, 539 - * keep this at most 31 bits, which is about 4 seconds on most 540 - * systems, which gives the watchdog a chance of catching timer 541 - * interrupt hard lockups. 542 - */ 543 - if (IS_ENABLED(CONFIG_PPC_WATCHDOG)) 544 - set_dec(0x7fffffff); 545 - else 546 - set_dec(decrementer_max); 547 - 548 617 /* Conditionally hard-enable interrupts. */ 549 - if (should_hard_irq_enable()) 618 + if (should_hard_irq_enable()) { 619 + /* 620 + * Ensure a positive value is written to the decrementer, or 621 + * else some CPUs will continue to take decrementer exceptions. 622 + * When the PPC_WATCHDOG (decrementer based) is configured, 623 + * keep this at most 31 bits, which is about 4 seconds on most 624 + * systems, which gives the watchdog a chance of catching timer 625 + * interrupt hard lockups. 626 + */ 627 + if (IS_ENABLED(CONFIG_PPC_WATCHDOG)) 628 + set_dec(0x7fffffff); 629 + else 630 + set_dec(decrementer_max); 631 + 550 632 do_hard_irq_enable(); 633 + } 551 634 552 635 #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_PMAC) 553 636 if (atomic_read(&ppc_n_lost_interrupts) != 0)

+1 -1

arch/powerpc/kernel/trace/ftrace_low.S

··· 48 48 * We might be called from a module. 49 49 * Switch to our TOC to run inside the core kernel. 50 50 */ 51 - ld r2, PACATOC(r13) 51 + LOAD_PACA_TOC() 52 52 #else 53 53 stwu r1, -16(r1) 54 54 stw r3, 8(r1)

+2 -4

arch/powerpc/kernel/trace/ftrace_mprofile.S

··· 83 83 #ifdef CONFIG_PPC64 84 84 /* Save callee's TOC in the ABI compliant location */ 85 85 std r2, STK_GOT(r1) 86 - ld r2,PACATOC(r13) /* get kernel TOC in r2 */ 87 - 88 - addis r3,r2,function_trace_op@toc@ha 89 - addi r3,r3,function_trace_op@toc@l 86 + LOAD_PACA_TOC() /* get kernel TOC in r2 */ 87 + LOAD_REG_ADDR(r3, function_trace_op) 90 88 ld r5,0(r3) 91 89 #else 92 90 lis r3,function_trace_op@ha

+17 -5

arch/powerpc/kernel/traps.c

··· 68 68 #include <asm/stacktrace.h> 69 69 #include <asm/nmi.h> 70 70 #include <asm/disassemble.h> 71 + #include <asm/udbg.h> 71 72 72 73 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 73 74 int (*__debugger)(struct pt_regs *regs) __read_mostly; ··· 601 600 602 601 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) 603 602 604 - #if defined(CONFIG_E500) 603 + #if defined(CONFIG_PPC_E500) 605 604 int machine_check_e500mc(struct pt_regs *regs) 606 605 { 607 606 unsigned long mcsr = mfspr(SPRN_MCSR); ··· 851 850 } 852 851 853 852 #ifdef CONFIG_PPC_BOOK3S_64 853 + DEFINE_INTERRUPT_HANDLER_RAW(machine_check_early_boot) 854 + { 855 + udbg_printf("Machine check (early boot)\n"); 856 + udbg_printf("SRR0=0x%016lx SRR1=0x%016lx\n", regs->nip, regs->msr); 857 + udbg_printf(" DAR=0x%016lx DSISR=0x%08lx\n", regs->dar, regs->dsisr); 858 + udbg_printf(" LR=0x%016lx R1=0x%08lx\n", regs->link, regs->gpr[1]); 859 + udbg_printf("------\n"); 860 + die("Machine check (early boot)", regs, SIGBUS); 861 + for (;;) 862 + ; 863 + return 0; 864 + } 865 + 854 866 DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception_async) 855 867 { 856 868 __machine_check_exception(regs); ··· 2099 2085 } 2100 2086 #endif /* CONFIG_ALTIVEC */ 2101 2087 2102 - #ifdef CONFIG_FSL_BOOKE 2088 + #ifdef CONFIG_PPC_85xx 2103 2089 DEFINE_INTERRUPT_HANDLER(CacheLockingException) 2104 2090 { 2105 2091 unsigned long error_code = regs->dsisr; ··· 2112 2098 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2113 2099 return; 2114 2100 } 2115 - #endif /* CONFIG_FSL_BOOKE */ 2101 + #endif /* CONFIG_PPC_85xx */ 2116 2102 2117 2103 #ifdef CONFIG_SPE 2118 2104 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException) 2119 2105 { 2120 - extern int do_spe_mathemu(struct pt_regs *regs); 2121 2106 unsigned long spefscr; 2122 2107 int fpexc_mode; 2123 2108 int code = FPE_FLTUNK; ··· 2166 2153 2167 2154 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException) 2168 2155 { 2169 - extern int speround_handler(struct pt_regs *regs); 2170 2156 int err; 2171 2157 2172 2158 interrupt_cond_local_irq_enable(regs);

+2

arch/powerpc/kernel/udbg.c

··· 67 67 udbg_init_debug_opal_raw(); 68 68 #elif defined(CONFIG_PPC_EARLY_DEBUG_OPAL_HVSI) 69 69 udbg_init_debug_opal_hvsi(); 70 + #elif defined(CONFIG_PPC_EARLY_DEBUG_16550) 71 + udbg_init_debug_16550(); 70 72 #endif 71 73 72 74 #ifdef CONFIG_PPC_EARLY_DEBUG

+22 -28

arch/powerpc/kernel/udbg_16550.c

··· 8 8 #include <asm/udbg.h> 9 9 #include <asm/io.h> 10 10 #include <asm/reg_a2.h> 11 + #include <asm/early_ioremap.h> 11 12 12 13 extern u8 real_readb(volatile u8 __iomem *addr); 13 14 extern void real_writeb(u8 data, volatile u8 __iomem *addr); ··· 298 297 299 298 #endif /* CONFIG_PPC_EARLY_DEBUG_40x */ 300 299 301 - #ifdef CONFIG_PPC_EARLY_DEBUG_MICROWATT 300 + #ifdef CONFIG_PPC_EARLY_DEBUG_16550 302 301 303 - #define UDBG_UART_MW_ADDR ((void __iomem *)0xc0002000) 302 + static void __iomem *udbg_uart_early_addr; 304 303 305 - static u8 udbg_uart_in_isa300_rm(unsigned int reg) 304 + void __init udbg_init_debug_16550(void) 306 305 { 307 - uint64_t msr = mfmsr(); 308 - uint8_t c; 309 - 310 - mtmsr(msr & ~(MSR_EE|MSR_DR)); 311 - isync(); 312 - eieio(); 313 - c = __raw_rm_readb(UDBG_UART_MW_ADDR + (reg << 2)); 314 - mtmsr(msr); 315 - isync(); 316 - return c; 306 + udbg_uart_early_addr = early_ioremap(CONFIG_PPC_EARLY_DEBUG_16550_PHYSADDR, 0x1000); 307 + udbg_uart_init_mmio(udbg_uart_early_addr, CONFIG_PPC_EARLY_DEBUG_16550_STRIDE); 317 308 } 318 309 319 - static void udbg_uart_out_isa300_rm(unsigned int reg, u8 val) 310 + static int __init udbg_init_debug_16550_ioremap(void) 320 311 { 321 - uint64_t msr = mfmsr(); 312 + void __iomem *addr; 322 313 323 - mtmsr(msr & ~(MSR_EE|MSR_DR)); 324 - isync(); 325 - eieio(); 326 - __raw_rm_writeb(val, UDBG_UART_MW_ADDR + (reg << 2)); 327 - mtmsr(msr); 328 - isync(); 314 + if (!udbg_uart_early_addr) 315 + return 0; 316 + 317 + addr = ioremap(CONFIG_PPC_EARLY_DEBUG_16550_PHYSADDR, 0x1000); 318 + if (WARN_ON(!addr)) 319 + return -ENOMEM; 320 + 321 + udbg_uart_init_mmio(addr, CONFIG_PPC_EARLY_DEBUG_16550_STRIDE); 322 + early_iounmap(udbg_uart_early_addr, 0x1000); 323 + udbg_uart_early_addr = NULL; 324 + 325 + return 0; 329 326 } 330 327 331 - void __init udbg_init_debug_microwatt(void) 332 - { 333 - udbg_uart_in = udbg_uart_in_isa300_rm; 334 - udbg_uart_out = udbg_uart_out_isa300_rm; 335 - udbg_use_uart(); 336 - } 328 + early_initcall(udbg_init_debug_16550_ioremap); 337 329 338 - #endif /* CONFIG_PPC_EARLY_DEBUG_MICROWATT */ 330 + #endif /* CONFIG_PPC_EARLY_DEBUG_16550 */

+6 -13

arch/powerpc/kernel/vdso.c

··· 39 39 extern char vdso32_start, vdso32_end; 40 40 extern char vdso64_start, vdso64_end; 41 41 42 + long sys_ni_syscall(void); 43 + 42 44 /* 43 45 * The vdso data page (aka. systemcfg for old ppc64 fans) is here. 44 46 * Once the early boot kernel code no longer needs to muck around ··· 202 200 if (is_32bit_task()) { 203 201 vdso_spec = &vdso32_spec; 204 202 vdso_size = &vdso32_end - &vdso32_start; 205 - vdso_base = VDSO32_MBASE; 206 203 } else { 207 204 vdso_spec = &vdso64_spec; 208 205 vdso_size = &vdso64_end - &vdso64_start; 209 - /* 210 - * On 64bit we don't have a preferred map address. This 211 - * allows get_unmapped_area to find an area near other mmaps 212 - * and most likely share a SLB entry. 213 - */ 214 - vdso_base = 0; 215 206 } 216 207 217 208 mappings_size = vdso_size + vvar_size; 218 209 mappings_size += (VDSO_ALIGNMENT - 1) & PAGE_MASK; 219 210 220 211 /* 221 - * pick a base address for the vDSO in process space. We try to put it 222 - * at vdso_base which is the "natural" base for it, but we might fail 223 - * and end up putting it elsewhere. 212 + * Pick a base address for the vDSO in process space. 224 213 * Add enough to the size so that the result can be aligned. 225 214 */ 226 - vdso_base = get_unmapped_area(NULL, vdso_base, mappings_size, 0, 0); 215 + vdso_base = get_unmapped_area(NULL, 0, mappings_size, 0, 0); 227 216 if (IS_ERR_VALUE(vdso_base)) 228 217 return vdso_base; 229 218 ··· 306 313 unsigned int i; 307 314 308 315 for (i = 0; i < NR_syscalls; i++) { 309 - if (sys_call_table[i] != (unsigned long)&sys_ni_syscall) 316 + if (sys_call_table[i] != (void *)&sys_ni_syscall) 310 317 vdso_data->syscall_map[i >> 5] |= 0x80000000UL >> (i & 0x1f); 311 318 if (IS_ENABLED(CONFIG_COMPAT) && 312 - compat_sys_call_table[i] != (unsigned long)&sys_ni_syscall) 319 + compat_sys_call_table[i] != (void *)&sys_ni_syscall) 313 320 vdso_data->compat_syscall_map[i >> 5] |= 0x80000000UL >> (i & 0x1f); 314 321 } 315 322 }

+2 -2

arch/powerpc/kernel/vdso/Makefile

··· 92 92 93 93 # actual build commands 94 94 quiet_cmd_vdso32ld_and_check = VDSO32L $@ 95 - cmd_vdso32ld_and_check = $(VDSOCC) $(c_flags) $(CC32FLAGS) -o $@ -Wl,-T$(filter %.lds,$^) $(filter %.o,$^) ; $(cmd_vdso_check) 95 + cmd_vdso32ld_and_check = $(VDSOCC) $(c_flags) $(CC32FLAGS) -o $@ -Wl,-T$(filter %.lds,$^) $(filter %.o,$^) -z noexecstack ; $(cmd_vdso_check) 96 96 quiet_cmd_vdso32as = VDSO32A $@ 97 97 cmd_vdso32as = $(VDSOCC) $(a_flags) $(CC32FLAGS) $(AS32FLAGS) -c -o $@ $< 98 98 quiet_cmd_vdso32cc = VDSO32C $@ 99 99 cmd_vdso32cc = $(VDSOCC) $(c_flags) $(CC32FLAGS) -c -o $@ $< 100 100 101 101 quiet_cmd_vdso64ld_and_check = VDSO64L $@ 102 - cmd_vdso64ld_and_check = $(VDSOCC) $(c_flags) $(CC64FLAGS) -o $@ -Wl,-T$(filter %.lds,$^) $(filter %.o,$^) ; $(cmd_vdso_check) 102 + cmd_vdso64ld_and_check = $(VDSOCC) $(c_flags) $(CC64FLAGS) -o $@ -Wl,-T$(filter %.lds,$^) $(filter %.o,$^) -z noexecstack ; $(cmd_vdso_check) 103 103 quiet_cmd_vdso64as = VDSO64A $@ 104 104 cmd_vdso64as = $(VDSOCC) $(a_flags) $(CC64FLAGS) $(AS64FLAGS) -c -o $@ $<

-1

arch/powerpc/kernel/vdso/vdso32.lds.S

··· 78 78 __end = .; 79 79 PROVIDE(end = .); 80 80 81 - STABS_DEBUG 82 81 DWARF_DEBUG 83 82 ELF_DETAILS 84 83

-1

arch/powerpc/kernel/vdso/vdso64.lds.S

··· 76 76 _end = .; 77 77 PROVIDE(end = .); 78 78 79 - STABS_DEBUG 80 79 DWARF_DEBUG 81 80 ELF_DETAILS 82 81

+7 -8

arch/powerpc/kernel/vector.S

··· 155 155 * usage of floating-point registers. These routines must be called 156 156 * with preempt disabled. 157 157 */ 158 - #ifdef CONFIG_PPC32 159 158 .data 159 + #ifdef CONFIG_PPC32 160 160 fpzero: 161 161 .long 0 162 162 fpone: ··· 169 169 lfs fr,name@l(r11) 170 170 #else 171 171 172 - .section ".toc","aw" 173 172 fpzero: 174 - .tc FD_0_0[TC],0 173 + .quad 0 175 174 fpone: 176 - .tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */ 175 + .quad 0x3ff0000000000000 /* 1.0 */ 177 176 fphalf: 178 - .tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */ 177 + .quad 0x3fe0000000000000 /* 0.5 */ 179 178 180 - #define LDCONST(fr, name) \ 181 - lfd fr,name@toc(r2) 179 + #define LDCONST(fr, name) \ 180 + addis r11,r2,name@toc@ha; \ 181 + lfd fr,name@toc@l(r11) 182 182 #endif 183 - 184 183 .text 185 184 /* 186 185 * Internal routine to enable floating point and set FPSCR to 0.

+61 -40

arch/powerpc/kernel/vmlinux.lds.S

··· 32 32 33 33 #define STRICT_ALIGN_SIZE (1 << CONFIG_DATA_SHIFT) 34 34 35 + #if STRICT_ALIGN_SIZE < PAGE_SIZE 36 + #error "CONFIG_DATA_SHIFT must be >= PAGE_SHIFT" 37 + #endif 38 + 35 39 ENTRY(_stext) 36 40 37 41 PHDRS { ··· 71 67 .head.text : AT(ADDR(.head.text) - LOAD_OFFSET) { 72 68 #ifdef CONFIG_PPC64 73 69 KEEP(*(.head.text.first_256B)); 74 - #ifdef CONFIG_PPC_BOOK3E 70 + #ifdef CONFIG_PPC_BOOK3E_64 75 71 #else 76 72 KEEP(*(.head.text.real_vectors)); 77 73 *(.head.text.real_trampolines); ··· 126 122 *(.sfpr); 127 123 MEM_KEEP(init.text) 128 124 MEM_KEEP(exit.text) 129 - 130 - #ifdef CONFIG_PPC32 131 - *(.got1) 132 - __got2_start = .; 133 - *(.got2) 134 - __got2_end = .; 135 - #endif /* CONFIG_PPC32 */ 136 - 137 125 } :text 138 126 139 127 . = ALIGN(PAGE_SIZE); ··· 135 139 /* Read-only data */ 136 140 RO_DATA(PAGE_SIZE) 137 141 138 - #ifdef CONFIG_PPC64 142 + #ifdef CONFIG_PPC32 143 + .sdata2 : AT(ADDR(.sdata2) - LOAD_OFFSET) { 144 + *(.sdata2) 145 + } 146 + #endif 147 + 148 + .data.rel.ro : AT(ADDR(.data.rel.ro) - LOAD_OFFSET) { 149 + *(.data.rel.ro*) 150 + } 151 + 152 + .branch_lt : AT(ADDR(.branch_lt) - LOAD_OFFSET) { 153 + *(.branch_lt) 154 + } 155 + 156 + #ifdef CONFIG_PPC32 157 + .got1 : AT(ADDR(.got1) - LOAD_OFFSET) { 158 + *(.got1) 159 + } 160 + .got2 : AT(ADDR(.got2) - LOAD_OFFSET) { 161 + __got2_start = .; 162 + *(.got2) 163 + __got2_end = .; 164 + } 165 + .got : AT(ADDR(.got) - LOAD_OFFSET) { 166 + *(.got) 167 + *(.got.plt) 168 + } 169 + .plt : AT(ADDR(.plt) - LOAD_OFFSET) { 170 + /* XXX: is .plt (and .got.plt) required? */ 171 + *(.plt) 172 + } 173 + 174 + #else /* CONFIG_PPC32 */ 175 + .toc1 : AT(ADDR(.toc1) - LOAD_OFFSET) { 176 + *(.toc1) 177 + } 178 + 179 + .got : AT(ADDR(.got) - LOAD_OFFSET) ALIGN(256) { 180 + *(.got .toc) 181 + } 182 + 139 183 SOFT_MASK_TABLE(8) 140 184 RESTART_TABLE(8) 141 185 186 + #ifdef CONFIG_PPC64_ELF_ABI_V1 142 187 .opd : AT(ADDR(.opd) - LOAD_OFFSET) { 143 188 __start_opd = .; 144 189 KEEP(*(.opd)) 145 190 __end_opd = .; 146 191 } 192 + #endif 147 193 148 194 . = ALIGN(8); 149 195 __stf_entry_barrier_fixup : AT(ADDR(__stf_entry_barrier_fixup) - LOAD_OFFSET) { ··· 228 190 *(__rfi_flush_fixup) 229 191 __stop___rfi_flush_fixup = .; 230 192 } 231 - #endif /* CONFIG_PPC64 */ 193 + #endif /* CONFIG_PPC32 */ 232 194 233 195 #ifdef CONFIG_PPC_BARRIER_NOSPEC 234 196 . = ALIGN(8); ··· 239 201 } 240 202 #endif /* CONFIG_PPC_BARRIER_NOSPEC */ 241 203 242 - #ifdef CONFIG_PPC_FSL_BOOK3E 204 + #ifdef CONFIG_PPC_E500 243 205 . = ALIGN(8); 244 206 __spec_btb_flush_fixup : AT(ADDR(__spec_btb_flush_fixup) - LOAD_OFFSET) { 245 207 __start__btb_flush_fixup = .; ··· 248 210 } 249 211 #endif 250 212 213 + /* 214 + * Various code relies on __init_begin being at the strict RWX boundary. 215 + */ 216 + . = ALIGN(STRICT_ALIGN_SIZE); 217 + __srwx_boundary = .; 218 + __end_rodata = .; 219 + __init_begin = .; 220 + 251 221 /* 252 222 * Init sections discarded at runtime 253 223 */ 254 - . = ALIGN(STRICT_ALIGN_SIZE); 255 - __init_begin = .; 256 - . = ALIGN(PAGE_SIZE); 257 224 .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) { 258 225 _sinittext = .; 259 226 INIT_TEXT ··· 360 317 . = ALIGN(PAGE_SIZE); 361 318 _sdata = .; 362 319 320 + .data : AT(ADDR(.data) - LOAD_OFFSET) { 321 + DATA_DATA 322 + *(.data.rel*) 363 323 #ifdef CONFIG_PPC32 364 - .data : AT(ADDR(.data) - LOAD_OFFSET) { 365 - DATA_DATA 366 - *(.data.rel*) 367 324 *(SDATA_MAIN) 368 - *(.sdata2) 369 - *(.got.plt) *(.got) 370 - *(.plt) 371 - *(.branch_lt) 372 - } 373 - #else 374 - .data : AT(ADDR(.data) - LOAD_OFFSET) { 375 - DATA_DATA 376 - *(.data.rel*) 377 - *(.toc1) 378 - *(.branch_lt) 379 - } 380 - 381 - .got : AT(ADDR(.got) - LOAD_OFFSET) ALIGN(256) { 382 - *(.got) 383 - #ifndef CONFIG_RELOCATABLE 384 - __prom_init_toc_start = .; 385 - arch/powerpc/kernel/prom_init.o*(.toc) 386 - __prom_init_toc_end = .; 387 325 #endif 388 - *(.toc) 389 326 } 390 - #endif 391 327 392 328 /* The initial task and kernel stack */ 393 329 INIT_TASK_DATA_SECTION(THREAD_ALIGN) ··· 404 382 _end = . ; 405 383 PROVIDE32 (end = .); 406 384 407 - STABS_DEBUG 408 385 DWARF_DEBUG 409 386 ELF_DETAILS 410 387

+3 -3

arch/powerpc/kexec/core.c

··· 136 136 #ifdef CONFIG_PPC64 137 137 /* 138 138 * On the LPAR platform place the crash kernel to mid of 139 - * RMA size (512MB or more) to ensure the crash kernel 139 + * RMA size (max. of 512MB) to ensure the crash kernel 140 140 * gets enough space to place itself and some stack to be 141 141 * in the first segment. At the same time normal kernel 142 142 * also get enough space to allocate memory for essential ··· 144 144 * kernel starts at 128MB offset on other platforms. 145 145 */ 146 146 if (firmware_has_feature(FW_FEATURE_LPAR)) 147 - crashk_res.start = ppc64_rma_size / 2; 147 + crashk_res.start = min_t(u64, ppc64_rma_size / 2, SZ_512M); 148 148 else 149 - crashk_res.start = min(0x8000000ULL, (ppc64_rma_size / 2)); 149 + crashk_res.start = min_t(u64, ppc64_rma_size / 2, SZ_128M); 150 150 #else 151 151 crashk_res.start = KDUMP_KERNELBASE; 152 152 #endif

+1 -1

arch/powerpc/kexec/core_32.c

··· 55 55 reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); 56 56 printk(KERN_INFO "Bye!\n"); 57 57 58 - if (!IS_ENABLED(CONFIG_FSL_BOOKE) && !IS_ENABLED(CONFIG_44x)) 58 + if (!IS_ENABLED(CONFIG_PPC_85xx) && !IS_ENABLED(CONFIG_44x)) 59 59 relocate_new_kernel(page_list, reboot_code_buffer_phys, image->start); 60 60 61 61 /* now call it */

+1 -1

arch/powerpc/kexec/core_64.c

··· 360 360 * the RMA. On BookE there is no real MMU off mode, so we have to 361 361 * keep it enabled as well (but then we have bolted TLB entries). 362 362 */ 363 - #ifdef CONFIG_PPC_BOOK3E 363 + #ifdef CONFIG_PPC_BOOK3E_64 364 364 copy_with_mmu_off = false; 365 365 #else 366 366 copy_with_mmu_off = radix_enabled() ||

+2 -2

arch/powerpc/kexec/relocate_32.S

··· 25 25 /* r4 = reboot_code_buffer */ 26 26 /* r5 = start_address */ 27 27 28 - #ifdef CONFIG_FSL_BOOKE 28 + #ifdef CONFIG_PPC_85xx 29 29 30 30 mr r29, r3 31 31 mr r30, r4 32 32 mr r31, r5 33 33 34 34 #define ENTRY_MAPPING_KEXEC_SETUP 35 - #include <kernel/fsl_booke_entry_mapping.S> 35 + #include <kernel/85xx_entry_mapping.S> 36 36 #undef ENTRY_MAPPING_KEXEC_SETUP 37 37 38 38 mr r3, r29

+2 -2

arch/powerpc/kvm/Kconfig

··· 189 189 190 190 config KVM_E500V2 191 191 bool "KVM support for PowerPC E500v2 processors" 192 - depends on E500 && !PPC_E500MC 192 + depends on PPC_E500 && !PPC_E500MC 193 193 select KVM 194 194 select KVM_MMIO 195 195 select MMU_NOTIFIER ··· 220 220 221 221 config KVM_MPIC 222 222 bool "KVM in-kernel MPIC emulation" 223 - depends on KVM && E500 223 + depends on KVM && PPC_E500 224 224 select HAVE_KVM_IRQCHIP 225 225 select HAVE_KVM_IRQFD 226 226 select HAVE_KVM_IRQ_ROUTING

+1 -1

arch/powerpc/kvm/book3s_64_entry.S

··· 315 315 reg = reg + 1 316 316 .endr 317 317 318 - ld r2,PACATOC(r13) 318 + LOAD_PACA_TOC() 319 319 320 320 mflr r4 321 321 std r4,VCPU_LR(r3)

+105 -41

arch/powerpc/kvm/book3s_hv.c

··· 249 249 250 250 /* 251 251 * We use the vcpu_load/put functions to measure stolen time. 252 + * 252 253 * Stolen time is counted as time when either the vcpu is able to 253 254 * run as part of a virtual core, but the task running the vcore 254 255 * is preempted or sleeping, or when the vcpu needs something done ··· 279 278 * lock. The stolen times are measured in units of timebase ticks. 280 279 * (Note that the != TB_NIL checks below are purely defensive; 281 280 * they should never fail.) 281 + * 282 + * The POWER9 path is simpler, one vcpu per virtual core so the 283 + * former case does not exist. If a vcpu is preempted when it is 284 + * BUSY_IN_HOST and not ceded or otherwise blocked, then accumulate 285 + * the stolen cycles in busy_stolen. RUNNING is not a preemptible 286 + * state in the P9 path. 282 287 */ 283 288 284 289 static void kvmppc_core_start_stolen(struct kvmppc_vcore *vc, u64 tb) ··· 318 311 unsigned long flags; 319 312 u64 now; 320 313 321 - if (cpu_has_feature(CPU_FTR_ARCH_300)) 314 + if (cpu_has_feature(CPU_FTR_ARCH_300)) { 315 + if (vcpu->arch.busy_preempt != TB_NIL) { 316 + WARN_ON_ONCE(vcpu->arch.state != KVMPPC_VCPU_BUSY_IN_HOST); 317 + vc->stolen_tb += mftb() - vcpu->arch.busy_preempt; 318 + vcpu->arch.busy_preempt = TB_NIL; 319 + } 322 320 return; 321 + } 323 322 324 323 now = mftb(); 325 324 ··· 353 340 unsigned long flags; 354 341 u64 now; 355 342 356 - if (cpu_has_feature(CPU_FTR_ARCH_300)) 343 + if (cpu_has_feature(CPU_FTR_ARCH_300)) { 344 + /* 345 + * In the P9 path, RUNNABLE is not preemptible 346 + * (nor takes host interrupts) 347 + */ 348 + WARN_ON_ONCE(vcpu->arch.state == KVMPPC_VCPU_RUNNABLE); 349 + /* 350 + * Account stolen time when preempted while the vcpu task is 351 + * running in the kernel (but not in qemu, which is INACTIVE). 352 + */ 353 + if (task_is_running(current) && 354 + vcpu->arch.state == KVMPPC_VCPU_BUSY_IN_HOST) 355 + vcpu->arch.busy_preempt = mftb(); 357 356 return; 357 + } 358 358 359 359 now = mftb(); 360 360 ··· 733 707 } 734 708 735 709 static void __kvmppc_create_dtl_entry(struct kvm_vcpu *vcpu, 710 + struct lppaca *vpa, 736 711 unsigned int pcpu, u64 now, 737 712 unsigned long stolen) 738 713 { 739 714 struct dtl_entry *dt; 740 - struct lppaca *vpa; 741 715 742 716 dt = vcpu->arch.dtl_ptr; 743 - vpa = vcpu->arch.vpa.pinned_addr; 744 717 745 - if (!dt || !vpa) 718 + if (!dt) 746 719 return; 747 720 748 721 dt->dispatch_reason = 7; ··· 762 737 /* order writing *dt vs. writing vpa->dtl_idx */ 763 738 smp_wmb(); 764 739 vpa->dtl_idx = cpu_to_be64(++vcpu->arch.dtl_index); 765 - vcpu->arch.dtl.dirty = true; 740 + 741 + /* vcpu->arch.dtl.dirty is set by the caller */ 766 742 } 767 743 768 - static void kvmppc_create_dtl_entry(struct kvm_vcpu *vcpu, 769 - struct kvmppc_vcore *vc) 744 + static void kvmppc_update_vpa_dispatch(struct kvm_vcpu *vcpu, 745 + struct kvmppc_vcore *vc) 770 746 { 747 + struct lppaca *vpa; 771 748 unsigned long stolen; 772 749 unsigned long core_stolen; 773 750 u64 now; 774 751 unsigned long flags; 752 + 753 + vpa = vcpu->arch.vpa.pinned_addr; 754 + if (!vpa) 755 + return; 775 756 776 757 now = mftb(); 777 758 ··· 789 758 vcpu->arch.busy_stolen = 0; 790 759 spin_unlock_irqrestore(&vcpu->arch.tbacct_lock, flags); 791 760 792 - __kvmppc_create_dtl_entry(vcpu, vc->pcpu, now + vc->tb_offset, stolen); 761 + vpa->enqueue_dispatch_tb = cpu_to_be64(be64_to_cpu(vpa->enqueue_dispatch_tb) + stolen); 762 + 763 + __kvmppc_create_dtl_entry(vcpu, vpa, vc->pcpu, now + vc->tb_offset, stolen); 764 + 765 + vcpu->arch.vpa.dirty = true; 766 + } 767 + 768 + static void kvmppc_update_vpa_dispatch_p9(struct kvm_vcpu *vcpu, 769 + struct kvmppc_vcore *vc, 770 + u64 now) 771 + { 772 + struct lppaca *vpa; 773 + unsigned long stolen; 774 + unsigned long stolen_delta; 775 + 776 + vpa = vcpu->arch.vpa.pinned_addr; 777 + if (!vpa) 778 + return; 779 + 780 + stolen = vc->stolen_tb; 781 + stolen_delta = stolen - vcpu->arch.stolen_logged; 782 + vcpu->arch.stolen_logged = stolen; 783 + 784 + vpa->enqueue_dispatch_tb = cpu_to_be64(stolen); 785 + 786 + __kvmppc_create_dtl_entry(vcpu, vpa, vc->pcpu, now, stolen_delta); 787 + 788 + vcpu->arch.vpa.dirty = true; 793 789 } 794 790 795 791 /* See if there is a doorbell interrupt pending for a vcpu */ ··· 2575 2517 r = set_vpa(vcpu, &vcpu->arch.dtl, addr, len); 2576 2518 break; 2577 2519 case KVM_REG_PPC_TB_OFFSET: 2520 + { 2578 2521 /* round up to multiple of 2^24 */ 2579 - vcpu->arch.vcore->tb_offset = 2580 - ALIGN(set_reg_val(id, *val), 1UL << 24); 2522 + u64 tb_offset = ALIGN(set_reg_val(id, *val), 1UL << 24); 2523 + 2524 + /* 2525 + * Now that we know the timebase offset, update the 2526 + * decrementer expiry with a guest timebase value. If 2527 + * the userspace does not set DEC_EXPIRY, this ensures 2528 + * a migrated vcpu at least starts with an expired 2529 + * decrementer, which is better than a large one that 2530 + * causes a hang. 2531 + */ 2532 + if (!vcpu->arch.dec_expires && tb_offset) 2533 + vcpu->arch.dec_expires = get_tb() + tb_offset; 2534 + 2535 + vcpu->arch.vcore->tb_offset = tb_offset; 2581 2536 break; 2537 + } 2582 2538 case KVM_REG_PPC_LPCR: 2583 2539 kvmppc_set_lpcr(vcpu, set_reg_val(id, *val), true); 2584 2540 break; ··· 3872 3800 * kvmppc_core_prepare_to_enter. 3873 3801 */ 3874 3802 kvmppc_start_thread(vcpu, pvc); 3875 - kvmppc_create_dtl_entry(vcpu, pvc); 3803 + kvmppc_update_vpa_dispatch(vcpu, pvc); 3876 3804 trace_kvm_guest_enter(vcpu); 3877 3805 if (!vcpu->arch.ptid) 3878 3806 thr0_done = true; ··· 3912 3840 for (sub = 0; sub < core_info.n_subcores; ++sub) 3913 3841 spin_unlock(&core_info.vc[sub]->lock); 3914 3842 3915 - guest_enter_irqoff(); 3843 + guest_timing_enter_irqoff(); 3916 3844 3917 3845 srcu_idx = srcu_read_lock(&vc->kvm->srcu); 3918 3846 3847 + guest_state_enter_irqoff(); 3919 3848 this_cpu_disable_ftrace(); 3920 - 3921 - /* 3922 - * Interrupts will be enabled once we get into the guest, 3923 - * so tell lockdep that we're about to enable interrupts. 3924 - */ 3925 - trace_hardirqs_on(); 3926 3849 3927 3850 trap = __kvmppc_vcore_entry(); 3928 3851 3929 - trace_hardirqs_off(); 3930 - 3931 3852 this_cpu_enable_ftrace(); 3853 + guest_state_exit_irqoff(); 3932 3854 3933 3855 srcu_read_unlock(&vc->kvm->srcu, srcu_idx); 3934 3856 ··· 3957 3891 3958 3892 kvmppc_set_host_core(pcpu); 3959 3893 3960 - context_tracking_guest_exit(); 3961 3894 if (!vtime_accounting_enabled_this_cpu()) { 3962 3895 local_irq_enable(); 3963 3896 /* 3964 - * Service IRQs here before vtime_account_guest_exit() so any 3897 + * Service IRQs here before guest_timing_exit_irqoff() so any 3965 3898 * ticks that occurred while running the guest are accounted to 3966 3899 * the guest. If vtime accounting is enabled, accounting uses 3967 3900 * TB rather than ticks, so it can be done without enabling ··· 3969 3904 */ 3970 3905 local_irq_disable(); 3971 3906 } 3972 - vtime_account_guest_exit(); 3907 + guest_timing_exit_irqoff(); 3973 3908 3974 3909 local_irq_enable(); 3975 3910 ··· 4469 4404 if ((vc->vcore_state == VCORE_PIGGYBACK || 4470 4405 vc->vcore_state == VCORE_RUNNING) && 4471 4406 !VCORE_IS_EXITING(vc)) { 4472 - kvmppc_create_dtl_entry(vcpu, vc); 4407 + kvmppc_update_vpa_dispatch(vcpu, vc); 4473 4408 kvmppc_start_thread(vcpu, vc); 4474 4409 trace_kvm_guest_enter(vcpu); 4475 4410 } else if (vc->vcore_state == VCORE_SLEEPING) { ··· 4585 4520 vc = vcpu->arch.vcore; 4586 4521 vcpu->arch.ceded = 0; 4587 4522 vcpu->arch.run_task = current; 4588 - vcpu->arch.state = KVMPPC_VCPU_RUNNABLE; 4589 4523 vcpu->arch.last_inst = KVM_INST_FETCH_FAILED; 4590 4524 4591 4525 /* See if the MMU is ready to go */ ··· 4610 4546 4611 4547 /* flags save not required, but irq_pmu has no disable/enable API */ 4612 4548 powerpc_local_irq_pmu_save(flags); 4549 + 4550 + vcpu->arch.state = KVMPPC_VCPU_RUNNABLE; 4613 4551 4614 4552 if (signal_pending(current)) 4615 4553 goto sigpend; ··· 4657 4591 4658 4592 tb = mftb(); 4659 4593 4660 - __kvmppc_create_dtl_entry(vcpu, pcpu, tb + vc->tb_offset, 0); 4594 + kvmppc_update_vpa_dispatch_p9(vcpu, vc, tb + vc->tb_offset); 4661 4595 4662 4596 trace_kvm_guest_enter(vcpu); 4663 4597 4664 - guest_enter_irqoff(); 4598 + guest_timing_enter_irqoff(); 4665 4599 4666 4600 srcu_idx = srcu_read_lock(&kvm->srcu); 4667 4601 4602 + guest_state_enter_irqoff(); 4668 4603 this_cpu_disable_ftrace(); 4669 - 4670 - /* Tell lockdep that we're about to enable interrupts */ 4671 - trace_hardirqs_on(); 4672 4604 4673 4605 trap = kvmhv_p9_guest_entry(vcpu, time_limit, lpcr, &tb); 4674 4606 vcpu->arch.trap = trap; 4675 4607 4676 - trace_hardirqs_off(); 4677 - 4678 4608 this_cpu_enable_ftrace(); 4609 + guest_state_exit_irqoff(); 4679 4610 4680 4611 srcu_read_unlock(&kvm->srcu, srcu_idx); 4681 4612 4682 4613 set_irq_happened(trap); 4683 4614 4684 - context_tracking_guest_exit(); 4615 + vcpu->cpu = -1; 4616 + vcpu->arch.thread_cpu = -1; 4617 + vcpu->arch.state = KVMPPC_VCPU_BUSY_IN_HOST; 4618 + 4685 4619 if (!vtime_accounting_enabled_this_cpu()) { 4686 - local_irq_enable(); 4620 + powerpc_local_irq_pmu_restore(flags); 4687 4621 /* 4688 - * Service IRQs here before vtime_account_guest_exit() so any 4622 + * Service IRQs here before guest_timing_exit_irqoff() so any 4689 4623 * ticks that occurred while running the guest are accounted to 4690 4624 * the guest. If vtime accounting is enabled, accounting uses 4691 4625 * TB rather than ticks, so it can be done without enabling 4692 4626 * interrupts here, which has the problem that it accounts 4693 4627 * interrupt processing overhead to the host. 4694 4628 */ 4695 - local_irq_disable(); 4629 + powerpc_local_irq_pmu_save(flags); 4696 4630 } 4697 - vtime_account_guest_exit(); 4698 - 4699 - vcpu->cpu = -1; 4700 - vcpu->arch.thread_cpu = -1; 4631 + guest_timing_exit_irqoff(); 4701 4632 4702 4633 powerpc_local_irq_pmu_restore(flags); 4703 4634 ··· 4757 4694 out: 4758 4695 vcpu->cpu = -1; 4759 4696 vcpu->arch.thread_cpu = -1; 4697 + vcpu->arch.state = KVMPPC_VCPU_BUSY_IN_HOST; 4760 4698 powerpc_local_irq_pmu_restore(flags); 4761 4699 preempt_enable(); 4762 4700 goto done;

+3 -3

arch/powerpc/kvm/book3s_hv_rmhandlers.S

··· 1024 1024 1025 1025 /* Restore R1/R2 so we can handle faults */ 1026 1026 ld r1, HSTATE_HOST_R1(r13) 1027 - ld r2, PACATOC(r13) 1027 + LOAD_PACA_TOC() 1028 1028 1029 1029 mfspr r10, SPRN_SRR0 1030 1030 mfspr r11, SPRN_SRR1 ··· 2727 2727 std r4, _CTR(r1) 2728 2728 std r5, _XER(r1) 2729 2729 std r6, SOFTE(r1) 2730 - ld r2, PACATOC(r13) 2731 - LOAD_REG_IMMEDIATE(3, 0x7265677368657265) 2730 + LOAD_PACA_TOC() 2731 + LOAD_REG_IMMEDIATE(3, STACK_FRAME_REGS_MARKER) 2732 2732 std r3, STACK_FRAME_OVERHEAD-16(r1) 2733 2733 2734 2734 /*

+2 -2

arch/powerpc/kvm/booke_interrupts.S

··· 223 223 lwz r3, VCPU_HOST_PID(r4) 224 224 mtspr SPRN_PID, r3 225 225 226 - #ifdef CONFIG_FSL_BOOKE 226 + #ifdef CONFIG_PPC_85xx 227 227 /* we cheat and know that Linux doesn't use PID1 which is always 0 */ 228 228 lis r3, 0 229 229 mtspr SPRN_PID1, r3 ··· 406 406 lwz r3, VCPU_SHADOW_PID(r4) 407 407 mtspr SPRN_PID, r3 408 408 409 - #ifdef CONFIG_FSL_BOOKE 409 + #ifdef CONFIG_PPC_85xx 410 410 lwz r3, VCPU_SHADOW_PID1(r4) 411 411 mtspr SPRN_PID1, r3 412 412 #endif

+1 -1

arch/powerpc/kvm/e500.h

··· 17 17 #define KVM_E500_H 18 18 19 19 #include <linux/kvm_host.h> 20 - #include <asm/nohash/mmu-book3e.h> 20 + #include <asm/nohash/mmu-e500.h> 21 21 #include <asm/tlb.h> 22 22 #include <asm/cputhreads.h> 23 23

-1

arch/powerpc/kvm/powerpc.c

··· 785 785 786 786 hrtimer_init(&vcpu->arch.dec_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); 787 787 vcpu->arch.dec_timer.function = kvmppc_decrementer_wakeup; 788 - vcpu->arch.dec_expires = get_tb(); 789 788 790 789 #ifdef CONFIG_KVM_EXIT_TIMING 791 790 mutex_init(&vcpu->arch.exit_timing_lock);

+1 -1

arch/powerpc/kvm/tm.S

··· 110 110 mtmsrd r2, 1 111 111 112 112 /* Reload TOC pointer. */ 113 - ld r2, PACATOC(r13) 113 + LOAD_PACA_TOC() 114 114 115 115 /* Save all but r0-r2, r9 & r13 */ 116 116 reg = 3

+19 -11

arch/powerpc/lib/code-patching.c

··· 94 94 static_branch_enable(&poking_init_done); 95 95 } 96 96 97 + static unsigned long get_patch_pfn(void *addr) 98 + { 99 + if (IS_ENABLED(CONFIG_MODULES) && is_vmalloc_or_module_addr(addr)) 100 + return vmalloc_to_pfn(addr); 101 + else 102 + return __pa_symbol(addr) >> PAGE_SHIFT; 103 + } 104 + 97 105 /* 98 106 * This can be called for kernel text or a module. 99 107 */ 100 108 static int map_patch_area(void *addr, unsigned long text_poke_addr) 101 109 { 102 - unsigned long pfn; 103 - 104 - if (IS_ENABLED(CONFIG_MODULES) && is_vmalloc_or_module_addr(addr)) 105 - pfn = vmalloc_to_pfn(addr); 106 - else 107 - pfn = __pa_symbol(addr) >> PAGE_SHIFT; 110 + unsigned long pfn = get_patch_pfn(addr); 108 111 109 112 return map_kernel_page(text_poke_addr, (pfn << PAGE_SHIFT), PAGE_KERNEL); 110 113 } ··· 152 149 int err; 153 150 u32 *patch_addr; 154 151 unsigned long text_poke_addr; 152 + pte_t *pte; 153 + unsigned long pfn = get_patch_pfn(addr); 155 154 156 - text_poke_addr = (unsigned long)__this_cpu_read(text_poke_area)->addr; 155 + text_poke_addr = (unsigned long)__this_cpu_read(text_poke_area)->addr & PAGE_MASK; 157 156 patch_addr = (u32 *)(text_poke_addr + offset_in_page(addr)); 158 157 159 - err = map_patch_area(addr, text_poke_addr); 160 - if (err) 161 - return err; 158 + pte = virt_to_kpte(text_poke_addr); 159 + __set_pte_at(&init_mm, text_poke_addr, pte, pfn_pte(pfn, PAGE_KERNEL), 0); 160 + /* See ptesync comment in radix__set_pte_at() */ 161 + if (radix_enabled()) 162 + asm volatile("ptesync": : :"memory"); 162 163 163 164 err = __patch_instruction(addr, instr, patch_addr); 164 165 165 - unmap_patch_area(text_poke_addr); 166 + pte_clear(&init_mm, text_poke_addr, pte); 167 + flush_tlb_kernel_range(text_poke_addr, text_poke_addr + PAGE_SIZE); 166 168 167 169 return err; 168 170 }

+1 -6

arch/powerpc/lib/copypage_64.S

··· 9 9 #include <asm/export.h> 10 10 #include <asm/feature-fixups.h> 11 11 12 - .section ".toc","aw" 13 - PPC64_CACHES: 14 - .tc ppc64_caches[TC],ppc64_caches 15 - .section ".text" 16 - 17 12 _GLOBAL_TOC(copy_page) 18 13 BEGIN_FTR_SECTION 19 14 lis r5,PAGE_SIZE@h ··· 19 24 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY) 20 25 ori r5,r5,PAGE_SIZE@l 21 26 BEGIN_FTR_SECTION 22 - ld r10,PPC64_CACHES@toc(r2) 27 + LOAD_REG_ADDR(r10, ppc64_caches) 23 28 lwz r11,DCACHEL1LOGBLOCKSIZE(r10) /* log2 of cache block size */ 24 29 lwz r12,DCACHEL1BLOCKSIZE(r10) /* get cache block size */ 25 30 li r9,0

+2 -2

arch/powerpc/lib/feature-fixups.c

··· 550 550 } 551 551 #endif /* CONFIG_PPC_BARRIER_NOSPEC */ 552 552 553 - #ifdef CONFIG_PPC_FSL_BOOK3E 553 + #ifdef CONFIG_PPC_E500 554 554 void do_barrier_nospec_fixups_range(bool enable, void *fixup_start, void *fixup_end) 555 555 { 556 556 unsigned int instr[2], *dest; ··· 602 602 for (; start < end; start += 2) 603 603 patch_btb_flush_section(start); 604 604 } 605 - #endif /* CONFIG_PPC_FSL_BOOK3E */ 605 + #endif /* CONFIG_PPC_E500 */ 606 606 607 607 void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end) 608 608 {

+1 -6

arch/powerpc/lib/string_64.S

··· 11 11 #include <asm/asm-offsets.h> 12 12 #include <asm/export.h> 13 13 14 - .section ".toc","aw" 15 - PPC64_CACHES: 16 - .tc ppc64_caches[TC],ppc64_caches 17 - .section ".text" 18 - 19 14 /** 20 15 * __arch_clear_user: - Zero a block of memory in user space, with less checking. 21 16 * @to: Destination address, in user space. ··· 128 133 blr 129 134 130 135 .Llong_clear: 131 - ld r5,PPC64_CACHES@toc(r2) 136 + LOAD_REG_ADDR(r5, ppc64_caches) 132 137 133 138 bf cr7*4+0,11f 134 139 err2; std r0,0(r3)

+6 -1

arch/powerpc/math-emu/Makefile

··· 17 17 CFLAGS_fabs.o = -fno-builtin-fabs 18 18 CFLAGS_math.o = -fno-builtin-fabs 19 19 20 - ccflags-y = -w 20 + ccflags-remove-y = -Wmissing-prototypes -Wmissing-declarations -Wunused-but-set-variable 21 + 22 + ifdef KBUILD_EXTRA_WARN 23 + CFLAGS_math.o += -Wmissing-prototypes -Wmissing-declarations -Wunused-but-set-variable 24 + CFLAGS_math_efp.o += -Wmissing-prototypes -Wmissing-declarations -Wunused-but-set-variable 25 + endif

+9 -9

arch/powerpc/math-emu/math.c

··· 24 24 FLOATFUNC(mtfsfi); 25 25 26 26 #ifdef CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED 27 - #undef FLOATFUNC(x) 27 + #undef FLOATFUNC 28 28 #define FLOATFUNC(x) static inline int x(void *op1, void *op2, void *op3, \ 29 - void *op4) { } 29 + void *op4) { return 0; } 30 30 #endif 31 31 32 32 FLOATFUNC(fadd); ··· 396 396 397 397 case XCR: 398 398 op0 = (void *)&regs->ccr; 399 - op1 = (void *)((insn >> 23) & 0x7); 399 + op1 = (void *)(long)((insn >> 23) & 0x7); 400 400 op2 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f); 401 401 op3 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f); 402 402 break; 403 403 404 404 case XCRL: 405 405 op0 = (void *)&regs->ccr; 406 - op1 = (void *)((insn >> 23) & 0x7); 407 - op2 = (void *)((insn >> 18) & 0x7); 406 + op1 = (void *)(long)((insn >> 23) & 0x7); 407 + op2 = (void *)(long)((insn >> 18) & 0x7); 408 408 break; 409 409 410 410 case XCRB: 411 - op0 = (void *)((insn >> 21) & 0x1f); 411 + op0 = (void *)(long)((insn >> 21) & 0x1f); 412 412 break; 413 413 414 414 case XCRI: 415 - op0 = (void *)((insn >> 23) & 0x7); 416 - op1 = (void *)((insn >> 12) & 0xf); 415 + op0 = (void *)(long)((insn >> 23) & 0x7); 416 + op1 = (void *)(long)((insn >> 12) & 0xf); 417 417 break; 418 418 419 419 case XFLB: 420 - op0 = (void *)((insn >> 17) & 0xff); 420 + op0 = (void *)(long)((insn >> 17) & 0xff); 421 421 op1 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f); 422 422 break; 423 423

+32 -28

arch/powerpc/math-emu/math_efp.c

··· 17 17 18 18 #include <linux/types.h> 19 19 #include <linux/prctl.h> 20 + #include <linux/module.h> 20 21 21 22 #include <linux/uaccess.h> 22 23 #include <asm/reg.h> ··· 219 218 case AB: 220 219 case XCR: 221 220 FP_UNPACK_SP(SA, va.wp + 1); 221 + fallthrough; 222 222 case XB: 223 223 FP_UNPACK_SP(SB, vb.wp + 1); 224 224 break; ··· 228 226 break; 229 227 } 230 228 231 - pr_debug("SA: %ld %08lx %ld (%ld)\n", SA_s, SA_f, SA_e, SA_c); 232 - pr_debug("SB: %ld %08lx %ld (%ld)\n", SB_s, SB_f, SB_e, SB_c); 229 + pr_debug("SA: %d %08x %d (%d)\n", SA_s, SA_f, SA_e, SA_c); 230 + pr_debug("SB: %d %08x %d (%d)\n", SB_s, SB_f, SB_e, SB_c); 233 231 234 232 switch (func) { 235 233 case EFSABS: ··· 280 278 } else { 281 279 SB_e += (func == EFSCTSF ? 31 : 32); 282 280 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, 283 - (func == EFSCTSF)); 281 + (func == EFSCTSF) ? 1 : 0); 284 282 } 285 283 goto update_regs; 286 284 ··· 289 287 FP_CLEAR_EXCEPTIONS; 290 288 FP_UNPACK_DP(DB, vb.dp); 291 289 292 - pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n", 290 + pr_debug("DB: %d %08x %08x %d (%d)\n", 293 291 DB_s, DB_f1, DB_f0, DB_e, DB_c); 294 292 295 293 FP_CONV(S, D, 1, 2, SR, DB); ··· 303 301 FP_SET_EXCEPTION(FP_EX_INVALID); 304 302 } else { 305 303 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, 306 - ((func & 0x3) != 0)); 304 + ((func & 0x3) != 0) ? 1 : 0); 307 305 } 308 306 goto update_regs; 309 307 ··· 314 312 FP_SET_EXCEPTION(FP_EX_INVALID); 315 313 } else { 316 314 FP_TO_INT_S(vc.wp[1], SB, 32, 317 - ((func & 0x3) != 0)); 315 + ((func & 0x3) != 0) ? 1 : 0); 318 316 } 319 317 goto update_regs; 320 318 ··· 324 322 break; 325 323 326 324 pack_s: 327 - pr_debug("SR: %ld %08lx %ld (%ld)\n", SR_s, SR_f, SR_e, SR_c); 325 + pr_debug("SR: %d %08x %d (%d)\n", SR_s, SR_f, SR_e, SR_c); 328 326 329 327 FP_PACK_SP(vc.wp + 1, SR); 330 328 goto update_regs; ··· 348 346 case AB: 349 347 case XCR: 350 348 FP_UNPACK_DP(DA, va.dp); 349 + fallthrough; 351 350 case XB: 352 351 FP_UNPACK_DP(DB, vb.dp); 353 352 break; ··· 357 354 break; 358 355 } 359 356 360 - pr_debug("DA: %ld %08lx %08lx %ld (%ld)\n", 357 + pr_debug("DA: %d %08x %08x %d (%d)\n", 361 358 DA_s, DA_f1, DA_f0, DA_e, DA_c); 362 - pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n", 359 + pr_debug("DB: %d %08x %08x %d (%d)\n", 363 360 DB_s, DB_f1, DB_f0, DB_e, DB_c); 364 361 365 362 switch (func) { ··· 411 408 } else { 412 409 DB_e += (func == EFDCTSF ? 31 : 32); 413 410 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, 414 - (func == EFDCTSF)); 411 + (func == EFDCTSF) ? 1 : 0); 415 412 } 416 413 goto update_regs; 417 414 ··· 420 417 FP_CLEAR_EXCEPTIONS; 421 418 FP_UNPACK_SP(SB, vb.wp + 1); 422 419 423 - pr_debug("SB: %ld %08lx %ld (%ld)\n", 420 + pr_debug("SB: %d %08x %d (%d)\n", 424 421 SB_s, SB_f, SB_e, SB_c); 425 422 426 423 FP_CONV(D, S, 2, 1, DR, SB); ··· 434 431 FP_SET_EXCEPTION(FP_EX_INVALID); 435 432 } else { 436 433 FP_TO_INT_D(vc.dp[0], DB, 64, 437 - ((func & 0x1) == 0)); 434 + ((func & 0x1) == 0) ? 1 : 0); 438 435 } 439 436 goto update_regs; 440 437 ··· 445 442 FP_SET_EXCEPTION(FP_EX_INVALID); 446 443 } else { 447 444 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, 448 - ((func & 0x3) != 0)); 445 + ((func & 0x3) != 0) ? 1 : 0); 449 446 } 450 447 goto update_regs; 451 448 ··· 456 453 FP_SET_EXCEPTION(FP_EX_INVALID); 457 454 } else { 458 455 FP_TO_INT_D(vc.wp[1], DB, 32, 459 - ((func & 0x3) != 0)); 456 + ((func & 0x3) != 0) ? 1 : 0); 460 457 } 461 458 goto update_regs; 462 459 ··· 466 463 break; 467 464 468 465 pack_d: 469 - pr_debug("DR: %ld %08lx %08lx %ld (%ld)\n", 466 + pr_debug("DR: %d %08x %08x %d (%d)\n", 470 467 DR_s, DR_f1, DR_f0, DR_e, DR_c); 471 468 472 469 FP_PACK_DP(vc.dp, DR); ··· 495 492 case XCR: 496 493 FP_UNPACK_SP(SA0, va.wp); 497 494 FP_UNPACK_SP(SA1, va.wp + 1); 495 + fallthrough; 498 496 case XB: 499 497 FP_UNPACK_SP(SB0, vb.wp); 500 498 FP_UNPACK_SP(SB1, vb.wp + 1); ··· 506 502 break; 507 503 } 508 504 509 - pr_debug("SA0: %ld %08lx %ld (%ld)\n", 505 + pr_debug("SA0: %d %08x %d (%d)\n", 510 506 SA0_s, SA0_f, SA0_e, SA0_c); 511 - pr_debug("SA1: %ld %08lx %ld (%ld)\n", 507 + pr_debug("SA1: %d %08x %d (%d)\n", 512 508 SA1_s, SA1_f, SA1_e, SA1_c); 513 - pr_debug("SB0: %ld %08lx %ld (%ld)\n", 509 + pr_debug("SB0: %d %08x %d (%d)\n", 514 510 SB0_s, SB0_f, SB0_e, SB0_c); 515 - pr_debug("SB1: %ld %08lx %ld (%ld)\n", 511 + pr_debug("SB1: %d %08x %d (%d)\n", 516 512 SB1_s, SB1_f, SB1_e, SB1_c); 517 513 518 514 switch (func) { ··· 571 567 } else { 572 568 SB0_e += (func == EVFSCTSF ? 31 : 32); 573 569 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, 574 - (func == EVFSCTSF)); 570 + (func == EVFSCTSF) ? 1 : 0); 575 571 } 576 572 if (SB1_c == FP_CLS_NAN) { 577 573 vc.wp[1] = 0; ··· 579 575 } else { 580 576 SB1_e += (func == EVFSCTSF ? 31 : 32); 581 577 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, 582 - (func == EVFSCTSF)); 578 + (func == EVFSCTSF) ? 1 : 0); 583 579 } 584 580 goto update_regs; 585 581 ··· 590 586 FP_SET_EXCEPTION(FP_EX_INVALID); 591 587 } else { 592 588 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, 593 - ((func & 0x3) != 0)); 589 + ((func & 0x3) != 0) ? 1 : 0); 594 590 } 595 591 if (SB1_c == FP_CLS_NAN) { 596 592 vc.wp[1] = 0; 597 593 FP_SET_EXCEPTION(FP_EX_INVALID); 598 594 } else { 599 595 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, 600 - ((func & 0x3) != 0)); 596 + ((func & 0x3) != 0) ? 1 : 0); 601 597 } 602 598 goto update_regs; 603 599 ··· 608 604 FP_SET_EXCEPTION(FP_EX_INVALID); 609 605 } else { 610 606 FP_TO_INT_S(vc.wp[0], SB0, 32, 611 - ((func & 0x3) != 0)); 607 + ((func & 0x3) != 0) ? 1 : 0); 612 608 } 613 609 if (SB1_c == FP_CLS_NAN) { 614 610 vc.wp[1] = 0; 615 611 FP_SET_EXCEPTION(FP_EX_INVALID); 616 612 } else { 617 613 FP_TO_INT_S(vc.wp[1], SB1, 32, 618 - ((func & 0x3) != 0)); 614 + ((func & 0x3) != 0) ? 1 : 0); 619 615 } 620 616 goto update_regs; 621 617 ··· 625 621 break; 626 622 627 623 pack_vs: 628 - pr_debug("SR0: %ld %08lx %ld (%ld)\n", 624 + pr_debug("SR0: %d %08x %d (%d)\n", 629 625 SR0_s, SR0_f, SR0_e, SR0_c); 630 - pr_debug("SR1: %ld %08lx %ld (%ld)\n", 626 + pr_debug("SR1: %d %08x %d (%d)\n", 631 627 SR1_s, SR1_f, SR1_e, SR1_c); 632 628 633 629 FP_PACK_SP(vc.wp, SR0); ··· 890 886 return 0; 891 887 } 892 888 893 - int __init spe_mathemu_init(void) 889 + static int __init spe_mathemu_init(void) 894 890 { 895 891 u32 pvr, maj, min; 896 892

+3 -5

arch/powerpc/mm/book3s32/mmu.c

··· 158 158 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) 159 159 { 160 160 unsigned long done; 161 - unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET; 161 + unsigned long border = (unsigned long)__srwx_boundary - PAGE_OFFSET; 162 162 unsigned long size; 163 163 164 164 size = roundup_pow_of_two((unsigned long)_einittext - PAGE_OFFSET); ··· 240 240 for (i = 0; i < nb; i++) { 241 241 struct ppc_bat *bat = BATS[i]; 242 242 243 - if (bat_addrs[i].start < (unsigned long)__init_begin) 243 + if (bat_addrs[i].start < (unsigned long)__end_rodata) 244 244 bat[1].batl = (bat[1].batl & ~BPP_RW) | BPP_RX; 245 245 } 246 246 ··· 314 314 * 315 315 * This must always be called with the pte lock held. 316 316 */ 317 - void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 317 + void __update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 318 318 pte_t *ptep) 319 319 { 320 - if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) 321 - return; 322 320 /* 323 321 * We don't need to worry about _PAGE_PRESENT here because we are 324 322 * called with either mm->page_table_lock held or ptl lock held

+2 -2

arch/powerpc/mm/book3s64/hash_pgtable.c

··· 256 256 * the __collapse_huge_page_copy can result in copying 257 257 * the old content. 258 258 */ 259 - flush_tlb_pmd_range(vma->vm_mm, &pmd, address); 259 + flush_hash_table_pmd_range(vma->vm_mm, &pmd, address); 260 260 return pmd; 261 261 } 262 262 ··· 541 541 unsigned long start, end, pp; 542 542 543 543 start = (unsigned long)_stext; 544 - end = (unsigned long)__init_begin; 544 + end = (unsigned long)__end_rodata; 545 545 546 546 pp = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL_ROX), HPTE_USE_KERNEL_KEY); 547 547

+1 -1

arch/powerpc/mm/book3s64/hash_tlb.c

··· 221 221 local_irq_restore(flags); 222 222 } 223 223 224 - void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr) 224 + void flush_hash_table_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr) 225 225 { 226 226 pte_t *pte; 227 227 pte_t *start_pte;

+15 -17

arch/powerpc/mm/book3s64/hash_utils.c

··· 123 123 #ifdef CONFIG_PPC_64K_PAGES 124 124 int mmu_ci_restrictions; 125 125 #endif 126 - #ifdef CONFIG_DEBUG_PAGEALLOC 127 126 static u8 *linear_map_hash_slots; 128 127 static unsigned long linear_map_hash_count; 129 - static DEFINE_SPINLOCK(linear_map_hash_lock); 130 - #endif /* CONFIG_DEBUG_PAGEALLOC */ 131 128 struct mmu_hash_ops mmu_hash_ops; 132 129 EXPORT_SYMBOL(mmu_hash_ops); 133 130 ··· 424 427 break; 425 428 426 429 cond_resched(); 427 - #ifdef CONFIG_DEBUG_PAGEALLOC 428 - if (debug_pagealloc_enabled() && 430 + if (debug_pagealloc_enabled_or_kfence() && 429 431 (paddr >> PAGE_SHIFT) < linear_map_hash_count) 430 432 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; 431 - #endif /* CONFIG_DEBUG_PAGEALLOC */ 432 433 } 433 434 return ret < 0 ? ret : 0; 434 435 } ··· 773 778 bool aligned = true; 774 779 init_hpte_page_sizes(); 775 780 776 - if (!debug_pagealloc_enabled()) { 781 + if (!debug_pagealloc_enabled_or_kfence()) { 777 782 /* 778 783 * Pick a size for the linear mapping. Currently, we only 779 784 * support 16M, 1M and 4K which is the default ··· 1061 1066 1062 1067 prot = pgprot_val(PAGE_KERNEL); 1063 1068 1064 - #ifdef CONFIG_DEBUG_PAGEALLOC 1065 - if (debug_pagealloc_enabled()) { 1069 + if (debug_pagealloc_enabled_or_kfence()) { 1066 1070 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; 1067 1071 linear_map_hash_slots = memblock_alloc_try_nid( 1068 1072 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT, ··· 1070 1076 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n", 1071 1077 __func__, linear_map_hash_count, &ppc64_rma_size); 1072 1078 } 1073 - #endif /* CONFIG_DEBUG_PAGEALLOC */ 1074 1079 1075 1080 /* create bolted the linear mapping in the hash table */ 1076 1081 for_each_mem_range(i, &base, &end) { ··· 1774 1781 * 1775 1782 * This must always be called with the pte lock held. 1776 1783 */ 1777 - void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 1784 + void __update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 1778 1785 pte_t *ptep) 1779 1786 { 1780 1787 /* ··· 1783 1790 */ 1784 1791 unsigned long trap; 1785 1792 bool is_exec; 1786 - 1787 - if (radix_enabled()) 1788 - return; 1789 1793 1790 1794 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ 1791 1795 if (!pte_young(*ptep) || address >= TASK_SIZE) ··· 1980 1990 return slot; 1981 1991 } 1982 1992 1983 - #ifdef CONFIG_DEBUG_PAGEALLOC 1993 + #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE) 1994 + static DEFINE_SPINLOCK(linear_map_hash_lock); 1995 + 1984 1996 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) 1985 1997 { 1986 1998 unsigned long hash; ··· 1995 2003 1996 2004 /* Don't create HPTE entries for bad address */ 1997 2005 if (!vsid) 2006 + return; 2007 + 2008 + if (linear_map_hash_slots[lmi] & 0x80) 1998 2009 return; 1999 2010 2000 2011 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, ··· 2019 2024 2020 2025 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 2021 2026 spin_lock(&linear_map_hash_lock); 2022 - BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); 2027 + if (!(linear_map_hash_slots[lmi] & 0x80)) { 2028 + spin_unlock(&linear_map_hash_lock); 2029 + return; 2030 + } 2023 2031 hidx = linear_map_hash_slots[lmi] & 0x7f; 2024 2032 linear_map_hash_slots[lmi] = 0; 2025 2033 spin_unlock(&linear_map_hash_lock); ··· 2053 2055 } 2054 2056 local_irq_restore(flags); 2055 2057 } 2056 - #endif /* CONFIG_DEBUG_PAGEALLOC */ 2058 + #endif /* CONFIG_DEBUG_PAGEALLOC || CONFIG_KFENCE */ 2057 2059 2058 2060 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 2059 2061 phys_addr_t first_memblock_size)

+9 -2

arch/powerpc/mm/book3s64/pgtable.c

··· 553 553 554 554 pgprot_t vm_get_page_prot(unsigned long vm_flags) 555 555 { 556 - unsigned long prot = pgprot_val(protection_map[vm_flags & 557 - (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]); 556 + unsigned long prot; 557 + 558 + /* Radix supports execute-only, but protection_map maps X -> RX */ 559 + if (radix_enabled() && ((vm_flags & VM_ACCESS_FLAGS) == VM_EXEC)) { 560 + prot = pgprot_val(PAGE_EXECONLY); 561 + } else { 562 + prot = pgprot_val(protection_map[vm_flags & 563 + (VM_ACCESS_FLAGS | VM_SHARED)]); 564 + } 558 565 559 566 if (vm_flags & VM_SAO) 560 567 prot |= _PAGE_SAO;

+20 -8

arch/powerpc/mm/book3s64/radix_pgtable.c

··· 30 30 #include <asm/trace.h> 31 31 #include <asm/uaccess.h> 32 32 #include <asm/ultravisor.h> 33 + #include <asm/set_memory.h> 33 34 34 35 #include <trace/events/thp.h> 36 + 37 + #include <mm/mmu_decl.h> 35 38 36 39 unsigned int mmu_base_pid; 37 40 unsigned long radix_mem_block_size __ro_after_init; ··· 231 228 unsigned long start, end; 232 229 233 230 start = (unsigned long)_stext; 234 - end = (unsigned long)__init_begin; 231 + end = (unsigned long)__end_rodata; 235 232 236 233 radix__change_memory_range(start, end, _PAGE_WRITE); 237 234 } ··· 262 259 static unsigned long next_boundary(unsigned long addr, unsigned long end) 263 260 { 264 261 #ifdef CONFIG_STRICT_KERNEL_RWX 265 - if (addr < __pa_symbol(__init_begin)) 266 - return __pa_symbol(__init_begin); 262 + if (addr < __pa_symbol(__srwx_boundary)) 263 + return __pa_symbol(__srwx_boundary); 267 264 #endif 268 265 return end; 269 266 } 270 267 271 268 static int __meminit create_physical_mapping(unsigned long start, 272 269 unsigned long end, 273 - unsigned long max_mapping_size, 274 270 int nid, pgprot_t _prot) 275 271 { 276 272 unsigned long vaddr, addr, mapping_size = 0; 277 273 bool prev_exec, exec = false; 278 274 pgprot_t prot; 279 275 int psize; 276 + unsigned long max_mapping_size = radix_mem_block_size; 277 + 278 + if (debug_pagealloc_enabled_or_kfence()) 279 + max_mapping_size = PAGE_SIZE; 280 280 281 281 start = ALIGN(start, PAGE_SIZE); 282 282 end = ALIGN_DOWN(end, PAGE_SIZE); ··· 358 352 } 359 353 360 354 WARN_ON(create_physical_mapping(start, end, 361 - radix_mem_block_size, 362 355 -1, PAGE_KERNEL)); 363 356 } 364 357 ··· 855 850 } 856 851 857 852 return create_physical_mapping(__pa(start), __pa(end), 858 - radix_mem_block_size, nid, prot); 853 + nid, prot); 859 854 } 860 855 861 856 int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end) ··· 901 896 #endif 902 897 #endif 903 898 904 - #ifdef CONFIG_DEBUG_PAGEALLOC 899 + #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE) 905 900 void radix__kernel_map_pages(struct page *page, int numpages, int enable) 906 901 { 907 - pr_warn_once("DEBUG_PAGEALLOC not supported in radix mode\n"); 902 + unsigned long addr; 903 + 904 + addr = (unsigned long)page_address(page); 905 + 906 + if (enable) 907 + set_memory_p(addr, numpages); 908 + else 909 + set_memory_np(addr, numpages); 908 910 } 909 911 #endif 910 912

+21 -2

arch/powerpc/mm/fault.c

··· 270 270 return false; 271 271 } 272 272 273 - if (unlikely(!vma_is_accessible(vma))) 273 + /* 274 + * Check for a read fault. This could be caused by a read on an 275 + * inaccessible page (i.e. PROT_NONE), or a Radix MMU execute-only page. 276 + */ 277 + if (unlikely(!(vma->vm_flags & VM_READ))) 274 278 return true; 275 279 /* 276 280 * We should ideally do the vma pkey access check here. But in the ··· 371 367 #elif defined(CONFIG_PPC_8xx) 372 368 #define page_fault_is_bad(__err) ((__err) & DSISR_NOEXEC_OR_G) 373 369 #elif defined(CONFIG_PPC64) 374 - #define page_fault_is_bad(__err) ((__err) & DSISR_BAD_FAULT_64S) 370 + static int page_fault_is_bad(unsigned long err) 371 + { 372 + unsigned long flag = DSISR_BAD_FAULT_64S; 373 + 374 + /* 375 + * PAPR+ v2.11 § 14.15.3.4.1 (unreleased) 376 + * If byte 0, bit 3 of pi-attribute-specifier-type in 377 + * ibm,pi-features property is defined, ignore the DSI error 378 + * which is caused by the paste instruction on the 379 + * suspended NX window. 380 + */ 381 + if (mmu_has_feature(MMU_FTR_NX_DSI)) 382 + flag &= ~DSISR_BAD_COPYPASTE; 383 + 384 + return err & flag; 385 + } 375 386 #else 376 387 #define page_fault_is_bad(__err) ((__err) & DSISR_BAD_FAULT_32S) 377 388 #endif

+4 -4

arch/powerpc/mm/hugetlbpage.c

··· 392 392 * single hugepage, but all of them point to 393 393 * the same kmem cache that holds the hugepte. 394 394 */ 395 - more = addr + (1 << hugepd_shift(*(hugepd_t *)pmd)); 395 + more = addr + (1UL << hugepd_shift(*(hugepd_t *)pmd)); 396 396 if (more > next) 397 397 next = more; 398 398 ··· 434 434 * single hugepage, but all of them point to 435 435 * the same kmem cache that holds the hugepte. 436 436 */ 437 - more = addr + (1 << hugepd_shift(*(hugepd_t *)pud)); 437 + more = addr + (1UL << hugepd_shift(*(hugepd_t *)pud)); 438 438 if (more > next) 439 439 next = more; 440 440 ··· 496 496 * for a single hugepage, but all of them point to the 497 497 * same kmem cache that holds the hugepte. 498 498 */ 499 - more = addr + (1 << hugepd_shift(*(hugepd_t *)pgd)); 499 + more = addr + (1UL << hugepd_shift(*(hugepd_t *)pgd)); 500 500 if (more > next) 501 501 next = more; 502 502 ··· 623 623 if (pdshift > shift) { 624 624 if (!IS_ENABLED(CONFIG_PPC_8xx)) 625 625 pgtable_cache_add(pdshift - shift); 626 - } else if (IS_ENABLED(CONFIG_PPC_FSL_BOOK3E) || 626 + } else if (IS_ENABLED(CONFIG_PPC_E500) || 627 627 IS_ENABLED(CONFIG_PPC_8xx)) { 628 628 pgtable_cache_add(PTE_T_ORDER); 629 629 }

+2 -15

arch/powerpc/mm/init_32.c

··· 82 82 if (ppc_md.progress) 83 83 ppc_md.progress("MMU:enter", 0x111); 84 84 85 - /* 86 - * Reserve gigantic pages for hugetlb. This MUST occur before 87 - * lowmem_end_addr is initialized below. 88 - */ 89 - if (memblock.memory.cnt > 1) { 90 - #ifndef CONFIG_WII 91 - memblock_enforce_memory_limit(memblock.memory.regions[0].size); 92 - pr_warn("Only using first contiguous memory region\n"); 93 - #else 94 - wii_memory_fixups(); 95 - #endif 96 - } 97 - 98 85 total_lowmem = total_memory = memblock_end_of_DRAM() - memstart_addr; 99 86 lowmem_end_addr = memstart_addr + total_lowmem; 100 87 101 - #ifdef CONFIG_FSL_BOOKE 88 + #ifdef CONFIG_PPC_85xx 102 89 /* Freescale Book-E parts expect lowmem to be mapped by fixed TLB 103 90 * entries, so we need to adjust lowmem to match the amount we can map 104 91 * in the fixed entries */ 105 92 adjust_total_lowmem(); 106 - #endif /* CONFIG_FSL_BOOKE */ 93 + #endif /* CONFIG_PPC_85xx */ 107 94 108 95 if (total_lowmem > __max_low_memory) { 109 96 total_lowmem = __max_low_memory;

+2 -2

arch/powerpc/mm/mem.c

··· 302 302 for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) { 303 303 phys_addr_t paddr = (phys_addr_t)pfn << PAGE_SHIFT; 304 304 struct page *page = pfn_to_page(pfn); 305 - if (!memblock_is_reserved(paddr)) 305 + if (memblock_is_memory(paddr) && !memblock_is_reserved(paddr)) 306 306 free_highmem_page(page); 307 307 } 308 308 } 309 309 #endif /* CONFIG_HIGHMEM */ 310 310 311 - #if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP) 311 + #if defined(CONFIG_PPC_E500) && !defined(CONFIG_SMP) 312 312 /* 313 313 * If smp is enabled, next_tlbcam_idx is initialized in the cpu up 314 314 * functions.... do it here for the non-smp case.

+7 -21

arch/powerpc/mm/mmu_decl.h

··· 38 38 #else /* CONFIG_40x || CONFIG_PPC_8xx */ 39 39 extern void _tlbil_all(void); 40 40 extern void _tlbil_pid(unsigned int pid); 41 - #ifdef CONFIG_PPC_BOOK3E 41 + #ifdef CONFIG_PPC_BOOK3E_64 42 42 extern void _tlbil_pid_noind(unsigned int pid); 43 43 #else 44 44 #define _tlbil_pid_noind(pid) _tlbil_pid(pid) ··· 55 55 asm volatile ("tlbie %0; sync" : : "r" (address) : "memory"); 56 56 trace_tlbie(0, 0, address, pid, 0, 0, 0); 57 57 } 58 - #elif defined(CONFIG_PPC_BOOK3E) 58 + #elif defined(CONFIG_PPC_BOOK3E_64) 59 59 extern void _tlbil_va(unsigned long address, unsigned int pid, 60 60 unsigned int tsize, unsigned int ind); 61 61 #else ··· 67 67 } 68 68 #endif /* CONFIG_PPC_8xx */ 69 69 70 - #if defined(CONFIG_PPC_BOOK3E) || defined(CONFIG_PPC_47x) 70 + #if defined(CONFIG_PPC_BOOK3E_64) || defined(CONFIG_PPC_47x) 71 71 extern void _tlbivax_bcast(unsigned long address, unsigned int pid, 72 72 unsigned int tsize, unsigned int ind); 73 73 #else ··· 92 92 extern void setbat(int index, unsigned long virt, phys_addr_t phys, 93 93 unsigned int size, pgprot_t prot); 94 94 95 - extern unsigned int rtas_data, rtas_size; 96 - 97 - struct hash_pte; 98 95 extern u8 early_hash[]; 99 96 100 97 #endif /* CONFIG_PPC32 */ 101 98 102 99 extern unsigned long __max_low_memory; 103 - extern phys_addr_t __initial_memory_limit_addr; 104 100 extern phys_addr_t total_memory; 105 101 extern phys_addr_t total_lowmem; 106 102 extern phys_addr_t memstart_addr; 107 103 extern phys_addr_t lowmem_end_addr; 108 - 109 - #ifdef CONFIG_WII 110 - extern unsigned long wii_hole_start; 111 - extern unsigned long wii_hole_size; 112 - 113 - extern unsigned long wii_mmu_mapin_mem2(unsigned long top); 114 - extern void wii_memory_fixups(void); 115 - #endif 116 104 117 105 /* ...and now those things that may be slightly different between processor 118 106 * architectures. -- Dan ··· 111 123 unsigned long mmu_mapin_ram(unsigned long base, unsigned long top); 112 124 #endif 113 125 114 - #ifdef CONFIG_PPC_FSL_BOOK3E 126 + #ifdef CONFIG_PPC_E500 115 127 extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx, 116 128 bool dryrun, bool init); 117 - extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, 118 - phys_addr_t phys); 119 129 #ifdef CONFIG_PPC32 120 130 extern void adjust_total_lowmem(void); 121 131 extern int switch_to_as1(void); ··· 146 160 extern struct tlbcam TLBCAM[NUM_TLBCAMS]; 147 161 #endif 148 162 149 - #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_FSL_BOOKE) || defined(CONFIG_PPC_8xx) 163 + #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_8xx) 150 164 /* 6xx have BATS */ 151 - /* FSL_BOOKE have TLBCAM */ 165 + /* PPC_85xx have TLBCAM */ 152 166 /* 8xx have LTLB */ 153 167 phys_addr_t v_block_mapped(unsigned long va); 154 168 unsigned long p_block_mapped(phys_addr_t pa); ··· 157 171 static inline unsigned long p_block_mapped(phys_addr_t pa) { return 0; } 158 172 #endif 159 173 160 - #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC_FSL_BOOK3E) 174 + #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC_E500) 161 175 void mmu_mark_initmem_nx(void); 162 176 void mmu_mark_rodata_ro(void); 163 177 #else

+3 -3

arch/powerpc/mm/nohash/Makefile

··· 7 7 obj-$(CONFIG_40x) += 40x.o 8 8 obj-$(CONFIG_44x) += 44x.o 9 9 obj-$(CONFIG_PPC_8xx) += 8xx.o 10 - obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_book3e.o 10 + obj-$(CONFIG_PPC_E500) += e500.o 11 11 obj-$(CONFIG_RANDOMIZE_BASE) += kaslr_booke.o 12 12 ifdef CONFIG_HUGETLB_PAGE 13 - obj-$(CONFIG_PPC_FSL_BOOK3E) += book3e_hugetlbpage.o 13 + obj-$(CONFIG_PPC_E500) += e500_hugetlbpage.o 14 14 endif 15 15 16 16 # Disable kcov instrumentation on sensitive code 17 17 # This is necessary for booting with kcov enabled on book3e machines 18 18 KCOV_INSTRUMENT_tlb.o := n 19 - KCOV_INSTRUMENT_fsl_book3e.o := n 19 + KCOV_INSTRUMENT_e500.o := n

arch/powerpc/mm/nohash/book3e_hugetlbpage.c arch/powerpc/mm/nohash/e500_hugetlbpage.c

+3 -3

arch/powerpc/mm/nohash/fsl_book3e.c arch/powerpc/mm/nohash/e500.c

··· 59 59 phys_addr_t phys; 60 60 } tlbcam_addrs[NUM_TLBCAMS]; 61 61 62 - #ifdef CONFIG_FSL_BOOKE 62 + #ifdef CONFIG_PPC_85xx 63 63 /* 64 64 * Return PA for this VA if it is mapped by a CAM, or 0 65 65 */ ··· 135 135 tlbcam_addrs[index].phys = phys; 136 136 } 137 137 138 - unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, 139 - phys_addr_t phys) 138 + static unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, 139 + phys_addr_t phys) 140 140 { 141 141 unsigned int camsize = __ilog2(ram); 142 142 unsigned int align = __ffs(virt | phys);

+23 -57

arch/powerpc/mm/nohash/tlb.c

··· 49 49 * other sizes not listed here. The .ind field is only used on MMUs that have 50 50 * indirect page table entries. 51 51 */ 52 - #if defined(CONFIG_PPC_BOOK3E_MMU) || defined(CONFIG_PPC_8xx) 53 - #ifdef CONFIG_PPC_FSL_BOOK3E 52 + #ifdef CONFIG_PPC_E500 54 53 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { 55 54 [MMU_PAGE_4K] = { 56 55 .shift = 12, ··· 80 81 .enc = BOOK3E_PAGESZ_1GB, 81 82 }, 82 83 }; 83 - #elif defined(CONFIG_PPC_8xx) 84 + 85 + static inline int mmu_get_tsize(int psize) 86 + { 87 + return mmu_psize_defs[psize].enc; 88 + } 89 + #else 90 + static inline int mmu_get_tsize(int psize) 91 + { 92 + /* This isn't used on !Book3E for now */ 93 + return 0; 94 + } 95 + #endif 96 + 97 + #ifdef CONFIG_PPC_8xx 84 98 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { 85 99 [MMU_PAGE_4K] = { 86 100 .shift = 12, ··· 108 96 .shift = 23, 109 97 }, 110 98 }; 111 - #else 112 - struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { 113 - [MMU_PAGE_4K] = { 114 - .shift = 12, 115 - .ind = 20, 116 - .enc = BOOK3E_PAGESZ_4K, 117 - }, 118 - [MMU_PAGE_16K] = { 119 - .shift = 14, 120 - .enc = BOOK3E_PAGESZ_16K, 121 - }, 122 - [MMU_PAGE_64K] = { 123 - .shift = 16, 124 - .ind = 28, 125 - .enc = BOOK3E_PAGESZ_64K, 126 - }, 127 - [MMU_PAGE_1M] = { 128 - .shift = 20, 129 - .enc = BOOK3E_PAGESZ_1M, 130 - }, 131 - [MMU_PAGE_16M] = { 132 - .shift = 24, 133 - .ind = 36, 134 - .enc = BOOK3E_PAGESZ_16M, 135 - }, 136 - [MMU_PAGE_256M] = { 137 - .shift = 28, 138 - .enc = BOOK3E_PAGESZ_256M, 139 - }, 140 - [MMU_PAGE_1G] = { 141 - .shift = 30, 142 - .enc = BOOK3E_PAGESZ_1GB, 143 - }, 144 - }; 145 - #endif /* CONFIG_FSL_BOOKE */ 146 - 147 - static inline int mmu_get_tsize(int psize) 148 - { 149 - return mmu_psize_defs[psize].enc; 150 - } 151 - #else 152 - static inline int mmu_get_tsize(int psize) 153 - { 154 - /* This isn't used on !Book3E for now */ 155 - return 0; 156 - } 157 - #endif /* CONFIG_PPC_BOOK3E_MMU */ 99 + #endif 158 100 159 101 /* The variables below are currently only used on 64-bit Book3E 160 102 * though this will probably be made common with other nohash ··· 132 166 133 167 #endif /* CONFIG_PPC64 */ 134 168 135 - #ifdef CONFIG_PPC_FSL_BOOK3E 169 + #ifdef CONFIG_PPC_E500 136 170 /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */ 137 171 DEFINE_PER_CPU(int, next_tlbcam_idx); 138 172 EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx); ··· 407 441 unsigned int eptcfg; 408 442 int i, psize; 409 443 410 - #ifdef CONFIG_PPC_FSL_BOOK3E 444 + #ifdef CONFIG_PPC_E500 411 445 unsigned int mmucfg = mfspr(SPRN_MMUCFG); 412 446 int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E); 413 447 ··· 550 584 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e); 551 585 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e); 552 586 break; 553 - #ifdef CONFIG_PPC_FSL_BOOK3E 587 + #ifdef CONFIG_PPC_E500 554 588 case PPC_HTW_E6500: 555 589 extlb_level_exc = EX_TLB_SIZE; 556 590 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e); ··· 593 627 } 594 628 mtspr(SPRN_MAS4, mas4); 595 629 596 - #ifdef CONFIG_PPC_FSL_BOOK3E 630 + #ifdef CONFIG_PPC_E500 597 631 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { 598 632 unsigned int num_cams; 599 633 bool map = true; ··· 646 680 /* Look for HW tablewalk support */ 647 681 setup_mmu_htw(); 648 682 649 - #ifdef CONFIG_PPC_FSL_BOOK3E 683 + #ifdef CONFIG_PPC_E500 650 684 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { 651 685 if (book3e_htw_mode == PPC_HTW_NONE) { 652 686 extlb_level_exc = EX_TLB_SIZE; ··· 667 701 668 702 static void __init early_mmu_set_memory_limit(void) 669 703 { 670 - #ifdef CONFIG_PPC_FSL_BOOK3E 704 + #ifdef CONFIG_PPC_E500 671 705 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { 672 706 /* 673 707 * Limit memory so we dont have linear faults. ··· 716 750 * We crop it to the size of the first MEMBLOCK to 717 751 * avoid going over total available memory just in case... 718 752 */ 719 - #ifdef CONFIG_PPC_FSL_BOOK3E 753 + #ifdef CONFIG_PPC_E500 720 754 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { 721 755 unsigned long linear_sz; 722 756 unsigned int num_cams;

+3 -3

arch/powerpc/mm/nohash/tlb_low.S

··· 221 221 blr 222 222 #endif /* CONFIG_PPC_47x */ 223 223 224 - #elif defined(CONFIG_FSL_BOOKE) 224 + #elif defined(CONFIG_PPC_85xx) 225 225 /* 226 226 * FSL BookE implementations. 227 227 * ··· 294 294 isync 295 295 1: wrtee r10 296 296 blr 297 - #elif defined(CONFIG_PPC_BOOK3E) 297 + #elif defined(CONFIG_PPC_BOOK3E_64) 298 298 /* 299 299 * New Book3E (>= 2.06) implementation 300 300 * ··· 364 364 #error Unsupported processor type ! 365 365 #endif 366 366 367 - #if defined(CONFIG_PPC_FSL_BOOK3E) 367 + #if defined(CONFIG_PPC_E500) 368 368 /* 369 369 * extern void loadcam_entry(unsigned int index) 370 370 *

+2 -8

arch/powerpc/mm/nohash/tlb_low_64e.S

··· 61 61 ld r14,PACAPGD(r13) 62 62 std r15,EX_TLB_R15(r12) 63 63 std r10,EX_TLB_CR(r12) 64 - #ifdef CONFIG_PPC_FSL_BOOK3E 65 64 START_BTB_FLUSH_SECTION 66 65 mfspr r11, SPRN_SRR1 67 66 andi. r10,r11,MSR_PR ··· 69 70 1: 70 71 END_BTB_FLUSH_SECTION 71 72 std r7,EX_TLB_R7(r12) 72 - #endif 73 73 .endm 74 74 75 75 .macro tlb_epilog_bolted 76 76 ld r14,EX_TLB_CR(r12) 77 - #ifdef CONFIG_PPC_FSL_BOOK3E 78 77 ld r7,EX_TLB_R7(r12) 79 - #endif 80 78 ld r10,EX_TLB_R10(r12) 81 79 ld r11,EX_TLB_R11(r12) 82 80 ld r13,EX_TLB_R13(r12) ··· 244 248 beq tlb_miss_user_bolted 245 249 b itlb_miss_kernel_bolted 246 250 247 - #ifdef CONFIG_PPC_FSL_BOOK3E 248 251 /* 249 252 * TLB miss handling for e6500 and derivatives, using hardware tablewalk. 250 253 * ··· 510 515 itlb_miss_fault_e6500: 511 516 tlb_epilog_bolted 512 517 b exc_instruction_storage_book3e 513 - #endif /* CONFIG_PPC_FSL_BOOK3E */ 514 518 515 519 /********************************************************************** 516 520 * * ··· 1118 1124 * we only use 1G pages for now. That might have to be changed in a 1119 1125 * final implementation, especially when dealing with hypervisors 1120 1126 */ 1121 - ld r11,PACATOC(r13) 1122 - ld r11,linear_map_top@got(r11) 1127 + __LOAD_PACA_TOC(r11) 1128 + LOAD_REG_ADDR_ALTTOC(r11, r11, linear_map_top) 1123 1129 ld r10,0(r11) 1124 1130 tovirt(10,10) 1125 1131 cmpld cr0,r16,r10

+3 -3

arch/powerpc/mm/numa.c

··· 1160 1160 { 1161 1161 int cpu; 1162 1162 1163 + max_low_pfn = max_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1164 + min_low_pfn = MEMORY_START >> PAGE_SHIFT; 1165 + 1163 1166 /* 1164 1167 * Linux/mm assumes node 0 to be online at boot. However this is not 1165 1168 * true on PowerPC, where node 0 is similar to any other node, it ··· 1206 1203 void __init initmem_init(void) 1207 1204 { 1208 1205 int nid; 1209 - 1210 - max_low_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1211 - max_pfn = max_low_pfn; 1212 1206 1213 1207 memblock_dump_all(); 1214 1208

+4 -3

arch/powerpc/mm/pgtable_32.c

··· 158 158 } 159 159 160 160 /* 161 - * mark .text and .rodata as read only. Use __init_begin rather than 162 - * __end_rodata to cover NOTES and EXCEPTION_TABLE. 161 + * mark text and rodata as read only. __end_rodata is set by 162 + * powerpc's linker script and includes tables and data 163 + * requiring relocation which are not put in RO_DATA. 163 164 */ 164 - numpages = PFN_UP((unsigned long)__init_begin) - 165 + numpages = PFN_UP((unsigned long)__end_rodata) - 165 166 PFN_DOWN((unsigned long)_stext); 166 167 167 168 set_memory_ro((unsigned long)_stext, numpages);

+1 -1

arch/powerpc/mm/ptdump/Makefile

··· 4 4 5 5 obj-$(CONFIG_4xx) += shared.o 6 6 obj-$(CONFIG_PPC_8xx) += 8xx.o 7 - obj-$(CONFIG_PPC_BOOK3E_MMU) += shared.o 7 + obj-$(CONFIG_PPC_E500) += shared.o 8 8 obj-$(CONFIG_PPC_BOOK3S_32) += shared.o 9 9 obj-$(CONFIG_PPC_BOOK3S_64) += book3s64.o 10 10

+1 -1

arch/powerpc/perf/bhrb.S

··· 21 21 _GLOBAL(read_bhrb) 22 22 cmpldi r3,31 23 23 bgt 1f 24 - ld r4,bhrb_table@got(r2) 24 + LOAD_REG_ADDR(r4, bhrb_table) 25 25 sldi r3,r3,3 26 26 add r3,r4,r3 27 27 mtctr r3

+1 -1

arch/powerpc/perf/callchain_32.c

··· 19 19 #include "callchain.h" 20 20 21 21 #ifdef CONFIG_PPC64 22 - #include "../kernel/ppc32.h" 22 + #include <asm/syscalls_32.h> 23 23 #else /* CONFIG_PPC64 */ 24 24 25 25 #define __SIGNAL_FRAMESIZE32 __SIGNAL_FRAMESIZE

+17

arch/powerpc/perf/core-book3s.c

··· 2131 2131 if (has_branch_stack(event)) { 2132 2132 u64 bhrb_filter = -1; 2133 2133 2134 + /* 2135 + * Currently no PMU supports having multiple branch filters 2136 + * at the same time. Branch filters are set via MMCRA IFM[32:33] 2137 + * bits for Power8 and above. Return EOPNOTSUPP when multiple 2138 + * branch filters are requested in the event attr. 2139 + * 2140 + * When opening event via perf_event_open(), branch_sample_type 2141 + * gets adjusted in perf_copy_attr(). Kernel will automatically 2142 + * adjust the branch_sample_type based on the event modifier 2143 + * settings to include PERF_SAMPLE_BRANCH_PLM_ALL. Hence drop 2144 + * the check for PERF_SAMPLE_BRANCH_PLM_ALL. 2145 + */ 2146 + if (hweight64(event->attr.branch_sample_type & ~PERF_SAMPLE_BRANCH_PLM_ALL) > 1) { 2147 + local_irq_restore(irq_flags); 2148 + return -EOPNOTSUPP; 2149 + } 2150 + 2134 2151 if (ppmu->bhrb_filter_map) 2135 2152 bhrb_filter = ppmu->bhrb_filter_map( 2136 2153 event->attr.branch_sample_type);

+8 -2

arch/powerpc/perf/imc-pmu.c

··· 240 240 ct = of_get_child_count(pmu_events); 241 241 242 242 /* Get the event prefix */ 243 - if (of_property_read_string(node, "events-prefix", &prefix)) 243 + if (of_property_read_string(node, "events-prefix", &prefix)) { 244 + of_node_put(pmu_events); 244 245 return 0; 246 + } 245 247 246 248 /* Get a global unit and scale data if available */ 247 249 if (of_property_read_string(node, "scale", &g_scale)) ··· 257 255 258 256 /* Allocate memory for the events */ 259 257 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL); 260 - if (!pmu->events) 258 + if (!pmu->events) { 259 + of_node_put(pmu_events); 261 260 return -ENOMEM; 261 + } 262 262 263 263 ct = 0; 264 264 /* Parse the events and update the struct */ ··· 269 265 if (!ret) 270 266 ct++; 271 267 } 268 + 269 + of_node_put(pmu_events); 272 270 273 271 /* Allocate memory for attribute group */ 274 272 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);

+2

arch/powerpc/platforms/44x/ppc476.c

··· 140 140 ppc_md.get_irq = mpic_get_irq; 141 141 } else 142 142 panic("Unrecognized top level interrupt controller"); 143 + 144 + of_node_put(np); 143 145 } 144 146 145 147 #ifdef CONFIG_SMP

+6 -2

arch/powerpc/platforms/512x/clock-commonclk.c

··· 950 950 */ 951 951 static void __init mpc5121_clk_provide_migration_support(void) 952 952 { 953 - 953 + struct device_node *np; 954 954 /* 955 955 * pre-enable those clock items which are not yet appropriately 956 956 * acquired by their peripheral driver ··· 970 970 * unused and so it gets disabled 971 971 */ 972 972 clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ 973 - if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci")) 973 + np = of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci"); 974 + of_node_put(np); 975 + if (np) 974 976 clk_prepare_enable(clks[MPC512x_CLK_PCI]); 975 977 } 976 978 ··· 1209 1207 1210 1208 /* register as an OF clock provider */ 1211 1209 mpc5121_clk_register_of_provider(clk_np); 1210 + 1211 + of_node_put(clk_np); 1212 1212 1213 1213 /* 1214 1214 * unbreak not yet adjusted peripheral drivers during migration

+3

arch/powerpc/platforms/52xx/media5200.c

··· 174 174 goto out; 175 175 pr_debug("%s: allocated irqhost\n", __func__); 176 176 177 + of_node_put(fpga_np); 178 + 177 179 irq_set_handler_data(cascade_virq, &media5200_irq); 178 180 irq_set_chained_handler(cascade_virq, media5200_irq_cascade); 179 181 ··· 183 181 184 182 out: 185 183 pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n"); 184 + of_node_put(fpga_np); 186 185 } 187 186 188 187 /*

+5 -1

arch/powerpc/platforms/83xx/mpc832x_rdb.c

··· 162 162 163 163 static int __init mpc832x_spi_init(void) 164 164 { 165 + struct device_node *np; 166 + 165 167 par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */ 166 168 par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */ 167 169 par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */ ··· 177 175 * Don't bother with legacy stuff when device tree contains 178 176 * mmc-spi-slot node. 179 177 */ 180 - if (of_find_compatible_node(NULL, NULL, "mmc-spi-slot")) 178 + np = of_find_compatible_node(NULL, NULL, "mmc-spi-slot"); 179 + of_node_put(np); 180 + if (np) 181 181 return 0; 182 182 return fsl_spi_init(&mpc832x_spi_boardinfo, 1, mpc83xx_spi_cs_control); 183 183 }

+1 -4

arch/powerpc/platforms/85xx/Kconfig

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 menuconfig FSL_SOC_BOOKE 3 3 bool "Freescale Book-E Machine Type" 4 - depends on PPC_85xx || PPC_BOOK3E 4 + depends on PPC_E500 5 5 select FSL_SOC 6 6 select PPC_UDBG_16550 7 7 select MPIC ··· 241 241 config PPC_QEMU_E500 242 242 bool "QEMU generic e500 platform" 243 243 select DEFAULT_UIMAGE 244 - select E500 245 - select PPC_E500MC if PPC64 246 244 help 247 245 This option enables support for running as a QEMU guest using 248 246 QEMU's generic e500 machine. This is not required if you're ··· 256 258 config CORENET_GENERIC 257 259 bool "Freescale CoreNet Generic" 258 260 select DEFAULT_UIMAGE 259 - select E500 260 261 select PPC_E500MC 261 262 select PHYS_64BIT 262 263 select SWIOTLB

-4

arch/powerpc/platforms/85xx/corenet_generic.c

··· 200 200 #endif 201 201 .calibrate_decr = generic_calibrate_decr, 202 202 .progress = udbg_progress, 203 - #ifdef CONFIG_PPC64 204 - .power_save = book3e_idle, 205 - #else 206 203 .power_save = e500_idle, 207 - #endif 208 204 };

+4 -2

arch/powerpc/platforms/85xx/ge_imp3a.c

··· 89 89 of_device_is_compatible(np, "fsl,mpc8548-pcie") || 90 90 of_device_is_compatible(np, "fsl,p2020-pcie")) { 91 91 of_address_to_resource(np, 0, &rsrc); 92 - if ((rsrc.start & 0xfffff) == 0x9000) 93 - fsl_pci_primary = np; 92 + if ((rsrc.start & 0xfffff) == 0x9000) { 93 + of_node_put(fsl_pci_primary); 94 + fsl_pci_primary = of_node_get(np); 95 + } 94 96 } 95 97 } 96 98 #endif

+2

arch/powerpc/platforms/85xx/ksi8560.c

··· 133 133 else 134 134 printk(KERN_ERR "Can't find CPLD in device tree\n"); 135 135 136 + of_node_put(cpld); 137 + 136 138 if (ppc_md.progress) 137 139 ppc_md.progress("ksi8560_setup_arch()", 0); 138 140

+1

arch/powerpc/platforms/85xx/mpc85xx_cds.c

··· 159 159 else 160 160 dev->irq = 10; 161 161 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 162 + break; 162 163 default: 163 164 break; 164 165 }

-4

arch/powerpc/platforms/85xx/qemu_e500.c

··· 68 68 .get_irq = mpic_get_coreint_irq, 69 69 .calibrate_decr = generic_calibrate_decr, 70 70 .progress = udbg_progress, 71 - #ifdef CONFIG_PPC64 72 - .power_save = book3e_idle, 73 - #else 74 71 .power_save = e500_idle, 75 - #endif 76 72 };

+22 -13

arch/powerpc/platforms/85xx/sgy_cts1000.c

··· 71 71 { 72 72 enum of_gpio_flags flags; 73 73 struct device_node *node = pdev->dev.of_node; 74 + struct device_node *child_node; 74 75 int gpio, err, irq; 75 76 int trigger; 76 77 ··· 79 78 return -ENODEV; 80 79 81 80 /* If there's no matching child, this isn't really an error */ 82 - halt_node = of_find_matching_node(node, child_match); 83 - if (!halt_node) 81 + child_node = of_find_matching_node(node, child_match); 82 + if (!child_node) 84 83 return 0; 85 84 86 85 /* Technically we could just read the first one, but punish 87 86 * DT writers for invalid form. */ 88 - if (of_gpio_count(halt_node) != 1) 89 - return -EINVAL; 87 + if (of_gpio_count(child_node) != 1) { 88 + err = -EINVAL; 89 + goto err_put; 90 + } 90 91 91 92 /* Get the gpio number relative to the dynamic base. */ 92 - gpio = of_get_gpio_flags(halt_node, 0, &flags); 93 - if (!gpio_is_valid(gpio)) 94 - return -EINVAL; 93 + gpio = of_get_gpio_flags(child_node, 0, &flags); 94 + if (!gpio_is_valid(gpio)) { 95 + err = -EINVAL; 96 + goto err_put; 97 + } 95 98 96 99 err = gpio_request(gpio, "gpio-halt"); 97 100 if (err) { 98 101 printk(KERN_ERR "gpio-halt: error requesting GPIO %d.\n", 99 102 gpio); 100 - halt_node = NULL; 101 - return err; 103 + goto err_put; 102 104 } 103 105 104 106 trigger = (flags == OF_GPIO_ACTIVE_LOW); ··· 109 105 gpio_direction_output(gpio, !trigger); 110 106 111 107 /* Now get the IRQ which tells us when the power button is hit */ 112 - irq = irq_of_parse_and_map(halt_node, 0); 108 + irq = irq_of_parse_and_map(child_node, 0); 113 109 err = request_irq(irq, gpio_halt_irq, IRQF_TRIGGER_RISING | 114 - IRQF_TRIGGER_FALLING, "gpio-halt", halt_node); 110 + IRQF_TRIGGER_FALLING, "gpio-halt", child_node); 115 111 if (err) { 116 112 printk(KERN_ERR "gpio-halt: error requesting IRQ %d for " 117 113 "GPIO %d.\n", irq, gpio); 118 114 gpio_free(gpio); 119 - halt_node = NULL; 120 - return err; 115 + goto err_put; 121 116 } 122 117 123 118 /* Register our halt function */ ··· 126 123 printk(KERN_INFO "gpio-halt: registered GPIO %d (%d trigger, %d" 127 124 " irq).\n", gpio, trigger, irq); 128 125 126 + halt_node = child_node; 129 127 return 0; 128 + 129 + err_put: 130 + of_node_put(child_node); 131 + return err; 130 132 } 131 133 132 134 static int gpio_halt_remove(struct platform_device *pdev) ··· 147 139 148 140 gpio_free(gpio); 149 141 142 + of_node_put(halt_node); 150 143 halt_node = NULL; 151 144 } 152 145

+3

arch/powerpc/platforms/8xx/tqm8xx_setup.c

··· 105 105 if (dnode == NULL) 106 106 return; 107 107 prop = of_find_property(dnode, "ethernet1", &len); 108 + 109 + of_node_put(dnode); 110 + 108 111 if (prop == NULL) 109 112 return; 110 113

+29 -42

arch/powerpc/platforms/Kconfig.cputype

··· 33 33 34 34 config PPC_85xx 35 35 bool "Freescale 85xx" 36 - select E500 36 + select PPC_E500 37 37 38 38 config PPC_8xx 39 39 bool "Freescale 8xx" ··· 107 107 108 108 config PPC_BOOK3E_64 109 109 bool "Embedded processors" 110 - select PPC_FSL_BOOK3E 110 + select PPC_E500 111 + select PPC_E500MC 111 112 select PPC_FPU # Make it a choice ? 112 113 select PPC_SMP_MUXED_IPI 113 114 select PPC_DOORBELL ··· 126 125 If unsure, select Generic. 127 126 128 127 config GENERIC_CPU 129 - bool "Generic (POWER4 and above)" 128 + bool "Generic (POWER5 and PowerPC 970 and above)" 130 129 depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN 131 130 select PPC_64S_HASH_MMU 132 131 ··· 145 144 depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN 146 145 select PPC_64S_HASH_MMU 147 146 148 - config POWER5_CPU 149 - bool "POWER5" 147 + config PPC_970_CPU 148 + bool "PowerPC 970 (including PowerPC G5)" 150 149 depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN 151 150 select PPC_64S_HASH_MMU 152 151 ··· 172 171 depends on PPC_BOOK3S_64 173 172 select ARCH_HAS_FAST_MULTIPLIER 174 173 174 + config POWER10_CPU 175 + bool "POWER10" 176 + depends on PPC_BOOK3S_64 177 + select ARCH_HAS_FAST_MULTIPLIER 178 + 175 179 config E5500_CPU 176 180 bool "Freescale e5500" 177 - depends on PPC64 && E500 181 + depends on PPC64 && PPC_E500 178 182 179 183 config E6500_CPU 180 184 bool "Freescale e6500" 181 - depends on PPC64 && E500 185 + depends on PPC64 && PPC_E500 182 186 183 187 config 405_CPU 184 188 bool "40x family" ··· 240 234 string 241 235 depends on TARGET_CPU_BOOL 242 236 default "cell" if CELL_CPU 243 - default "power5" if POWER5_CPU 237 + default "970" if PPC_970_CPU 244 238 default "power6" if POWER6_CPU 245 239 default "power7" if POWER7_CPU 246 240 default "power8" if POWER8_CPU 247 241 default "power9" if POWER9_CPU 242 + default "power10" if POWER10_CPU 248 243 default "405" if 405_CPU 249 244 default "440" if 440_CPU 250 245 default "464" if 464_CPU ··· 262 255 def_bool y 263 256 depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 264 257 265 - config PPC_BOOK3E 266 - def_bool y 267 - depends on PPC_BOOK3E_64 268 - 269 - config E500 258 + config PPC_E500 270 259 select FSL_EMB_PERFMON 271 - select PPC_FSL_BOOK3E 272 260 bool 261 + select ARCH_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64 262 + select PPC_SMP_MUXED_IPI 263 + select PPC_DOORBELL 264 + select PPC_KUEP 273 265 274 266 config PPC_E500MC 275 267 bool "e500mc Support" 276 268 select PPC_FPU 277 269 select COMMON_CLK 278 - depends on E500 270 + depends on PPC_E500 279 271 help 280 272 This must be enabled for running on e500mc (and derivatives 281 273 such as e5500/e6500), and must be disabled for running on ··· 297 291 298 292 config FSL_EMB_PERFMON 299 293 bool "Freescale Embedded Perfmon" 300 - depends on E500 || PPC_83xx 294 + depends on PPC_E500 || PPC_83xx 301 295 help 302 296 This is the Performance Monitor support found on the e500 core 303 297 and some e300 cores (c3 and c4). Select this only if your ··· 310 304 311 305 config FSL_EMB_PERF_EVENT_E500 312 306 bool 313 - depends on FSL_EMB_PERF_EVENT && E500 307 + depends on FSL_EMB_PERF_EVENT && PPC_E500 314 308 default y 315 309 316 310 config 4xx ··· 320 314 321 315 config BOOKE 322 316 bool 323 - depends on E500 || 44x || PPC_BOOK3E 317 + depends on PPC_E500 || 44x 324 318 default y 325 319 326 320 config BOOKE_OR_40x ··· 328 322 depends on BOOKE || 40x 329 323 default y 330 324 331 - config FSL_BOOKE 332 - bool 333 - depends on E500 && PPC32 334 - default y 335 - 336 - # this is for common code between PPC32 & PPC64 FSL BOOKE 337 - config PPC_FSL_BOOK3E 338 - bool 339 - select ARCH_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64 340 - imply FSL_EMB_PERFMON 341 - select PPC_SMP_MUXED_IPI 342 - select PPC_DOORBELL 343 - select PPC_KUEP 344 - default y if FSL_BOOKE 345 - 346 325 config PTE_64BIT 347 326 bool 348 - depends on 44x || E500 || PPC_86xx 327 + depends on 44x || PPC_E500 || PPC_86xx 349 328 default y if PHYS_64BIT 350 329 351 330 config PHYS_64BIT 352 - bool 'Large physical address support' if E500 || PPC_86xx 353 - depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx 331 + bool 'Large physical address support' if PPC_E500 || PPC_86xx 332 + depends on (44x || PPC_E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx 354 333 select PHYS_ADDR_T_64BIT 355 334 help 356 335 This option enables kernel support for larger than 32-bit physical ··· 382 391 383 392 config SPE_POSSIBLE 384 393 def_bool y 385 - depends on E500 && !PPC_E500MC 394 + depends on PPC_E500 && !PPC_E500MC 386 395 387 396 config SPE 388 397 bool "SPE Support" ··· 472 481 def_bool y 473 482 depends on !PPC_BOOK3S 474 483 475 - config PPC_BOOK3E_MMU 476 - def_bool y 477 - depends on FSL_BOOKE || PPC_BOOK3E 478 - 479 484 config PPC_HAVE_PMU_SUPPORT 480 485 bool 481 486 ··· 493 506 select SMP 494 507 495 508 config SMP 496 - depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x 509 + depends on PPC_BOOK3S || PPC_E500 || PPC_47x 497 510 select GENERIC_IRQ_MIGRATION 498 511 bool "Symmetric multi-processing support" if !FORCE_SMP 499 512 help

+1 -1

arch/powerpc/platforms/book3s/vas-api.c

··· 431 431 * The window may be inactive due to lost credit (Ex: core 432 432 * removal with DLPAR). If the window is active again when 433 433 * the credit is available, map the new paste address at the 434 - * the window virtual address. 434 + * window virtual address. 435 435 */ 436 436 if (txwin->status == VAS_WIN_ACTIVE) { 437 437 paste_addr = cp_inst->coproc->vops->paste_addr(txwin);

+27 -10

arch/powerpc/platforms/cell/cbe_regs.c

··· 182 182 if (WARN_ON_ONCE(!cpu_handle)) 183 183 return np; 184 184 185 - for (i=0; i<len; i++) 186 - if (of_find_node_by_phandle(cpu_handle[i]) == of_get_cpu_node(cpu_id, NULL)) 185 + for (i = 0; i < len; i++) { 186 + struct device_node *ch_np = of_find_node_by_phandle(cpu_handle[i]); 187 + struct device_node *ci_np = of_get_cpu_node(cpu_id, NULL); 188 + 189 + of_node_put(ch_np); 190 + of_node_put(ci_np); 191 + 192 + if (ch_np == ci_np) 187 193 return np; 194 + } 188 195 } 189 196 190 197 return NULL; ··· 200 193 static void __init cbe_fill_regs_map(struct cbe_regs_map *map) 201 194 { 202 195 if(map->be_node) { 203 - struct device_node *be, *np; 196 + struct device_node *be, *np, *parent_np; 204 197 205 198 be = map->be_node; 206 199 207 - for_each_node_by_type(np, "pervasive") 208 - if (of_get_parent(np) == be) 200 + for_each_node_by_type(np, "pervasive") { 201 + parent_np = of_get_parent(np); 202 + if (parent_np == be) 209 203 map->pmd_regs = of_iomap(np, 0); 204 + of_node_put(parent_np); 205 + } 210 206 211 - for_each_node_by_type(np, "CBEA-Internal-Interrupt-Controller") 212 - if (of_get_parent(np) == be) 207 + for_each_node_by_type(np, "CBEA-Internal-Interrupt-Controller") { 208 + parent_np = of_get_parent(np); 209 + if (parent_np == be) 213 210 map->iic_regs = of_iomap(np, 2); 211 + of_node_put(parent_np); 212 + } 214 213 215 - for_each_node_by_type(np, "mic-tm") 216 - if (of_get_parent(np) == be) 214 + for_each_node_by_type(np, "mic-tm") { 215 + parent_np = of_get_parent(np); 216 + if (parent_np == be) 217 217 map->mic_tm_regs = of_iomap(np, 0); 218 + of_node_put(parent_np); 219 + } 218 220 } else { 219 221 struct device_node *cpu; 220 222 /* That hack must die die die ! */ ··· 277 261 of_node_put(cpu); 278 262 return; 279 263 } 280 - map->cpu_node = cpu; 264 + of_node_put(map->cpu_node); 265 + map->cpu_node = of_node_get(cpu); 281 266 282 267 for_each_possible_cpu(i) { 283 268 struct cbe_thread_map *thread = &cbe_thread_map[i];

+3 -1

arch/powerpc/platforms/cell/iommu.c

··· 720 720 cell_disable_iommus(); 721 721 722 722 /* If we have no Axon, we set up the spider DMA magic offset */ 723 - if (of_find_node_by_name(NULL, "axon") == NULL) 723 + np = of_find_node_by_name(NULL, "axon"); 724 + if (!np) 724 725 cell_dma_nommu_offset = SPIDER_DMA_OFFSET; 726 + of_node_put(np); 725 727 726 728 /* Now we need to check to see where the memory is mapped 727 729 * in PCI space. We assume that all busses use the same dma

+2

arch/powerpc/platforms/cell/setup.c

··· 167 167 of_platform_device_create(np, NULL, NULL); 168 168 } 169 169 170 + of_node_put(root); 171 + 170 172 /* There is no device for the MIC memory controller, thus we create 171 173 * a platform device for it to attach the EDAC driver to. 172 174 */

+3 -3

arch/powerpc/platforms/cell/spu_callbacks.c

··· 34 34 * mbind, mq_open, ipc, ... 35 35 */ 36 36 37 - static void *spu_syscall_table[] = { 37 + static const syscall_fn spu_syscall_table[] = { 38 38 #define __SYSCALL_WITH_COMPAT(nr, entry, compat) __SYSCALL(nr, entry) 39 - #define __SYSCALL(nr, entry) [nr] = entry, 39 + #define __SYSCALL(nr, entry) [nr] = (void *) entry, 40 40 #include <asm/syscall_table_spu.h> 41 41 }; 42 42 43 43 long spu_sys_callback(struct spu_syscall_block *s) 44 44 { 45 - long (*syscall)(u64 a1, u64 a2, u64 a3, u64 a4, u64 a5, u64 a6); 45 + syscall_fn syscall; 46 46 47 47 if (s->nr_ret >= ARRAY_SIZE(spu_syscall_table)) { 48 48 pr_debug("%s: invalid syscall #%lld", __func__, s->nr_ret);

+2

arch/powerpc/platforms/cell/spu_manage.c

··· 488 488 avoid_ph = vic_dn->phandle; 489 489 } 490 490 491 + of_node_put(vic_dn); 492 + 491 493 list_add_tail(&spu->aff_list, &last_spu->aff_list); 492 494 last_spu = spu; 493 495 break;

-2

arch/powerpc/platforms/cell/spufs/spufs.h

··· 333 333 void spufs_mfc_callback(struct spu *spu); 334 334 void spufs_dma_callback(struct spu *spu, int type); 335 335 336 - extern struct spu_coredump_calls spufs_coredump_calls; 337 336 struct spufs_coredump_reader { 338 337 char *name; 339 338 ssize_t (*dump)(struct spu_context *ctx, struct coredump_params *cprm); ··· 340 341 size_t size; 341 342 }; 342 343 extern const struct spufs_coredump_reader spufs_coredump_read[]; 343 - extern int spufs_coredump_num_notes; 344 344 345 345 extern int spu_init_csa(struct spu_state *csa); 346 346 extern void spu_fini_csa(struct spu_state *csa);

-1

arch/powerpc/platforms/chrp/chrp.h

··· 9 9 extern long chrp_time_init(void); 10 10 11 11 extern void chrp_find_bridges(void); 12 - extern void chrp_event_scan(unsigned long);

+6

arch/powerpc/platforms/embedded6xx/holly.c

··· 123 123 if (np) 124 124 tsi108_setup_pci(np, HOLLY_PCI_CFG_PHYS, 1); 125 125 126 + of_node_put(np); 127 + 126 128 ppc_md.pci_exclude_device = holly_exclude_device; 127 129 if (ppc_md.progress) 128 130 ppc_md.progress("tsi108: resources set", 0x100); ··· 186 184 tsi108_pci_int_init(cascade_node); 187 185 irq_set_handler_data(cascade_pci_irq, mpic); 188 186 irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); 187 + 188 + of_node_put(tsi_pci); 189 + of_node_put(cascade_node); 189 190 #endif 190 191 /* Configure MPIC outputs to CPU0 */ 191 192 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); ··· 215 210 if (bridge) { 216 211 prop = of_get_property(bridge, "reg", &size); 217 212 addr = of_translate_address(bridge, prop); 213 + of_node_put(bridge); 218 214 } 219 215 addr += (TSI108_PB_OFFSET + 0x414); 220 216

+2

arch/powerpc/platforms/embedded6xx/ls_uart.c

··· 124 124 avr_clock = *(u32*)of_get_property(avr, "clock-frequency", &len); 125 125 phys_addr = ((u32*)of_get_property(avr, "reg", &len))[0]; 126 126 127 + of_node_put(avr); 128 + 127 129 if (!avr_clock || !phys_addr) 128 130 return -EINVAL; 129 131

+3

arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c

··· 135 135 tsi108_pci_int_init(cascade_node); 136 136 irq_set_handler_data(cascade_pci_irq, mpic); 137 137 irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); 138 + 139 + of_node_put(tsi_pci); 140 + of_node_put(cascade_node); 138 141 #endif 139 142 /* Configure MPIC outputs to CPU0 */ 140 143 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);

-15

arch/powerpc/platforms/embedded6xx/wii.c

··· 15 15 #include <linux/seq_file.h> 16 16 #include <linux/of_address.h> 17 17 #include <linux/of_platform.h> 18 - #include <linux/memblock.h> 19 - #include <mm/mmu_decl.h> 20 18 21 19 #include <asm/io.h> 22 20 #include <asm/machdep.h> ··· 46 48 47 49 static void __iomem *hw_ctrl; 48 50 static void __iomem *hw_gpio; 49 - 50 - static int __init page_aligned(unsigned long x) 51 - { 52 - return !(x & (PAGE_SIZE-1)); 53 - } 54 - 55 - void __init wii_memory_fixups(void) 56 - { 57 - struct memblock_region *p = memblock.memory.regions; 58 - 59 - BUG_ON(memblock.memory.cnt != 2); 60 - BUG_ON(!page_aligned(p[0].base) || !page_aligned(p[1].base)); 61 - } 62 51 63 52 static void __noreturn wii_spin(void) 64 53 {

+1

arch/powerpc/platforms/maple/time.c

··· 153 153 maple_rtc_addr); 154 154 } 155 155 bail: 156 + of_node_put(rtcs); 156 157 if (maple_rtc_addr == 0) { 157 158 maple_rtc_addr = RTC_PORT(0); /* legacy address */ 158 159 printk(KERN_INFO "Maple: No device node for RTC, assuming "

+1 -2

arch/powerpc/platforms/pasemi/misc.c

··· 36 36 for (i = 0; i < ARRAY_SIZE(i2c_devices); i++) { 37 37 if (!of_device_is_compatible(node, i2c_devices[i].of_device)) 38 38 continue; 39 - if (strlcpy(info->type, i2c_devices[i].i2c_type, 40 - I2C_NAME_SIZE) >= I2C_NAME_SIZE) 39 + if (strscpy(info->type, i2c_devices[i].i2c_type, I2C_NAME_SIZE) < 0) 41 40 return -ENOMEM; 42 41 return 0; 43 42 }

+2 -8

arch/powerpc/platforms/pasemi/pci.c

··· 270 270 271 271 void __init pas_pci_init(void) 272 272 { 273 - struct device_node *np, *root; 273 + struct device_node *np; 274 274 int res; 275 - 276 - root = of_find_node_by_path("/"); 277 - if (!root) { 278 - pr_crit("pas_pci_init: can't find root of device tree\n"); 279 - return; 280 - } 281 275 282 276 pci_set_flags(PCI_SCAN_ALL_PCIE_DEVS); 283 277 284 - np = of_find_compatible_node(root, NULL, "pasemi,rootbus"); 278 + np = of_find_compatible_node(of_root, NULL, "pasemi,rootbus"); 285 279 if (np) { 286 280 res = pas_add_bridge(np); 287 281 of_node_put(np);

+10 -5

arch/powerpc/platforms/powermac/feature.c

··· 2632 2632 if (!macio_chips[i].of_node) 2633 2633 break; 2634 2634 if (macio_chips[i].of_node == node) 2635 - return; 2635 + goto out_put; 2636 2636 } 2637 2637 2638 2638 if (i >= MAX_MACIO_CHIPS) { 2639 2639 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n"); 2640 2640 printk(KERN_ERR "pmac_feature: %pOF skipped\n", node); 2641 - return; 2641 + goto out_put; 2642 2642 } 2643 2643 addrp = of_get_pci_address(node, 0, &size, NULL); 2644 2644 if (addrp == NULL) { 2645 2645 printk(KERN_ERR "pmac_feature: %pOF: can't find base !\n", 2646 2646 node); 2647 - return; 2647 + goto out_put; 2648 2648 } 2649 2649 addr = of_translate_address(node, addrp); 2650 2650 if (addr == 0) { 2651 2651 printk(KERN_ERR "pmac_feature: %pOF, can't translate base !\n", 2652 2652 node); 2653 - return; 2653 + goto out_put; 2654 2654 } 2655 2655 base = ioremap(addr, (unsigned long)size); 2656 2656 if (!base) { 2657 2657 printk(KERN_ERR "pmac_feature: %pOF, can't map mac-io chip !\n", 2658 2658 node); 2659 - return; 2659 + goto out_put; 2660 2660 } 2661 2661 if (type == macio_keylargo || type == macio_keylargo2) { 2662 2662 const u32 *did = of_get_property(node, "device-id", NULL); ··· 2677 2677 macio_chips[i].rev = *revp; 2678 2678 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n", 2679 2679 macio_names[type], macio_chips[i].rev, macio_chips[i].base); 2680 + 2681 + return; 2682 + 2683 + out_put: 2684 + of_node_put(node); 2680 2685 } 2681 2686 2682 2687 static int __init

+1

arch/powerpc/platforms/powermac/low_i2c.c

··· 627 627 if (parent == NULL) 628 628 continue; 629 629 chans = parent->name[0] == 'u' ? 2 : 1; 630 + of_node_put(parent); 630 631 for (i = 0; i < chans; i++) 631 632 kw_i2c_add(host, np, np, i); 632 633 } else {

+2

arch/powerpc/platforms/powermac/pfunc_base.c

··· 136 136 for_each_child_of_node(gparent, gp) 137 137 pmf_do_functions(gp, NULL, 0, PMF_FLAGS_ON_INIT, NULL); 138 138 139 + of_node_put(gparent); 140 + 139 141 /* Note: We do not at this point implement the "at sleep" or "at wake" 140 142 * functions. I yet to find any for GPIOs anyway 141 143 */

+1

arch/powerpc/platforms/powermac/smp.c

··· 711 711 printk(KERN_INFO "Processor timebase sync using" 712 712 " platform function\n"); 713 713 } 714 + of_node_put(cpus); 714 715 } 715 716 716 717 #else /* CONFIG_PPC64 */

+6 -2

arch/powerpc/platforms/powermac/udbg_scc.c

··· 81 81 if (path != NULL) 82 82 stdout = of_find_node_by_path(path); 83 83 for_each_child_of_node(escc, ch) { 84 - if (ch == stdout) 84 + if (ch == stdout) { 85 + of_node_put(ch_def); 85 86 ch_def = of_node_get(ch); 86 - if (of_node_name_eq(ch, "ch-a")) 87 + } 88 + if (of_node_name_eq(ch, "ch-a")) { 89 + of_node_put(ch_a); 87 90 ch_a = of_node_get(ch); 91 + } 88 92 } 89 93 if (ch_def == NULL && !force_scc) 90 94 goto bail;

+2 -1

arch/powerpc/platforms/powernv/idle.c

··· 1411 1411 goto out; 1412 1412 } 1413 1413 for (i = 0; i < nr_idle_states; i++) 1414 - strlcpy(pnv_idle_states[i].name, temp_string[i], 1414 + strscpy(pnv_idle_states[i].name, temp_string[i], 1415 1415 PNV_IDLE_NAME_LEN); 1416 1416 nr_pnv_idle_states = nr_idle_states; 1417 1417 rc = 0; ··· 1419 1419 kfree(temp_u32); 1420 1420 kfree(temp_u64); 1421 1421 kfree(temp_string); 1422 + of_node_put(np); 1422 1423 return rc; 1423 1424 } 1424 1425

+1 -3

arch/powerpc/platforms/powernv/ocxl.c

··· 478 478 int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle) 479 479 { 480 480 struct spa_data *data = (struct spa_data *) platform_data; 481 - int rc; 482 481 483 - rc = opal_npu_spa_clear_cache(data->phb_opal_id, data->bdfn, pe_handle); 484 - return rc; 482 + return opal_npu_spa_clear_cache(data->phb_opal_id, data->bdfn, pe_handle); 485 483 } 486 484 EXPORT_SYMBOL_GPL(pnv_ocxl_spa_remove_pe_from_cache); 487 485

+2

arch/powerpc/platforms/powernv/opal-core.c

··· 348 348 if (!dn || ret) 349 349 pr_warn("WARNING: Failed to read OPAL base & entry values\n"); 350 350 351 + of_node_put(dn); 352 + 351 353 /* Use count to keep track of the program headers */ 352 354 count = 0; 353 355

+5 -1

arch/powerpc/platforms/powernv/opal-powercap.c

··· 153 153 pcaps = kcalloc(of_get_child_count(powercap), sizeof(*pcaps), 154 154 GFP_KERNEL); 155 155 if (!pcaps) 156 - return; 156 + goto out_put_powercap; 157 157 158 158 powercap_kobj = kobject_create_and_add("powercap", opal_kobj); 159 159 if (!powercap_kobj) { ··· 226 226 } 227 227 i++; 228 228 } 229 + of_node_put(powercap); 229 230 230 231 return; 231 232 ··· 237 236 kfree(pcaps[i].pg.name); 238 237 } 239 238 kobject_put(powercap_kobj); 239 + of_node_put(node); 240 240 out_pcaps: 241 241 kfree(pcaps); 242 + out_put_powercap: 243 + of_node_put(powercap); 242 244 }

+5 -1

arch/powerpc/platforms/powernv/opal-psr.c

··· 135 135 psr_attrs = kcalloc(of_get_child_count(psr), sizeof(*psr_attrs), 136 136 GFP_KERNEL); 137 137 if (!psr_attrs) 138 - return; 138 + goto out_put_psr; 139 139 140 140 psr_kobj = kobject_create_and_add("psr", opal_kobj); 141 141 if (!psr_kobj) { ··· 162 162 } 163 163 i++; 164 164 } 165 + of_node_put(psr); 165 166 166 167 return; 167 168 out_kobj: 169 + of_node_put(node); 168 170 kobject_put(psr_kobj); 169 171 out: 170 172 kfree(psr_attrs); 173 + out_put_psr: 174 + of_node_put(psr); 171 175 }

+5 -1

arch/powerpc/platforms/powernv/opal-sensor-groups.c

··· 170 170 171 171 sgs = kcalloc(of_get_child_count(sg), sizeof(*sgs), GFP_KERNEL); 172 172 if (!sgs) 173 - return; 173 + goto out_sg_put; 174 174 175 175 sg_kobj = kobject_create_and_add("sensor_groups", opal_kobj); 176 176 if (!sg_kobj) { ··· 222 222 } 223 223 i++; 224 224 } 225 + of_node_put(sg); 225 226 226 227 return; 227 228 ··· 232 231 kfree(sgs[i].sg.attrs); 233 232 } 234 233 kobject_put(sg_kobj); 234 + of_node_put(node); 235 235 out_sgs: 236 236 kfree(sgs); 237 + out_sg_put: 238 + of_node_put(sg); 237 239 }

+1 -1

arch/powerpc/platforms/powernv/opal-wrappers.S

··· 57 57 .long 0xa64b7b7d /* mthsrr1 r11 */ 58 58 .long 0x2402004c /* hrfid */ 59 59 #endif 60 - ld r2,PACATOC(r13) 60 + LOAD_PACA_TOC() 61 61 ld r0,PPC_LR_STKOFF(r1) 62 62 mtlr r0 63 63 blr

+3

arch/powerpc/platforms/powernv/opal.c

··· 892 892 kobj = kobject_create_and_add("exports", opal_kobj); 893 893 if (!kobj) { 894 894 pr_warn("kobject_create_and_add() of exports failed\n"); 895 + of_node_put(np); 895 896 return; 896 897 } 897 898 ··· 953 952 np = of_find_compatible_node(NULL, NULL, IMC_DTB_COMPAT); 954 953 if (np) 955 954 of_platform_device_create(np, NULL, NULL); 955 + 956 + of_node_put(np); 956 957 } 957 958 958 959 static int kopald(void *unused)

+1 -1

arch/powerpc/platforms/powernv/pci-ioda.c

··· 67 67 vaf.va = &args; 68 68 69 69 if (pe->flags & PNV_IODA_PE_DEV) 70 - strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 70 + strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 71 71 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) 72 72 sprintf(pfix, "%04x:%02x ", 73 73 pci_domain_nr(pe->pbus), pe->pbus->number);

+22

arch/powerpc/platforms/powernv/setup.c

··· 17 17 #include <linux/console.h> 18 18 #include <linux/delay.h> 19 19 #include <linux/irq.h> 20 + #include <linux/seq_buf.h> 20 21 #include <linux/seq_file.h> 21 22 #include <linux/of.h> 22 23 #include <linux/of_fdt.h> ··· 208 207 pnv_rng_init(); 209 208 } 210 209 210 + static void __init pnv_add_hw_description(void) 211 + { 212 + struct device_node *dn; 213 + const char *s; 214 + 215 + dn = of_find_node_by_path("/ibm,opal/firmware"); 216 + if (!dn) 217 + return; 218 + 219 + if (of_property_read_string(dn, "version", &s) == 0 || 220 + of_property_read_string(dn, "git-id", &s) == 0) 221 + seq_buf_printf(&ppc_hw_desc, "opal:%s ", s); 222 + 223 + if (of_property_read_string(dn, "mi-version", &s) == 0) 224 + seq_buf_printf(&ppc_hw_desc, "mi:%s ", s); 225 + 226 + of_node_put(dn); 227 + } 228 + 211 229 static void __init pnv_init(void) 212 230 { 231 + pnv_add_hw_description(); 232 + 213 233 /* 214 234 * Initialize the LPC bus now so that legacy serial 215 235 * ports can be found on it

+8

arch/powerpc/platforms/pseries/Kconfig

··· 23 23 select SWIOTLB 24 24 default y 25 25 26 + config PARAVIRT 27 + bool 28 + 26 29 config PARAVIRT_SPINLOCKS 30 + bool 31 + 32 + config PARAVIRT_TIME_ACCOUNTING 33 + select PARAVIRT 27 34 bool 28 35 29 36 config PPC_SPLPAR 30 37 bool "Support for shared-processor logical partitions" 31 38 depends on PPC_PSERIES 32 39 select PARAVIRT_SPINLOCKS if PPC_QUEUED_SPINLOCKS 40 + select PARAVIRT_TIME_ACCOUNTING if VIRT_CPU_ACCOUNTING_GEN 33 41 default y 34 42 help 35 43 Enabling this option will make the kernel run more efficiently

+81

arch/powerpc/platforms/pseries/dtl.c

··· 37 37 static int dtl_buf_entries = N_DISPATCH_LOG; 38 38 39 39 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 40 + 41 + /* 42 + * When CONFIG_VIRT_CPU_ACCOUNTING_NATIVE = y, the cpu accounting code controls 43 + * reading from the dispatch trace log. If other code wants to consume 44 + * DTL entries, it can set this pointer to a function that will get 45 + * called once for each DTL entry that gets processed. 46 + */ 47 + static void (*dtl_consumer)(struct dtl_entry *entry, u64 index); 48 + 40 49 struct dtl_ring { 41 50 u64 write_index; 42 51 struct dtl_entry *write_ptr; ··· 56 47 static DEFINE_PER_CPU(struct dtl_ring, dtl_rings); 57 48 58 49 static atomic_t dtl_count; 50 + 51 + /* 52 + * Scan the dispatch trace log and count up the stolen time. 53 + * Should be called with interrupts disabled. 54 + */ 55 + static notrace u64 scan_dispatch_log(u64 stop_tb) 56 + { 57 + u64 i = local_paca->dtl_ridx; 58 + struct dtl_entry *dtl = local_paca->dtl_curr; 59 + struct dtl_entry *dtl_end = local_paca->dispatch_log_end; 60 + struct lppaca *vpa = local_paca->lppaca_ptr; 61 + u64 tb_delta; 62 + u64 stolen = 0; 63 + u64 dtb; 64 + 65 + if (!dtl) 66 + return 0; 67 + 68 + if (i == be64_to_cpu(vpa->dtl_idx)) 69 + return 0; 70 + while (i < be64_to_cpu(vpa->dtl_idx)) { 71 + dtb = be64_to_cpu(dtl->timebase); 72 + tb_delta = be32_to_cpu(dtl->enqueue_to_dispatch_time) + 73 + be32_to_cpu(dtl->ready_to_enqueue_time); 74 + barrier(); 75 + if (i + N_DISPATCH_LOG < be64_to_cpu(vpa->dtl_idx)) { 76 + /* buffer has overflowed */ 77 + i = be64_to_cpu(vpa->dtl_idx) - N_DISPATCH_LOG; 78 + dtl = local_paca->dispatch_log + (i % N_DISPATCH_LOG); 79 + continue; 80 + } 81 + if (dtb > stop_tb) 82 + break; 83 + if (dtl_consumer) 84 + dtl_consumer(dtl, i); 85 + stolen += tb_delta; 86 + ++i; 87 + ++dtl; 88 + if (dtl == dtl_end) 89 + dtl = local_paca->dispatch_log; 90 + } 91 + local_paca->dtl_ridx = i; 92 + local_paca->dtl_curr = dtl; 93 + return stolen; 94 + } 95 + 96 + /* 97 + * Accumulate stolen time by scanning the dispatch trace log. 98 + * Called on entry from user mode. 99 + */ 100 + void notrace pseries_accumulate_stolen_time(void) 101 + { 102 + u64 sst, ust; 103 + struct cpu_accounting_data *acct = &local_paca->accounting; 104 + 105 + sst = scan_dispatch_log(acct->starttime_user); 106 + ust = scan_dispatch_log(acct->starttime); 107 + acct->stime -= sst; 108 + acct->utime -= ust; 109 + acct->steal_time += ust + sst; 110 + } 111 + 112 + u64 pseries_calculate_stolen_time(u64 stop_tb) 113 + { 114 + if (!firmware_has_feature(FW_FEATURE_SPLPAR)) 115 + return 0; 116 + 117 + if (get_paca()->dtl_ridx != be64_to_cpu(get_lppaca()->dtl_idx)) 118 + return scan_dispatch_log(stop_tb); 119 + 120 + return 0; 121 + } 59 122 60 123 /* 61 124 * The cpu accounting code controls the DTL ring buffer, and we get

+11 -4

arch/powerpc/platforms/pseries/hotplug-cpu.c

··· 619 619 static unsigned int pseries_cpuhp_cache_use_count(const struct device_node *cachedn) 620 620 { 621 621 unsigned int use_count = 0; 622 - struct device_node *dn; 622 + struct device_node *dn, *tn; 623 623 624 624 WARN_ON(!of_node_is_type(cachedn, "cache")); 625 625 626 626 for_each_of_cpu_node(dn) { 627 - if (of_find_next_cache_node(dn) == cachedn) 627 + tn = of_find_next_cache_node(dn); 628 + of_node_put(tn); 629 + if (tn == cachedn) 628 630 use_count++; 629 631 } 630 632 631 633 for_each_node_by_type(dn, "cache") { 632 - if (of_find_next_cache_node(dn) == cachedn) 634 + tn = of_find_next_cache_node(dn); 635 + of_node_put(tn); 636 + if (tn == cachedn) 633 637 use_count++; 634 638 } 635 639 ··· 653 649 654 650 dn = cpudn; 655 651 while ((dn = of_find_next_cache_node(dn))) { 656 - if (pseries_cpuhp_cache_use_count(dn) > 1) 652 + if (pseries_cpuhp_cache_use_count(dn) > 1) { 653 + of_node_put(dn); 657 654 break; 655 + } 658 656 659 657 ret = of_changeset_detach_node(&cs, dn); 658 + of_node_put(dn); 660 659 if (ret) 661 660 goto out; 662 661 }

+2 -2

arch/powerpc/platforms/pseries/hvCall.S

··· 16 16 #ifdef CONFIG_TRACEPOINTS 17 17 18 18 #ifndef CONFIG_JUMP_LABEL 19 - .section ".toc","aw" 19 + .data 20 20 21 21 .globl hcall_tracepoint_refcount 22 22 hcall_tracepoint_refcount: ··· 88 88 BEGIN_FTR_SECTION; \ 89 89 b 1f; \ 90 90 END_FTR_SECTION(0, 1); \ 91 - ld r12,hcall_tracepoint_refcount@toc(r2); \ 91 + LOAD_REG_ADDR(r12, hcall_tracepoint_refcount) ; \ 92 92 std r12,32(r1); \ 93 93 cmpdi r12,0; \ 94 94 bne- LABEL; \

+1 -1

arch/powerpc/platforms/pseries/hvcserver.c

··· 176 176 = (unsigned int)last_p_partition_ID; 177 177 178 178 /* copy the Null-term char too */ 179 - strlcpy(&next_partner_info->location_code[0], 179 + strscpy(&next_partner_info->location_code[0], 180 180 (char *)&pi_buff[2], 181 181 sizeof(next_partner_info->location_code)); 182 182

+5 -1

arch/powerpc/platforms/pseries/ibmebus.c

··· 152 152 static int ibmebus_match_path(struct device *dev, const void *data) 153 153 { 154 154 struct device_node *dn = to_platform_device(dev)->dev.of_node; 155 - return (of_find_node_by_path(data) == dn); 155 + struct device_node *tn = of_find_node_by_path(data); 156 + 157 + of_node_put(tn); 158 + 159 + return (tn == dn); 156 160 } 157 161 158 162 static int ibmebus_match_node(struct device *dev, const void *data)

+11

arch/powerpc/platforms/pseries/lpar.c

··· 660 660 } 661 661 662 662 machine_device_initcall(pseries, vcpudispatch_stats_procfs_init); 663 + 664 + #ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING 665 + u64 pseries_paravirt_steal_clock(int cpu) 666 + { 667 + struct lppaca *lppaca = &lppaca_of(cpu); 668 + 669 + return be64_to_cpu(READ_ONCE(lppaca->enqueue_dispatch_tb)) + 670 + be64_to_cpu(READ_ONCE(lppaca->ready_enqueue_tb)); 671 + } 672 + #endif 673 + 663 674 #endif /* CONFIG_PPC_SPLPAR */ 664 675 665 676 void vpa_init(int cpu)

+13 -4

arch/powerpc/platforms/pseries/mobility.c

··· 216 216 nprops = be32_to_cpu(upwa->nprops); 217 217 218 218 /* On the first call to ibm,update-properties for a node the 219 - * the first property value descriptor contains an empty 219 + * first property value descriptor contains an empty 220 220 * property name, the property value length encoded as u32, 221 221 * and the property value is the node path being updated. 222 222 */ ··· 740 740 #ifdef CONFIG_PPC_WATCHDOG 741 741 factor = nmi_wd_lpm_factor; 742 742 #endif 743 + /* 744 + * When the migration is initiated, the hypervisor changes VAS 745 + * mappings to prepare before OS gets the notification and 746 + * closes all VAS windows. NX generates continuous faults during 747 + * this time and the user space can not differentiate these 748 + * faults from the migration event. So reduce this time window 749 + * by closing VAS windows at the beginning of this function. 750 + */ 751 + vas_migration_handler(VAS_SUSPEND); 752 + 743 753 ret = wait_for_vasi_session_suspending(handle); 744 754 if (ret) 745 - return ret; 746 - 747 - vas_migration_handler(VAS_SUSPEND); 755 + goto out; 748 756 749 757 if (factor) 750 758 watchdog_nmi_set_timeout_pct(factor); ··· 773 765 if (factor) 774 766 watchdog_nmi_set_timeout_pct(0); 775 767 768 + out: 776 769 vas_migration_handler(VAS_RESUME); 777 770 778 771 return ret;

+5

arch/powerpc/platforms/pseries/reconfig.c

··· 10 10 #include <linux/kernel.h> 11 11 #include <linux/notifier.h> 12 12 #include <linux/proc_fs.h> 13 + #include <linux/security.h> 13 14 #include <linux/slab.h> 14 15 #include <linux/of.h> 15 16 ··· 361 360 int rv; 362 361 char *kbuf; 363 362 char *tmp; 363 + 364 + rv = security_locked_down(LOCKDOWN_DEVICE_TREE); 365 + if (rv) 366 + return rv; 364 367 365 368 kbuf = memdup_user_nul(buf, count); 366 369 if (IS_ERR(kbuf))

+49

arch/powerpc/platforms/pseries/setup.c

··· 41 41 #include <linux/of_pci.h> 42 42 #include <linux/memblock.h> 43 43 #include <linux/swiotlb.h> 44 + #include <linux/seq_buf.h> 44 45 45 46 #include <asm/mmu.h> 46 47 #include <asm/processor.h> ··· 80 79 81 80 DEFINE_STATIC_KEY_FALSE(shared_processor); 82 81 EXPORT_SYMBOL(shared_processor); 82 + 83 + #ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING 84 + struct static_key paravirt_steal_enabled; 85 + struct static_key paravirt_steal_rq_enabled; 86 + 87 + static bool steal_acc = true; 88 + static int __init parse_no_stealacc(char *arg) 89 + { 90 + steal_acc = false; 91 + return 0; 92 + } 93 + 94 + early_param("no-steal-acc", parse_no_stealacc); 95 + #endif 83 96 84 97 int CMO_PrPSP = -1; 85 98 int CMO_SecPSP = -1; ··· 849 834 if (lppaca_shared_proc(get_lppaca())) { 850 835 static_branch_enable(&shared_processor); 851 836 pv_spinlocks_init(); 837 + #ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING 838 + static_key_slow_inc(&paravirt_steal_enabled); 839 + if (steal_acc) 840 + static_key_slow_inc(&paravirt_steal_rq_enabled); 841 + #endif 852 842 } 853 843 854 844 ppc_md.power_save = pseries_lpar_idle; ··· 1012 992 pr_debug(" <- fw_cmo_feature_init()\n"); 1013 993 } 1014 994 995 + static void __init pseries_add_hw_description(void) 996 + { 997 + struct device_node *dn; 998 + const char *s; 999 + 1000 + dn = of_find_node_by_path("/openprom"); 1001 + if (dn) { 1002 + if (of_property_read_string(dn, "model", &s) == 0) 1003 + seq_buf_printf(&ppc_hw_desc, "of:%s ", s); 1004 + 1005 + of_node_put(dn); 1006 + } 1007 + 1008 + dn = of_find_node_by_path("/hypervisor"); 1009 + if (dn) { 1010 + if (of_property_read_string(dn, "compatible", &s) == 0) 1011 + seq_buf_printf(&ppc_hw_desc, "hv:%s ", s); 1012 + 1013 + of_node_put(dn); 1014 + return; 1015 + } 1016 + 1017 + if (of_property_read_bool(of_root, "ibm,powervm-partition") || 1018 + of_property_read_bool(of_root, "ibm,fw-net-version")) 1019 + seq_buf_printf(&ppc_hw_desc, "hv:phyp "); 1020 + } 1021 + 1015 1022 /* 1016 1023 * Early initialization. Relocation is on but do not reference unbolted pages 1017 1024 */ 1018 1025 static void __init pseries_init(void) 1019 1026 { 1020 1027 pr_debug(" -> pseries_init()\n"); 1028 + 1029 + pseries_add_hw_description(); 1021 1030 1022 1031 #ifdef CONFIG_HVC_CONSOLE 1023 1032 if (firmware_has_feature(FW_FEATURE_LPAR))

+2 -6

arch/powerpc/platforms/pseries/vas.c

··· 333 333 * So no unpacking needs to be done. 334 334 */ 335 335 rc = plpar_hcall9(H_HOME_NODE_ASSOCIATIVITY, domain, 336 - VPHN_FLAG_VCPU, smp_processor_id()); 336 + VPHN_FLAG_VCPU, hard_smp_processor_id()); 337 337 if (rc != H_SUCCESS) { 338 338 pr_err("H_HOME_NODE_ASSOCIATIVITY error: %d\n", rc); 339 339 goto out; ··· 501 501 int vas_register_api_pseries(struct module *mod, enum vas_cop_type cop_type, 502 502 const char *name) 503 503 { 504 - int rc; 505 - 506 504 if (!copypaste_feat) 507 505 return -ENOTSUPP; 508 506 509 - rc = vas_register_coproc_api(mod, cop_type, name, &vops_pseries); 510 - 511 - return rc; 507 + return vas_register_coproc_api(mod, cop_type, name, &vops_pseries); 512 508 } 513 509 EXPORT_SYMBOL_GPL(vas_register_api_pseries); 514 510

+2

arch/powerpc/sysdev/fsl_msi.c

··· 209 209 dev_err(&pdev->dev, 210 210 "node %pOF has an invalid fsl,msi phandle %u\n", 211 211 hose->dn, np->phandle); 212 + of_node_put(np); 212 213 return -EINVAL; 213 214 } 215 + of_node_put(np); 214 216 } 215 217 216 218 msi_for_each_desc(entry, &pdev->dev, MSI_DESC_NOTASSOCIATED) {

+6 -3

arch/powerpc/sysdev/fsl_pci.c

··· 181 181 static bool is_kdump(void) 182 182 { 183 183 struct device_node *node; 184 + bool ret; 184 185 185 186 node = of_find_node_by_type(NULL, "memory"); 186 187 if (!node) { ··· 189 188 return false; 190 189 } 191 190 192 - return of_property_read_bool(node, "linux,usable-memory"); 191 + ret = of_property_read_bool(node, "linux,usable-memory"); 192 + of_node_put(node); 193 + 194 + return ret; 193 195 } 194 196 195 197 /* atmu setup for fsl pci/pcie controller */ ··· 943 939 return 0; 944 940 } 945 941 946 - #ifdef CONFIG_E500 942 + #ifdef CONFIG_PPC_E500 947 943 static int mcheck_handle_load(struct pt_regs *regs, u32 inst) 948 944 { 949 945 unsigned int rd, ra, rb, d; ··· 1146 1142 for_each_matching_node(np, pci_ids) { 1147 1143 if (of_device_is_available(np)) { 1148 1144 fsl_pci_primary = np; 1149 - of_node_put(np); 1150 1145 return; 1151 1146 } 1152 1147 }

+1 -1

arch/powerpc/sysdev/fsl_rio.c

··· 98 98 struct fsl_rio_dbell *dbell; 99 99 struct fsl_rio_pw *pw; 100 100 101 - #ifdef CONFIG_E500 101 + #ifdef CONFIG_PPC_E500 102 102 int fsl_rio_mcheck_exception(struct pt_regs *regs) 103 103 { 104 104 const struct exception_table_entry *entry;

+8 -1

arch/powerpc/sysdev/mpic_msgr.c

··· 121 121 122 122 count += 1; 123 123 } 124 + of_node_put(aliases); 124 125 } 125 126 126 127 return count; ··· 145 144 146 145 for (index = 0; index < number_of_blocks; ++index) { 147 146 struct property *prop; 147 + struct device_node *tn; 148 148 149 149 snprintf(buf, sizeof(buf), "mpic-msgr-block%d", index); 150 150 prop = of_find_property(aliases, buf, NULL); 151 - if (node == of_find_node_by_path(prop->value)) 151 + tn = of_find_node_by_path(prop->value); 152 + if (node == tn) { 153 + of_node_put(tn); 152 154 break; 155 + } 156 + of_node_put(tn); 153 157 } 158 + of_node_put(aliases); 154 159 155 160 return index == number_of_blocks ? -1 : index; 156 161 }

+11 -11

arch/powerpc/sysdev/xics/ics-rtas.c

··· 36 36 37 37 server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0); 38 38 39 - call_status = rtas_call_reentrant(ibm_set_xive, 3, 1, NULL, hw_irq, 40 - server, DEFAULT_PRIORITY); 39 + call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hw_irq, server, 40 + DEFAULT_PRIORITY); 41 41 if (call_status != 0) { 42 42 printk(KERN_ERR 43 43 "%s: ibm_set_xive irq %u server %x returned %d\n", ··· 46 46 } 47 47 48 48 /* Now unmask the interrupt (often a no-op) */ 49 - call_status = rtas_call_reentrant(ibm_int_on, 1, 1, NULL, hw_irq); 49 + call_status = rtas_call(ibm_int_on, 1, 1, NULL, hw_irq); 50 50 if (call_status != 0) { 51 51 printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n", 52 52 __func__, hw_irq, call_status); ··· 68 68 if (hw_irq == XICS_IPI) 69 69 return; 70 70 71 - call_status = rtas_call_reentrant(ibm_int_off, 1, 1, NULL, hw_irq); 71 + call_status = rtas_call(ibm_int_off, 1, 1, NULL, hw_irq); 72 72 if (call_status != 0) { 73 73 printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", 74 74 __func__, hw_irq, call_status); ··· 76 76 } 77 77 78 78 /* Have to set XIVE to 0xff to be able to remove a slot */ 79 - call_status = rtas_call_reentrant(ibm_set_xive, 3, 1, NULL, hw_irq, 80 - xics_default_server, 0xff); 79 + call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hw_irq, 80 + xics_default_server, 0xff); 81 81 if (call_status != 0) { 82 82 printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", 83 83 __func__, hw_irq, call_status); ··· 108 108 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS) 109 109 return -1; 110 110 111 - status = rtas_call_reentrant(ibm_get_xive, 1, 3, xics_status, hw_irq); 111 + status = rtas_call(ibm_get_xive, 1, 3, xics_status, hw_irq); 112 112 113 113 if (status) { 114 114 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", ··· 126 126 pr_debug("%s: irq %d [hw 0x%x] server: 0x%x\n", __func__, d->irq, 127 127 hw_irq, irq_server); 128 128 129 - status = rtas_call_reentrant(ibm_set_xive, 3, 1, NULL, 130 - hw_irq, irq_server, xics_status[1]); 129 + status = rtas_call(ibm_set_xive, 3, 1, NULL, 130 + hw_irq, irq_server, xics_status[1]); 131 131 132 132 if (status) { 133 133 printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", ··· 158 158 return -EINVAL; 159 159 160 160 /* Check if RTAS knows about this interrupt */ 161 - rc = rtas_call_reentrant(ibm_get_xive, 1, 3, status, hw_irq); 161 + rc = rtas_call(ibm_get_xive, 1, 3, status, hw_irq); 162 162 if (rc) 163 163 return -ENXIO; 164 164 ··· 174 174 { 175 175 int rc, status[2]; 176 176 177 - rc = rtas_call_reentrant(ibm_get_xive, 1, 3, status, vec); 177 + rc = rtas_call(ibm_get_xive, 1, 3, status, vec); 178 178 if (rc) 179 179 return -1; 180 180 return status[0];

+1 -1

arch/powerpc/sysdev/xive/common.c

··· 783 783 * the corresponding descriptor bits mind you but those will in turn 784 784 * affect the resend function when re-enabling an edge interrupt. 785 785 * 786 - * Set set the default to edge as explained in map(). 786 + * Set the default to edge as explained in map(). 787 787 */ 788 788 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE) 789 789 flow_type = IRQ_TYPE_EDGE_RISING;

+10 -5

arch/powerpc/sysdev/xive/native.c

··· 579 579 /* Resource 1 is HV window */ 580 580 if (of_address_to_resource(np, 1, &r)) { 581 581 pr_err("Failed to get thread mgmnt area resource\n"); 582 - return false; 582 + goto err_put; 583 583 } 584 584 tima = ioremap(r.start, resource_size(&r)); 585 585 if (!tima) { 586 586 pr_err("Failed to map thread mgmnt area\n"); 587 - return false; 587 + goto err_put; 588 588 } 589 589 590 590 /* Read number of priorities */ ··· 612 612 /* Resource 2 is OS window */ 613 613 if (of_address_to_resource(np, 2, &r)) { 614 614 pr_err("Failed to get thread mgmnt area resource\n"); 615 - return false; 615 + goto err_put; 616 616 } 617 617 618 618 xive_tima_os = r.start; ··· 624 624 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL); 625 625 if (rc) { 626 626 pr_err("Switch to exploitation mode failed with error %lld\n", rc); 627 - return false; 627 + goto err_put; 628 628 } 629 629 630 630 /* Setup some dummy HV pool VPs */ ··· 634 634 if (!xive_core_init(np, &xive_native_ops, tima, TM_QW3_HV_PHYS, 635 635 max_prio)) { 636 636 opal_xive_reset(OPAL_XIVE_MODE_EMU); 637 - return false; 637 + goto err_put; 638 638 } 639 + of_node_put(np); 639 640 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); 640 641 return true; 642 + 643 + err_put: 644 + of_node_put(np); 645 + return false; 641 646 } 642 647 643 648 static bool xive_native_provision_pages(void)

-2

arch/powerpc/xmon/ppc.h

··· 435 435 extern const struct powerpc_macro powerpc_macros[]; 436 436 extern const int powerpc_num_macros; 437 437 438 - extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); 439 - 440 438 static inline long 441 439 ppc_optional_operand_value (const struct powerpc_operand *operand) 442 440 {

+2 -2

arch/powerpc/xmon/spr_access.S

··· 4 4 5 5 /* unsigned long xmon_mfspr(sprn, default_value) */ 6 6 _GLOBAL(xmon_mfspr) 7 - PPC_LL r5, .Lmfspr_table@got(r2) 7 + LOAD_REG_ADDR(r5, .Lmfspr_table) 8 8 b xmon_mxspr 9 9 10 10 /* void xmon_mtspr(sprn, new_value) */ 11 11 _GLOBAL(xmon_mtspr) 12 - PPC_LL r5, .Lmtspr_table@got(r2) 12 + LOAD_REG_ADDR(r5, .Lmtspr_table) 13 13 b xmon_mxspr 14 14 15 15 /*

+8 -8

arch/powerpc/xmon/xmon.c

··· 195 195 #ifdef CONFIG_44x 196 196 static void dump_tlb_44x(void); 197 197 #endif 198 - #ifdef CONFIG_PPC_BOOK3E 198 + #ifdef CONFIG_PPC_BOOK3E_64 199 199 static void dump_tlb_book3e(void); 200 200 #endif 201 201 ··· 288 288 t print backtrace\n\ 289 289 x exit monitor and recover\n\ 290 290 X exit monitor and don't recover\n" 291 - #if defined(CONFIG_PPC64) && !defined(CONFIG_PPC_BOOK3E) 291 + #if defined(CONFIG_PPC_BOOK3S_64) 292 292 " u dump segment table or SLB\n" 293 293 #elif defined(CONFIG_PPC_BOOK3S_32) 294 294 " u dump segment registers\n" 295 - #elif defined(CONFIG_44x) || defined(CONFIG_PPC_BOOK3E) 295 + #elif defined(CONFIG_44x) || defined(CONFIG_PPC_BOOK3E_64) 296 296 " u dump TLB\n" 297 297 #endif 298 298 " U show uptime information\n" ··· 1166 1166 case 'u': 1167 1167 dump_tlb_44x(); 1168 1168 break; 1169 - #elif defined(CONFIG_PPC_BOOK3E) 1169 + #elif defined(CONFIG_PPC_BOOK3E_64) 1170 1170 case 'u': 1171 1171 dump_tlb_book3e(); 1172 1172 break; ··· 2686 2686 DUMP(p, rfi_flush_fallback_area, "%-*px"); 2687 2687 #endif 2688 2688 DUMP(p, dscr_default, "%#-*llx"); 2689 - #ifdef CONFIG_PPC_BOOK3E 2689 + #ifdef CONFIG_PPC_BOOK3E_64 2690 2690 DUMP(p, pgd, "%-*px"); 2691 2691 DUMP(p, kernel_pgd, "%-*px"); 2692 2692 DUMP(p, tcd_ptr, "%-*px"); ··· 2701 2701 DUMP(p, canary, "%#-*lx"); 2702 2702 #endif 2703 2703 DUMP(p, saved_r1, "%#-*llx"); 2704 - #ifdef CONFIG_PPC_BOOK3E 2704 + #ifdef CONFIG_PPC_BOOK3E_64 2705 2705 DUMP(p, trap_save, "%#-*x"); 2706 2706 #endif 2707 2707 DUMP(p, irq_soft_mask, "%#-*x"); ··· 3823 3823 } 3824 3824 #endif /* CONFIG_44x */ 3825 3825 3826 - #ifdef CONFIG_PPC_BOOK3E 3826 + #ifdef CONFIG_PPC_BOOK3E_64 3827 3827 static void dump_tlb_book3e(void) 3828 3828 { 3829 3829 u32 mmucfg, pidmask, lpidmask; ··· 3965 3965 } 3966 3966 } 3967 3967 } 3968 - #endif /* CONFIG_PPC_BOOK3E */ 3968 + #endif /* CONFIG_PPC_BOOK3E_64 */ 3969 3969 3970 3970 static void xmon_init(int enable) 3971 3971 {

+4 -2

drivers/macintosh/therm_windtunnel.c

··· 317 317 if (x.running || strncmp(adapter->name, "uni-n", 5)) 318 318 return; 319 319 320 + of_node_get(adapter->dev.of_node); 320 321 np = of_find_compatible_node(adapter->dev.of_node, NULL, "MAC,ds1775"); 321 322 if (np) { 322 323 of_node_put(np); 323 324 } else { 324 - strlcpy(info.type, "MAC,ds1775", I2C_NAME_SIZE); 325 + strscpy(info.type, "MAC,ds1775", I2C_NAME_SIZE); 325 326 i2c_new_scanned_device(adapter, &info, scan_ds1775, NULL); 326 327 } 327 328 329 + of_node_get(adapter->dev.of_node); 328 330 np = of_find_compatible_node(adapter->dev.of_node, NULL, "MAC,adm1030"); 329 331 if (np) { 330 332 of_node_put(np); 331 333 } else { 332 - strlcpy(info.type, "MAC,adm1030", I2C_NAME_SIZE); 334 + strscpy(info.type, "MAC,adm1030", I2C_NAME_SIZE); 333 335 i2c_new_scanned_device(adapter, &info, scan_adm1030, NULL); 334 336 } 335 337 }

+4 -4

drivers/watchdog/Kconfig

··· 1935 1935 config BOOKE_WDT_DEFAULT_TIMEOUT 1936 1936 int "PowerPC Book-E Watchdog Timer Default Timeout" 1937 1937 depends on BOOKE_WDT 1938 - default 38 if PPC_FSL_BOOK3E 1939 - range 0 63 if PPC_FSL_BOOK3E 1940 - default 3 if !PPC_FSL_BOOK3E 1941 - range 0 3 if !PPC_FSL_BOOK3E 1938 + default 38 if PPC_E500 1939 + range 0 63 if PPC_E500 1940 + default 3 if !PPC_E500 1941 + range 0 3 if !PPC_E500 1942 1942 help 1943 1943 Select the default watchdog timer period to be used by the PowerPC 1944 1944 Book-E watchdog driver. A watchdog "event" occurs when the bit

+4 -4

drivers/watchdog/booke_wdt.c

··· 27 27 */ 28 28 29 29 30 - #ifdef CONFIG_PPC_FSL_BOOK3E 30 + #ifdef CONFIG_PPC_E500 31 31 #define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15)) 32 32 #define WDTP_MASK (WDTP(0x3f)) 33 33 #else ··· 45 45 "Watchdog cannot be stopped once started (default=" 46 46 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 47 47 48 - #ifdef CONFIG_PPC_FSL_BOOK3E 48 + #ifdef CONFIG_PPC_E500 49 49 50 50 /* For the specified period, determine the number of seconds 51 51 * corresponding to the reset time. There will be a watchdog ··· 88 88 89 89 #define MAX_WDT_TIMEOUT period_to_sec(1) 90 90 91 - #else /* CONFIG_PPC_FSL_BOOK3E */ 91 + #else /* CONFIG_PPC_E500 */ 92 92 93 93 static unsigned long long period_to_sec(unsigned int period) 94 94 { ··· 102 102 103 103 #define MAX_WDT_TIMEOUT 3 /* from Kconfig */ 104 104 105 - #endif /* !CONFIG_PPC_FSL_BOOK3E */ 105 + #endif /* !CONFIG_PPC_E500 */ 106 106 107 107 static void __booke_wdt_set(void *data) 108 108 {

+7 -2

include/asm-generic/compat.h

··· 14 14 #define COMPAT_OFF_T_MAX 0x7fffffff 15 15 #endif 16 16 17 - #if !defined(compat_arg_u64) && !defined(CONFIG_CPU_BIG_ENDIAN) 17 + #ifndef compat_arg_u64 18 + #ifdef CONFIG_CPU_BIG_ENDIAN 18 19 #define compat_arg_u64(name) u32 name##_lo, u32 name##_hi 19 20 #define compat_arg_u64_dual(name) u32, name##_lo, u32, name##_hi 21 + #else 22 + #define compat_arg_u64(name) u32 name##_hi, u32 name##_lo 23 + #define compat_arg_u64_dual(name) u32, name##_hi, u32, name##_lo 24 + #endif 20 25 #define compat_arg_u64_glue(name) (((u64)name##_lo & 0xffffffffUL) | \ 21 26 ((u64)name##_hi << 32)) 22 - #endif 27 + #endif /* compat_arg_u64 */ 23 28 24 29 /* These types are common across all compat ABIs */ 25 30 typedef u32 compat_size_t;

+1 -1

include/linux/hugetlb.h

··· 17 17 struct user_struct; 18 18 struct mmu_gather; 19 19 20 - #ifndef is_hugepd 20 + #ifndef CONFIG_ARCH_HAS_HUGEPD 21 21 typedef struct { unsigned long pd; } hugepd_t; 22 22 #define is_hugepd(hugepd) (0) 23 23 #define __hugepd(x) ((hugepd_t) { (x) })

+2

include/linux/security.h

··· 114 114 LOCKDOWN_IOPORT, 115 115 LOCKDOWN_MSR, 116 116 LOCKDOWN_ACPI_TABLES, 117 + LOCKDOWN_DEVICE_TREE, 117 118 LOCKDOWN_PCMCIA_CIS, 118 119 LOCKDOWN_TIOCSSERIAL, 119 120 LOCKDOWN_MODULE_PARAMETERS, ··· 123 122 LOCKDOWN_XMON_WR, 124 123 LOCKDOWN_BPF_WRITE_USER, 125 124 LOCKDOWN_DBG_WRITE_KERNEL, 125 + LOCKDOWN_RTAS_ERROR_INJECTION, 126 126 LOCKDOWN_INTEGRITY_MAX, 127 127 LOCKDOWN_KCORE, 128 128 LOCKDOWN_KPROBES,

+3

include/math-emu/op-common.h

··· 662 662 if (X##_e < 0) \ 663 663 { \ 664 664 FP_SET_EXCEPTION(FP_EX_INEXACT); \ 665 + fallthrough; \ 665 666 case FP_CLS_ZERO: \ 666 667 r = 0; \ 667 668 } \ 668 669 else if (X##_e >= rsize - (rsigned > 0 || X##_s) \ 669 670 || (!rsigned && X##_s)) \ 670 671 { /* overflow */ \ 672 + fallthrough; \ 671 673 case FP_CLS_NAN: \ 672 674 case FP_CLS_INF: \ 673 675 if (rsigned == 2) \ ··· 769 767 if (X##_e >= rsize - (rsigned > 0 || X##_s) \ 770 768 || (!rsigned && X##_s)) \ 771 769 { /* overflow */ \ 770 + fallthrough; \ 772 771 case FP_CLS_NAN: \ 773 772 case FP_CLS_INF: \ 774 773 if (!rsigned) \

+1 -2

init/Kconfig

··· 473 473 474 474 choice 475 475 prompt "Cputime accounting" 476 - default TICK_CPU_ACCOUNTING if !PPC64 477 - default VIRT_CPU_ACCOUNTING_NATIVE if PPC64 476 + default TICK_CPU_ACCOUNTING 478 477 479 478 # Kind of a stub config for the pure tick based cputime accounting 480 479 config TICK_CPU_ACCOUNTING

+2

security/security.c

··· 52 52 [LOCKDOWN_IOPORT] = "raw io port access", 53 53 [LOCKDOWN_MSR] = "raw MSR access", 54 54 [LOCKDOWN_ACPI_TABLES] = "modifying ACPI tables", 55 + [LOCKDOWN_DEVICE_TREE] = "modifying device tree contents", 55 56 [LOCKDOWN_PCMCIA_CIS] = "direct PCMCIA CIS storage", 56 57 [LOCKDOWN_TIOCSSERIAL] = "reconfiguration of serial port IO", 57 58 [LOCKDOWN_MODULE_PARAMETERS] = "unsafe module parameters", ··· 61 60 [LOCKDOWN_XMON_WR] = "xmon write access", 62 61 [LOCKDOWN_BPF_WRITE_USER] = "use of bpf to write user RAM", 63 62 [LOCKDOWN_DBG_WRITE_KERNEL] = "use of kgdb/kdb to write kernel RAM", 63 + [LOCKDOWN_RTAS_ERROR_INJECTION] = "RTAS error injection", 64 64 [LOCKDOWN_INTEGRITY_MAX] = "integrity", 65 65 [LOCKDOWN_KCORE] = "/proc/kcore access", 66 66 [LOCKDOWN_KPROBES] = "use of kprobes",

+12 -12

tools/perf/arch/powerpc/entry/syscalls/syscall.tbl

··· 110 110 79 common settimeofday sys_settimeofday compat_sys_settimeofday 111 111 80 common getgroups sys_getgroups 112 112 81 common setgroups sys_setgroups 113 - 82 32 select ppc_select sys_ni_syscall 113 + 82 32 select sys_old_select compat_sys_old_select 114 114 82 64 select sys_ni_syscall 115 115 82 spu select sys_ni_syscall 116 116 83 common symlink sys_symlink ··· 178 178 133 common fchdir sys_fchdir 179 179 134 common bdflush sys_ni_syscall 180 180 135 common sysfs sys_sysfs 181 - 136 32 personality sys_personality ppc64_personality 182 - 136 64 personality ppc64_personality 183 - 136 spu personality ppc64_personality 181 + 136 32 personality sys_personality compat_sys_ppc64_personality 182 + 136 64 personality sys_ppc64_personality 183 + 136 spu personality sys_ppc64_personality 184 184 137 common afs_syscall sys_ni_syscall 185 185 138 common setfsuid sys_setfsuid 186 186 139 common setfsgid sys_setfsgid ··· 228 228 176 64 rt_sigtimedwait sys_rt_sigtimedwait 229 229 177 nospu rt_sigqueueinfo sys_rt_sigqueueinfo compat_sys_rt_sigqueueinfo 230 230 178 nospu rt_sigsuspend sys_rt_sigsuspend compat_sys_rt_sigsuspend 231 - 179 common pread64 sys_pread64 compat_sys_pread64 232 - 180 common pwrite64 sys_pwrite64 compat_sys_pwrite64 231 + 179 common pread64 sys_pread64 compat_sys_ppc_pread64 232 + 180 common pwrite64 sys_pwrite64 compat_sys_ppc_pwrite64 233 233 181 common chown sys_chown 234 234 182 common getcwd sys_getcwd 235 235 183 common capget sys_capget ··· 242 242 188 common putpmsg sys_ni_syscall 243 243 189 nospu vfork sys_vfork 244 244 190 common ugetrlimit sys_getrlimit compat_sys_getrlimit 245 - 191 common readahead sys_readahead compat_sys_readahead 245 + 191 common readahead sys_readahead compat_sys_ppc_readahead 246 246 192 32 mmap2 sys_mmap2 compat_sys_mmap2 247 - 193 32 truncate64 sys_truncate64 compat_sys_truncate64 248 - 194 32 ftruncate64 sys_ftruncate64 compat_sys_ftruncate64 247 + 193 32 truncate64 sys_truncate64 compat_sys_ppc_truncate64 248 + 194 32 ftruncate64 sys_ftruncate64 compat_sys_ppc_ftruncate64 249 249 195 32 stat64 sys_stat64 250 250 196 32 lstat64 sys_lstat64 251 251 197 32 fstat64 sys_fstat64 ··· 288 288 230 common io_submit sys_io_submit compat_sys_io_submit 289 289 231 common io_cancel sys_io_cancel 290 290 232 nospu set_tid_address sys_set_tid_address 291 - 233 common fadvise64 sys_fadvise64 ppc32_fadvise64 291 + 233 common fadvise64 sys_fadvise64 compat_sys_ppc32_fadvise64 292 292 234 nospu exit_group sys_exit_group 293 293 235 nospu lookup_dcookie sys_lookup_dcookie compat_sys_lookup_dcookie 294 294 236 common epoll_create sys_epoll_create ··· 323 323 251 spu utimes sys_utimes 324 324 252 common statfs64 sys_statfs64 compat_sys_statfs64 325 325 253 common fstatfs64 sys_fstatfs64 compat_sys_fstatfs64 326 - 254 32 fadvise64_64 ppc_fadvise64_64 326 + 254 32 fadvise64_64 sys_ppc_fadvise64_64 327 327 254 spu fadvise64_64 sys_ni_syscall 328 328 255 common rtas sys_rtas 329 329 256 32 sys_debug_setcontext sys_debug_setcontext sys_ni_syscall ··· 390 390 305 common signalfd sys_signalfd compat_sys_signalfd 391 391 306 common timerfd_create sys_timerfd_create 392 392 307 common eventfd sys_eventfd 393 - 308 common sync_file_range2 sys_sync_file_range2 compat_sys_sync_file_range2 393 + 308 common sync_file_range2 sys_sync_file_range2 compat_sys_ppc_sync_file_range2 394 394 309 nospu fallocate sys_fallocate compat_sys_fallocate 395 395 310 nospu subpage_prot sys_subpage_prot 396 396 311 32 timerfd_settime sys_timerfd_settime32

+4 -2

tools/testing/selftests/powerpc/benchmarks/gettimeofday.c

··· 12 12 { 13 13 int i; 14 14 15 - struct timeval tv_start, tv_end; 15 + struct timeval tv_start, tv_end, tv_diff; 16 16 17 17 gettimeofday(&tv_start, NULL); 18 18 ··· 20 20 gettimeofday(&tv_end, NULL); 21 21 } 22 22 23 - printf("time = %.6f\n", tv_end.tv_sec - tv_start.tv_sec + (tv_end.tv_usec - tv_start.tv_usec) * 1e-6); 23 + timersub(&tv_start, &tv_end, &tv_diff); 24 + 25 + printf("time = %.6f\n", tv_diff.tv_sec + (tv_diff.tv_usec) * 1e-6); 24 26 25 27 return 0; 26 28 }

+2 -1

tools/testing/selftests/powerpc/mm/Makefile

··· 3 3 $(MAKE) -C ../ 4 4 5 5 TEST_GEN_PROGS := hugetlb_vs_thp_test subpage_prot prot_sao segv_errors wild_bctr \ 6 - large_vm_fork_separation bad_accesses pkey_exec_prot \ 6 + large_vm_fork_separation bad_accesses exec_prot pkey_exec_prot \ 7 7 pkey_siginfo stack_expansion_signal stack_expansion_ldst \ 8 8 large_vm_gpr_corruption 9 9 TEST_PROGS := stress_code_patching.sh ··· 22 22 $(OUTPUT)/large_vm_fork_separation: CFLAGS += -m64 23 23 $(OUTPUT)/large_vm_gpr_corruption: CFLAGS += -m64 24 24 $(OUTPUT)/bad_accesses: CFLAGS += -m64 25 + $(OUTPUT)/exec_prot: CFLAGS += -m64 25 26 $(OUTPUT)/pkey_exec_prot: CFLAGS += -m64 26 27 $(OUTPUT)/pkey_siginfo: CFLAGS += -m64 27 28

+231

tools/testing/selftests/powerpc/mm/exec_prot.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + /* 4 + * Copyright 2022, Nicholas Miehlbradt, IBM Corporation 5 + * based on pkey_exec_prot.c 6 + * 7 + * Test if applying execute protection on pages works as expected. 8 + */ 9 + 10 + #define _GNU_SOURCE 11 + #include <stdio.h> 12 + #include <stdlib.h> 13 + #include <string.h> 14 + #include <signal.h> 15 + 16 + #include <unistd.h> 17 + #include <sys/mman.h> 18 + 19 + #include "pkeys.h" 20 + 21 + 22 + #define PPC_INST_NOP 0x60000000 23 + #define PPC_INST_TRAP 0x7fe00008 24 + #define PPC_INST_BLR 0x4e800020 25 + 26 + static volatile sig_atomic_t fault_code; 27 + static volatile sig_atomic_t remaining_faults; 28 + static volatile unsigned int *fault_addr; 29 + static unsigned long pgsize, numinsns; 30 + static unsigned int *insns; 31 + static bool pkeys_supported; 32 + 33 + static bool is_fault_expected(int fault_code) 34 + { 35 + if (fault_code == SEGV_ACCERR) 36 + return true; 37 + 38 + /* Assume any pkey error is fine since pkey_exec_prot test covers them */ 39 + if (fault_code == SEGV_PKUERR && pkeys_supported) 40 + return true; 41 + 42 + return false; 43 + } 44 + 45 + static void trap_handler(int signum, siginfo_t *sinfo, void *ctx) 46 + { 47 + /* Check if this fault originated from the expected address */ 48 + if (sinfo->si_addr != (void *)fault_addr) 49 + sigsafe_err("got a fault for an unexpected address\n"); 50 + 51 + _exit(1); 52 + } 53 + 54 + static void segv_handler(int signum, siginfo_t *sinfo, void *ctx) 55 + { 56 + fault_code = sinfo->si_code; 57 + 58 + /* Check if this fault originated from the expected address */ 59 + if (sinfo->si_addr != (void *)fault_addr) { 60 + sigsafe_err("got a fault for an unexpected address\n"); 61 + _exit(1); 62 + } 63 + 64 + /* Check if too many faults have occurred for a single test case */ 65 + if (!remaining_faults) { 66 + sigsafe_err("got too many faults for the same address\n"); 67 + _exit(1); 68 + } 69 + 70 + 71 + /* Restore permissions in order to continue */ 72 + if (is_fault_expected(fault_code)) { 73 + if (mprotect(insns, pgsize, PROT_READ | PROT_WRITE | PROT_EXEC)) { 74 + sigsafe_err("failed to set access permissions\n"); 75 + _exit(1); 76 + } 77 + } else { 78 + sigsafe_err("got a fault with an unexpected code\n"); 79 + _exit(1); 80 + } 81 + 82 + remaining_faults--; 83 + } 84 + 85 + static int check_exec_fault(int rights) 86 + { 87 + /* 88 + * Jump to the executable region. 89 + * 90 + * The first iteration also checks if the overwrite of the 91 + * first instruction word from a trap to a no-op succeeded. 92 + */ 93 + fault_code = -1; 94 + remaining_faults = 0; 95 + if (!(rights & PROT_EXEC)) 96 + remaining_faults = 1; 97 + 98 + FAIL_IF(mprotect(insns, pgsize, rights) != 0); 99 + asm volatile("mtctr %0; bctrl" : : "r"(insns)); 100 + 101 + FAIL_IF(remaining_faults != 0); 102 + if (!(rights & PROT_EXEC)) 103 + FAIL_IF(!is_fault_expected(fault_code)); 104 + 105 + return 0; 106 + } 107 + 108 + static int test(void) 109 + { 110 + struct sigaction segv_act, trap_act; 111 + int i; 112 + 113 + /* Skip the test if the CPU doesn't support Radix */ 114 + SKIP_IF(!have_hwcap2(PPC_FEATURE2_ARCH_3_00)); 115 + 116 + /* Check if pkeys are supported */ 117 + pkeys_supported = pkeys_unsupported() == 0; 118 + 119 + /* Setup SIGSEGV handler */ 120 + segv_act.sa_handler = 0; 121 + segv_act.sa_sigaction = segv_handler; 122 + FAIL_IF(sigprocmask(SIG_SETMASK, 0, &segv_act.sa_mask) != 0); 123 + segv_act.sa_flags = SA_SIGINFO; 124 + segv_act.sa_restorer = 0; 125 + FAIL_IF(sigaction(SIGSEGV, &segv_act, NULL) != 0); 126 + 127 + /* Setup SIGTRAP handler */ 128 + trap_act.sa_handler = 0; 129 + trap_act.sa_sigaction = trap_handler; 130 + FAIL_IF(sigprocmask(SIG_SETMASK, 0, &trap_act.sa_mask) != 0); 131 + trap_act.sa_flags = SA_SIGINFO; 132 + trap_act.sa_restorer = 0; 133 + FAIL_IF(sigaction(SIGTRAP, &trap_act, NULL) != 0); 134 + 135 + /* Setup executable region */ 136 + pgsize = getpagesize(); 137 + numinsns = pgsize / sizeof(unsigned int); 138 + insns = (unsigned int *)mmap(NULL, pgsize, PROT_READ | PROT_WRITE, 139 + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 140 + FAIL_IF(insns == MAP_FAILED); 141 + 142 + /* Write the instruction words */ 143 + for (i = 1; i < numinsns - 1; i++) 144 + insns[i] = PPC_INST_NOP; 145 + 146 + /* 147 + * Set the first instruction as an unconditional trap. If 148 + * the last write to this address succeeds, this should 149 + * get overwritten by a no-op. 150 + */ 151 + insns[0] = PPC_INST_TRAP; 152 + 153 + /* 154 + * Later, to jump to the executable region, we use a branch 155 + * and link instruction (bctrl) which sets the return address 156 + * automatically in LR. Use that to return back. 157 + */ 158 + insns[numinsns - 1] = PPC_INST_BLR; 159 + 160 + /* 161 + * Pick the first instruction's address from the executable 162 + * region. 163 + */ 164 + fault_addr = insns; 165 + 166 + /* 167 + * Read an instruction word from the address when the page 168 + * is execute only. This should generate an access fault. 169 + */ 170 + fault_code = -1; 171 + remaining_faults = 1; 172 + printf("Testing read on --x, should fault..."); 173 + FAIL_IF(mprotect(insns, pgsize, PROT_EXEC) != 0); 174 + i = *fault_addr; 175 + FAIL_IF(remaining_faults != 0 || !is_fault_expected(fault_code)); 176 + printf("ok!\n"); 177 + 178 + /* 179 + * Write an instruction word to the address when the page 180 + * execute only. This should also generate an access fault. 181 + */ 182 + fault_code = -1; 183 + remaining_faults = 1; 184 + printf("Testing write on --x, should fault..."); 185 + FAIL_IF(mprotect(insns, pgsize, PROT_EXEC) != 0); 186 + *fault_addr = PPC_INST_NOP; 187 + FAIL_IF(remaining_faults != 0 || !is_fault_expected(fault_code)); 188 + printf("ok!\n"); 189 + 190 + printf("Testing exec on ---, should fault..."); 191 + FAIL_IF(check_exec_fault(PROT_NONE)); 192 + printf("ok!\n"); 193 + 194 + printf("Testing exec on r--, should fault..."); 195 + FAIL_IF(check_exec_fault(PROT_READ)); 196 + printf("ok!\n"); 197 + 198 + printf("Testing exec on -w-, should fault..."); 199 + FAIL_IF(check_exec_fault(PROT_WRITE)); 200 + printf("ok!\n"); 201 + 202 + printf("Testing exec on rw-, should fault..."); 203 + FAIL_IF(check_exec_fault(PROT_READ | PROT_WRITE)); 204 + printf("ok!\n"); 205 + 206 + printf("Testing exec on --x, should succeed..."); 207 + FAIL_IF(check_exec_fault(PROT_EXEC)); 208 + printf("ok!\n"); 209 + 210 + printf("Testing exec on r-x, should succeed..."); 211 + FAIL_IF(check_exec_fault(PROT_READ | PROT_EXEC)); 212 + printf("ok!\n"); 213 + 214 + printf("Testing exec on -wx, should succeed..."); 215 + FAIL_IF(check_exec_fault(PROT_WRITE | PROT_EXEC)); 216 + printf("ok!\n"); 217 + 218 + printf("Testing exec on rwx, should succeed..."); 219 + FAIL_IF(check_exec_fault(PROT_READ | PROT_WRITE | PROT_EXEC)); 220 + printf("ok!\n"); 221 + 222 + /* Cleanup */ 223 + FAIL_IF(munmap((void *)insns, pgsize)); 224 + 225 + return 0; 226 + } 227 + 228 + int main(void) 229 + { 230 + return test_harness(test, "exec_prot"); 231 + }

+2

tools/testing/selftests/powerpc/mm/large_vm_gpr_corruption.c

··· 112 112 // This tests a hash MMU specific bug. 113 113 FAIL_IF(using_hash_mmu(&hash_mmu)); 114 114 SKIP_IF(!hash_mmu); 115 + // 4K kernels don't support 4PB address space 116 + SKIP_IF(sysconf(_SC_PAGESIZE) < 65536); 115 117 116 118 page_size = sysconf(_SC_PAGESIZE); 117 119

+9

tools/testing/selftests/powerpc/pmu/sampling_tests/bhrb_filter_map_test.c

··· 96 96 } 97 97 } 98 98 99 + /* 100 + * Combine filter maps which includes a valid branch filter and an invalid branch 101 + * filter. Example: any ( PERF_SAMPLE_BRANCH_ANY) and any_call 102 + * (PERF_SAMPLE_BRANCH_ANY_CALL). 103 + * The perf_event_open should fail in this case. 104 + */ 105 + event.attr.branch_sample_type = PERF_SAMPLE_BRANCH_ANY | PERF_SAMPLE_BRANCH_ANY_CALL; 106 + FAIL_IF(!event_open(&event)); 107 + 99 108 return 0; 100 109 } 101 110

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