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PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window

On RK3588 PCIe3_4L in EP mode, the integrated DMA controller registers
are permanently mapped to BAR4 and must not be repurposed by EPF
drivers.

When the remote peer needs to access these registers, it must use the
fixed BAR4 window instead of creating another inbound mapping in a
different BAR. Mixing the fixed window with an additional mapping can
lead to incorrect behavior.

Advertise the DMA controller MMIO window as a reserved BAR subregion so
EPF drivers can reuse it safely.

Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Koichiro Den <den@valinux.co.jp>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260312130229.2282001-16-cassel@kernel.org

authored by

Koichiro Den and committed by
Manivannan Sadhasivam 489d3abb f51644eb

+14 -1
+14 -1
drivers/pci/controller/dwc/pcie-dw-rockchip.c
··· 403 403 .bar[BAR_5] = { .type = BAR_RESIZABLE, }, 404 404 }; 405 405 406 + static const struct pci_epc_bar_rsvd_region rk3588_bar4_rsvd[] = { 407 + { 408 + /* DMA_CAP (BAR4: DMA Port Logic Structure) */ 409 + .type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO, 410 + .offset = 0x0, 411 + .size = 0x2000, 412 + }, 413 + }; 414 + 406 415 /* 407 416 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of 408 417 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver, ··· 429 420 .bar[BAR_1] = { .type = BAR_RESIZABLE, }, 430 421 .bar[BAR_2] = { .type = BAR_RESIZABLE, }, 431 422 .bar[BAR_3] = { .type = BAR_RESIZABLE, }, 432 - .bar[BAR_4] = { .type = BAR_RESERVED, }, 423 + .bar[BAR_4] = { 424 + .type = BAR_RESERVED, 425 + .nr_rsvd_regions = ARRAY_SIZE(rk3588_bar4_rsvd), 426 + .rsvd_regions = rk3588_bar4_rsvd, 427 + }, 433 428 .bar[BAR_5] = { .type = BAR_RESIZABLE, }, 434 429 }; 435 430