Merge tag 'pci-v5.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

+9

Documentation/ABI/testing/sysfs-bus-pci

··· 366 366 Description: If ASPM is supported for an endpoint, these files can be 367 367 used to disable or enable the individual power management 368 368 states. Write y/1/on to enable, n/0/off to disable. 369 + 370 + What: /sys/bus/pci/devices/.../power_state 371 + Date: November 2020 372 + Contact: Linux PCI developers <linux-pci@vger.kernel.org> 373 + Description: 374 + This file contains the current PCI power state of the device. 375 + The value comes from the PCI kernel device state and can be one 376 + of: "unknown", "error", "D0", D1", "D2", "D3hot", "D3cold". 377 + The file is read only.

-3

Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml

··· 20 20 maximum: 32 21 21 default: 32 22 22 23 - required: 24 - - cdns,max-outbound-regions 25 - 26 23 additionalProperties: true

+4 -2

Documentation/devicetree/bindings/pci/qcom,pcie.txt

··· 13 13 - "qcom,pcie-ipq8074" for ipq8074 14 14 - "qcom,pcie-qcs404" for qcs404 15 15 - "qcom,pcie-sdm845" for sdm845 16 + - "qcom,pcie-sm8250" for sm8250 16 17 17 18 - reg: 18 19 Usage: required ··· 28 27 - "dbi" DesignWare PCIe registers 29 28 - "elbi" External local bus interface registers 30 29 - "config" PCIe configuration space 30 + - "atu" ATU address space (optional) 31 31 32 32 - device_type: 33 33 Usage: required ··· 133 131 - "slave_bus" AXI Slave clock 134 132 135 133 -clock-names: 136 - Usage: required for sdm845 134 + Usage: required for sdm845 and sm8250 137 135 Value type: <stringlist> 138 136 Definition: Should contain the following entries 139 137 - "aux" Auxiliary clock ··· 208 206 - "ahb" AHB reset 209 207 210 208 - reset-names: 211 - Usage: required for sdm845 209 + Usage: required for sdm845 and sm8250 212 210 Value type: <stringlist> 213 211 Definition: Should contain the following entries 214 212 - "pci" PCIe core reset

+115

Documentation/devicetree/bindings/pci/rcar-pci-host.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright (C) 2020 Renesas Electronics Corp. 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Renesas R-Car PCIe Host 9 + 10 + maintainers: 11 + - Marek Vasut <marek.vasut+renesas@gmail.com> 12 + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 13 + 14 + allOf: 15 + - $ref: pci-bus.yaml# 16 + 17 + properties: 18 + compatible: 19 + oneOf: 20 + - items: 21 + - enum: 22 + - renesas,pcie-r8a7742 # RZ/G1H 23 + - renesas,pcie-r8a7743 # RZ/G1M 24 + - renesas,pcie-r8a7744 # RZ/G1N 25 + - renesas,pcie-r8a7790 # R-Car H2 26 + - renesas,pcie-r8a7791 # R-Car M2-W 27 + - renesas,pcie-r8a7793 # R-Car M2-N 28 + - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1 29 + - items: 30 + - enum: 31 + - renesas,pcie-r8a774a1 # RZ/G2M 32 + - renesas,pcie-r8a774b1 # RZ/G2N 33 + - renesas,pcie-r8a774c0 # RZ/G2E 34 + - renesas,pcie-r8a774e1 # RZ/G2H 35 + - renesas,pcie-r8a7795 # R-Car H3 36 + - renesas,pcie-r8a7796 # R-Car M3-W 37 + - renesas,pcie-r8a77961 # R-Car M3-W+ 38 + - renesas,pcie-r8a77965 # R-Car M3-N 39 + - renesas,pcie-r8a77980 # R-Car V3H 40 + - renesas,pcie-r8a77990 # R-Car E3 41 + - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2 42 + 43 + reg: 44 + maxItems: 1 45 + 46 + interrupts: 47 + minItems: 3 48 + maxItems: 3 49 + 50 + clocks: 51 + maxItems: 2 52 + 53 + clock-names: 54 + items: 55 + - const: pcie 56 + - const: pcie_bus 57 + 58 + power-domains: 59 + maxItems: 1 60 + 61 + resets: 62 + maxItems: 1 63 + 64 + phys: 65 + maxItems: 1 66 + 67 + phy-names: 68 + const: pcie 69 + 70 + required: 71 + - compatible 72 + - reg 73 + - interrupts 74 + - clocks 75 + - clock-names 76 + - power-domains 77 + - resets 78 + 79 + unevaluatedProperties: false 80 + 81 + examples: 82 + - | 83 + #include <dt-bindings/clock/r8a7791-cpg-mssr.h> 84 + #include <dt-bindings/interrupt-controller/arm-gic.h> 85 + #include <dt-bindings/power/r8a7791-sysc.h> 86 + 87 + soc { 88 + #address-cells = <2>; 89 + #size-cells = <2>; 90 + 91 + pcie: pcie@fe000000 { 92 + compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; 93 + reg = <0 0xfe000000 0 0x80000>; 94 + #address-cells = <3>; 95 + #size-cells = <2>; 96 + bus-range = <0x00 0xff>; 97 + device_type = "pci"; 98 + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 99 + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 100 + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 101 + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 102 + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>, 103 + <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; 104 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 105 + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 106 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 107 + #interrupt-cells = <1>; 108 + interrupt-map-mask = <0 0 0 0>; 109 + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 110 + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 111 + clock-names = "pcie", "pcie_bus"; 112 + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 113 + resets = <&cpg 319>; 114 + }; 115 + };

-72

Documentation/devicetree/bindings/pci/rcar-pci.txt

··· 1 - * Renesas R-Car PCIe interface 2 - 3 - Required properties: 4 - compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC; 5 - "renesas,pcie-r8a7743" for the R8A7743 SoC; 6 - "renesas,pcie-r8a7744" for the R8A7744 SoC; 7 - "renesas,pcie-r8a774a1" for the R8A774A1 SoC; 8 - "renesas,pcie-r8a774b1" for the R8A774B1 SoC; 9 - "renesas,pcie-r8a774c0" for the R8A774C0 SoC; 10 - "renesas,pcie-r8a7779" for the R8A7779 SoC; 11 - "renesas,pcie-r8a7790" for the R8A7790 SoC; 12 - "renesas,pcie-r8a7791" for the R8A7791 SoC; 13 - "renesas,pcie-r8a7793" for the R8A7793 SoC; 14 - "renesas,pcie-r8a7795" for the R8A7795 SoC; 15 - "renesas,pcie-r8a7796" for the R8A77960 SoC; 16 - "renesas,pcie-r8a77961" for the R8A77961 SoC; 17 - "renesas,pcie-r8a77980" for the R8A77980 SoC; 18 - "renesas,pcie-r8a77990" for the R8A77990 SoC; 19 - "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or 20 - RZ/G1 compatible device. 21 - "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or 22 - RZ/G2 compatible device. 23 - 24 - When compatible with the generic version, nodes must list the 25 - SoC-specific version corresponding to the platform first 26 - followed by the generic version. 27 - 28 - - reg: base address and length of the PCIe controller registers. 29 - - #address-cells: set to <3> 30 - - #size-cells: set to <2> 31 - - bus-range: PCI bus numbers covered 32 - - device_type: set to "pci" 33 - - ranges: ranges for the PCI memory and I/O regions. 34 - - dma-ranges: ranges for the inbound memory regions. 35 - - interrupts: two interrupt sources for MSI interrupts, followed by interrupt 36 - source for hardware related interrupts (e.g. link speed change). 37 - - #interrupt-cells: set to <1> 38 - - interrupt-map-mask and interrupt-map: standard PCI properties 39 - to define the mapping of the PCIe interface to interrupt numbers. 40 - - clocks: from common clock binding: clock specifiers for the PCIe controller 41 - and PCIe bus clocks. 42 - - clock-names: from common clock binding: should be "pcie" and "pcie_bus". 43 - 44 - Optional properties: 45 - - phys: from common PHY binding: PHY phandle and specifier (only make sense 46 - for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). 47 - - phy-names: from common PHY binding: should be "pcie". 48 - 49 - Example: 50 - 51 - SoC-specific DT Entry: 52 - 53 - pcie: pcie@fe000000 { 54 - compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; 55 - reg = <0 0xfe000000 0 0x80000>; 56 - #address-cells = <3>; 57 - #size-cells = <2>; 58 - bus-range = <0x00 0xff>; 59 - device_type = "pci"; 60 - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 61 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 62 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 63 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 64 - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000 65 - 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; 66 - interrupts = <0 116 4>, <0 117 4>, <0 118 4>; 67 - #interrupt-cells = <1>; 68 - interrupt-map-mask = <0 0 0 0>; 69 - interrupt-map = <0 0 0 0 &gic 0 116 4>; 70 - clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>; 71 - clock-names = "pcie", "pcie_bus"; 72 - };

+119

Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung SoC series PCIe Host Controller Device Tree Bindings 8 + 9 + maintainers: 10 + - Marek Szyprowski <m.szyprowski@samsung.com> 11 + - Jaehoon Chung <jh80.chung@samsung.com> 12 + 13 + description: |+ 14 + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare 15 + PCIe IP and thus inherits all the common properties defined in 16 + designware-pcie.txt. 17 + 18 + allOf: 19 + - $ref: /schemas/pci/pci-bus.yaml# 20 + 21 + properties: 22 + compatible: 23 + const: samsung,exynos5433-pcie 24 + 25 + reg: 26 + items: 27 + - description: Data Bus Interface (DBI) registers. 28 + - description: External Local Bus interface (ELBI) registers. 29 + - description: PCIe configuration space region. 30 + 31 + reg-names: 32 + items: 33 + - const: dbi 34 + - const: elbi 35 + - const: config 36 + 37 + interrupts: 38 + maxItems: 1 39 + 40 + clocks: 41 + items: 42 + - description: PCIe bridge clock 43 + - description: PCIe bus clock 44 + 45 + clock-names: 46 + items: 47 + - const: pcie 48 + - const: pcie_bus 49 + 50 + phys: 51 + maxItems: 1 52 + 53 + vdd10-supply: 54 + description: 55 + Phandle to a regulator that provides 1.0V power to the PCIe block. 56 + 57 + vdd18-supply: 58 + description: 59 + Phandle to a regulator that provides 1.8V power to the PCIe block. 60 + 61 + num-lanes: 62 + const: 1 63 + 64 + num-viewport: 65 + const: 3 66 + 67 + required: 68 + - reg 69 + - reg-names 70 + - interrupts 71 + - "#address-cells" 72 + - "#size-cells" 73 + - "#interrupt-cells" 74 + - interrupt-map 75 + - interrupt-map-mask 76 + - ranges 77 + - bus-range 78 + - device_type 79 + - num-lanes 80 + - num-viewport 81 + - clocks 82 + - clock-names 83 + - phys 84 + - vdd10-supply 85 + - vdd18-supply 86 + 87 + unevaluatedProperties: false 88 + 89 + examples: 90 + - | 91 + #include <dt-bindings/interrupt-controller/irq.h> 92 + #include <dt-bindings/interrupt-controller/arm-gic.h> 93 + #include <dt-bindings/clock/exynos5433.h> 94 + 95 + pcie: pcie@15700000 { 96 + compatible = "samsung,exynos5433-pcie"; 97 + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; 98 + reg-names = "dbi", "elbi", "config"; 99 + #address-cells = <3>; 100 + #size-cells = <2>; 101 + #interrupt-cells = <1>; 102 + device_type = "pci"; 103 + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 104 + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; 105 + clock-names = "pcie", "pcie_bus"; 106 + phys = <&pcie_phy>; 107 + pinctrl-0 = <&pcie_bus &pcie_wlanen>; 108 + pinctrl-names = "default"; 109 + num-lanes = <1>; 110 + num-viewport = <3>; 111 + bus-range = <0x00 0xff>; 112 + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, 113 + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; 114 + vdd10-supply = <&ldo6_reg>; 115 + vdd18-supply = <&ldo7_reg>; 116 + interrupt-map-mask = <0 0 0 0>; 117 + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 118 + }; 119 + ...

-58

Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt

··· 1 - * Samsung Exynos 5440 PCIe interface 2 - 3 - This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4 - and thus inherits all the common properties defined in designware-pcie.txt. 5 - 6 - Required properties: 7 - - compatible: "samsung,exynos5440-pcie" 8 - - reg: base addresses and lengths of the PCIe controller, 9 - - reg-names : First name should be set to "elbi". 10 - And use the "config" instead of getting the configuration address space 11 - from "ranges". 12 - NOTE: When using the "config" property, reg-names must be set. 13 - - interrupts: A list of interrupt outputs for level interrupt, 14 - pulse interrupt, special interrupt. 15 - - phys: From PHY binding. Phandle for the generic PHY. 16 - Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt 17 - 18 - For other common properties, refer to 19 - Documentation/devicetree/bindings/pci/designware-pcie.txt 20 - 21 - Example: 22 - 23 - SoC-specific DT Entry (with using PHY framework): 24 - 25 - pcie_phy0: pcie-phy@270000 { 26 - ... 27 - reg = <0x270000 0x1000>, <0x271000 0x40>; 28 - reg-names = "phy", "block"; 29 - ... 30 - }; 31 - 32 - pcie@290000 { 33 - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; 34 - reg = <0x290000 0x1000>, <0x40000000 0x1000>; 35 - reg-names = "elbi", "config"; 36 - clocks = <&clock 28>, <&clock 27>; 37 - clock-names = "pcie", "pcie_bus"; 38 - #address-cells = <3>; 39 - #size-cells = <2>; 40 - device_type = "pci"; 41 - phys = <&pcie_phy0>; 42 - ranges = <0x81000000 0 0 0x60001000 0 0x00010000 43 - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; 44 - #interrupt-cells = <1>; 45 - interrupt-map-mask = <0 0 0 0>; 46 - interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 47 - num-lanes = <4>; 48 - }; 49 - 50 - Board-specific DT Entry: 51 - 52 - pcie@290000 { 53 - reset-gpio = <&pin_ctrl 5 0>; 54 - }; 55 - 56 - pcie@2a0000 { 57 - reset-gpio = <&pin_ctrl 22 0>; 58 - };

+15 -8

Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

··· 15 15 16 16 properties: 17 17 compatible: 18 - enum: 19 - - ti,j721e-pcie-ep 18 + oneOf: 19 + - description: PCIe EP controller in J7200 20 + items: 21 + - const: ti,j7200-pcie-ep 22 + - const: ti,j721e-pcie-ep 23 + - description: PCIe EP controller in J721E 24 + items: 25 + - const: ti,j721e-pcie-ep 20 26 21 27 reg: 22 28 maxItems: 4 ··· 35 29 - const: mem 36 30 37 31 ti,syscon-pcie-ctrl: 38 - description: Phandle to the SYSCON entry required for configuring PCIe mode 39 - and link speed. 40 - $ref: /schemas/types.yaml#/definitions/phandle 32 + $ref: /schemas/types.yaml#/definitions/phandle-array 33 + items: 34 + - items: 35 + - description: Phandle to the SYSCON entry 36 + - description: pcie_ctrl register offset within SYSCON 37 + description: Specifier for configuring PCIe mode and link speed. 41 38 42 39 power-domains: 43 40 maxItems: 1 ··· 66 57 - power-domains 67 58 - clocks 68 59 - clock-names 69 - - cdns,max-outbound-regions 70 60 - dma-coherent 71 61 - max-functions 72 62 - phys ··· 88 80 <0x00 0x0d000000 0x00 0x00800000>, 89 81 <0x00 0x10000000 0x00 0x08000000>; 90 82 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 91 - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 83 + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; 92 84 max-link-speed = <3>; 93 85 num-lanes = <2>; 94 86 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 95 87 clocks = <&k3_clks 239 1>; 96 88 clock-names = "fck"; 97 - cdns,max-outbound-regions = <16>; 98 89 max-functions = /bits/ 8 <6>; 99 90 dma-coherent; 100 91 phys = <&serdes0_pcie_link>;

+20 -7

Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

··· 15 15 16 16 properties: 17 17 compatible: 18 - enum: 19 - - ti,j721e-pcie-host 18 + oneOf: 19 + - description: PCIe controller in J7200 20 + items: 21 + - const: ti,j7200-pcie-host 22 + - const: ti,j721e-pcie-host 23 + - description: PCIe controller in J721E 24 + items: 25 + - const: ti,j721e-pcie-host 20 26 21 27 reg: 22 28 maxItems: 4 ··· 35 29 - const: cfg 36 30 37 31 ti,syscon-pcie-ctrl: 38 - description: Phandle to the SYSCON entry required for configuring PCIe mode 39 - and link speed. 40 - $ref: /schemas/types.yaml#/definitions/phandle 32 + $ref: /schemas/types.yaml#/definitions/phandle-array 33 + items: 34 + - items: 35 + - description: Phandle to the SYSCON entry 36 + - description: pcie_ctrl register offset within SYSCON 37 + description: Specifier for configuring PCIe mode and link speed. 41 38 42 39 power-domains: 43 40 maxItems: 1 ··· 57 48 const: 0x104c 58 49 59 50 device-id: 60 - const: 0xb00d 51 + oneOf: 52 + - items: 53 + - const: 0xb00d 54 + - items: 55 + - const: 0xb00f 61 56 62 57 msi-map: true 63 58 ··· 103 90 <0x00 0x0d000000 0x00 0x00800000>, 104 91 <0x00 0x10000000 0x00 0x00001000>; 105 92 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 106 - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 93 + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; 107 94 max-link-speed = <3>; 108 95 num-lanes = <2>; 109 96 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;

+51

Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Samsung SoC series PCIe PHY Device Tree Bindings 8 + 9 + maintainers: 10 + - Marek Szyprowski <m.szyprowski@samsung.com> 11 + - Jaehoon Chung <jh80.chung@samsung.com> 12 + 13 + properties: 14 + "#phy-cells": 15 + const: 0 16 + 17 + compatible: 18 + const: samsung,exynos5433-pcie-phy 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + samsung,pmu-syscon: 24 + $ref: '/schemas/types.yaml#/definitions/phandle' 25 + description: phandle for PMU system controller interface, used to 26 + control PMU registers bits for PCIe PHY 27 + 28 + samsung,fsys-sysreg: 29 + $ref: '/schemas/types.yaml#/definitions/phandle' 30 + description: phandle for FSYS sysreg interface, used to control 31 + sysreg registers bits for PCIe PHY 32 + 33 + required: 34 + - "#phy-cells" 35 + - compatible 36 + - reg 37 + - samsung,pmu-syscon 38 + - samsung,fsys-sysreg 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + pcie_phy: pcie-phy@15680000 { 45 + compatible = "samsung,exynos5433-pcie-phy"; 46 + reg = <0x15680000 0x1000>; 47 + samsung,pmu-syscon = <&pmu_system_controller>; 48 + samsung,fsys-sysreg = <&syscon_fsys>; 49 + #phy-cells = <0>; 50 + }; 51 + ...

+2

MAINTAINERS

··· 13656 13656 M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 13657 13657 L: linux-pci@vger.kernel.org 13658 13658 S: Supported 13659 + F: Documentation/PCI/endpoint/* 13660 + F: Documentation/misc-devices/pci-endpoint-test.rst 13659 13661 T: git git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git 13660 13662 F: drivers/misc/pci_endpoint_test.c 13661 13663 F: drivers/pci/endpoint/

+1 -1

drivers/gpu/vga/vga_switcheroo.c

··· 1038 1038 mutex_lock(&vgasr_mutex); 1039 1039 vga_switcheroo_power_switch(pdev, VGA_SWITCHEROO_ON); 1040 1040 mutex_unlock(&vgasr_mutex); 1041 - pci_wakeup_bus(pdev->bus); 1041 + pci_resume_bus(pdev->bus); 1042 1042 return dev->bus->pm->runtime_resume(dev); 1043 1043 } 1044 1044

+1 -2

drivers/pci/Makefile

··· 5 5 obj-$(CONFIG_PCI) += access.o bus.o probe.o host-bridge.o \ 6 6 remove.o pci.o pci-driver.o search.o \ 7 7 pci-sysfs.o rom.o setup-res.o irq.o vpd.o \ 8 - setup-bus.o vc.o mmap.o setup-irq.o 8 + setup-bus.o vc.o mmap.o setup-irq.o msi.o 9 9 10 10 obj-$(CONFIG_PCI) += pcie/ 11 11 ··· 18 18 obj-$(CONFIG_OF) += of.o 19 19 obj-$(CONFIG_PCI_QUIRKS) += quirks.o 20 20 obj-$(CONFIG_HOTPLUG_PCI) += hotplug/ 21 - obj-$(CONFIG_PCI_MSI) += msi.o 22 21 obj-$(CONFIG_PCI_ATS) += ats.o 23 22 obj-$(CONFIG_PCI_IOV) += iov.o 24 23 obj-$(CONFIG_PCI_BRIDGE_EMUL) += pci-bridge-emul.o

+19 -9

drivers/pci/controller/cadence/pci-j721e.c

··· 12 12 #include <linux/irqchip/chained_irq.h> 13 13 #include <linux/irqdomain.h> 14 14 #include <linux/mfd/syscon.h> 15 + #include <linux/of.h> 15 16 #include <linux/of_device.h> 16 17 #include <linux/of_irq.h> 17 18 #include <linux/pci.h> ··· 154 153 .link_up = j721e_pcie_link_up, 155 154 }; 156 155 157 - static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) 156 + static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, 157 + unsigned int offset) 158 158 { 159 159 struct device *dev = pcie->dev; 160 160 u32 mask = J721E_MODE_RC; ··· 166 164 if (mode == PCI_MODE_RC) 167 165 val = J721E_MODE_RC; 168 166 169 - ret = regmap_update_bits(syscon, 0, mask, val); 167 + ret = regmap_update_bits(syscon, offset, mask, val); 170 168 if (ret) 171 169 dev_err(dev, "failed to set pcie mode\n"); 172 170 ··· 174 172 } 175 173 176 174 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 177 - struct regmap *syscon) 175 + struct regmap *syscon, unsigned int offset) 178 176 { 179 177 struct device *dev = pcie->dev; 180 178 struct device_node *np = dev->of_node; ··· 187 185 link_speed = 2; 188 186 189 187 val = link_speed - 1; 190 - ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val); 188 + ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); 191 189 if (ret) 192 190 dev_err(dev, "failed to set link speed\n"); 193 191 ··· 195 193 } 196 194 197 195 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 198 - struct regmap *syscon) 196 + struct regmap *syscon, unsigned int offset) 199 197 { 200 198 struct device *dev = pcie->dev; 201 199 u32 lanes = pcie->num_lanes; ··· 203 201 int ret; 204 202 205 203 val = LANE_COUNT(lanes - 1); 206 - ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val); 204 + ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); 207 205 if (ret) 208 206 dev_err(dev, "failed to set link count\n"); 209 207 ··· 214 212 { 215 213 struct device *dev = pcie->dev; 216 214 struct device_node *node = dev->of_node; 215 + struct of_phandle_args args; 216 + unsigned int offset = 0; 217 217 struct regmap *syscon; 218 218 int ret; 219 219 ··· 225 221 return PTR_ERR(syscon); 226 222 } 227 223 228 - ret = j721e_pcie_set_mode(pcie, syscon); 224 + /* Do not error out to maintain old DT compatibility */ 225 + ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, 226 + 0, &args); 227 + if (!ret) 228 + offset = args.args[0]; 229 + 230 + ret = j721e_pcie_set_mode(pcie, syscon, offset); 229 231 if (ret < 0) { 230 232 dev_err(dev, "Failed to set pci mode\n"); 231 233 return ret; 232 234 } 233 235 234 - ret = j721e_pcie_set_link_speed(pcie, syscon); 236 + ret = j721e_pcie_set_link_speed(pcie, syscon, offset); 235 237 if (ret < 0) { 236 238 dev_err(dev, "Failed to set link speed\n"); 237 239 return ret; 238 240 } 239 241 240 - ret = j721e_pcie_set_lane_count(pcie, syscon); 242 + ret = j721e_pcie_set_lane_count(pcie, syscon, offset); 241 243 if (ret < 0) { 242 244 dev_err(dev, "Failed to set num-lanes\n"); 243 245 return ret;

+3 -6

drivers/pci/controller/cadence/pcie-cadence-ep.c

··· 530 530 } 531 531 pcie->mem_res = res; 532 532 533 - ret = of_property_read_u32(np, "cdns,max-outbound-regions", 534 - &ep->max_regions); 535 - if (ret < 0) { 536 - dev_err(dev, "missing \"cdns,max-outbound-regions\"\n"); 537 - return ret; 538 - } 533 + ep->max_regions = CDNS_PCIE_MAX_OB; 534 + of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions); 535 + 539 536 ep->ob_addr = devm_kcalloc(dev, 540 537 ep->max_regions, sizeof(*ep->ob_addr), 541 538 GFP_KERNEL);

+1

drivers/pci/controller/cadence/pcie-cadence.h

··· 197 197 }; 198 198 199 199 #define CDNS_PCIE_RP_MAX_IB 0x3 200 + #define CDNS_PCIE_MAX_OB 32 200 201 201 202 struct cdns_pcie_rp_ib_bar { 202 203 u64 size;

+10 -4

drivers/pci/controller/dwc/Kconfig

··· 83 83 selected. 84 84 85 85 config PCI_EXYNOS 86 - bool "Samsung Exynos PCIe controller" 87 - depends on SOC_EXYNOS5440 || COMPILE_TEST 86 + tristate "Samsung Exynos PCIe controller" 87 + depends on ARCH_EXYNOS || COMPILE_TEST 88 88 depends on PCI_MSI_IRQ_DOMAIN 89 89 select PCIE_DW_HOST 90 + help 91 + Enables support for the PCIe controller in the Samsung Exynos SoCs 92 + to work in host mode. The PCI controller is based on the DesignWare 93 + hardware and therefore the driver re-uses the DesignWare core 94 + functions to implement the driver. 90 95 91 96 config PCI_IMX6 92 97 bool "Freescale i.MX6/7/8 PCIe controller" ··· 112 107 113 108 config PCI_KEYSTONE_HOST 114 109 bool "PCI Keystone Host Mode" 115 - depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) 110 + depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST 116 111 depends on PCI_MSI_IRQ_DOMAIN 117 112 select PCIE_DW_HOST 118 113 select PCI_KEYSTONE ··· 124 119 125 120 config PCI_KEYSTONE_EP 126 121 bool "PCI Keystone Endpoint Mode" 127 - depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) 122 + depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST 128 123 depends on PCI_ENDPOINT 129 124 select PCIE_DW_EP 130 125 select PCI_KEYSTONE ··· 174 169 depends on OF && (ARCH_QCOM || COMPILE_TEST) 175 170 depends on PCI_MSI_IRQ_DOMAIN 176 171 select PCIE_DW_HOST 172 + select CRC8 177 173 help 178 174 Say Y here to enable PCIe controller support on Qualcomm SoCs. The 179 175 PCIe controller uses the DesignWare core plus Qualcomm-specific

+3 -138

drivers/pci/controller/dwc/pci-dra7xx.c

··· 181 181 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 182 182 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 183 183 184 - dw_pcie_setup_rc(pp); 185 - 186 - dra7xx_pcie_establish_link(pci); 187 - dw_pcie_wait_for_link(pci); 188 - dw_pcie_msi_init(pp); 189 184 dra7xx_pcie_enable_interrupts(dra7xx); 190 185 191 186 return 0; ··· 372 377 return 0; 373 378 } 374 379 375 - static void dra7xx_pcie_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 376 - { 377 - struct pcie_port *pp = irq_data_get_irq_chip_data(d); 378 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 379 - u64 msi_target; 380 - 381 - msi_target = (u64)pp->msi_data; 382 - 383 - msg->address_lo = lower_32_bits(msi_target); 384 - msg->address_hi = upper_32_bits(msi_target); 385 - 386 - msg->data = d->hwirq; 387 - 388 - dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 389 - (int)d->hwirq, msg->address_hi, msg->address_lo); 390 - } 391 - 392 - static int dra7xx_pcie_msi_set_affinity(struct irq_data *d, 393 - const struct cpumask *mask, 394 - bool force) 395 - { 396 - return -EINVAL; 397 - } 398 - 399 - static void dra7xx_pcie_bottom_mask(struct irq_data *d) 400 - { 401 - struct pcie_port *pp = irq_data_get_irq_chip_data(d); 402 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 403 - unsigned int res, bit, ctrl; 404 - unsigned long flags; 405 - 406 - raw_spin_lock_irqsave(&pp->lock, flags); 407 - 408 - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 409 - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 410 - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 411 - 412 - pp->irq_mask[ctrl] |= BIT(bit); 413 - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, 414 - pp->irq_mask[ctrl]); 415 - 416 - raw_spin_unlock_irqrestore(&pp->lock, flags); 417 - } 418 - 419 - static void dra7xx_pcie_bottom_unmask(struct irq_data *d) 420 - { 421 - struct pcie_port *pp = irq_data_get_irq_chip_data(d); 422 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 423 - unsigned int res, bit, ctrl; 424 - unsigned long flags; 425 - 426 - raw_spin_lock_irqsave(&pp->lock, flags); 427 - 428 - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 429 - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 430 - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 431 - 432 - pp->irq_mask[ctrl] &= ~BIT(bit); 433 - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, 434 - pp->irq_mask[ctrl]); 435 - 436 - raw_spin_unlock_irqrestore(&pp->lock, flags); 437 - } 438 - 439 - static void dra7xx_pcie_bottom_ack(struct irq_data *d) 440 - { 441 - struct pcie_port *pp = irq_data_get_irq_chip_data(d); 442 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 443 - unsigned int res, bit, ctrl; 444 - 445 - ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 446 - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 447 - bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 448 - 449 - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); 450 - } 451 - 452 - static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = { 453 - .name = "DRA7XX-PCI-MSI", 454 - .irq_ack = dra7xx_pcie_bottom_ack, 455 - .irq_compose_msi_msg = dra7xx_pcie_setup_msi_msg, 456 - .irq_set_affinity = dra7xx_pcie_msi_set_affinity, 457 - .irq_mask = dra7xx_pcie_bottom_mask, 458 - .irq_unmask = dra7xx_pcie_bottom_unmask, 459 - }; 460 - 461 - static int dra7xx_pcie_msi_host_init(struct pcie_port *pp) 462 - { 463 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 464 - struct device *dev = pci->dev; 465 - u32 ctrl, num_ctrls; 466 - int ret; 467 - 468 - pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip; 469 - 470 - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 471 - /* Initialize IRQ Status array */ 472 - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 473 - pp->irq_mask[ctrl] = ~0; 474 - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + 475 - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 476 - pp->irq_mask[ctrl]); 477 - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + 478 - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 479 - ~0); 480 - } 481 - 482 - ret = dw_pcie_allocate_domains(pp); 483 - if (ret) 484 - return ret; 485 - 486 - pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg, 487 - sizeof(pp->msi_msg), 488 - DMA_FROM_DEVICE, 489 - DMA_ATTR_SKIP_CPU_SYNC); 490 - ret = dma_mapping_error(dev, pp->msi_data); 491 - if (ret) { 492 - dev_err(dev, "Failed to map MSI data\n"); 493 - pp->msi_data = 0; 494 - dw_pcie_free_msi(pp); 495 - } 496 - return ret; 497 - } 498 - 499 380 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { 500 381 .host_init = dra7xx_pcie_host_init, 501 - .msi_host_init = dra7xx_pcie_msi_host_init, 502 382 }; 503 383 504 384 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) ··· 448 578 { 449 579 int ret; 450 580 struct dw_pcie_ep *ep; 451 - struct resource *res; 452 581 struct device *dev = &pdev->dev; 453 582 struct dw_pcie *pci = dra7xx->pci; 454 583 ··· 462 593 devm_platform_ioremap_resource_byname(pdev, "ep_dbics2"); 463 594 if (IS_ERR(pci->dbi_base2)) 464 595 return PTR_ERR(pci->dbi_base2); 465 - 466 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 467 - if (!res) 468 - return -EINVAL; 469 - 470 - ep->phys_base = res->start; 471 - ep->addr_size = resource_size(res); 472 596 473 597 ret = dw_pcie_ep_init(ep); 474 598 if (ret) { ··· 483 621 pp->irq = platform_get_irq(pdev, 1); 484 622 if (pp->irq < 0) 485 623 return pp->irq; 624 + 625 + /* MSI IRQ is muxed */ 626 + pp->msi_irq = -ENODEV; 486 627 487 628 ret = dra7xx_pcie_init_irq_domain(pp); 488 629 if (ret < 0)

+148 -241

drivers/pci/controller/dwc/pci-exynos.c

··· 2 2 /* 3 3 * PCIe host controller driver for Samsung Exynos SoCs 4 4 * 5 - * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 + * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd. 6 6 * https://www.samsung.com 7 7 * 8 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 + * Jaehoon Chung <jh80.chung@samsung.com> 9 10 */ 10 11 11 12 #include <linux/clk.h> 12 13 #include <linux/delay.h> 13 - #include <linux/gpio.h> 14 14 #include <linux/interrupt.h> 15 15 #include <linux/kernel.h> 16 16 #include <linux/init.h> 17 17 #include <linux/of_device.h> 18 - #include <linux/of_gpio.h> 19 18 #include <linux/pci.h> 20 19 #include <linux/platform_device.h> 21 20 #include <linux/phy/phy.h> 22 - #include <linux/resource.h> 23 - #include <linux/signal.h> 24 - #include <linux/types.h> 21 + #include <linux/regulator/consumer.h> 25 22 26 23 #include "pcie-designware.h" 27 24 ··· 34 37 #define PCIE_IRQ_SPECIAL 0x008 35 38 #define PCIE_IRQ_EN_PULSE 0x00c 36 39 #define PCIE_IRQ_EN_LEVEL 0x010 37 - #define IRQ_MSI_ENABLE BIT(2) 38 40 #define PCIE_IRQ_EN_SPECIAL 0x014 39 - #define PCIE_PWR_RESET 0x018 41 + #define PCIE_SW_WAKE 0x018 42 + #define PCIE_BUS_EN BIT(1) 40 43 #define PCIE_CORE_RESET 0x01c 41 44 #define PCIE_CORE_RESET_ENABLE BIT(0) 42 45 #define PCIE_STICKY_RESET 0x020 43 46 #define PCIE_NONSTICKY_RESET 0x024 44 47 #define PCIE_APP_INIT_RESET 0x028 45 48 #define PCIE_APP_LTSSM_ENABLE 0x02c 46 - #define PCIE_ELBI_RDLH_LINKUP 0x064 49 + #define PCIE_ELBI_RDLH_LINKUP 0x074 50 + #define PCIE_ELBI_XMLH_LINKUP BIT(4) 47 51 #define PCIE_ELBI_LTSSM_ENABLE 0x1 48 52 #define PCIE_ELBI_SLV_AWMISC 0x11c 49 53 #define PCIE_ELBI_SLV_ARMISC 0x120 50 54 #define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) 51 55 52 - struct exynos_pcie_mem_res { 53 - void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */ 54 - }; 55 - 56 - struct exynos_pcie_clk_res { 57 - struct clk *clk; 58 - struct clk *bus_clk; 59 - }; 60 - 61 56 struct exynos_pcie { 62 - struct dw_pcie *pci; 63 - struct exynos_pcie_mem_res *mem_res; 64 - struct exynos_pcie_clk_res *clk_res; 65 - const struct exynos_pcie_ops *ops; 66 - int reset_gpio; 67 - 57 + struct dw_pcie pci; 58 + void __iomem *elbi_base; 59 + struct clk *clk; 60 + struct clk *bus_clk; 68 61 struct phy *phy; 62 + struct regulator_bulk_data supplies[2]; 69 63 }; 70 64 71 - struct exynos_pcie_ops { 72 - int (*get_mem_resources)(struct platform_device *pdev, 73 - struct exynos_pcie *ep); 74 - int (*get_clk_resources)(struct exynos_pcie *ep); 75 - int (*init_clk_resources)(struct exynos_pcie *ep); 76 - void (*deinit_clk_resources)(struct exynos_pcie *ep); 77 - }; 78 - 79 - static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev, 80 - struct exynos_pcie *ep) 65 + static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) 81 66 { 82 - struct dw_pcie *pci = ep->pci; 83 - struct device *dev = pci->dev; 84 - 85 - ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL); 86 - if (!ep->mem_res) 87 - return -ENOMEM; 88 - 89 - ep->mem_res->elbi_base = devm_platform_ioremap_resource(pdev, 0); 90 - if (IS_ERR(ep->mem_res->elbi_base)) 91 - return PTR_ERR(ep->mem_res->elbi_base); 92 - 93 - return 0; 94 - } 95 - 96 - static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep) 97 - { 98 - struct dw_pcie *pci = ep->pci; 99 - struct device *dev = pci->dev; 100 - 101 - ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL); 102 - if (!ep->clk_res) 103 - return -ENOMEM; 104 - 105 - ep->clk_res->clk = devm_clk_get(dev, "pcie"); 106 - if (IS_ERR(ep->clk_res->clk)) { 107 - dev_err(dev, "Failed to get pcie rc clock\n"); 108 - return PTR_ERR(ep->clk_res->clk); 109 - } 110 - 111 - ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus"); 112 - if (IS_ERR(ep->clk_res->bus_clk)) { 113 - dev_err(dev, "Failed to get pcie bus clock\n"); 114 - return PTR_ERR(ep->clk_res->bus_clk); 115 - } 116 - 117 - return 0; 118 - } 119 - 120 - static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep) 121 - { 122 - struct dw_pcie *pci = ep->pci; 123 - struct device *dev = pci->dev; 67 + struct device *dev = ep->pci.dev; 124 68 int ret; 125 69 126 - ret = clk_prepare_enable(ep->clk_res->clk); 70 + ret = clk_prepare_enable(ep->clk); 127 71 if (ret) { 128 72 dev_err(dev, "cannot enable pcie rc clock"); 129 73 return ret; 130 74 } 131 75 132 - ret = clk_prepare_enable(ep->clk_res->bus_clk); 76 + ret = clk_prepare_enable(ep->bus_clk); 133 77 if (ret) { 134 78 dev_err(dev, "cannot enable pcie bus clock"); 135 79 goto err_bus_clk; ··· 79 141 return 0; 80 142 81 143 err_bus_clk: 82 - clk_disable_unprepare(ep->clk_res->clk); 144 + clk_disable_unprepare(ep->clk); 83 145 84 146 return ret; 85 147 } 86 148 87 - static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie *ep) 149 + static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) 88 150 { 89 - clk_disable_unprepare(ep->clk_res->bus_clk); 90 - clk_disable_unprepare(ep->clk_res->clk); 151 + clk_disable_unprepare(ep->bus_clk); 152 + clk_disable_unprepare(ep->clk); 91 153 } 92 - 93 - static const struct exynos_pcie_ops exynos5440_pcie_ops = { 94 - .get_mem_resources = exynos5440_pcie_get_mem_resources, 95 - .get_clk_resources = exynos5440_pcie_get_clk_resources, 96 - .init_clk_resources = exynos5440_pcie_init_clk_resources, 97 - .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources, 98 - }; 99 154 100 155 static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) 101 156 { ··· 104 173 { 105 174 u32 val; 106 175 107 - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_AWMISC); 176 + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); 108 177 if (on) 109 178 val |= PCIE_ELBI_SLV_DBI_ENABLE; 110 179 else 111 180 val &= ~PCIE_ELBI_SLV_DBI_ENABLE; 112 - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_AWMISC); 181 + exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); 113 182 } 114 183 115 184 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) 116 185 { 117 186 u32 val; 118 187 119 - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_ARMISC); 188 + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); 120 189 if (on) 121 190 val |= PCIE_ELBI_SLV_DBI_ENABLE; 122 191 else 123 192 val &= ~PCIE_ELBI_SLV_DBI_ENABLE; 124 - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_ARMISC); 193 + exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); 125 194 } 126 195 127 196 static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) 128 197 { 129 198 u32 val; 130 199 131 - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET); 200 + val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); 132 201 val &= ~PCIE_CORE_RESET_ENABLE; 133 - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET); 134 - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_PWR_RESET); 135 - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_STICKY_RESET); 136 - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_NONSTICKY_RESET); 202 + exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); 203 + exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); 204 + exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); 137 205 } 138 206 139 207 static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) 140 208 { 141 209 u32 val; 142 210 143 - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET); 211 + val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); 144 212 val |= PCIE_CORE_RESET_ENABLE; 145 213 146 - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET); 147 - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_STICKY_RESET); 148 - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET); 149 - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET); 150 - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET); 214 + exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); 215 + exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); 216 + exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); 217 + exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); 218 + exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); 151 219 } 152 220 153 - static void exynos_pcie_assert_reset(struct exynos_pcie *ep) 221 + static int exynos_pcie_start_link(struct dw_pcie *pci) 154 222 { 155 - struct dw_pcie *pci = ep->pci; 156 - struct device *dev = pci->dev; 223 + struct exynos_pcie *ep = to_exynos_pcie(pci); 224 + u32 val; 157 225 158 - if (ep->reset_gpio >= 0) 159 - devm_gpio_request_one(dev, ep->reset_gpio, 160 - GPIOF_OUT_INIT_HIGH, "RESET"); 161 - } 162 - 163 - static int exynos_pcie_establish_link(struct exynos_pcie *ep) 164 - { 165 - struct dw_pcie *pci = ep->pci; 166 - struct pcie_port *pp = &pci->pp; 167 - struct device *dev = pci->dev; 168 - 169 - if (dw_pcie_link_up(pci)) { 170 - dev_err(dev, "Link already up\n"); 171 - return 0; 172 - } 173 - 174 - exynos_pcie_assert_core_reset(ep); 175 - 176 - phy_reset(ep->phy); 177 - 178 - exynos_pcie_writel(ep->mem_res->elbi_base, 1, 179 - PCIE_PWR_RESET); 180 - 181 - phy_power_on(ep->phy); 182 - phy_init(ep->phy); 183 - 184 - exynos_pcie_deassert_core_reset(ep); 185 - dw_pcie_setup_rc(pp); 186 - exynos_pcie_assert_reset(ep); 226 + val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); 227 + val &= ~PCIE_BUS_EN; 228 + exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); 187 229 188 230 /* assert LTSSM enable */ 189 - exynos_pcie_writel(ep->mem_res->elbi_base, PCIE_ELBI_LTSSM_ENABLE, 231 + exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, 190 232 PCIE_APP_LTSSM_ENABLE); 191 - 192 - /* check if the link is up or not */ 193 - if (!dw_pcie_wait_for_link(pci)) 194 - return 0; 195 - 196 - phy_power_off(ep->phy); 197 - return -ETIMEDOUT; 233 + return 0; 198 234 } 199 235 200 236 static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) 201 237 { 202 - u32 val; 238 + u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); 203 239 204 - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE); 205 - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE); 206 - } 207 - 208 - static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) 209 - { 210 - u32 val; 211 - 212 - /* enable INTX interrupt */ 213 - val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | 214 - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; 215 - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE); 240 + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); 216 241 } 217 242 218 243 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) ··· 179 292 return IRQ_HANDLED; 180 293 } 181 294 182 - static void exynos_pcie_msi_init(struct exynos_pcie *ep) 295 + static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) 183 296 { 184 - struct dw_pcie *pci = ep->pci; 185 - struct pcie_port *pp = &pci->pp; 186 - u32 val; 297 + u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | 298 + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; 187 299 188 - dw_pcie_msi_init(pp); 189 - 190 - /* enable MSI interrupt */ 191 - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL); 192 - val |= IRQ_MSI_ENABLE; 193 - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL); 194 - } 195 - 196 - static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep) 197 - { 198 - exynos_pcie_enable_irq_pulse(ep); 199 - 200 - if (IS_ENABLED(CONFIG_PCI_MSI)) 201 - exynos_pcie_msi_init(ep); 300 + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); 301 + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); 302 + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); 202 303 } 203 304 204 305 static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, ··· 245 370 static int exynos_pcie_link_up(struct dw_pcie *pci) 246 371 { 247 372 struct exynos_pcie *ep = to_exynos_pcie(pci); 248 - u32 val; 373 + u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); 249 374 250 - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_RDLH_LINKUP); 251 - if (val == PCIE_ELBI_LTSSM_ENABLE) 252 - return 1; 253 - 254 - return 0; 375 + return (val & PCIE_ELBI_XMLH_LINKUP); 255 376 } 256 377 257 378 static int exynos_pcie_host_init(struct pcie_port *pp) ··· 257 386 258 387 pp->bridge->ops = &exynos_pci_ops; 259 388 260 - exynos_pcie_establish_link(ep); 261 - exynos_pcie_enable_interrupts(ep); 389 + exynos_pcie_assert_core_reset(ep); 390 + 391 + phy_reset(ep->phy); 392 + phy_power_on(ep->phy); 393 + phy_init(ep->phy); 394 + 395 + exynos_pcie_deassert_core_reset(ep); 396 + exynos_pcie_enable_irq_pulse(ep); 262 397 263 398 return 0; 264 399 } ··· 273 396 .host_init = exynos_pcie_host_init, 274 397 }; 275 398 276 - static int __init exynos_add_pcie_port(struct exynos_pcie *ep, 399 + static int exynos_add_pcie_port(struct exynos_pcie *ep, 277 400 struct platform_device *pdev) 278 401 { 279 - struct dw_pcie *pci = ep->pci; 402 + struct dw_pcie *pci = &ep->pci; 280 403 struct pcie_port *pp = &pci->pp; 281 404 struct device *dev = &pdev->dev; 282 405 int ret; 283 406 284 - pp->irq = platform_get_irq(pdev, 1); 407 + pp->irq = platform_get_irq(pdev, 0); 285 408 if (pp->irq < 0) 286 409 return pp->irq; 287 410 288 411 ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, 289 - IRQF_SHARED, "exynos-pcie", ep); 412 + IRQF_SHARED, "exynos-pcie", ep); 290 413 if (ret) { 291 414 dev_err(dev, "failed to request irq\n"); 292 415 return ret; 293 416 } 294 417 295 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 296 - pp->msi_irq = platform_get_irq(pdev, 0); 297 - if (pp->msi_irq < 0) 298 - return pp->msi_irq; 299 - } 300 - 301 418 pp->ops = &exynos_pcie_host_ops; 419 + pp->msi_irq = -ENODEV; 302 420 303 421 ret = dw_pcie_host_init(pp); 304 422 if (ret) { ··· 308 436 .read_dbi = exynos_pcie_read_dbi, 309 437 .write_dbi = exynos_pcie_write_dbi, 310 438 .link_up = exynos_pcie_link_up, 439 + .start_link = exynos_pcie_start_link, 311 440 }; 312 441 313 - static int __init exynos_pcie_probe(struct platform_device *pdev) 442 + static int exynos_pcie_probe(struct platform_device *pdev) 314 443 { 315 444 struct device *dev = &pdev->dev; 316 - struct dw_pcie *pci; 317 445 struct exynos_pcie *ep; 318 446 struct device_node *np = dev->of_node; 319 447 int ret; ··· 322 450 if (!ep) 323 451 return -ENOMEM; 324 452 325 - pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 326 - if (!pci) 327 - return -ENOMEM; 328 - 329 - pci->dev = dev; 330 - pci->ops = &dw_pcie_ops; 331 - 332 - ep->pci = pci; 333 - ep->ops = (const struct exynos_pcie_ops *) 334 - of_device_get_match_data(dev); 335 - 336 - ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); 453 + ep->pci.dev = dev; 454 + ep->pci.ops = &dw_pcie_ops; 337 455 338 456 ep->phy = devm_of_phy_get(dev, np, NULL); 339 - if (IS_ERR(ep->phy)) { 340 - if (PTR_ERR(ep->phy) != -ENODEV) 341 - return PTR_ERR(ep->phy); 457 + if (IS_ERR(ep->phy)) 458 + return PTR_ERR(ep->phy); 342 459 343 - ep->phy = NULL; 460 + /* External Local Bus interface (ELBI) registers */ 461 + ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); 462 + if (IS_ERR(ep->elbi_base)) 463 + return PTR_ERR(ep->elbi_base); 464 + 465 + ep->clk = devm_clk_get(dev, "pcie"); 466 + if (IS_ERR(ep->clk)) { 467 + dev_err(dev, "Failed to get pcie rc clock\n"); 468 + return PTR_ERR(ep->clk); 344 469 } 345 470 346 - if (ep->ops && ep->ops->get_mem_resources) { 347 - ret = ep->ops->get_mem_resources(pdev, ep); 348 - if (ret) 349 - return ret; 471 + ep->bus_clk = devm_clk_get(dev, "pcie_bus"); 472 + if (IS_ERR(ep->bus_clk)) { 473 + dev_err(dev, "Failed to get pcie bus clock\n"); 474 + return PTR_ERR(ep->bus_clk); 350 475 } 351 476 352 - if (ep->ops && ep->ops->get_clk_resources && 353 - ep->ops->init_clk_resources) { 354 - ret = ep->ops->get_clk_resources(ep); 355 - if (ret) 356 - return ret; 357 - ret = ep->ops->init_clk_resources(ep); 358 - if (ret) 359 - return ret; 360 - } 477 + ep->supplies[0].supply = "vdd18"; 478 + ep->supplies[1].supply = "vdd10"; 479 + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies), 480 + ep->supplies); 481 + if (ret) 482 + return ret; 483 + 484 + ret = exynos_pcie_init_clk_resources(ep); 485 + if (ret) 486 + return ret; 487 + 488 + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); 489 + if (ret) 490 + return ret; 361 491 362 492 platform_set_drvdata(pdev, ep); 363 493 ··· 371 497 372 498 fail_probe: 373 499 phy_exit(ep->phy); 500 + exynos_pcie_deinit_clk_resources(ep); 501 + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); 374 502 375 - if (ep->ops && ep->ops->deinit_clk_resources) 376 - ep->ops->deinit_clk_resources(ep); 377 503 return ret; 378 504 } 379 505 ··· 381 507 { 382 508 struct exynos_pcie *ep = platform_get_drvdata(pdev); 383 509 384 - if (ep->ops && ep->ops->deinit_clk_resources) 385 - ep->ops->deinit_clk_resources(ep); 510 + dw_pcie_host_deinit(&ep->pci.pp); 511 + exynos_pcie_assert_core_reset(ep); 512 + phy_power_off(ep->phy); 513 + phy_exit(ep->phy); 514 + exynos_pcie_deinit_clk_resources(ep); 515 + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); 386 516 387 517 return 0; 388 518 } 389 519 520 + static int __maybe_unused exynos_pcie_suspend_noirq(struct device *dev) 521 + { 522 + struct exynos_pcie *ep = dev_get_drvdata(dev); 523 + 524 + exynos_pcie_assert_core_reset(ep); 525 + phy_power_off(ep->phy); 526 + phy_exit(ep->phy); 527 + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); 528 + 529 + return 0; 530 + } 531 + 532 + static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev) 533 + { 534 + struct exynos_pcie *ep = dev_get_drvdata(dev); 535 + struct dw_pcie *pci = &ep->pci; 536 + struct pcie_port *pp = &pci->pp; 537 + int ret; 538 + 539 + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); 540 + if (ret) 541 + return ret; 542 + 543 + /* exynos_pcie_host_init controls ep->phy */ 544 + exynos_pcie_host_init(pp); 545 + dw_pcie_setup_rc(pp); 546 + exynos_pcie_start_link(pci); 547 + return dw_pcie_wait_for_link(pci); 548 + } 549 + 550 + static const struct dev_pm_ops exynos_pcie_pm_ops = { 551 + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq, 552 + exynos_pcie_resume_noirq) 553 + }; 554 + 390 555 static const struct of_device_id exynos_pcie_of_match[] = { 391 - { 392 - .compatible = "samsung,exynos5440-pcie", 393 - .data = &exynos5440_pcie_ops 394 - }, 395 - {}, 556 + { .compatible = "samsung,exynos5433-pcie", }, 557 + { }, 396 558 }; 397 559 398 560 static struct platform_driver exynos_pcie_driver = { 561 + .probe = exynos_pcie_probe, 399 562 .remove = __exit_p(exynos_pcie_remove), 400 563 .driver = { 401 564 .name = "exynos-pcie", 402 565 .of_match_table = exynos_pcie_of_match, 566 + .pm = &exynos_pcie_pm_ops, 403 567 }, 404 568 }; 405 - 406 - /* Exynos PCIe driver does not allow module unload */ 407 - 408 - static int __init exynos_pcie_init(void) 409 - { 410 - return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe); 411 - } 412 - subsys_initcall(exynos_pcie_init); 569 + module_platform_driver(exynos_pcie_driver); 570 + MODULE_LICENSE("GPL v2"); 571 + MODULE_DEVICE_TABLE(of, exynos_pcie_of_match);

+6 -33

drivers/pci/controller/dwc/pci-imx6.c

··· 745 745 } 746 746 } 747 747 748 - static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) 748 + static int imx6_pcie_start_link(struct dw_pcie *pci) 749 749 { 750 - struct dw_pcie *pci = imx6_pcie->pci; 750 + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 751 751 struct device *dev = pci->dev; 752 752 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 753 753 u32 tmp; ··· 834 834 imx6_pcie_init_phy(imx6_pcie); 835 835 imx6_pcie_deassert_core_reset(imx6_pcie); 836 836 imx6_setup_phy_mpll(imx6_pcie); 837 - dw_pcie_setup_rc(pp); 838 - imx6_pcie_establish_link(imx6_pcie); 839 - dw_pcie_msi_init(pp); 840 837 841 838 return 0; 842 839 } ··· 842 845 .host_init = imx6_pcie_host_init, 843 846 }; 844 847 845 - static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie, 846 - struct platform_device *pdev) 847 - { 848 - struct dw_pcie *pci = imx6_pcie->pci; 849 - struct pcie_port *pp = &pci->pp; 850 - struct device *dev = &pdev->dev; 851 - int ret; 852 - 853 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 854 - pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 855 - if (pp->msi_irq < 0) 856 - return pp->msi_irq; 857 - } 858 - 859 - pp->ops = &imx6_pcie_host_ops; 860 - 861 - ret = dw_pcie_host_init(pp); 862 - if (ret) { 863 - dev_err(dev, "failed to initialize host\n"); 864 - return ret; 865 - } 866 - 867 - return 0; 868 - } 869 - 870 848 static const struct dw_pcie_ops dw_pcie_ops = { 871 - /* No special ops needed, but pcie-designware still expects this struct */ 849 + .start_link = imx6_pcie_start_link, 872 850 }; 873 851 874 852 #ifdef CONFIG_PM_SLEEP ··· 952 980 imx6_pcie_deassert_core_reset(imx6_pcie); 953 981 dw_pcie_setup_rc(pp); 954 982 955 - ret = imx6_pcie_establish_link(imx6_pcie); 983 + ret = imx6_pcie_start_link(imx6_pcie->pci); 956 984 if (ret < 0) 957 985 dev_info(dev, "pcie link is down after resume.\n"); 958 986 ··· 986 1014 987 1015 pci->dev = dev; 988 1016 pci->ops = &dw_pcie_ops; 1017 + pci->pp.ops = &imx6_pcie_host_ops; 989 1018 990 1019 imx6_pcie->pci = pci; 991 1020 imx6_pcie->drvdata = of_device_get_match_data(dev); ··· 1136 1163 if (ret) 1137 1164 return ret; 1138 1165 1139 - ret = imx6_add_pcie_port(imx6_pcie, pdev); 1166 + ret = dw_pcie_host_init(&pci->pp); 1140 1167 if (ret < 0) 1141 1168 return ret; 1142 1169

+12 -67

drivers/pci/controller/dwc/pci-keystone.c

··· 121 121 122 122 int msi_host_irq; 123 123 int num_lanes; 124 + u32 num_viewport; 124 125 struct phy **phy; 125 126 struct device_link **link; 126 127 struct device_node *msi_intc_np; ··· 273 272 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 274 273 } 275 274 276 - /* 277 - * Dummy function so that DW core doesn't configure MSI 278 - */ 279 - static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) 280 - { 281 - return 0; 282 - } 283 - 284 275 static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 285 276 { 286 277 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); ··· 387 394 static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 388 395 { 389 396 u32 val; 397 + u32 num_viewport = ks_pcie->num_viewport; 390 398 struct dw_pcie *pci = ks_pcie->pci; 391 399 struct pcie_port *pp = &pci->pp; 392 - u32 num_viewport = pci->num_viewport; 393 400 u64 start, end; 394 401 struct resource *mem; 395 402 int i; ··· 512 519 static int ks_pcie_start_link(struct dw_pcie *pci) 513 520 { 514 521 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 515 - struct device *dev = pci->dev; 516 522 u32 val; 517 - 518 - if (dw_pcie_link_up(pci)) { 519 - dev_dbg(dev, "link is already up\n"); 520 - return 0; 521 - } 522 523 523 524 /* Initiate Link Training */ 524 525 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); ··· 808 821 if (ret) 809 822 return ret; 810 823 811 - dw_pcie_setup_rc(pp); 812 - 813 824 ks_pcie_stop_link(pci); 814 825 ks_pcie_setup_rc_app_regs(ks_pcie); 815 826 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), ··· 826 841 "Asynchronous external abort"); 827 842 #endif 828 843 829 - ks_pcie_start_link(pci); 830 - dw_pcie_wait_for_link(pci); 831 - 832 844 return 0; 833 845 } 834 846 ··· 836 854 837 855 static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 838 856 .host_init = ks_pcie_host_init, 839 - .msi_host_init = ks_pcie_am654_msi_host_init, 840 857 }; 841 858 842 859 static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) ··· 843 862 struct keystone_pcie *ks_pcie = priv; 844 863 845 864 return ks_pcie_handle_error_irq(ks_pcie); 846 - } 847 - 848 - static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, 849 - struct platform_device *pdev) 850 - { 851 - struct dw_pcie *pci = ks_pcie->pci; 852 - struct pcie_port *pp = &pci->pp; 853 - struct device *dev = &pdev->dev; 854 - int ret; 855 - 856 - ret = dw_pcie_host_init(pp); 857 - if (ret) { 858 - dev_err(dev, "failed to initialize host\n"); 859 - return ret; 860 - } 861 - 862 - return 0; 863 865 } 864 866 865 867 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, ··· 940 976 .raise_irq = ks_pcie_am654_raise_irq, 941 977 .get_features = &ks_pcie_am654_get_features, 942 978 }; 943 - 944 - static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, 945 - struct platform_device *pdev) 946 - { 947 - int ret; 948 - struct dw_pcie_ep *ep; 949 - struct resource *res; 950 - struct device *dev = &pdev->dev; 951 - struct dw_pcie *pci = ks_pcie->pci; 952 - 953 - ep = &pci->ep; 954 - 955 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 956 - if (!res) 957 - return -EINVAL; 958 - 959 - ep->phys_base = res->start; 960 - ep->addr_size = resource_size(res); 961 - 962 - ret = dw_pcie_ep_init(ep); 963 - if (ret) { 964 - dev_err(dev, "failed to initialize endpoint\n"); 965 - return ret; 966 - } 967 - 968 - return 0; 969 - } 970 979 971 980 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 972 981 { ··· 1094 1157 struct resource *res; 1095 1158 unsigned int version; 1096 1159 void __iomem *base; 1160 + u32 num_viewport; 1097 1161 struct phy **phy; 1098 1162 u32 num_lanes; 1099 1163 char name[10]; ··· 1226 1288 goto err_get_sync; 1227 1289 } 1228 1290 1291 + ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1292 + if (ret < 0) { 1293 + dev_err(dev, "unable to read *num-viewport* property\n"); 1294 + goto err_get_sync; 1295 + } 1296 + 1229 1297 /* 1230 1298 * "Power Sequencing and Reset Signal Timings" table in 1231 1299 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 ··· 1245 1301 gpiod_set_value_cansleep(gpiod, 1); 1246 1302 } 1247 1303 1304 + ks_pcie->num_viewport = num_viewport; 1248 1305 pci->pp.ops = host_ops; 1249 - ret = ks_pcie_add_pcie_port(ks_pcie, pdev); 1306 + ret = dw_pcie_host_init(&pci->pp); 1250 1307 if (ret < 0) 1251 1308 goto err_get_sync; 1252 1309 break; ··· 1258 1313 } 1259 1314 1260 1315 pci->ep.ops = ep_ops; 1261 - ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); 1316 + ret = dw_pcie_ep_init(&pci->ep); 1262 1317 if (ret < 0) 1263 1318 goto err_get_sync; 1264 1319 break;

+2 -35

drivers/pci/controller/dwc/pci-layerscape-ep.c

··· 18 18 19 19 #include "pcie-designware.h" 20 20 21 - #define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/ 22 - 23 21 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) 24 22 25 23 struct ls_pcie_ep_drvdata { ··· 122 124 { }, 123 125 }; 124 126 125 - static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie, 126 - struct platform_device *pdev) 127 - { 128 - struct dw_pcie *pci = pcie->pci; 129 - struct device *dev = pci->dev; 130 - struct dw_pcie_ep *ep; 131 - struct resource *res; 132 - int ret; 133 - 134 - ep = &pci->ep; 135 - ep->ops = pcie->drvdata->ops; 136 - 137 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 138 - if (!res) 139 - return -EINVAL; 140 - 141 - ep->phys_base = res->start; 142 - ep->addr_size = resource_size(res); 143 - 144 - ret = dw_pcie_ep_init(ep); 145 - if (ret) { 146 - dev_err(dev, "failed to initialize endpoint\n"); 147 - return ret; 148 - } 149 - 150 - return 0; 151 - } 152 - 153 127 static int __init ls_pcie_ep_probe(struct platform_device *pdev) 154 128 { 155 129 struct device *dev = &pdev->dev; ··· 129 159 struct ls_pcie_ep *pcie; 130 160 struct pci_epc_features *ls_epc; 131 161 struct resource *dbi_base; 132 - int ret; 133 162 134 163 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 135 164 if (!pcie) ··· 157 188 if (IS_ERR(pci->dbi_base)) 158 189 return PTR_ERR(pci->dbi_base); 159 190 160 - pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET; 191 + pci->ep.ops = &ls_pcie_ep_ops; 161 192 162 193 platform_set_drvdata(pdev, pcie); 163 194 164 - ret = ls_add_pcie_ep(pcie, pdev); 165 - 166 - return ret; 195 + return dw_pcie_ep_init(&pci->ep); 167 196 } 168 197 169 198 static struct platform_driver ls_pcie_ep_driver = {

+2 -65

drivers/pci/controller/dwc/pci-layerscape.c

··· 83 83 iowrite32(val, pci->dbi_base + PCIE_STRFMR1); 84 84 } 85 85 86 - static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) 87 - { 88 - int i; 89 - 90 - for (i = 0; i < PCIE_IATU_NUM; i++) 91 - dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND); 92 - } 93 - 94 86 static int ls1021_pcie_link_up(struct dw_pcie *pci) 95 87 { 96 88 u32 state; ··· 128 136 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 129 137 struct ls_pcie *pcie = to_ls_pcie(pci); 130 138 131 - /* 132 - * Disable outbound windows configured by the bootloader to avoid 133 - * one transaction hitting multiple outbound windows. 134 - * dw_pcie_setup_rc() will reconfigure the outbound windows. 135 - */ 136 - ls_pcie_disable_outbound_atus(pcie); 137 139 ls_pcie_fix_error_response(pcie); 138 140 139 141 dw_pcie_dbi_ro_wr_en(pci); ··· 135 149 dw_pcie_dbi_ro_wr_dis(pci); 136 150 137 151 ls_pcie_drop_msg_tlp(pcie); 138 - 139 - dw_pcie_setup_rc(pp); 140 152 141 153 return 0; 142 154 } ··· 166 182 return ls_pcie_host_init(pp); 167 183 } 168 184 169 - static int ls_pcie_msi_host_init(struct pcie_port *pp) 170 - { 171 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 172 - struct device *dev = pci->dev; 173 - struct device_node *np = dev->of_node; 174 - struct device_node *msi_node; 175 - 176 - /* 177 - * The MSI domain is set by the generic of_msi_configure(). This 178 - * .msi_host_init() function keeps us from doing the default MSI 179 - * domain setup in dw_pcie_host_init() and also enforces the 180 - * requirement that "msi-parent" exists. 181 - */ 182 - msi_node = of_parse_phandle(np, "msi-parent", 0); 183 - if (!msi_node) { 184 - dev_err(dev, "failed to find msi-parent\n"); 185 - return -EINVAL; 186 - } 187 - 188 - of_node_put(msi_node); 189 - return 0; 190 - } 191 - 192 185 static const struct dw_pcie_host_ops ls1021_pcie_host_ops = { 193 186 .host_init = ls1021_pcie_host_init, 194 - .msi_host_init = ls_pcie_msi_host_init, 195 187 }; 196 188 197 189 static const struct dw_pcie_host_ops ls_pcie_host_ops = { 198 190 .host_init = ls_pcie_host_init, 199 - .msi_host_init = ls_pcie_msi_host_init, 200 191 }; 201 192 202 193 static const struct dw_pcie_ops dw_ls1021_pcie_ops = { ··· 232 273 { }, 233 274 }; 234 275 235 - static int __init ls_add_pcie_port(struct ls_pcie *pcie) 236 - { 237 - struct dw_pcie *pci = pcie->pci; 238 - struct pcie_port *pp = &pci->pp; 239 - struct device *dev = pci->dev; 240 - int ret; 241 - 242 - pp->ops = pcie->drvdata->ops; 243 - 244 - ret = dw_pcie_host_init(pp); 245 - if (ret) { 246 - dev_err(dev, "failed to initialize host\n"); 247 - return ret; 248 - } 249 - 250 - return 0; 251 - } 252 - 253 276 static int __init ls_pcie_probe(struct platform_device *pdev) 254 277 { 255 278 struct device *dev = &pdev->dev; 256 279 struct dw_pcie *pci; 257 280 struct ls_pcie *pcie; 258 281 struct resource *dbi_base; 259 - int ret; 260 282 261 283 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 262 284 if (!pcie) ··· 251 311 252 312 pci->dev = dev; 253 313 pci->ops = pcie->drvdata->dw_pcie_ops; 314 + pci->pp.ops = pcie->drvdata->ops; 254 315 255 316 pcie->pci = pci; 256 317 ··· 267 326 268 327 platform_set_drvdata(pdev, pcie); 269 328 270 - ret = ls_add_pcie_port(pcie); 271 - if (ret < 0) 272 - return ret; 273 - 274 - return 0; 329 + return dw_pcie_host_init(&pci->pp); 275 330 } 276 331 277 332 static struct platform_driver ls_pcie_driver = {

+10 -43

drivers/pci/controller/dwc/pci-meson.c

··· 231 231 gpiod_set_value_cansleep(mp->reset_gpio, 0); 232 232 } 233 233 234 - static void meson_pcie_init_dw(struct meson_pcie *mp) 234 + static void meson_pcie_ltssm_enable(struct meson_pcie *mp) 235 235 { 236 236 u32 val; 237 237 ··· 289 289 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); 290 290 } 291 291 292 - static int meson_pcie_establish_link(struct meson_pcie *mp) 292 + static int meson_pcie_start_link(struct dw_pcie *pci) 293 293 { 294 - struct dw_pcie *pci = &mp->pci; 295 - struct pcie_port *pp = &pci->pp; 294 + struct meson_pcie *mp = to_meson_pcie(pci); 296 295 297 - meson_pcie_init_dw(mp); 298 - meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); 299 - meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); 300 - 301 - dw_pcie_setup_rc(pp); 302 - 296 + meson_pcie_ltssm_enable(mp); 303 297 meson_pcie_assert_reset(mp); 304 298 305 - return dw_pcie_wait_for_link(pci); 299 + return 0; 306 300 } 307 301 308 302 static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, ··· 374 380 { 375 381 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 376 382 struct meson_pcie *mp = to_meson_pcie(pci); 377 - int ret; 378 383 379 384 pp->bridge->ops = &meson_pci_ops; 380 385 381 - ret = meson_pcie_establish_link(mp); 382 - if (ret) 383 - return ret; 384 - 385 - dw_pcie_msi_init(pp); 386 + meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); 387 + meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); 386 388 387 389 return 0; 388 390 } ··· 387 397 .host_init = meson_pcie_host_init, 388 398 }; 389 399 390 - static int meson_add_pcie_port(struct meson_pcie *mp, 391 - struct platform_device *pdev) 392 - { 393 - struct dw_pcie *pci = &mp->pci; 394 - struct pcie_port *pp = &pci->pp; 395 - struct device *dev = &pdev->dev; 396 - int ret; 397 - 398 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 399 - pp->msi_irq = platform_get_irq(pdev, 0); 400 - if (pp->msi_irq < 0) 401 - return pp->msi_irq; 402 - } 403 - 404 - pp->ops = &meson_pcie_host_ops; 405 - 406 - ret = dw_pcie_host_init(pp); 407 - if (ret) { 408 - dev_err(dev, "failed to initialize host\n"); 409 - return ret; 410 - } 411 - 412 - return 0; 413 - } 414 - 415 400 static const struct dw_pcie_ops dw_pcie_ops = { 416 401 .link_up = meson_pcie_link_up, 402 + .start_link = meson_pcie_start_link, 417 403 }; 418 404 419 405 static int meson_pcie_probe(struct platform_device *pdev) ··· 406 440 pci = &mp->pci; 407 441 pci->dev = dev; 408 442 pci->ops = &dw_pcie_ops; 443 + pci->pp.ops = &meson_pcie_host_ops; 409 444 pci->num_lanes = 1; 410 445 411 446 mp->phy = devm_phy_get(dev, "pcie"); ··· 453 486 454 487 platform_set_drvdata(pdev, mp); 455 488 456 - ret = meson_add_pcie_port(mp, pdev); 489 + ret = dw_pcie_host_init(&pci->pp); 457 490 if (ret < 0) { 458 491 dev_err(dev, "Add PCIe port failed, %d\n", ret); 459 492 goto err_phy;

+5 -36

drivers/pci/controller/dwc/pcie-al.c

··· 76 76 } 77 77 78 78 const struct pci_ecam_ops al_pcie_ops = { 79 - .bus_shift = 20, 80 79 .init = al_pcie_init, 81 80 .pci_ops = { 82 81 .map_bus = al_pcie_map_bus, ··· 136 137 struct al_pcie_reg_offsets reg_offsets; 137 138 struct al_pcie_target_bus_cfg target_bus_cfg; 138 139 }; 139 - 140 - #define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12) 141 140 142 141 #define to_al_pcie(x) dev_get_drvdata((x)->dev) 143 142 ··· 223 226 struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg; 224 227 unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask; 225 228 unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask; 226 - void __iomem *pci_base_addr; 227 - 228 - pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base + 229 - (busnr_ecam << 20) + 230 - PCIE_ECAM_DEVFN(devfn)); 231 229 232 230 if (busnr_reg != target_bus_cfg->reg_val) { 233 231 dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n", ··· 233 241 target_bus_cfg->reg_mask); 234 242 } 235 243 236 - return pci_base_addr + where; 244 + return pp->va_cfg0_base + PCIE_ECAM_OFFSET(busnr_ecam, devfn, where); 237 245 } 238 246 239 247 static struct pci_ops al_child_pci_ops = { ··· 256 264 257 265 target_bus_cfg = &pcie->target_bus_cfg; 258 266 259 - ecam_bus_mask = (pcie->ecam_size >> 20) - 1; 267 + ecam_bus_mask = (pcie->ecam_size >> PCIE_ECAM_BUS_SHIFT) - 1; 260 268 if (ecam_bus_mask > 255) { 261 269 dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n"); 262 270 ecam_bus_mask = 255; ··· 314 322 .host_init = al_pcie_host_init, 315 323 }; 316 324 317 - static int al_add_pcie_port(struct pcie_port *pp, 318 - struct platform_device *pdev) 319 - { 320 - struct device *dev = &pdev->dev; 321 - int ret; 322 - 323 - pp->ops = &al_pcie_host_ops; 324 - 325 - ret = dw_pcie_host_init(pp); 326 - if (ret) { 327 - dev_err(dev, "failed to initialize host\n"); 328 - return ret; 329 - } 330 - 331 - return 0; 332 - } 333 - 334 325 static const struct dw_pcie_ops dw_pcie_ops = { 335 326 }; 336 327 ··· 322 347 struct device *dev = &pdev->dev; 323 348 struct resource *controller_res; 324 349 struct resource *ecam_res; 325 - struct resource *dbi_res; 326 350 struct al_pcie *al_pcie; 327 351 struct dw_pcie *pci; 328 352 ··· 335 361 336 362 pci->dev = dev; 337 363 pci->ops = &dw_pcie_ops; 364 + pci->pp.ops = &al_pcie_host_ops; 338 365 339 366 al_pcie->pci = pci; 340 367 al_pcie->dev = dev; 341 - 342 - dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 343 - pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res); 344 - if (IS_ERR(pci->dbi_base)) 345 - return PTR_ERR(pci->dbi_base); 346 368 347 369 ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 348 370 if (!ecam_res) { ··· 356 386 return PTR_ERR(al_pcie->controller_base); 357 387 } 358 388 359 - dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n", 360 - dbi_res, controller_res); 389 + dev_dbg(dev, "From DT: controller_base: %pR\n", controller_res); 361 390 362 391 platform_set_drvdata(pdev, al_pcie); 363 392 364 - return al_add_pcie_port(&pci->pp, pdev); 393 + return dw_pcie_host_init(&pci->pp); 365 394 } 366 395 367 396 static const struct of_device_id al_pcie_of_match[] = {

+15 -22

drivers/pci/controller/dwc/pcie-armada8k.c

··· 154 154 return 0; 155 155 } 156 156 157 - static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) 157 + static int armada8k_pcie_start_link(struct dw_pcie *pci) 158 158 { 159 - struct dw_pcie *pci = pcie->pci; 160 159 u32 reg; 160 + 161 + /* Start LTSSM */ 162 + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 163 + reg |= PCIE_APP_LTSSM_EN; 164 + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 165 + 166 + return 0; 167 + } 168 + 169 + static int armada8k_pcie_host_init(struct pcie_port *pp) 170 + { 171 + u32 reg; 172 + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 161 173 162 174 if (!dw_pcie_link_up(pci)) { 163 175 /* Disable LTSSM state machine to enable configuration */ ··· 204 192 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | 205 193 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; 206 194 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); 207 - 208 - if (!dw_pcie_link_up(pci)) { 209 - /* Configuration done. Start LTSSM */ 210 - reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 211 - reg |= PCIE_APP_LTSSM_EN; 212 - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 213 - } 214 - 215 - /* Wait until the link becomes active again */ 216 - if (dw_pcie_wait_for_link(pci)) 217 - dev_err(pci->dev, "Link not up after reconfiguration\n"); 218 - } 219 - 220 - static int armada8k_pcie_host_init(struct pcie_port *pp) 221 - { 222 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 223 - struct armada8k_pcie *pcie = to_armada8k_pcie(pci); 224 - 225 - dw_pcie_setup_rc(pp); 226 - armada8k_pcie_establish_link(pcie); 227 195 228 196 return 0; 229 197 } ··· 261 269 262 270 static const struct dw_pcie_ops dw_pcie_ops = { 263 271 .link_up = armada8k_pcie_link_up, 272 + .start_link = armada8k_pcie_start_link, 264 273 }; 265 274 266 275 static int armada8k_pcie_probe(struct platform_device *pdev)

+7 -69

drivers/pci/controller/dwc/pcie-artpec6.c

··· 328 328 artpec6_pcie_init_phy(artpec6_pcie); 329 329 artpec6_pcie_deassert_core_reset(artpec6_pcie); 330 330 artpec6_pcie_wait_for_phy(artpec6_pcie); 331 - dw_pcie_setup_rc(pp); 332 - artpec6_pcie_establish_link(pci); 333 - dw_pcie_wait_for_link(pci); 334 - dw_pcie_msi_init(pp); 335 331 336 332 return 0; 337 333 } ··· 335 339 static const struct dw_pcie_host_ops artpec6_pcie_host_ops = { 336 340 .host_init = artpec6_pcie_host_init, 337 341 }; 338 - 339 - static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie, 340 - struct platform_device *pdev) 341 - { 342 - struct dw_pcie *pci = artpec6_pcie->pci; 343 - struct pcie_port *pp = &pci->pp; 344 - struct device *dev = pci->dev; 345 - int ret; 346 - 347 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 348 - pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 349 - if (pp->msi_irq < 0) 350 - return pp->msi_irq; 351 - } 352 - 353 - pp->ops = &artpec6_pcie_host_ops; 354 - 355 - ret = dw_pcie_host_init(pp); 356 - if (ret) { 357 - dev_err(dev, "failed to initialize host\n"); 358 - return ret; 359 - } 360 - 361 - return 0; 362 - } 363 342 364 343 static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep) 365 344 { ··· 374 403 .raise_irq = artpec6_pcie_raise_irq, 375 404 }; 376 405 377 - static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie, 378 - struct platform_device *pdev) 379 - { 380 - int ret; 381 - struct dw_pcie_ep *ep; 382 - struct resource *res; 383 - struct device *dev = &pdev->dev; 384 - struct dw_pcie *pci = artpec6_pcie->pci; 385 - 386 - ep = &pci->ep; 387 - ep->ops = &pcie_ep_ops; 388 - 389 - pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2"); 390 - if (IS_ERR(pci->dbi_base2)) 391 - return PTR_ERR(pci->dbi_base2); 392 - 393 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 394 - if (!res) 395 - return -EINVAL; 396 - 397 - ep->phys_base = res->start; 398 - ep->addr_size = resource_size(res); 399 - 400 - ret = dw_pcie_ep_init(ep); 401 - if (ret) { 402 - dev_err(dev, "failed to initialize endpoint\n"); 403 - return ret; 404 - } 405 - 406 - return 0; 407 - } 408 - 409 406 static int artpec6_pcie_probe(struct platform_device *pdev) 410 407 { 411 408 struct device *dev = &pdev->dev; ··· 408 469 artpec6_pcie->variant = variant; 409 470 artpec6_pcie->mode = mode; 410 471 411 - pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi"); 412 - if (IS_ERR(pci->dbi_base)) 413 - return PTR_ERR(pci->dbi_base); 414 - 415 472 artpec6_pcie->phy_base = 416 473 devm_platform_ioremap_resource_byname(pdev, "phy"); 417 474 if (IS_ERR(artpec6_pcie->phy_base)) ··· 426 491 if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_HOST)) 427 492 return -ENODEV; 428 493 429 - ret = artpec6_add_pcie_port(artpec6_pcie, pdev); 494 + pci->pp.ops = &artpec6_pcie_host_ops; 495 + 496 + ret = dw_pcie_host_init(&pci->pp); 430 497 if (ret < 0) 431 498 return ret; 432 499 break; ··· 441 504 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); 442 505 val &= ~PCIECFG_DEVICE_TYPE_MASK; 443 506 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); 444 - ret = artpec6_add_pcie_ep(artpec6_pcie, pdev); 445 - if (ret < 0) 446 - return ret; 507 + 508 + pci->ep.ops = &pcie_ep_ops; 509 + 510 + return dw_pcie_ep_init(&pci->ep); 447 511 break; 448 512 } 449 513 default:

+31 -27

drivers/pci/controller/dwc/pcie-designware-ep.c

··· 7 7 */ 8 8 9 9 #include <linux/of.h> 10 + #include <linux/platform_device.h> 10 11 11 12 #include "pcie-designware.h" 12 13 #include <linux/pci-epc.h> ··· 161 160 u32 free_win; 162 161 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 163 162 164 - free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows); 165 - if (free_win >= ep->num_ib_windows) { 163 + free_win = find_first_zero_bit(ep->ib_window_map, pci->num_ib_windows); 164 + if (free_win >= pci->num_ib_windows) { 166 165 dev_err(pci->dev, "No free inbound window\n"); 167 166 return -EINVAL; 168 167 } ··· 187 186 u32 free_win; 188 187 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 189 188 190 - free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows); 191 - if (free_win >= ep->num_ob_windows) { 189 + free_win = find_first_zero_bit(ep->ob_window_map, pci->num_ob_windows); 190 + if (free_win >= pci->num_ob_windows) { 192 191 dev_err(pci->dev, "No free outbound window\n"); 193 192 return -EINVAL; 194 193 } ··· 264 263 u32 *atu_index) 265 264 { 266 265 u32 index; 266 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 267 267 268 - for (index = 0; index < ep->num_ob_windows; index++) { 268 + for (index = 0; index < pci->num_ob_windows; index++) { 269 269 if (ep->outbound_addr[index] != addr) 270 270 continue; 271 271 *atu_index = index; ··· 678 676 int ret; 679 677 void *addr; 680 678 u8 func_no; 679 + struct resource *res; 681 680 struct pci_epc *epc; 682 681 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 683 682 struct device *dev = pci->dev; 683 + struct platform_device *pdev = to_platform_device(dev); 684 684 struct device_node *np = dev->of_node; 685 685 const struct pci_epc_features *epc_features; 686 686 struct dw_pcie_ep_func *ep_func; 687 687 688 688 INIT_LIST_HEAD(&ep->func_list); 689 689 690 - if (!pci->dbi_base || !pci->dbi_base2) { 691 - dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); 692 - return -EINVAL; 690 + if (!pci->dbi_base) { 691 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 692 + pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 693 + if (IS_ERR(pci->dbi_base)) 694 + return PTR_ERR(pci->dbi_base); 693 695 } 694 696 695 - ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); 696 - if (ret < 0) { 697 - dev_err(dev, "Unable to read *num-ib-windows* property\n"); 698 - return ret; 699 - } 700 - if (ep->num_ib_windows > MAX_IATU_IN) { 701 - dev_err(dev, "Invalid *num-ib-windows*\n"); 702 - return -EINVAL; 697 + if (!pci->dbi_base2) { 698 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 699 + if (!res) 700 + pci->dbi_base2 = pci->dbi_base + SZ_4K; 701 + else { 702 + pci->dbi_base2 = devm_pci_remap_cfg_resource(dev, res); 703 + if (IS_ERR(pci->dbi_base2)) 704 + return PTR_ERR(pci->dbi_base2); 705 + } 703 706 } 704 707 705 - ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows); 706 - if (ret < 0) { 707 - dev_err(dev, "Unable to read *num-ob-windows* property\n"); 708 - return ret; 709 - } 710 - if (ep->num_ob_windows > MAX_IATU_OUT) { 711 - dev_err(dev, "Invalid *num-ob-windows*\n"); 708 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 709 + if (!res) 712 710 return -EINVAL; 713 - } 711 + 712 + ep->phys_base = res->start; 713 + ep->addr_size = resource_size(res); 714 714 715 715 ep->ib_window_map = devm_kcalloc(dev, 716 - BITS_TO_LONGS(ep->num_ib_windows), 716 + BITS_TO_LONGS(pci->num_ib_windows), 717 717 sizeof(long), 718 718 GFP_KERNEL); 719 719 if (!ep->ib_window_map) 720 720 return -ENOMEM; 721 721 722 722 ep->ob_window_map = devm_kcalloc(dev, 723 - BITS_TO_LONGS(ep->num_ob_windows), 723 + BITS_TO_LONGS(pci->num_ob_windows), 724 724 sizeof(long), 725 725 GFP_KERNEL); 726 726 if (!ep->ob_window_map) 727 727 return -ENOMEM; 728 728 729 - addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t), 729 + addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t), 730 730 GFP_KERNEL); 731 731 if (!addr) 732 732 return -ENOMEM;

+92 -53

drivers/pci/controller/dwc/pcie-designware-host.c

··· 256 256 return 0; 257 257 } 258 258 259 - void dw_pcie_free_msi(struct pcie_port *pp) 259 + static void dw_pcie_free_msi(struct pcie_port *pp) 260 260 { 261 261 if (pp->msi_irq) { 262 262 irq_set_chained_handler(pp->msi_irq, NULL); ··· 275 275 } 276 276 } 277 277 278 - void dw_pcie_msi_init(struct pcie_port *pp) 278 + static void dw_pcie_msi_init(struct pcie_port *pp) 279 279 { 280 280 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 281 281 u64 msi_target = (u64)pp->msi_data; 282 282 283 - if (!IS_ENABLED(CONFIG_PCI_MSI)) 283 + if (!pci_msi_enabled() || !pp->has_msi_ctrl) 284 284 return; 285 285 286 286 /* Program the msi_data */ 287 287 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); 288 288 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); 289 289 } 290 - EXPORT_SYMBOL_GPL(dw_pcie_msi_init); 291 290 292 291 int dw_pcie_host_init(struct pcie_port *pp) 293 292 { ··· 307 308 pp->cfg0_base = cfg_res->start; 308 309 } else if (!pp->va_cfg0_base) { 309 310 dev_err(dev, "Missing *config* reg space\n"); 311 + } 312 + 313 + if (!pci->dbi_base) { 314 + struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 315 + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res); 316 + if (IS_ERR(pci->dbi_base)) 317 + return PTR_ERR(pci->dbi_base); 310 318 } 311 319 312 320 bridge = devm_pci_alloc_host_bridge(dev, 0); ··· 356 350 } 357 351 } 358 352 359 - ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); 360 - if (ret) 361 - pci->num_viewport = 2; 362 - 363 353 if (pci->link_gen < 1) 364 354 pci->link_gen = of_pci_get_max_link_speed(np); 365 355 366 356 if (pci_msi_enabled()) { 367 - /* 368 - * If a specific SoC driver needs to change the 369 - * default number of vectors, it needs to implement 370 - * the set_num_vectors callback. 371 - */ 372 - if (!pp->ops->set_num_vectors) { 373 - pp->num_vectors = MSI_DEF_NUM_VECTORS; 374 - } else { 375 - pp->ops->set_num_vectors(pp); 357 + pp->has_msi_ctrl = !(pp->ops->msi_host_init || 358 + of_property_read_bool(np, "msi-parent") || 359 + of_property_read_bool(np, "msi-map")); 376 360 377 - if (pp->num_vectors > MAX_MSI_IRQS || 378 - pp->num_vectors == 0) { 379 - dev_err(dev, 380 - "Invalid number of vectors\n"); 381 - return -EINVAL; 382 - } 361 + if (!pp->num_vectors) { 362 + pp->num_vectors = MSI_DEF_NUM_VECTORS; 363 + } else if (pp->num_vectors > MAX_MSI_IRQS) { 364 + dev_err(dev, "Invalid number of vectors\n"); 365 + return -EINVAL; 383 366 } 384 367 385 - if (!pp->ops->msi_host_init) { 368 + if (pp->ops->msi_host_init) { 369 + ret = pp->ops->msi_host_init(pp); 370 + if (ret < 0) 371 + return ret; 372 + } else if (pp->has_msi_ctrl) { 373 + if (!pp->msi_irq) { 374 + pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi"); 375 + if (pp->msi_irq < 0) { 376 + pp->msi_irq = platform_get_irq(pdev, 0); 377 + if (pp->msi_irq < 0) 378 + return pp->msi_irq; 379 + } 380 + } 381 + 386 382 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; 387 383 388 384 ret = dw_pcie_allocate_domains(pp); 389 385 if (ret) 390 386 return ret; 391 387 392 - if (pp->msi_irq) 388 + if (pp->msi_irq > 0) 393 389 irq_set_chained_handler_and_data(pp->msi_irq, 394 390 dw_chained_msi_isr, 395 391 pp); 392 + 393 + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); 394 + if (!ret) { 395 + dev_warn(pci->dev, 396 + "Failed to set DMA mask to 32-bit. " 397 + "Devices with only 32-bit MSI support" 398 + " may not work properly\n"); 399 + } 396 400 397 401 pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, 398 402 sizeof(pp->msi_msg), ··· 413 397 pp->msi_data = 0; 414 398 goto err_free_msi; 415 399 } 416 - } else { 417 - ret = pp->ops->msi_host_init(pp); 418 - if (ret < 0) 419 - return ret; 420 400 } 421 401 } 422 402 ··· 426 414 goto err_free_msi; 427 415 } 428 416 417 + dw_pcie_setup_rc(pp); 418 + dw_pcie_msi_init(pp); 419 + 420 + if (!dw_pcie_link_up(pci) && pci->ops->start_link) { 421 + ret = pci->ops->start_link(pci); 422 + if (ret) 423 + goto err_free_msi; 424 + } 425 + 426 + /* Ignore errors, the link may come up later */ 427 + dw_pcie_wait_for_link(pci); 428 + 429 429 bridge->sysdata = pp; 430 430 431 431 ret = pci_host_probe(bridge); ··· 445 421 return 0; 446 422 447 423 err_free_msi: 448 - if (pci_msi_enabled() && !pp->ops->msi_host_init) 424 + if (pp->has_msi_ctrl) 449 425 dw_pcie_free_msi(pp); 450 426 return ret; 451 427 } ··· 455 431 { 456 432 pci_stop_root_bus(pp->bridge->bus); 457 433 pci_remove_root_bus(pp->bridge->bus); 458 - if (pci_msi_enabled() && !pp->ops->msi_host_init) 434 + if (pp->has_msi_ctrl) 459 435 dw_pcie_free_msi(pp); 460 436 } 461 437 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); ··· 488 464 type = PCIE_ATU_TYPE_CFG1; 489 465 490 466 491 - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 492 - type, pp->cfg0_base, 493 - busdev, pp->cfg0_size); 467 + dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, pp->cfg0_size); 494 468 495 469 return pp->va_cfg0_base + where; 496 470 } ··· 502 480 503 481 ret = pci_generic_config_read(bus, devfn, where, size, val); 504 482 505 - if (!ret && pci->num_viewport <= 2) 506 - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 507 - PCIE_ATU_TYPE_IO, pp->io_base, 483 + if (!ret && pci->io_cfg_atu_shared) 484 + dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base, 508 485 pp->io_bus_addr, pp->io_size); 509 486 510 487 return ret; ··· 518 497 519 498 ret = pci_generic_config_write(bus, devfn, where, size, val); 520 499 521 - if (!ret && pci->num_viewport <= 2) 522 - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 523 - PCIE_ATU_TYPE_IO, pp->io_base, 500 + if (!ret && pci->io_cfg_atu_shared) 501 + dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base, 524 502 pp->io_bus_addr, pp->io_size); 525 503 526 504 return ret; ··· 551 531 552 532 void dw_pcie_setup_rc(struct pcie_port *pp) 553 533 { 534 + int i; 554 535 u32 val, ctrl, num_ctrls; 555 536 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 556 537 ··· 563 542 564 543 dw_pcie_setup(pci); 565 544 566 - if (pci_msi_enabled() && !pp->ops->msi_host_init) { 545 + if (pp->has_msi_ctrl) { 567 546 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 568 547 569 548 /* Initialize IRQ Status array */ ··· 601 580 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 602 581 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 603 582 583 + /* Ensure all outbound windows are disabled so there are multiple matches */ 584 + for (i = 0; i < pci->num_ob_windows; i++) 585 + dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); 586 + 604 587 /* 605 588 * If the platform provides its own child bus config accesses, it means 606 589 * the platform uses its own address translation component rather than 607 590 * ATU, so we should not program the ATU here. 608 591 */ 609 592 if (pp->bridge->child_ops == &dw_child_pcie_ops) { 610 - struct resource_entry *tmp, *entry = NULL; 593 + int atu_idx = 0; 594 + struct resource_entry *entry; 611 595 612 596 /* Get last memory resource entry */ 613 - resource_list_for_each_entry(tmp, &pp->bridge->windows) 614 - if (resource_type(tmp->res) == IORESOURCE_MEM) 615 - entry = tmp; 597 + resource_list_for_each_entry(entry, &pp->bridge->windows) { 598 + if (resource_type(entry->res) != IORESOURCE_MEM) 599 + continue; 616 600 617 - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, 618 - PCIE_ATU_TYPE_MEM, entry->res->start, 619 - entry->res->start - entry->offset, 620 - resource_size(entry->res)); 621 - if (pci->num_viewport > 2) 622 - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2, 623 - PCIE_ATU_TYPE_IO, pp->io_base, 624 - pp->io_bus_addr, pp->io_size); 601 + if (pci->num_ob_windows <= ++atu_idx) 602 + break; 603 + 604 + dw_pcie_prog_outbound_atu(pci, atu_idx, 605 + PCIE_ATU_TYPE_MEM, entry->res->start, 606 + entry->res->start - entry->offset, 607 + resource_size(entry->res)); 608 + } 609 + 610 + if (pp->io_size) { 611 + if (pci->num_ob_windows > ++atu_idx) 612 + dw_pcie_prog_outbound_atu(pci, atu_idx, 613 + PCIE_ATU_TYPE_IO, pp->io_base, 614 + pp->io_bus_addr, pp->io_size); 615 + else 616 + pci->io_cfg_atu_shared = true; 617 + } 618 + 619 + if (pci->num_ob_windows <= atu_idx) 620 + dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)", 621 + pci->num_ob_windows); 625 622 } 626 623 627 624 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);

+3 -67

drivers/pci/controller/dwc/pcie-designware-plat.c

··· 33 33 34 34 static const struct of_device_id dw_plat_pcie_of_match[]; 35 35 36 - static int dw_plat_pcie_host_init(struct pcie_port *pp) 37 - { 38 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 39 - 40 - dw_pcie_setup_rc(pp); 41 - dw_pcie_wait_for_link(pci); 42 - dw_pcie_msi_init(pp); 43 - 44 - return 0; 45 - } 46 - 47 - static void dw_plat_set_num_vectors(struct pcie_port *pp) 48 - { 49 - pp->num_vectors = MAX_MSI_IRQS; 50 - } 51 - 52 36 static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { 53 - .host_init = dw_plat_pcie_host_init, 54 - .set_num_vectors = dw_plat_set_num_vectors, 55 37 }; 56 38 57 39 static int dw_plat_pcie_establish_link(struct dw_pcie *pci) ··· 104 122 if (pp->irq < 0) 105 123 return pp->irq; 106 124 107 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 108 - pp->msi_irq = platform_get_irq(pdev, 0); 109 - if (pp->msi_irq < 0) 110 - return pp->msi_irq; 111 - } 112 - 125 + pp->num_vectors = MAX_MSI_IRQS; 113 126 pp->ops = &dw_plat_pcie_host_ops; 114 127 115 128 ret = dw_pcie_host_init(pp); ··· 116 139 return 0; 117 140 } 118 141 119 - static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie, 120 - struct platform_device *pdev) 121 - { 122 - int ret; 123 - struct dw_pcie_ep *ep; 124 - struct resource *res; 125 - struct device *dev = &pdev->dev; 126 - struct dw_pcie *pci = dw_plat_pcie->pci; 127 - 128 - ep = &pci->ep; 129 - ep->ops = &pcie_ep_ops; 130 - 131 - pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2"); 132 - if (IS_ERR(pci->dbi_base2)) 133 - return PTR_ERR(pci->dbi_base2); 134 - 135 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 136 - if (!res) 137 - return -EINVAL; 138 - 139 - ep->phys_base = res->start; 140 - ep->addr_size = resource_size(res); 141 - 142 - ret = dw_pcie_ep_init(ep); 143 - if (ret) { 144 - dev_err(dev, "Failed to initialize endpoint\n"); 145 - return ret; 146 - } 147 - return 0; 148 - } 149 - 150 142 static int dw_plat_pcie_probe(struct platform_device *pdev) 151 143 { 152 144 struct device *dev = &pdev->dev; 153 145 struct dw_plat_pcie *dw_plat_pcie; 154 146 struct dw_pcie *pci; 155 - struct resource *res; /* Resource from DT */ 156 147 int ret; 157 148 const struct of_device_id *match; 158 149 const struct dw_plat_pcie_of_data *data; ··· 147 202 dw_plat_pcie->pci = pci; 148 203 dw_plat_pcie->mode = mode; 149 204 150 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 151 - if (!res) 152 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 153 - 154 - pci->dbi_base = devm_ioremap_resource(dev, res); 155 - if (IS_ERR(pci->dbi_base)) 156 - return PTR_ERR(pci->dbi_base); 157 - 158 205 platform_set_drvdata(pdev, dw_plat_pcie); 159 206 160 207 switch (dw_plat_pcie->mode) { ··· 162 225 if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP)) 163 226 return -ENODEV; 164 227 165 - ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev); 166 - if (ret < 0) 167 - return ret; 228 + pci->ep.ops = &pcie_ep_ops; 229 + return dw_pcie_ep_init(&pci->ep); 168 230 break; 169 231 default: 170 232 dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);

+93 -12

drivers/pci/controller/dwc/pcie-designware.c

··· 228 228 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, 229 229 int index, int type, 230 230 u64 cpu_addr, u64 pci_addr, 231 - u32 size) 231 + u64 size) 232 232 { 233 233 u32 retries, val; 234 234 u64 limit_addr = cpu_addr + size - 1; ··· 245 245 lower_32_bits(pci_addr)); 246 246 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 247 247 upper_32_bits(pci_addr)); 248 - dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 249 - type | PCIE_ATU_FUNC_NUM(func_no)); 248 + val = type | PCIE_ATU_FUNC_NUM(func_no); 249 + val = upper_32_bits(size - 1) ? 250 + val | PCIE_ATU_INCREASE_REGION_SIZE : val; 251 + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val); 250 252 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 251 253 PCIE_ATU_ENABLE); 252 254 ··· 269 267 270 268 static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, 271 269 int index, int type, u64 cpu_addr, 272 - u64 pci_addr, u32 size) 270 + u64 pci_addr, u64 size) 273 271 { 274 272 u32 retries, val; 275 273 ··· 313 311 } 314 312 315 313 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, 316 - u64 cpu_addr, u64 pci_addr, u32 size) 314 + u64 cpu_addr, u64 pci_addr, u64 size) 317 315 { 318 316 __dw_pcie_prog_outbound_atu(pci, 0, index, type, 319 317 cpu_addr, pci_addr, size); ··· 546 544 return 0; 547 545 } 548 546 547 + static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci) 548 + { 549 + int max_region, i, ob = 0, ib = 0; 550 + u32 val; 551 + 552 + max_region = min((int)pci->atu_size / 512, 256); 553 + 554 + for (i = 0; i < max_region; i++) { 555 + dw_pcie_writel_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET, 556 + 0x11110000); 557 + 558 + val = dw_pcie_readl_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET); 559 + if (val == 0x11110000) 560 + ob++; 561 + else 562 + break; 563 + } 564 + 565 + for (i = 0; i < max_region; i++) { 566 + dw_pcie_writel_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET, 567 + 0x11110000); 568 + 569 + val = dw_pcie_readl_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET); 570 + if (val == 0x11110000) 571 + ib++; 572 + else 573 + break; 574 + } 575 + pci->num_ib_windows = ib; 576 + pci->num_ob_windows = ob; 577 + } 578 + 579 + static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci) 580 + { 581 + int max_region, i, ob = 0, ib = 0; 582 + u32 val; 583 + 584 + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); 585 + max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; 586 + 587 + for (i = 0; i < max_region; i++) { 588 + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | i); 589 + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000); 590 + val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET); 591 + if (val == 0x11110000) 592 + ob++; 593 + else 594 + break; 595 + } 596 + 597 + for (i = 0; i < max_region; i++) { 598 + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | i); 599 + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000); 600 + val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET); 601 + if (val == 0x11110000) 602 + ib++; 603 + else 604 + break; 605 + } 606 + 607 + pci->num_ib_windows = ib; 608 + pci->num_ob_windows = ob; 609 + } 610 + 549 611 void dw_pcie_setup(struct dw_pcie *pci) 550 612 { 551 613 u32 val; ··· 620 554 if (pci->version >= 0x480A || (!pci->version && 621 555 dw_pcie_iatu_unroll_enabled(pci))) { 622 556 pci->iatu_unroll_enabled = true; 623 - if (!pci->atu_base) 624 - pci->atu_base = 625 - devm_platform_ioremap_resource_byname(pdev, "atu"); 626 - if (IS_ERR(pci->atu_base)) 627 - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 628 - } 629 - dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? 557 + if (!pci->atu_base) { 558 + struct resource *res = 559 + platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 560 + if (res) 561 + pci->atu_size = resource_size(res); 562 + pci->atu_base = devm_ioremap_resource(dev, res); 563 + if (IS_ERR(pci->atu_base)) 564 + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 565 + } 566 + 567 + if (!pci->atu_size) 568 + /* Pick a minimal default, enough for 8 in and 8 out windows */ 569 + pci->atu_size = SZ_4K; 570 + 571 + dw_pcie_iatu_detect_regions_unroll(pci); 572 + } else 573 + dw_pcie_iatu_detect_regions(pci); 574 + 575 + dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? 630 576 "enabled" : "disabled"); 577 + 578 + dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound", 579 + pci->num_ob_windows, pci->num_ib_windows); 631 580 632 581 if (pci->link_gen > 0) 633 582 dw_pcie_link_set_max_speed(pci, pci->link_gen);

+8 -19

drivers/pci/controller/dwc/pcie-designware.h

··· 80 80 #define PCIE_ATU_VIEWPORT 0x900 81 81 #define PCIE_ATU_REGION_INBOUND BIT(31) 82 82 #define PCIE_ATU_REGION_OUTBOUND 0 83 - #define PCIE_ATU_REGION_INDEX2 0x2 84 - #define PCIE_ATU_REGION_INDEX1 0x1 85 - #define PCIE_ATU_REGION_INDEX0 0x0 86 83 #define PCIE_ATU_CR1 0x904 84 + #define PCIE_ATU_INCREASE_REGION_SIZE BIT(13) 87 85 #define PCIE_ATU_TYPE_MEM 0x0 88 86 #define PCIE_ATU_TYPE_IO 0x2 89 87 #define PCIE_ATU_TYPE_CFG0 0x4 ··· 172 174 173 175 struct dw_pcie_host_ops { 174 176 int (*host_init)(struct pcie_port *pp); 175 - void (*set_num_vectors)(struct pcie_port *pp); 176 177 int (*msi_host_init)(struct pcie_port *pp); 177 178 }; 178 179 179 180 struct pcie_port { 181 + bool has_msi_ctrl:1; 180 182 u64 cfg0_base; 181 183 void __iomem *va_cfg0_base; 182 184 u32 cfg0_size; ··· 237 239 phys_addr_t *outbound_addr; 238 240 unsigned long *ib_window_map; 239 241 unsigned long *ob_window_map; 240 - u32 num_ib_windows; 241 - u32 num_ob_windows; 242 242 void __iomem *msi_mem; 243 243 phys_addr_t msi_mem_phys; 244 244 struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; ··· 261 265 void __iomem *dbi_base2; 262 266 /* Used when iatu_unroll_enabled is true */ 263 267 void __iomem *atu_base; 264 - u32 num_viewport; 265 - u8 iatu_unroll_enabled; 268 + size_t atu_size; 269 + u32 num_ib_windows; 270 + u32 num_ob_windows; 266 271 struct pcie_port pp; 267 272 struct dw_pcie_ep ep; 268 273 const struct dw_pcie_ops *ops; ··· 271 274 int num_lanes; 272 275 int link_gen; 273 276 u8 n_fts[2]; 277 + bool iatu_unroll_enabled: 1; 278 + bool io_cfg_atu_shared: 1; 274 279 }; 275 280 276 281 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) ··· 294 295 int dw_pcie_wait_for_link(struct dw_pcie *pci); 295 296 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, 296 297 int type, u64 cpu_addr, u64 pci_addr, 297 - u32 size); 298 + u64 size); 298 299 void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, 299 300 int type, u64 cpu_addr, u64 pci_addr, 300 301 u32 size); ··· 364 365 365 366 #ifdef CONFIG_PCIE_DW_HOST 366 367 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); 367 - void dw_pcie_msi_init(struct pcie_port *pp); 368 - void dw_pcie_free_msi(struct pcie_port *pp); 369 368 void dw_pcie_setup_rc(struct pcie_port *pp); 370 369 int dw_pcie_host_init(struct pcie_port *pp); 371 370 void dw_pcie_host_deinit(struct pcie_port *pp); ··· 374 377 static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) 375 378 { 376 379 return IRQ_NONE; 377 - } 378 - 379 - static inline void dw_pcie_msi_init(struct pcie_port *pp) 380 - { 381 - } 382 - 383 - static inline void dw_pcie_free_msi(struct pcie_port *pp) 384 - { 385 380 } 386 381 387 382 static inline void dw_pcie_setup_rc(struct pcie_port *pp)

-2

drivers/pci/controller/dwc/pcie-hisi.c

··· 100 100 } 101 101 102 102 const struct pci_ecam_ops hisi_pcie_ops = { 103 - .bus_shift = 20, 104 103 .init = hisi_pcie_init, 105 104 .pci_ops = { 106 105 .map_bus = hisi_pcie_map_bus, ··· 134 135 } 135 136 136 137 static const struct pci_ecam_ops hisi_pcie_platform_ops = { 137 - .bus_shift = 20, 138 138 .init = hisi_pcie_platform_init, 139 139 .pci_ops = { 140 140 .map_bus = hisi_pcie_map_bus,

+12 -25

drivers/pci/controller/dwc/pcie-histb.c

··· 169 169 return 0; 170 170 } 171 171 172 - static int histb_pcie_establish_link(struct pcie_port *pp) 172 + static int histb_pcie_start_link(struct dw_pcie *pci) 173 173 { 174 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 175 174 struct histb_pcie *hipcie = to_histb_pcie(pci); 176 175 u32 regval; 177 - 178 - if (dw_pcie_link_up(pci)) { 179 - dev_info(pci->dev, "Link already up\n"); 180 - return 0; 181 - } 182 - 183 - /* PCIe RC work mode */ 184 - regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0); 185 - regval &= ~PCIE_DEVICE_TYPE_MASK; 186 - regval |= PCIE_WM_RC; 187 - histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval); 188 - 189 - /* setup root complex */ 190 - dw_pcie_setup_rc(pp); 191 176 192 177 /* assert LTSSM enable */ 193 178 regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7); 194 179 regval |= PCIE_APP_LTSSM_ENABLE; 195 180 histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval); 196 181 197 - return dw_pcie_wait_for_link(pci); 182 + return 0; 198 183 } 199 184 200 185 static int histb_pcie_host_init(struct pcie_port *pp) 201 186 { 187 + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 188 + struct histb_pcie *hipcie = to_histb_pcie(pci); 189 + u32 regval; 190 + 202 191 pp->bridge->ops = &histb_pci_ops; 203 192 204 - histb_pcie_establish_link(pp); 205 - dw_pcie_msi_init(pp); 193 + /* PCIe RC work mode */ 194 + regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0); 195 + regval &= ~PCIE_DEVICE_TYPE_MASK; 196 + regval |= PCIE_WM_RC; 197 + histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval); 206 198 207 199 return 0; 208 200 } ··· 292 300 .read_dbi = histb_pcie_read_dbi, 293 301 .write_dbi = histb_pcie_write_dbi, 294 302 .link_up = histb_pcie_link_up, 303 + .start_link = histb_pcie_start_link, 295 304 }; 296 305 297 306 static int histb_pcie_probe(struct platform_device *pdev) ··· 391 398 if (IS_ERR(hipcie->bus_reset)) { 392 399 dev_err(dev, "couldn't get bus reset\n"); 393 400 return PTR_ERR(hipcie->bus_reset); 394 - } 395 - 396 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 397 - pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 398 - if (pp->msi_irq < 0) 399 - return pp->msi_irq; 400 401 } 401 402 402 403 hipcie->phy = devm_phy_get(dev, "phy");

+16 -51

drivers/pci/controller/dwc/pcie-intel-gw.c

··· 58 58 59 59 struct intel_pcie_soc { 60 60 unsigned int pcie_ver; 61 - unsigned int pcie_atu_offset; 62 - u32 num_viewport; 63 61 }; 64 62 65 63 struct intel_pcie_port { ··· 151 153 pci->n_fts[0] = PORT_AFR_N_FTS_GEN12_DFT; 152 154 } 153 155 154 - static void intel_pcie_rc_setup(struct intel_pcie_port *lpp) 155 - { 156 - intel_pcie_ltssm_disable(lpp); 157 - intel_pcie_link_setup(lpp); 158 - intel_pcie_init_n_fts(&lpp->pci); 159 - dw_pcie_setup_rc(&lpp->pci.pp); 160 - dw_pcie_upconfig_setup(&lpp->pci); 161 - } 162 - 163 156 static int intel_pcie_ep_rst_init(struct intel_pcie_port *lpp) 164 157 { 165 158 struct device *dev = lpp->pci.dev; ··· 202 213 gpiod_set_value_cansleep(lpp->reset_gpio, 0); 203 214 } 204 215 205 - static int intel_pcie_app_logic_setup(struct intel_pcie_port *lpp) 206 - { 207 - intel_pcie_device_rst_deassert(lpp); 208 - intel_pcie_ltssm_enable(lpp); 209 - 210 - return dw_pcie_wait_for_link(&lpp->pci); 211 - } 212 - 213 216 static void intel_pcie_core_irq_disable(struct intel_pcie_port *lpp) 214 217 { 215 218 pcie_app_wr(lpp, PCIE_APP_IRNEN, 0); ··· 214 233 struct dw_pcie *pci = &lpp->pci; 215 234 struct device *dev = pci->dev; 216 235 int ret; 217 - 218 - pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi"); 219 - if (IS_ERR(pci->dbi_base)) 220 - return PTR_ERR(pci->dbi_base); 221 236 222 237 lpp->core_clk = devm_clk_get(dev, NULL); 223 238 if (IS_ERR(lpp->core_clk)) { ··· 249 272 } 250 273 251 274 return 0; 252 - } 253 - 254 - static void intel_pcie_deinit_phy(struct intel_pcie_port *lpp) 255 - { 256 - phy_exit(lpp->phy); 257 275 } 258 276 259 277 static int intel_pcie_wait_l2(struct intel_pcie_port *lpp) ··· 287 315 static int intel_pcie_host_setup(struct intel_pcie_port *lpp) 288 316 { 289 317 int ret; 318 + struct dw_pcie *pci = &lpp->pci; 290 319 291 320 intel_pcie_core_rst_assert(lpp); 292 321 intel_pcie_device_rst_assert(lpp); ··· 304 331 goto clk_err; 305 332 } 306 333 307 - intel_pcie_rc_setup(lpp); 308 - ret = intel_pcie_app_logic_setup(lpp); 334 + pci->atu_base = pci->dbi_base + 0xC0000; 335 + 336 + intel_pcie_ltssm_disable(lpp); 337 + intel_pcie_link_setup(lpp); 338 + intel_pcie_init_n_fts(pci); 339 + dw_pcie_setup_rc(&pci->pp); 340 + dw_pcie_upconfig_setup(pci); 341 + 342 + intel_pcie_device_rst_deassert(lpp); 343 + intel_pcie_ltssm_enable(lpp); 344 + 345 + ret = dw_pcie_wait_for_link(pci); 309 346 if (ret) 310 347 goto app_init_err; 311 348 ··· 329 346 clk_disable_unprepare(lpp->core_clk); 330 347 clk_err: 331 348 intel_pcie_core_rst_assert(lpp); 332 - intel_pcie_deinit_phy(lpp); 349 + phy_exit(lpp->phy); 333 350 334 351 return ret; 335 352 } ··· 340 357 intel_pcie_turn_off(lpp); 341 358 clk_disable_unprepare(lpp->core_clk); 342 359 intel_pcie_core_rst_assert(lpp); 343 - intel_pcie_deinit_phy(lpp); 360 + phy_exit(lpp->phy); 344 361 } 345 362 346 363 static int intel_pcie_remove(struct platform_device *pdev) ··· 364 381 if (ret) 365 382 return ret; 366 383 367 - intel_pcie_deinit_phy(lpp); 384 + phy_exit(lpp->phy); 368 385 clk_disable_unprepare(lpp->core_clk); 369 386 return ret; 370 387 } ··· 384 401 return intel_pcie_host_setup(lpp); 385 402 } 386 403 387 - /* 388 - * Dummy function so that DW core doesn't configure MSI 389 - */ 390 - static int intel_pcie_msi_init(struct pcie_port *pp) 391 - { 392 - return 0; 393 - } 394 - 395 404 static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr) 396 405 { 397 406 return cpu_addr + BUS_IATU_OFFSET; ··· 395 420 396 421 static const struct dw_pcie_host_ops intel_pcie_dw_ops = { 397 422 .host_init = intel_pcie_rc_init, 398 - .msi_host_init = intel_pcie_msi_init, 399 423 }; 400 424 401 425 static const struct intel_pcie_soc pcie_data = { 402 426 .pcie_ver = 0x520A, 403 - .pcie_atu_offset = 0xC0000, 404 - .num_viewport = 3, 405 427 }; 406 428 407 429 static int intel_pcie_probe(struct platform_device *pdev) ··· 433 461 434 462 pci->ops = &intel_pcie_ops; 435 463 pci->version = data->pcie_ver; 436 - pci->atu_base = pci->dbi_base + data->pcie_atu_offset; 437 464 pp->ops = &intel_pcie_dw_ops; 438 465 439 466 ret = dw_pcie_host_init(pp); ··· 440 469 dev_err(dev, "Cannot initialize host\n"); 441 470 return ret; 442 471 } 443 - 444 - /* 445 - * Intel PCIe doesn't configure IO region, so set viewport 446 - * to not perform IO region access. 447 - */ 448 - pci->num_viewport = data->num_viewport; 449 472 450 473 return 0; 451 474 }

+4 -58

drivers/pci/controller/dwc/pcie-kirin.c

··· 157 157 if (IS_ERR(kirin_pcie->phy_base)) 158 158 return PTR_ERR(kirin_pcie->phy_base); 159 159 160 - kirin_pcie->pci->dbi_base = 161 - devm_platform_ioremap_resource_byname(pdev, "dbi"); 162 - if (IS_ERR(kirin_pcie->pci->dbi_base)) 163 - return PTR_ERR(kirin_pcie->pci->dbi_base); 164 - 165 160 kirin_pcie->crgctrl = 166 161 syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); 167 162 if (IS_ERR(kirin_pcie->crgctrl)) ··· 390 395 return 0; 391 396 } 392 397 393 - static int kirin_pcie_establish_link(struct pcie_port *pp) 398 + static int kirin_pcie_start_link(struct dw_pcie *pci) 394 399 { 395 - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 396 400 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 397 - struct device *dev = kirin_pcie->pci->dev; 398 - int count = 0; 399 - 400 - if (kirin_pcie_link_up(pci)) 401 - return 0; 402 - 403 - dw_pcie_setup_rc(pp); 404 401 405 402 /* assert LTSSM enable */ 406 403 kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT, 407 404 PCIE_APP_LTSSM_ENABLE); 408 - 409 - /* check if the link is up or not */ 410 - while (!kirin_pcie_link_up(pci)) { 411 - usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); 412 - count++; 413 - if (count == 1000) { 414 - dev_err(dev, "Link Fail\n"); 415 - return -EINVAL; 416 - } 417 - } 418 405 419 406 return 0; 420 407 } ··· 405 428 { 406 429 pp->bridge->ops = &kirin_pci_ops; 407 430 408 - kirin_pcie_establish_link(pp); 409 - dw_pcie_msi_init(pp); 410 - 411 431 return 0; 412 432 } 413 433 ··· 412 438 .read_dbi = kirin_pcie_read_dbi, 413 439 .write_dbi = kirin_pcie_write_dbi, 414 440 .link_up = kirin_pcie_link_up, 441 + .start_link = kirin_pcie_start_link, 415 442 }; 416 443 417 444 static const struct dw_pcie_host_ops kirin_pcie_host_ops = { 418 445 .host_init = kirin_pcie_host_init, 419 446 }; 420 - 421 - static int kirin_pcie_add_msi(struct dw_pcie *pci, 422 - struct platform_device *pdev) 423 - { 424 - int irq; 425 - 426 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 427 - irq = platform_get_irq(pdev, 0); 428 - if (irq < 0) 429 - return irq; 430 - 431 - pci->pp.msi_irq = irq; 432 - } 433 - 434 - return 0; 435 - } 436 - 437 - static int kirin_add_pcie_port(struct dw_pcie *pci, 438 - struct platform_device *pdev) 439 - { 440 - int ret; 441 - 442 - ret = kirin_pcie_add_msi(pci, pdev); 443 - if (ret) 444 - return ret; 445 - 446 - pci->pp.ops = &kirin_pcie_host_ops; 447 - 448 - return dw_pcie_host_init(&pci->pp); 449 - } 450 447 451 448 static int kirin_pcie_probe(struct platform_device *pdev) 452 449 { ··· 441 496 442 497 pci->dev = dev; 443 498 pci->ops = &kirin_dw_pcie_ops; 499 + pci->pp.ops = &kirin_pcie_host_ops; 444 500 kirin_pcie->pci = pci; 445 501 446 502 ret = kirin_pcie_get_clk(kirin_pcie, pdev); ··· 467 521 468 522 platform_set_drvdata(pdev, kirin_pcie); 469 523 470 - return kirin_add_pcie_port(pci, pdev); 524 + return dw_pcie_host_init(&pci->pp); 471 525 } 472 526 473 527 static const struct of_device_id kirin_pcie_match[] = {

+99 -28

drivers/pci/controller/dwc/pcie-qcom.c

··· 9 9 */ 10 10 11 11 #include <linux/clk.h> 12 + #include <linux/crc8.h> 12 13 #include <linux/delay.h> 13 14 #include <linux/gpio/consumer.h> 14 15 #include <linux/interrupt.h> ··· 58 57 #define PCIE20_PARF_SID_OFFSET 0x234 59 58 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C 60 59 #define PCIE20_PARF_DEVICE_TYPE 0x1000 60 + #define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 61 61 62 62 #define PCIE20_ELBI_SYS_CTRL 0x04 63 63 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) ··· 99 97 100 98 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 101 99 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 100 + 101 + #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) 102 + 102 103 struct qcom_pcie_resources_2_1_0 { 103 104 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; 104 105 struct reset_control *pci_reset; ··· 184 179 void (*deinit)(struct qcom_pcie *pcie); 185 180 void (*post_deinit)(struct qcom_pcie *pcie); 186 181 void (*ltssm_enable)(struct qcom_pcie *pcie); 182 + int (*config_sid)(struct qcom_pcie *pcie); 187 183 }; 188 184 189 185 struct qcom_pcie { ··· 213 207 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 214 208 } 215 209 216 - static int qcom_pcie_establish_link(struct qcom_pcie *pcie) 210 + static int qcom_pcie_start_link(struct dw_pcie *pci) 217 211 { 218 - struct dw_pcie *pci = pcie->pci; 219 - 220 - if (dw_pcie_link_up(pci)) 221 - return 0; 212 + struct qcom_pcie *pcie = to_qcom_pcie(pci); 222 213 223 214 /* Enable Link Training state machine */ 224 215 if (pcie->ops->ltssm_enable) 225 216 pcie->ops->ltssm_enable(pcie); 226 217 227 - return dw_pcie_wait_for_link(pci); 218 + return 0; 228 219 } 229 220 230 221 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) ··· 1264 1261 return !!(val & PCI_EXP_LNKSTA_DLLLA); 1265 1262 } 1266 1263 1264 + static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) 1265 + { 1266 + /* iommu map structure */ 1267 + struct { 1268 + u32 bdf; 1269 + u32 phandle; 1270 + u32 smmu_sid; 1271 + u32 smmu_sid_len; 1272 + } *map; 1273 + void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N; 1274 + struct device *dev = pcie->pci->dev; 1275 + u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; 1276 + int i, nr_map, size = 0; 1277 + u32 smmu_sid_base; 1278 + 1279 + of_get_property(dev->of_node, "iommu-map", &size); 1280 + if (!size) 1281 + return 0; 1282 + 1283 + map = kzalloc(size, GFP_KERNEL); 1284 + if (!map) 1285 + return -ENOMEM; 1286 + 1287 + of_property_read_u32_array(dev->of_node, 1288 + "iommu-map", (u32 *)map, size / sizeof(u32)); 1289 + 1290 + nr_map = size / (sizeof(*map)); 1291 + 1292 + crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); 1293 + 1294 + /* Registers need to be zero out first */ 1295 + memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); 1296 + 1297 + /* Extract the SMMU SID base from the first entry of iommu-map */ 1298 + smmu_sid_base = map[0].smmu_sid; 1299 + 1300 + /* Look for an available entry to hold the mapping */ 1301 + for (i = 0; i < nr_map; i++) { 1302 + u16 bdf_be = cpu_to_be16(map[i].bdf); 1303 + u32 val; 1304 + u8 hash; 1305 + 1306 + hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 1307 + 0); 1308 + 1309 + val = readl(bdf_to_sid_base + hash * sizeof(u32)); 1310 + 1311 + /* If the register is already populated, look for next available entry */ 1312 + while (val) { 1313 + u8 current_hash = hash++; 1314 + u8 next_mask = 0xff; 1315 + 1316 + /* If NEXT field is NULL then update it with next hash */ 1317 + if (!(val & next_mask)) { 1318 + val |= (u32)hash; 1319 + writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); 1320 + } 1321 + 1322 + val = readl(bdf_to_sid_base + hash * sizeof(u32)); 1323 + } 1324 + 1325 + /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ 1326 + val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; 1327 + writel(val, bdf_to_sid_base + hash * sizeof(u32)); 1328 + } 1329 + 1330 + kfree(map); 1331 + 1332 + return 0; 1333 + } 1334 + 1267 1335 static int qcom_pcie_host_init(struct pcie_port *pp) 1268 1336 { 1269 1337 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ··· 1357 1283 goto err_disable_phy; 1358 1284 } 1359 1285 1360 - dw_pcie_setup_rc(pp); 1361 - dw_pcie_msi_init(pp); 1362 - 1363 1286 qcom_ep_reset_deassert(pcie); 1364 1287 1365 - ret = qcom_pcie_establish_link(pcie); 1366 - if (ret) 1367 - goto err; 1288 + if (pcie->ops->config_sid) { 1289 + ret = pcie->ops->config_sid(pcie); 1290 + if (ret) 1291 + goto err; 1292 + } 1368 1293 1369 1294 return 0; 1295 + 1370 1296 err: 1371 1297 qcom_ep_reset_assert(pcie); 1372 1298 if (pcie->ops->post_deinit) ··· 1435 1361 .post_deinit = qcom_pcie_post_deinit_2_7_0, 1436 1362 }; 1437 1363 1364 + /* Qcom IP rev.: 1.9.0 */ 1365 + static const struct qcom_pcie_ops ops_1_9_0 = { 1366 + .get_resources = qcom_pcie_get_resources_2_7_0, 1367 + .init = qcom_pcie_init_2_7_0, 1368 + .deinit = qcom_pcie_deinit_2_7_0, 1369 + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1370 + .post_init = qcom_pcie_post_init_2_7_0, 1371 + .post_deinit = qcom_pcie_post_deinit_2_7_0, 1372 + .config_sid = qcom_pcie_config_sid_sm8250, 1373 + }; 1374 + 1438 1375 static const struct dw_pcie_ops dw_pcie_ops = { 1439 1376 .link_up = qcom_pcie_link_up, 1377 + .start_link = qcom_pcie_start_link, 1440 1378 }; 1441 1379 1442 1380 static int qcom_pcie_probe(struct platform_device *pdev) 1443 1381 { 1444 1382 struct device *dev = &pdev->dev; 1445 - struct resource *res; 1446 1383 struct pcie_port *pp; 1447 1384 struct dw_pcie *pci; 1448 1385 struct qcom_pcie *pcie; ··· 1492 1407 goto err_pm_runtime_put; 1493 1408 } 1494 1409 1495 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 1496 - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 1497 - if (IS_ERR(pci->dbi_base)) { 1498 - ret = PTR_ERR(pci->dbi_base); 1499 - goto err_pm_runtime_put; 1500 - } 1501 - 1502 1410 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); 1503 1411 if (IS_ERR(pcie->elbi)) { 1504 1412 ret = PTR_ERR(pcie->elbi); ··· 1509 1431 goto err_pm_runtime_put; 1510 1432 1511 1433 pp->ops = &qcom_pcie_dw_ops; 1512 - 1513 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 1514 - pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 1515 - if (pp->msi_irq < 0) { 1516 - ret = pp->msi_irq; 1517 - goto err_pm_runtime_put; 1518 - } 1519 - } 1520 1434 1521 1435 ret = phy_init(pcie->phy); 1522 1436 if (ret) { ··· 1544 1474 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, 1545 1475 { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, 1546 1476 { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, 1477 + { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, 1547 1478 { } 1548 1479 }; 1549 1480

+22 -40

drivers/pci/controller/dwc/pcie-spear13xx.c

··· 66 66 67 67 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev) 68 68 69 - static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) 69 + static int spear13xx_pcie_start_link(struct dw_pcie *pci) 70 70 { 71 - struct dw_pcie *pci = spear13xx_pcie->pci; 72 - struct pcie_port *pp = &pci->pp; 71 + struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); 73 72 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; 74 - u32 val; 75 - u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 76 - 77 - if (dw_pcie_link_up(pci)) { 78 - dev_err(pci->dev, "link already up\n"); 79 - return 0; 80 - } 81 - 82 - dw_pcie_setup_rc(pp); 83 - 84 - /* 85 - * this controller support only 128 bytes read size, however its 86 - * default value in capability register is 512 bytes. So force 87 - * it to 128 here. 88 - */ 89 - val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL); 90 - val &= ~PCI_EXP_DEVCTL_READRQ; 91 - dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val); 92 - 93 - dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A); 94 - dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80); 95 73 96 74 /* enable ltssm */ 97 75 writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID) ··· 77 99 | ((u32)1 << REG_TRANSLATION_ENABLE), 78 100 &app_reg->app_ctrl_0); 79 101 80 - return dw_pcie_wait_for_link(pci); 102 + return 0; 81 103 } 82 104 83 105 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) ··· 102 124 103 125 static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie) 104 126 { 105 - struct dw_pcie *pci = spear13xx_pcie->pci; 106 - struct pcie_port *pp = &pci->pp; 107 127 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; 108 128 109 129 /* Enable MSI interrupt */ 110 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 111 - dw_pcie_msi_init(pp); 130 + if (IS_ENABLED(CONFIG_PCI_MSI)) 112 131 writel(readl(&app_reg->int_mask) | 113 132 MSI_CTRL_INT, &app_reg->int_mask); 114 - } 115 133 } 116 134 117 135 static int spear13xx_pcie_link_up(struct dw_pcie *pci) ··· 125 151 { 126 152 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 127 153 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); 154 + u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 155 + u32 val; 128 156 129 - spear13xx_pcie_establish_link(spear13xx_pcie); 157 + spear13xx_pcie->app_base = pci->dbi_base + 0x2000; 158 + 159 + /* 160 + * this controller support only 128 bytes read size, however its 161 + * default value in capability register is 512 bytes. So force 162 + * it to 128 here. 163 + */ 164 + val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL); 165 + val &= ~PCI_EXP_DEVCTL_READRQ; 166 + dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val); 167 + 168 + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A); 169 + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80); 170 + 130 171 spear13xx_pcie_enable_interrupts(spear13xx_pcie); 131 172 132 173 return 0; ··· 172 183 } 173 184 174 185 pp->ops = &spear13xx_pcie_host_ops; 186 + pp->msi_irq = -ENODEV; 175 187 176 188 ret = dw_pcie_host_init(pp); 177 189 if (ret) { ··· 185 195 186 196 static const struct dw_pcie_ops dw_pcie_ops = { 187 197 .link_up = spear13xx_pcie_link_up, 198 + .start_link = spear13xx_pcie_start_link, 188 199 }; 189 200 190 201 static int spear13xx_pcie_probe(struct platform_device *pdev) ··· 194 203 struct dw_pcie *pci; 195 204 struct spear13xx_pcie *spear13xx_pcie; 196 205 struct device_node *np = dev->of_node; 197 - struct resource *dbi_base; 198 206 int ret; 199 207 200 208 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL); ··· 231 241 dev_err(dev, "couldn't enable clk for pcie\n"); 232 242 return ret; 233 243 } 234 - 235 - dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 236 - pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); 237 - if (IS_ERR(pci->dbi_base)) { 238 - ret = PTR_ERR(pci->dbi_base); 239 - goto fail_clk; 240 - } 241 - spear13xx_pcie->app_base = pci->dbi_base + 0x2000; 242 244 243 245 if (of_property_read_bool(np, "st,pcie-is-gen1")) 244 246 pci->link_gen = 1;

+49 -80

drivers/pci/controller/dwc/pcie-tegra194.c

··· 765 765 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 766 766 u32 val; 767 767 768 - dw_pcie_msi_init(pp); 769 - 770 768 /* Enable MSI interrupt generation */ 771 769 val = appl_readl(pcie, APPL_INTR_EN_L0_0); 772 770 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN; ··· 859 861 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 860 862 u32 val; 861 863 864 + if (!pcie->pcie_cap_base) 865 + pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 866 + PCI_CAP_ID_EXP); 867 + 862 868 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); 863 869 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); 864 870 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); ··· 890 888 config_gen3_gen4_eq_presets(pcie); 891 889 892 890 init_host_aspm(pcie); 891 + 892 + /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ 893 + if (!pcie->supports_clkreq) { 894 + disable_aspm_l11(pcie); 895 + disable_aspm_l12(pcie); 896 + } 893 897 894 898 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); 895 899 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; ··· 998 990 return !!(val & PCI_EXP_LNKSTA_DLLLA); 999 991 } 1000 992 1001 - static void tegra_pcie_set_msi_vec_num(struct pcie_port *pp) 1002 - { 1003 - pp->num_vectors = MAX_MSI_IRQS; 1004 - } 1005 - 1006 993 static int tegra_pcie_dw_start_link(struct dw_pcie *pci) 1007 994 { 1008 995 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); ··· 1022 1019 1023 1020 static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { 1024 1021 .host_init = tegra_pcie_dw_host_init, 1025 - .set_num_vectors = tegra_pcie_set_msi_vec_num, 1026 1022 }; 1027 1023 1028 1024 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) ··· 1063 1061 1064 1062 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) 1065 1063 { 1064 + struct platform_device *pdev = to_platform_device(pcie->dev); 1066 1065 struct device_node *np = pcie->dev->of_node; 1067 1066 int ret; 1067 + 1068 + pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 1069 + if (!pcie->dbi_res) { 1070 + dev_err(pcie->dev, "Failed to find \"dbi\" region\n"); 1071 + return -ENODEV; 1072 + } 1068 1073 1069 1074 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); 1070 1075 if (ret < 0) { ··· 1399 1390 1400 1391 reset_control_deassert(pcie->core_rst); 1401 1392 1402 - pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, 1403 - PCI_CAP_ID_EXP); 1404 - 1405 - /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */ 1406 - if (!pcie->supports_clkreq) { 1407 - disable_aspm_l11(pcie); 1408 - disable_aspm_l12(pcie); 1409 - } 1410 - 1411 1393 return ret; 1412 1394 1413 1395 fail_phy: ··· 1415 1415 return ret; 1416 1416 } 1417 1417 1418 - static int __deinit_controller(struct tegra_pcie_dw *pcie) 1418 + static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie) 1419 1419 { 1420 1420 int ret; 1421 1421 1422 1422 ret = reset_control_assert(pcie->core_rst); 1423 - if (ret) { 1424 - dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", 1425 - ret); 1426 - return ret; 1427 - } 1423 + if (ret) 1424 + dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); 1428 1425 1429 1426 tegra_pcie_disable_phy(pcie); 1430 1427 1431 1428 ret = reset_control_assert(pcie->core_apb_rst); 1432 - if (ret) { 1429 + if (ret) 1433 1430 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); 1434 - return ret; 1435 - } 1436 1431 1437 1432 clk_disable_unprepare(pcie->core_clk); 1438 1433 1439 1434 ret = regulator_disable(pcie->pex_ctl_supply); 1440 - if (ret) { 1435 + if (ret) 1441 1436 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); 1442 - return ret; 1443 - } 1444 1437 1445 1438 tegra_pcie_disable_slot_regulators(pcie); 1446 1439 1447 1440 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); 1448 - if (ret) { 1441 + if (ret) 1449 1442 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", 1450 1443 pcie->cid, ret); 1451 - return ret; 1452 - } 1453 - 1454 - return ret; 1455 1444 } 1456 1445 1457 1446 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) ··· 1464 1475 return 0; 1465 1476 1466 1477 fail_host_init: 1467 - return __deinit_controller(pcie); 1478 + tegra_pcie_unconfig_controller(pcie); 1479 + return ret; 1468 1480 } 1469 1481 1470 1482 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) ··· 1506 1516 data &= ~APPL_PINMUX_PEX_RST; 1507 1517 appl_writel(pcie, data, APPL_PINMUX); 1508 1518 1519 + /* 1520 + * Some cards do not go to detect state even after de-asserting 1521 + * PERST#. So, de-assert LTSSM to bring link to detect state. 1522 + */ 1523 + data = readl(pcie->appl_base + APPL_CTRL); 1524 + data &= ~APPL_CTRL_LTSSM_EN; 1525 + writel(data, pcie->appl_base + APPL_CTRL); 1526 + 1509 1527 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, 1510 1528 data, 1511 1529 ((data & ··· 1521 1523 APPL_DEBUG_LTSSM_STATE_SHIFT) == 1522 1524 LTSSM_STATE_PRE_DETECT, 1523 1525 1, LTSSM_TIMEOUT); 1524 - if (err) { 1526 + if (err) 1525 1527 dev_info(pcie->dev, "Link didn't go to detect state\n"); 1526 - } else { 1527 - /* Disable LTSSM after link is in detect state */ 1528 - data = appl_readl(pcie, APPL_CTRL); 1529 - data &= ~APPL_CTRL_LTSSM_EN; 1530 - appl_writel(pcie, data, APPL_CTRL); 1531 - } 1532 1528 } 1533 1529 /* 1534 1530 * DBI registers may not be accessible after this as PLL-E would be ··· 1536 1544 appl_writel(pcie, data, APPL_PINMUX); 1537 1545 } 1538 1546 1539 - static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) 1547 + static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) 1540 1548 { 1541 1549 tegra_pcie_downstream_dev_to_D0(pcie); 1542 1550 dw_pcie_host_deinit(&pcie->pci.pp); 1543 1551 tegra_pcie_dw_pme_turnoff(pcie); 1544 - 1545 - return __deinit_controller(pcie); 1552 + tegra_pcie_unconfig_controller(pcie); 1546 1553 } 1547 1554 1548 1555 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) 1549 1556 { 1550 - struct pcie_port *pp = &pcie->pci.pp; 1551 1557 struct device *dev = pcie->dev; 1552 1558 char *name; 1553 1559 int ret; 1554 - 1555 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 1556 - pp->msi_irq = of_irq_get_byname(dev->of_node, "msi"); 1557 - if (!pp->msi_irq) { 1558 - dev_err(dev, "Failed to get MSI interrupt\n"); 1559 - return -ENODEV; 1560 - } 1561 - } 1562 1560 1563 1561 pm_runtime_enable(dev); 1564 1562 ··· 1565 1583 goto fail_pm_get_sync; 1566 1584 } 1567 1585 1568 - tegra_pcie_init_controller(pcie); 1586 + ret = tegra_pcie_init_controller(pcie); 1587 + if (ret < 0) { 1588 + dev_err(dev, "Failed to initialize controller: %d\n", ret); 1589 + goto fail_pm_get_sync; 1590 + } 1569 1591 1570 1592 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); 1571 1593 if (!pcie->link_state) { ··· 1893 1907 struct dw_pcie *pci = &pcie->pci; 1894 1908 struct device *dev = pcie->dev; 1895 1909 struct dw_pcie_ep *ep; 1896 - struct resource *res; 1897 1910 char *name; 1898 1911 int ret; 1899 1912 1900 1913 ep = &pci->ep; 1901 1914 ep->ops = &pcie_ep_ops; 1902 1915 1903 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 1904 - if (!res) 1905 - return -EINVAL; 1906 - 1907 - ep->phys_base = res->start; 1908 - ep->addr_size = resource_size(res); 1909 1916 ep->page_size = SZ_64K; 1910 1917 1911 1918 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); ··· 1961 1982 struct device *dev = &pdev->dev; 1962 1983 struct resource *atu_dma_res; 1963 1984 struct tegra_pcie_dw *pcie; 1964 - struct resource *dbi_res; 1965 1985 struct pcie_port *pp; 1966 1986 struct dw_pcie *pci; 1967 1987 struct phy **phys; ··· 1979 2001 pci->ops = &tegra_dw_pcie_ops; 1980 2002 pci->n_fts[0] = N_FTS_VAL; 1981 2003 pci->n_fts[1] = FTS_VAL; 2004 + pci->version = 0x490A; 1982 2005 1983 2006 pp = &pci->pp; 2007 + pp->num_vectors = MAX_MSI_IRQS; 1984 2008 pcie->dev = &pdev->dev; 1985 2009 pcie->mode = (enum dw_pcie_device_mode)data->mode; 1986 2010 ··· 2071 2091 2072 2092 pcie->phys = phys; 2073 2093 2074 - dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 2075 - if (!dbi_res) { 2076 - dev_err(dev, "Failed to find \"dbi\" region\n"); 2077 - return -ENODEV; 2078 - } 2079 - pcie->dbi_res = dbi_res; 2080 - 2081 - pci->dbi_base = devm_ioremap_resource(dev, dbi_res); 2082 - if (IS_ERR(pci->dbi_base)) 2083 - return PTR_ERR(pci->dbi_base); 2084 - 2085 - /* Tegra HW locates DBI2 at a fixed offset from DBI */ 2086 - pci->dbi_base2 = pci->dbi_base + 0x1000; 2087 - 2088 2094 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2089 2095 "atu_dma"); 2090 2096 if (!atu_dma_res) { ··· 2079 2113 } 2080 2114 pcie->atu_dma_res = atu_dma_res; 2081 2115 2116 + pci->atu_size = resource_size(atu_dma_res); 2082 2117 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); 2083 2118 if (IS_ERR(pci->atu_base)) 2084 2119 return PTR_ERR(pci->atu_base); ··· 2192 2225 PORT_LOGIC_MSI_CTRL_INT_0_EN); 2193 2226 tegra_pcie_downstream_dev_to_D0(pcie); 2194 2227 tegra_pcie_dw_pme_turnoff(pcie); 2228 + tegra_pcie_unconfig_controller(pcie); 2195 2229 2196 - return __deinit_controller(pcie); 2230 + return 0; 2197 2231 } 2198 2232 2199 2233 static int tegra_pcie_dw_resume_noirq(struct device *dev) ··· 2222 2254 return 0; 2223 2255 2224 2256 fail_host_init: 2225 - return __deinit_controller(pcie); 2257 + tegra_pcie_unconfig_controller(pcie); 2258 + return ret; 2226 2259 } 2227 2260 2228 2261 static int tegra_pcie_dw_resume_early(struct device *dev) ··· 2261 2292 disable_irq(pcie->pci.pp.msi_irq); 2262 2293 2263 2294 tegra_pcie_dw_pme_turnoff(pcie); 2264 - __deinit_controller(pcie); 2295 + tegra_pcie_unconfig_controller(pcie); 2265 2296 } 2266 2297 2267 2298 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = {

+2 -36

drivers/pci/controller/dwc/pcie-uniphier-ep.c

··· 218 218 .get_features = uniphier_pcie_get_features, 219 219 }; 220 220 221 - static int uniphier_add_pcie_ep(struct uniphier_pcie_ep_priv *priv, 222 - struct platform_device *pdev) 223 - { 224 - struct dw_pcie *pci = &priv->pci; 225 - struct dw_pcie_ep *ep = &pci->ep; 226 - struct device *dev = &pdev->dev; 227 - struct resource *res; 228 - int ret; 229 - 230 - ep->ops = &uniphier_pcie_ep_ops; 231 - 232 - pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2"); 233 - if (IS_ERR(pci->dbi_base2)) 234 - return PTR_ERR(pci->dbi_base2); 235 - 236 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 237 - if (!res) 238 - return -EINVAL; 239 - 240 - ep->phys_base = res->start; 241 - ep->addr_size = resource_size(res); 242 - 243 - ret = dw_pcie_ep_init(ep); 244 - if (ret) 245 - dev_err(dev, "Failed to initialize endpoint (%d)\n", ret); 246 - 247 - return ret; 248 - } 249 - 250 221 static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv) 251 222 { 252 223 int ret; ··· 271 300 { 272 301 struct device *dev = &pdev->dev; 273 302 struct uniphier_pcie_ep_priv *priv; 274 - struct resource *res; 275 303 int ret; 276 304 277 305 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 283 313 284 314 priv->pci.dev = dev; 285 315 priv->pci.ops = &dw_pcie_ops; 286 - 287 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 288 - priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res); 289 - if (IS_ERR(priv->pci.dbi_base)) 290 - return PTR_ERR(priv->pci.dbi_base); 291 316 292 317 priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); 293 318 if (IS_ERR(priv->base)) ··· 317 352 if (ret) 318 353 return ret; 319 354 320 - return uniphier_add_pcie_ep(priv, pdev); 355 + priv->pci.ep.ops = &uniphier_pcie_ep_ops; 356 + return dw_pcie_ep_init(&priv->pci.ep); 321 357 } 322 358 323 359 static const struct pci_epc_features uniphier_pro5_data = {

+6 -45

drivers/pci/controller/dwc/pcie-uniphier.c

··· 146 146 return (val & mask) == mask; 147 147 } 148 148 149 - static int uniphier_pcie_establish_link(struct dw_pcie *pci) 149 + static int uniphier_pcie_start_link(struct dw_pcie *pci) 150 150 { 151 151 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); 152 152 153 - if (dw_pcie_link_up(pci)) 154 - return 0; 155 - 156 153 uniphier_pcie_ltssm_enable(priv, true); 157 154 158 - return dw_pcie_wait_for_link(pci); 155 + return 0; 159 156 } 160 157 161 158 static void uniphier_pcie_stop_link(struct dw_pcie *pci) ··· 314 317 315 318 uniphier_pcie_irq_enable(priv); 316 319 317 - dw_pcie_setup_rc(pp); 318 - ret = uniphier_pcie_establish_link(pci); 319 - if (ret) 320 - return ret; 321 - 322 - dw_pcie_msi_init(pp); 323 - 324 320 return 0; 325 321 } 326 322 327 323 static const struct dw_pcie_host_ops uniphier_pcie_host_ops = { 328 324 .host_init = uniphier_pcie_host_init, 329 325 }; 330 - 331 - static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, 332 - struct platform_device *pdev) 333 - { 334 - struct dw_pcie *pci = &priv->pci; 335 - struct pcie_port *pp = &pci->pp; 336 - struct device *dev = &pdev->dev; 337 - int ret; 338 - 339 - pp->ops = &uniphier_pcie_host_ops; 340 - 341 - if (IS_ENABLED(CONFIG_PCI_MSI)) { 342 - pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 343 - if (pp->msi_irq < 0) 344 - return pp->msi_irq; 345 - } 346 - 347 - ret = dw_pcie_host_init(pp); 348 - if (ret) { 349 - dev_err(dev, "Failed to initialize host (%d)\n", ret); 350 - return ret; 351 - } 352 - 353 - return 0; 354 - } 355 326 356 327 static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv) 357 328 { ··· 356 391 } 357 392 358 393 static const struct dw_pcie_ops dw_pcie_ops = { 359 - .start_link = uniphier_pcie_establish_link, 394 + .start_link = uniphier_pcie_start_link, 360 395 .stop_link = uniphier_pcie_stop_link, 361 396 .link_up = uniphier_pcie_link_up, 362 397 }; ··· 365 400 { 366 401 struct device *dev = &pdev->dev; 367 402 struct uniphier_pcie_priv *priv; 368 - struct resource *res; 369 403 int ret; 370 404 371 405 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 373 409 374 410 priv->pci.dev = dev; 375 411 priv->pci.ops = &dw_pcie_ops; 376 - 377 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 378 - priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res); 379 - if (IS_ERR(priv->pci.dbi_base)) 380 - return PTR_ERR(priv->pci.dbi_base); 381 412 382 413 priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); 383 414 if (IS_ERR(priv->base)) ··· 396 437 if (ret) 397 438 return ret; 398 439 399 - return uniphier_add_pcie_port(priv, pdev); 440 + priv->pci.pp.ops = &uniphier_pcie_host_ops; 441 + 442 + return dw_pcie_host_init(&priv->pci.pp); 400 443 } 401 444 402 445 static const struct of_device_id uniphier_pcie_match[] = {

+11 -11

drivers/pci/controller/pci-aardvark.c

··· 16 16 #include <linux/kernel.h> 17 17 #include <linux/module.h> 18 18 #include <linux/pci.h> 19 + #include <linux/pci-ecam.h> 19 20 #include <linux/init.h> 20 21 #include <linux/phy/phy.h> 21 22 #include <linux/platform_device.h> ··· 165 164 #define PCIE_CONFIG_WR_TYPE0 0xa 166 165 #define PCIE_CONFIG_WR_TYPE1 0xb 167 166 168 - #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) 169 - #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) 170 - #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) 171 - #define PCIE_CONF_REG(reg) ((reg) & 0xffc) 172 - #define PCIE_CONF_ADDR(bus, devfn, where) \ 173 - (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 174 - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) 175 - 176 167 #define PIO_RETRY_CNT 500 177 168 #define PIO_RETRY_DELAY 2 /* 2 us*/ 178 169 ··· 252 259 if (!pcie->reset_gpio) 253 260 return; 254 261 255 - /* PERST does not work for some cards when link training is enabled */ 262 + /* 263 + * As required by PCI Express spec (PCI Express Base Specification, REV. 264 + * 4.0 PCI Express, February 19 2014, 6.6.1 Conventional Reset) a delay 265 + * for at least 100ms after de-asserting PERST# signal is needed before 266 + * link training is enabled. So ensure that link training is disabled 267 + * prior de-asserting PERST# signal to fulfill that PCI Express spec 268 + * requirement. 269 + */ 256 270 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 257 271 reg &= ~LINK_TRAINING_EN; 258 272 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); ··· 687 687 advk_writel(pcie, reg, PIO_CTRL); 688 688 689 689 /* Program the address registers */ 690 - reg = PCIE_CONF_ADDR(bus->number, devfn, where); 690 + reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 691 691 advk_writel(pcie, reg, PIO_ADDR_LS); 692 692 advk_writel(pcie, 0, PIO_ADDR_MS); 693 693 ··· 748 748 advk_writel(pcie, reg, PIO_CTRL); 749 749 750 750 /* Program the address registers */ 751 - reg = PCIE_CONF_ADDR(bus->number, devfn, where); 751 + reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); 752 752 advk_writel(pcie, reg, PIO_ADDR_LS); 753 753 advk_writel(pcie, 0, PIO_ADDR_MS); 754 754

-1

drivers/pci/controller/pci-host-generic.c

··· 49 49 } 50 50 51 51 static const struct pci_ecam_ops pci_dw_ecam_bus_ops = { 52 - .bus_shift = 20, 53 52 .pci_ops = { 54 53 .map_bus = pci_dw_ecam_map_bus, 55 54 .read = pci_generic_config_read,

-1

drivers/pci/controller/pci-thunder-ecam.c

··· 346 346 } 347 347 348 348 const struct pci_ecam_ops pci_thunder_ecam_ops = { 349 - .bus_shift = 20, 350 349 .pci_ops = { 351 350 .map_bus = pci_ecam_map_bus, 352 351 .read = thunder_ecam_config_read,

+11 -2

drivers/pci/controller/pci-thunder-pem.c

··· 19 19 #define PEM_CFG_WR 0x28 20 20 #define PEM_CFG_RD 0x30 21 21 22 + /* 23 + * Enhanced Configuration Access Mechanism (ECAM) 24 + * 25 + * N.B. This is a non-standard platform-specific ECAM bus shift value. For 26 + * standard values defined in the PCI Express Base Specification see 27 + * include/linux/pci-ecam.h. 28 + */ 29 + #define THUNDER_PCIE_ECAM_BUS_SHIFT 24 30 + 22 31 struct thunder_pem_pci { 23 32 u32 ea_entry[3]; 24 33 void __iomem *pem_reg_base; ··· 413 404 } 414 405 415 406 const struct pci_ecam_ops thunder_pem_ecam_ops = { 416 - .bus_shift = 24, 407 + .bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT, 417 408 .init = thunder_pem_acpi_init, 418 409 .pci_ops = { 419 410 .map_bus = pci_ecam_map_bus, ··· 450 441 } 451 442 452 443 static const struct pci_ecam_ops pci_thunder_pem_ops = { 453 - .bus_shift = 24, 444 + .bus_shift = THUNDER_PCIE_ECAM_BUS_SHIFT, 454 445 .init = thunder_pem_platform_init, 455 446 .pci_ops = { 456 447 .map_bus = pci_ecam_map_bus,

-2

drivers/pci/controller/pci-xgene.c

··· 257 257 } 258 258 259 259 const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { 260 - .bus_shift = 16, 261 260 .init = xgene_v1_pcie_ecam_init, 262 261 .pci_ops = { 263 262 .map_bus = xgene_pcie_map_bus, ··· 271 272 } 272 273 273 274 const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { 274 - .bus_shift = 16, 275 275 .init = xgene_v2_pcie_ecam_init, 276 276 .pci_ops = { 277 277 .map_bus = xgene_pcie_map_bus,

+3 -14

drivers/pci/controller/pcie-brcmstb.c

··· 22 22 #include <linux/of_pci.h> 23 23 #include <linux/of_platform.h> 24 24 #include <linux/pci.h> 25 + #include <linux/pci-ecam.h> 25 26 #include <linux/printk.h> 26 27 #include <linux/reset.h> 27 28 #include <linux/sizes.h> ··· 128 127 #define MSI_INT_MASK_CLR 0x14 129 128 130 129 #define PCIE_EXT_CFG_DATA 0x8000 131 - 132 130 #define PCIE_EXT_CFG_INDEX 0x9000 133 - #define PCIE_EXT_BUSNUM_SHIFT 20 134 - #define PCIE_EXT_SLOT_SHIFT 15 135 - #define PCIE_EXT_FUNC_SHIFT 12 136 131 137 132 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 138 133 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 ··· 692 695 return dla && plu; 693 696 } 694 697 695 - /* Configuration space read/write support */ 696 - static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) 697 - { 698 - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) 699 - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) 700 - | (busnr << PCIE_EXT_BUSNUM_SHIFT) 701 - | (reg & ~3); 702 - } 703 - 704 698 static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, 705 699 int where) 706 700 { ··· 704 716 return PCI_SLOT(devfn) ? NULL : base + where; 705 717 706 718 /* For devices, write to the config space index register */ 707 - idx = brcm_pcie_cfg_index(bus->number, devfn, 0); 719 + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); 708 720 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); 709 721 return base + PCIE_EXT_CFG_DATA + where; 710 722 } ··· 881 893 burst = 0x2; /* 512 bytes */ 882 894 883 895 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ 896 + tmp = readl(base + PCIE_MISC_MISC_CTRL); 884 897 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); 885 898 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); 886 899 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);

+30 -30

drivers/pci/controller/pcie-iproc.c

··· 6 6 7 7 #include <linux/kernel.h> 8 8 #include <linux/pci.h> 9 + #include <linux/pci-ecam.h> 9 10 #include <linux/msi.h> 10 11 #include <linux/clk.h> 11 12 #include <linux/module.h> ··· 40 39 41 40 #define CFG_IND_ADDR_MASK 0x00001ffc 42 41 43 - #define CFG_ADDR_BUS_NUM_SHIFT 20 44 - #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 45 - #define CFG_ADDR_DEV_NUM_SHIFT 15 46 - #define CFG_ADDR_DEV_NUM_MASK 0x000f8000 47 - #define CFG_ADDR_FUNC_NUM_SHIFT 12 48 - #define CFG_ADDR_FUNC_NUM_MASK 0x00007000 49 - #define CFG_ADDR_REG_NUM_SHIFT 2 50 42 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc 51 - #define CFG_ADDR_CFG_TYPE_SHIFT 0 52 - #define CFG_ADDR_CFG_TYPE_MASK 0x00000003 43 + #define CFG_ADDR_CFG_TYPE_1 1 53 44 54 45 #define SYS_RC_INTX_MASK 0xf 55 46 ··· 185 192 .imap_window_offset = 0x4, 186 193 }, 187 194 { 188 - /* IARR1/IMAP1 (currently unused) */ 189 - .type = IPROC_PCIE_IB_MAP_INVALID, 195 + /* IARR1/IMAP1 */ 196 + .type = IPROC_PCIE_IB_MAP_MEM, 197 + .size_unit = SZ_1M, 198 + .region_sizes = { 8 }, 199 + .nr_sizes = 1, 200 + .nr_windows = 8, 201 + .imap_addr_offset = 0x4, 202 + .imap_window_offset = 0x8, 203 + 190 204 }, 191 205 { 192 206 /* IARR2/IMAP2 */ ··· 307 307 }; 308 308 309 309 /* iProc PCIe PAXB BCMA registers */ 310 - static const u16 iproc_pcie_reg_paxb_bcma[] = { 310 + static const u16 iproc_pcie_reg_paxb_bcma[IPROC_PCIE_MAX_NUM_REG] = { 311 311 [IPROC_PCIE_CLK_CTRL] = 0x000, 312 312 [IPROC_PCIE_CFG_IND_ADDR] = 0x120, 313 313 [IPROC_PCIE_CFG_IND_DATA] = 0x124, ··· 318 318 }; 319 319 320 320 /* iProc PCIe PAXB registers */ 321 - static const u16 iproc_pcie_reg_paxb[] = { 321 + static const u16 iproc_pcie_reg_paxb[IPROC_PCIE_MAX_NUM_REG] = { 322 322 [IPROC_PCIE_CLK_CTRL] = 0x000, 323 323 [IPROC_PCIE_CFG_IND_ADDR] = 0x120, 324 324 [IPROC_PCIE_CFG_IND_DATA] = 0x124, ··· 334 334 }; 335 335 336 336 /* iProc PCIe PAXB v2 registers */ 337 - static const u16 iproc_pcie_reg_paxb_v2[] = { 337 + static const u16 iproc_pcie_reg_paxb_v2[IPROC_PCIE_MAX_NUM_REG] = { 338 338 [IPROC_PCIE_CLK_CTRL] = 0x000, 339 339 [IPROC_PCIE_CFG_IND_ADDR] = 0x120, 340 340 [IPROC_PCIE_CFG_IND_DATA] = 0x124, ··· 351 351 [IPROC_PCIE_OMAP3] = 0xdf8, 352 352 [IPROC_PCIE_IARR0] = 0xd00, 353 353 [IPROC_PCIE_IMAP0] = 0xc00, 354 + [IPROC_PCIE_IARR1] = 0xd08, 355 + [IPROC_PCIE_IMAP1] = 0xd70, 354 356 [IPROC_PCIE_IARR2] = 0xd10, 355 357 [IPROC_PCIE_IMAP2] = 0xcc0, 356 358 [IPROC_PCIE_IARR3] = 0xe00, ··· 365 363 }; 366 364 367 365 /* iProc PCIe PAXC v1 registers */ 368 - static const u16 iproc_pcie_reg_paxc[] = { 366 + static const u16 iproc_pcie_reg_paxc[IPROC_PCIE_MAX_NUM_REG] = { 369 367 [IPROC_PCIE_CLK_CTRL] = 0x000, 370 368 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, 371 369 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, ··· 374 372 }; 375 373 376 374 /* iProc PCIe PAXC v2 registers */ 377 - static const u16 iproc_pcie_reg_paxc_v2[] = { 375 + static const u16 iproc_pcie_reg_paxc_v2[IPROC_PCIE_MAX_NUM_REG] = { 378 376 [IPROC_PCIE_MSI_GIC_MODE] = 0x050, 379 377 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074, 380 378 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078, ··· 461 459 462 460 static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, 463 461 unsigned int busno, 464 - unsigned int slot, 465 - unsigned int fn, 462 + unsigned int devfn, 466 463 int where) 467 464 { 468 465 u16 offset; 469 466 u32 val; 470 467 471 468 /* EP device access */ 472 - val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | 473 - (slot << CFG_ADDR_DEV_NUM_SHIFT) | 474 - (fn << CFG_ADDR_FUNC_NUM_SHIFT) | 475 - (where & CFG_ADDR_REG_NUM_MASK) | 476 - (1 & CFG_ADDR_CFG_TYPE_MASK); 469 + val = ALIGN_DOWN(PCIE_ECAM_OFFSET(busno, devfn, where), 4) | 470 + CFG_ADDR_CFG_TYPE_1; 477 471 478 472 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); 479 473 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); ··· 572 574 int where, int size, u32 *val) 573 575 { 574 576 struct iproc_pcie *pcie = iproc_data(bus); 575 - unsigned int slot = PCI_SLOT(devfn); 576 - unsigned int fn = PCI_FUNC(devfn); 577 577 unsigned int busno = bus->number; 578 578 void __iomem *cfg_data_p; 579 579 unsigned int data; ··· 586 590 return ret; 587 591 } 588 592 589 - cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); 593 + cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); 590 594 591 595 if (!cfg_data_p) 592 596 return PCIBIOS_DEVICE_NOT_FOUND; ··· 627 631 int busno, unsigned int devfn, 628 632 int where) 629 633 { 630 - unsigned slot = PCI_SLOT(devfn); 631 - unsigned fn = PCI_FUNC(devfn); 632 634 u16 offset; 633 635 634 636 /* root complex access */ 635 637 if (busno == 0) { 636 - if (slot > 0 || fn > 0) 638 + if (PCIE_ECAM_DEVFN(devfn) > 0) 637 639 return NULL; 638 640 639 641 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, ··· 643 649 return (pcie->base + offset); 644 650 } 645 651 646 - return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); 652 + return iproc_pcie_map_ep_cfg_reg(pcie, busno, devfn, where); 647 653 } 648 654 649 655 static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus, ··· 1464 1470 { 1465 1471 struct device *dev; 1466 1472 int ret; 1473 + struct pci_dev *pdev; 1467 1474 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1468 1475 1469 1476 dev = pcie->dev; ··· 1526 1531 if (ret < 0) { 1527 1532 dev_err(dev, "failed to scan host: %d\n", ret); 1528 1533 goto err_power_off_phy; 1534 + } 1535 + 1536 + for_each_pci_bridge(pdev, host->bus) { 1537 + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 1538 + pcie_print_link_status(pdev); 1529 1539 } 1530 1540 1531 1541 return 0;

-2

drivers/pci/controller/pcie-rcar-host.c

··· 50 50 /* Structure representing the PCIe interface */ 51 51 struct rcar_pcie_host { 52 52 struct rcar_pcie pcie; 53 - struct device *dev; 54 53 struct phy *phy; 55 - void __iomem *base; 56 54 struct clk *bus_clk; 57 55 struct rcar_msi msi; 58 56 int (*phy_init_fn)(struct rcar_pcie_host *host);

+13 -14

drivers/pci/controller/pcie-rockchip-host.c

··· 157 157 struct pci_bus *bus, u32 devfn, 158 158 int where, int size, u32 *val) 159 159 { 160 - u32 busdev; 160 + void __iomem *addr; 161 161 162 - busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), 163 - PCI_FUNC(devfn), where); 162 + addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 164 163 165 - if (!IS_ALIGNED(busdev, size)) { 164 + if (!IS_ALIGNED((uintptr_t)addr, size)) { 166 165 *val = 0; 167 166 return PCIBIOS_BAD_REGISTER_NUMBER; 168 167 } ··· 174 175 AXI_WRAPPER_TYPE1_CFG); 175 176 176 177 if (size == 4) { 177 - *val = readl(rockchip->reg_base + busdev); 178 + *val = readl(addr); 178 179 } else if (size == 2) { 179 - *val = readw(rockchip->reg_base + busdev); 180 + *val = readw(addr); 180 181 } else if (size == 1) { 181 - *val = readb(rockchip->reg_base + busdev); 182 + *val = readb(addr); 182 183 } else { 183 184 *val = 0; 184 185 return PCIBIOS_BAD_REGISTER_NUMBER; ··· 190 191 struct pci_bus *bus, u32 devfn, 191 192 int where, int size, u32 val) 192 193 { 193 - u32 busdev; 194 + void __iomem *addr; 194 195 195 - busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), 196 - PCI_FUNC(devfn), where); 197 - if (!IS_ALIGNED(busdev, size)) 196 + addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 197 + 198 + if (!IS_ALIGNED((uintptr_t)addr, size)) 198 199 return PCIBIOS_BAD_REGISTER_NUMBER; 199 200 200 201 if (pci_is_root_bus(bus->parent)) ··· 205 206 AXI_WRAPPER_TYPE1_CFG); 206 207 207 208 if (size == 4) 208 - writel(val, rockchip->reg_base + busdev); 209 + writel(val, addr); 209 210 else if (size == 2) 210 - writew(val, rockchip->reg_base + busdev); 211 + writew(val, addr); 211 212 else if (size == 1) 212 - writeb(val, rockchip->reg_base + busdev); 213 + writeb(val, addr); 213 214 else 214 215 return PCIBIOS_BAD_REGISTER_NUMBER; 215 216

+1 -7

drivers/pci/controller/pcie-rockchip.h

··· 13 13 14 14 #include <linux/kernel.h> 15 15 #include <linux/pci.h> 16 + #include <linux/pci-ecam.h> 16 17 17 18 /* 18 19 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 ··· 179 178 #define MIN_AXI_ADDR_BITS_PASSED 8 180 179 #define PCIE_RC_SEND_PME_OFF 0x11960 181 180 #define ROCKCHIP_VENDOR_ID 0x1d87 182 - #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20) 183 - #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15) 184 - #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12) 185 - #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0) 186 - #define PCIE_ECAM_ADDR(bus, dev, func, reg) \ 187 - (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \ 188 - PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg)) 189 181 #define PCIE_LINK_IS_L2(x) \ 190 182 (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) 191 183 #define PCIE_LINK_UP(x) \

-1

drivers/pci/controller/pcie-tango.c

··· 208 208 } 209 209 210 210 static const struct pci_ecam_ops smp8759_ecam_ops = { 211 - .bus_shift = 20, 212 211 .pci_ops = { 213 212 .map_bus = pci_ecam_map_bus, 214 213 .read = smp8759_config_read,

+2 -7

drivers/pci/controller/pcie-xilinx-nwl.c

··· 18 18 #include <linux/of_platform.h> 19 19 #include <linux/of_irq.h> 20 20 #include <linux/pci.h> 21 + #include <linux/pci-ecam.h> 21 22 #include <linux/platform_device.h> 22 23 #include <linux/irqchip/chained_irq.h> 23 24 ··· 125 124 #define E_ECAM_CR_ENABLE BIT(0) 126 125 #define E_ECAM_SIZE_LOC GENMASK(20, 16) 127 126 #define E_ECAM_SIZE_SHIFT 16 128 - #define ECAM_BUS_LOC_SHIFT 20 129 - #define ECAM_DEV_LOC_SHIFT 12 130 127 #define NWL_ECAM_VALUE_DEFAULT 12 131 128 132 129 #define CFG_DMA_REG_BAR GENMASK(2, 0) ··· 239 240 int where) 240 241 { 241 242 struct nwl_pcie *pcie = bus->sysdata; 242 - int relbus; 243 243 244 244 if (!nwl_pcie_valid_device(bus, devfn)) 245 245 return NULL; 246 246 247 - relbus = (bus->number << ECAM_BUS_LOC_SHIFT) | 248 - (devfn << ECAM_DEV_LOC_SHIFT); 249 - 250 - return pcie->ecam_base + relbus + where; 247 + return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 251 248 } 252 249 253 250 /* PCIe operations */

+2 -9

drivers/pci/controller/pcie-xilinx.c

··· 21 21 #include <linux/of_platform.h> 22 22 #include <linux/of_irq.h> 23 23 #include <linux/pci.h> 24 + #include <linux/pci-ecam.h> 24 25 #include <linux/platform_device.h> 25 26 26 27 #include "../pci.h" ··· 86 85 87 86 /* Phy Status/Control Register definitions */ 88 87 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) 89 - 90 - /* ECAM definitions */ 91 - #define ECAM_BUS_NUM_SHIFT 20 92 - #define ECAM_DEV_NUM_SHIFT 12 93 88 94 89 /* Number of MSI IRQs */ 95 90 #define XILINX_NUM_MSI_IRQS 128 ··· 180 183 unsigned int devfn, int where) 181 184 { 182 185 struct xilinx_pcie_port *port = bus->sysdata; 183 - int relbus; 184 186 185 187 if (!xilinx_pcie_valid_device(bus, devfn)) 186 188 return NULL; 187 189 188 - relbus = (bus->number << ECAM_BUS_NUM_SHIFT) | 189 - (devfn << ECAM_DEV_NUM_SHIFT); 190 - 191 - return port->reg_base + relbus + where; 190 + return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 192 191 } 193 192 194 193 /* PCIe operations */

+35 -21

drivers/pci/controller/vmd.c

··· 11 11 #include <linux/module.h> 12 12 #include <linux/msi.h> 13 13 #include <linux/pci.h> 14 + #include <linux/pci-ecam.h> 14 15 #include <linux/srcu.h> 15 16 #include <linux/rculist.h> 16 17 #include <linux/rcupdate.h> ··· 53 52 * vendor-specific capability space 54 53 */ 55 54 VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2), 55 + 56 + /* 57 + * Device may use MSI-X vector 0 for software triggering and will not 58 + * be used for MSI remapping 59 + */ 60 + VMD_FEAT_OFFSET_FIRST_VECTOR = (1 << 3), 56 61 }; 57 62 58 63 /* ··· 100 93 struct pci_dev *dev; 101 94 102 95 spinlock_t cfg_lock; 103 - char __iomem *cfgbar; 96 + void __iomem *cfgbar; 104 97 105 98 int msix_count; 106 99 struct vmd_irq_list *irqs; ··· 110 103 struct irq_domain *irq_domain; 111 104 struct pci_bus *bus; 112 105 u8 busn_start; 106 + u8 first_vec; 113 107 }; 114 108 115 109 static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus) ··· 206 198 */ 207 199 static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc) 208 200 { 209 - int i, best = 1; 210 201 unsigned long flags; 202 + int i, best; 211 203 212 - if (vmd->msix_count == 1) 213 - return &vmd->irqs[0]; 204 + if (vmd->msix_count == 1 + vmd->first_vec) 205 + return &vmd->irqs[vmd->first_vec]; 214 206 215 207 /* 216 208 * White list for fast-interrupt handlers. All others will share the ··· 220 212 case PCI_CLASS_STORAGE_EXPRESS: 221 213 break; 222 214 default: 223 - return &vmd->irqs[0]; 215 + return &vmd->irqs[vmd->first_vec]; 224 216 } 225 217 226 218 raw_spin_lock_irqsave(&list_lock, flags); 227 - for (i = 1; i < vmd->msix_count; i++) 219 + best = vmd->first_vec + 1; 220 + for (i = best; i < vmd->msix_count; i++) 228 221 if (vmd->irqs[i].count < vmd->irqs[best].count) 229 222 best = i; 230 223 vmd->irqs[best].count++; ··· 333 324 } 334 325 } 335 326 336 - static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, 327 + static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, 337 328 unsigned int devfn, int reg, int len) 338 329 { 339 - char __iomem *addr = vmd->cfgbar + 340 - ((bus->number - vmd->busn_start) << 20) + 341 - (devfn << 12) + reg; 330 + unsigned int busnr_ecam = bus->number - vmd->busn_start; 331 + u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); 342 332 343 - if ((addr - vmd->cfgbar) + len >= 344 - resource_size(&vmd->dev->resource[VMD_CFGBAR])) 333 + if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) 345 334 return NULL; 346 335 347 - return addr; 336 + return vmd->cfgbar + offset; 348 337 } 349 338 350 339 /* ··· 353 346 int len, u32 *value) 354 347 { 355 348 struct vmd_dev *vmd = vmd_from_bus(bus); 356 - char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 349 + void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 357 350 unsigned long flags; 358 351 int ret = 0; 359 352 ··· 388 381 int len, u32 value) 389 382 { 390 383 struct vmd_dev *vmd = vmd_from_bus(bus); 391 - char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 384 + void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 392 385 unsigned long flags; 393 386 int ret = 0; 394 387 ··· 556 549 if (vmd->msix_count < 0) 557 550 return -ENODEV; 558 551 559 - vmd->msix_count = pci_alloc_irq_vectors(dev, 1, vmd->msix_count, 560 - PCI_IRQ_MSIX); 552 + vmd->msix_count = pci_alloc_irq_vectors(dev, vmd->first_vec + 1, 553 + vmd->msix_count, PCI_IRQ_MSIX); 561 554 if (vmd->msix_count < 0) 562 555 return vmd->msix_count; 563 556 ··· 725 718 726 719 static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id) 727 720 { 721 + unsigned long features = (unsigned long) id->driver_data; 728 722 struct vmd_dev *vmd; 729 723 int err; 730 724 ··· 750 742 dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) 751 743 return -ENODEV; 752 744 745 + if (features & VMD_FEAT_OFFSET_FIRST_VECTOR) 746 + vmd->first_vec = 1; 747 + 753 748 err = vmd_alloc_irqs(vmd); 754 749 if (err) 755 750 return err; 756 751 757 752 spin_lock_init(&vmd->cfg_lock); 758 753 pci_set_drvdata(dev, vmd); 759 - err = vmd_enable_domain(vmd, (unsigned long) id->driver_data); 754 + err = vmd_enable_domain(vmd, features); 760 755 if (err) 761 756 return err; 762 757 ··· 828 817 VMD_FEAT_HAS_BUS_RESTRICTIONS,}, 829 818 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x467f), 830 819 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | 831 - VMD_FEAT_HAS_BUS_RESTRICTIONS,}, 820 + VMD_FEAT_HAS_BUS_RESTRICTIONS | 821 + VMD_FEAT_OFFSET_FIRST_VECTOR,}, 832 822 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c3d), 833 823 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | 834 - VMD_FEAT_HAS_BUS_RESTRICTIONS,}, 824 + VMD_FEAT_HAS_BUS_RESTRICTIONS | 825 + VMD_FEAT_OFFSET_FIRST_VECTOR,}, 835 826 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B), 836 827 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | 837 - VMD_FEAT_HAS_BUS_RESTRICTIONS,}, 828 + VMD_FEAT_HAS_BUS_RESTRICTIONS | 829 + VMD_FEAT_OFFSET_FIRST_VECTOR,}, 838 830 {0,} 839 831 }; 840 832 MODULE_DEVICE_TABLE(pci, vmd_ids);

+23 -9

drivers/pci/ecam.c

··· 28 28 struct resource *cfgres, struct resource *busr, 29 29 const struct pci_ecam_ops *ops) 30 30 { 31 + unsigned int bus_shift = ops->bus_shift; 31 32 struct pci_config_window *cfg; 32 33 unsigned int bus_range, bus_range_max, bsz; 33 34 struct resource *conflict; ··· 41 40 if (!cfg) 42 41 return ERR_PTR(-ENOMEM); 43 42 43 + /* ECAM-compliant platforms need not supply ops->bus_shift */ 44 + if (!bus_shift) 45 + bus_shift = PCIE_ECAM_BUS_SHIFT; 46 + 44 47 cfg->parent = dev; 45 48 cfg->ops = ops; 46 49 cfg->busr.start = busr->start; 47 50 cfg->busr.end = busr->end; 48 51 cfg->busr.flags = IORESOURCE_BUS; 49 52 bus_range = resource_size(&cfg->busr); 50 - bus_range_max = resource_size(cfgres) >> ops->bus_shift; 53 + bus_range_max = resource_size(cfgres) >> bus_shift; 51 54 if (bus_range > bus_range_max) { 52 55 bus_range = bus_range_max; 53 56 cfg->busr.end = busr->start + bus_range - 1; 54 57 dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR desired)\n", 55 58 cfgres, &cfg->busr, busr); 56 59 } 57 - bsz = 1 << ops->bus_shift; 60 + bsz = 1 << bus_shift; 58 61 59 62 cfg->res.start = cfgres->start; 60 63 cfg->res.end = cfgres->end; ··· 136 131 int where) 137 132 { 138 133 struct pci_config_window *cfg = bus->sysdata; 134 + unsigned int bus_shift = cfg->ops->bus_shift; 139 135 unsigned int devfn_shift = cfg->ops->bus_shift - 8; 140 136 unsigned int busn = bus->number; 141 137 void __iomem *base; 138 + u32 bus_offset, devfn_offset; 142 139 143 140 if (busn < cfg->busr.start || busn > cfg->busr.end) 144 141 return NULL; 145 142 146 143 busn -= cfg->busr.start; 147 - if (per_bus_mapping) 144 + if (per_bus_mapping) { 148 145 base = cfg->winp[busn]; 149 - else 150 - base = cfg->win + (busn << cfg->ops->bus_shift); 151 - return base + (devfn << devfn_shift) + where; 146 + busn = 0; 147 + } else 148 + base = cfg->win; 149 + 150 + if (cfg->ops->bus_shift) { 151 + bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift; 152 + devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift; 153 + where &= PCIE_ECAM_REG_MASK; 154 + 155 + return base + (bus_offset | devfn_offset | where); 156 + } 157 + 158 + return base + PCIE_ECAM_OFFSET(busn, devfn, where); 152 159 } 153 160 EXPORT_SYMBOL_GPL(pci_ecam_map_bus); 154 161 155 162 /* ECAM ops */ 156 163 const struct pci_ecam_ops pci_generic_ecam_ops = { 157 - .bus_shift = 20, 158 164 .pci_ops = { 159 165 .map_bus = pci_ecam_map_bus, 160 166 .read = pci_generic_config_read, ··· 177 161 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) 178 162 /* ECAM ops for 32-bit access only (non-compliant) */ 179 163 const struct pci_ecam_ops pci_32b_ops = { 180 - .bus_shift = 20, 181 164 .pci_ops = { 182 165 .map_bus = pci_ecam_map_bus, 183 166 .read = pci_generic_config_read32, ··· 186 171 187 172 /* ECAM ops for 32-bit read only (non-compliant) */ 188 173 const struct pci_ecam_ops pci_32b_read_ops = { 189 - .bus_shift = 20, 190 174 .pci_ops = { 191 175 .map_bus = pci_ecam_map_bus, 192 176 .read = pci_generic_config_read32,

-2

drivers/pci/hotplug/ibmphp_pci.c

··· 294 294 default: 295 295 err("MAJOR PROBLEM!!!!, header type not supported? %x\n", hdr_type); 296 296 return -ENXIO; 297 - break; 298 297 } /* end of switch */ 299 298 } /* end of valid device */ 300 299 } /* end of for */ ··· 1508 1509 default: 1509 1510 err("MAJOR PROBLEM!!!! Cannot read device's header\n"); 1510 1511 return -1; 1511 - break; 1512 1512 } /* end of switch */ 1513 1513 } /* end of valid device */ 1514 1514 } /* end of for */

+65 -5

drivers/pci/msi.c

··· 26 26 27 27 #include "pci.h" 28 28 29 + #ifdef CONFIG_PCI_MSI 30 + 29 31 static int pci_msi_enable = 1; 30 32 int pci_msi_ignore_mask; 31 33 ··· 412 410 pci_intx(dev, enable); 413 411 } 414 412 413 + static void pci_msi_set_enable(struct pci_dev *dev, int enable) 414 + { 415 + u16 control; 416 + 417 + pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 418 + control &= ~PCI_MSI_FLAGS_ENABLE; 419 + if (enable) 420 + control |= PCI_MSI_FLAGS_ENABLE; 421 + pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 422 + } 423 + 415 424 static void __pci_restore_msi_state(struct pci_dev *dev) 416 425 { 417 426 u16 control; ··· 443 430 control &= ~PCI_MSI_FLAGS_QSIZE; 444 431 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; 445 432 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 433 + } 434 + 435 + static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) 436 + { 437 + u16 ctrl; 438 + 439 + pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 440 + ctrl &= ~clear; 441 + ctrl |= set; 442 + pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); 446 443 } 447 444 448 445 static void __pci_restore_msix_state(struct pci_dev *dev) ··· 623 600 struct msi_desc *entry; 624 601 625 602 for_each_pci_msi_entry(entry, dev) { 626 - if (!dev->no_64bit_msi || !entry->msg.address_hi) 627 - continue; 628 - pci_err(dev, "Device has broken 64-bit MSI but arch" 629 - " tried to assign one above 4G\n"); 630 - return -EIO; 603 + if (entry->msg.address_hi && dev->no_64bit_msi) { 604 + pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", 605 + entry->msg.address_hi, entry->msg.address_lo); 606 + return -EIO; 607 + } 631 608 } 632 609 return 0; 633 610 } ··· 1600 1577 } 1601 1578 1602 1579 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ 1580 + #endif /* CONFIG_PCI_MSI */ 1581 + 1582 + void pci_msi_init(struct pci_dev *dev) 1583 + { 1584 + u16 ctrl; 1585 + 1586 + /* 1587 + * Disable the MSI hardware to avoid screaming interrupts 1588 + * during boot. This is the power on reset default so 1589 + * usually this should be a noop. 1590 + */ 1591 + dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); 1592 + if (!dev->msi_cap) 1593 + return; 1594 + 1595 + pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); 1596 + if (ctrl & PCI_MSI_FLAGS_ENABLE) 1597 + pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, 1598 + ctrl & ~PCI_MSI_FLAGS_ENABLE); 1599 + 1600 + if (!(ctrl & PCI_MSI_FLAGS_64BIT)) 1601 + dev->no_64bit_msi = 1; 1602 + } 1603 + 1604 + void pci_msix_init(struct pci_dev *dev) 1605 + { 1606 + u16 ctrl; 1607 + 1608 + dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1609 + if (!dev->msix_cap) 1610 + return; 1611 + 1612 + pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 1613 + if (ctrl & PCI_MSIX_FLAGS_ENABLE) 1614 + pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, 1615 + ctrl & ~PCI_MSIX_FLAGS_ENABLE); 1616 + }

+5

drivers/pci/of.c

··· 556 556 break; 557 557 case IORESOURCE_MEM: 558 558 res_valid |= !(res->flags & IORESOURCE_PREFETCH); 559 + 560 + if (!(res->flags & IORESOURCE_PREFETCH)) 561 + if (upper_32_bits(resource_size(res))) 562 + dev_warn(dev, "Memory resource size exceeds max for 32 bits\n"); 563 + 559 564 break; 560 565 } 561 566 }

+5 -5

drivers/pci/p2pdma.c

··· 609 609 EXPORT_SYMBOL_GPL(pci_has_p2pmem); 610 610 611 611 /** 612 - * pci_p2pmem_find - find a peer-to-peer DMA memory device compatible with 612 + * pci_p2pmem_find_many - find a peer-to-peer DMA memory device compatible with 613 613 * the specified list of clients and shortest distance (as determined 614 614 * by pci_p2pmem_dma()) 615 615 * @clients: array of devices to check (NULL-terminated) ··· 674 674 EXPORT_SYMBOL_GPL(pci_p2pmem_find_many); 675 675 676 676 /** 677 - * pci_alloc_p2p_mem - allocate peer-to-peer DMA memory 677 + * pci_alloc_p2pmem - allocate peer-to-peer DMA memory 678 678 * @pdev: the device to allocate memory from 679 679 * @size: number of bytes to allocate 680 680 * ··· 727 727 EXPORT_SYMBOL_GPL(pci_free_p2pmem); 728 728 729 729 /** 730 - * pci_virt_to_bus - return the PCI bus address for a given virtual 730 + * pci_p2pmem_virt_to_bus - return the PCI bus address for a given virtual 731 731 * address obtained with pci_alloc_p2pmem() 732 732 * @pdev: the device the memory was allocated from 733 733 * @addr: address of the memory that was allocated ··· 859 859 } 860 860 861 861 /** 862 - * pci_p2pdma_map_sg - map a PCI peer-to-peer scatterlist for DMA 862 + * pci_p2pdma_map_sg_attrs - map a PCI peer-to-peer scatterlist for DMA 863 863 * @dev: device doing the DMA request 864 864 * @sg: scatter list to map 865 865 * @nents: elements in the scatterlist ··· 896 896 EXPORT_SYMBOL_GPL(pci_p2pdma_map_sg_attrs); 897 897 898 898 /** 899 - * pci_p2pdma_unmap_sg - unmap a PCI peer-to-peer scatterlist that was 899 + * pci_p2pdma_unmap_sg_attrs - unmap a PCI peer-to-peer scatterlist that was 900 900 * mapped with pci_p2pdma_map_sg() 901 901 * @dev: device doing the DMA request 902 902 * @sg: scatter list to map

+21 -1

drivers/pci/pci-acpi.c

··· 1162 1162 static struct acpi_device *acpi_pci_find_companion(struct device *dev) 1163 1163 { 1164 1164 struct pci_dev *pci_dev = to_pci_dev(dev); 1165 + struct acpi_device *adev; 1165 1166 bool check_children; 1166 1167 u64 addr; 1167 1168 1168 1169 check_children = pci_is_bridge(pci_dev); 1169 1170 /* Please ref to ACPI spec for the syntax of _ADR */ 1170 1171 addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn); 1171 - return acpi_find_child_device(ACPI_COMPANION(dev->parent), addr, 1172 + adev = acpi_find_child_device(ACPI_COMPANION(dev->parent), addr, 1172 1173 check_children); 1174 + 1175 + /* 1176 + * There may be ACPI device objects in the ACPI namespace that are 1177 + * children of the device object representing the host bridge, but don't 1178 + * represent PCI devices. Both _HID and _ADR may be present for them, 1179 + * even though that is against the specification (for example, see 1180 + * Section 6.1 of ACPI 6.3), but in many cases the _ADR returns 0 which 1181 + * appears to indicate that they should not be taken into consideration 1182 + * as potential companions of PCI devices on the root bus. 1183 + * 1184 + * To catch this special case, disregard the returned device object if 1185 + * it has a valid _HID, addr is 0 and the PCI device at hand is on the 1186 + * root bus. 1187 + */ 1188 + if (adev && adev->pnp.type.platform_id && !addr && 1189 + pci_is_root_bus(pci_dev->bus)) 1190 + return NULL; 1191 + 1192 + return adev; 1173 1193 } 1174 1194 1175 1195 /**

+76 -75

drivers/pci/pci-driver.c

··· 90 90 } 91 91 92 92 /** 93 - * store_new_id - sysfs frontend to pci_add_dynid() 93 + * pci_match_id - See if a PCI device matches a given pci_id table 94 + * @ids: array of PCI device ID structures to search in 95 + * @dev: the PCI device structure to match against. 96 + * 97 + * Used by a driver to check whether a PCI device is in its list of 98 + * supported devices. Returns the matching pci_device_id structure or 99 + * %NULL if there is no match. 100 + * 101 + * Deprecated; don't use this as it will not catch any dynamic IDs 102 + * that a driver might want to check for. 103 + */ 104 + const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 105 + struct pci_dev *dev) 106 + { 107 + if (ids) { 108 + while (ids->vendor || ids->subvendor || ids->class_mask) { 109 + if (pci_match_one_device(ids, dev)) 110 + return ids; 111 + ids++; 112 + } 113 + } 114 + return NULL; 115 + } 116 + EXPORT_SYMBOL(pci_match_id); 117 + 118 + static const struct pci_device_id pci_device_id_any = { 119 + .vendor = PCI_ANY_ID, 120 + .device = PCI_ANY_ID, 121 + .subvendor = PCI_ANY_ID, 122 + .subdevice = PCI_ANY_ID, 123 + }; 124 + 125 + /** 126 + * pci_match_device - See if a device matches a driver's list of IDs 127 + * @drv: the PCI driver to match against 128 + * @dev: the PCI device structure to match against 129 + * 130 + * Used by a driver to check whether a PCI device is in its list of 131 + * supported devices or in the dynids list, which may have been augmented 132 + * via the sysfs "new_id" file. Returns the matching pci_device_id 133 + * structure or %NULL if there is no match. 134 + */ 135 + static const struct pci_device_id *pci_match_device(struct pci_driver *drv, 136 + struct pci_dev *dev) 137 + { 138 + struct pci_dynid *dynid; 139 + const struct pci_device_id *found_id = NULL; 140 + 141 + /* When driver_override is set, only bind to the matching driver */ 142 + if (dev->driver_override && strcmp(dev->driver_override, drv->name)) 143 + return NULL; 144 + 145 + /* Look at the dynamic ids first, before the static ones */ 146 + spin_lock(&drv->dynids.lock); 147 + list_for_each_entry(dynid, &drv->dynids.list, node) { 148 + if (pci_match_one_device(&dynid->id, dev)) { 149 + found_id = &dynid->id; 150 + break; 151 + } 152 + } 153 + spin_unlock(&drv->dynids.lock); 154 + 155 + if (!found_id) 156 + found_id = pci_match_id(drv->id_table, dev); 157 + 158 + /* driver_override will always match, send a dummy id */ 159 + if (!found_id && dev->driver_override) 160 + found_id = &pci_device_id_any; 161 + 162 + return found_id; 163 + } 164 + 165 + /** 166 + * new_id_store - sysfs frontend to pci_add_dynid() 94 167 * @driver: target device driver 95 168 * @buf: buffer for scanning device ID data 96 169 * @count: input size ··· 198 125 pdev->subsystem_device = subdevice; 199 126 pdev->class = class; 200 127 201 - if (pci_match_id(pdrv->id_table, pdev)) 128 + if (pci_match_device(pdrv, pdev)) 202 129 retval = -EEXIST; 203 130 204 131 kfree(pdev); ··· 231 158 static DRIVER_ATTR_WO(new_id); 232 159 233 160 /** 234 - * store_remove_id - remove a PCI device ID from this driver 161 + * remove_id_store - remove a PCI device ID from this driver 235 162 * @driver: target device driver 236 163 * @buf: buffer for scanning device ID data 237 164 * @count: input size ··· 280 207 NULL, 281 208 }; 282 209 ATTRIBUTE_GROUPS(pci_drv); 283 - 284 - /** 285 - * pci_match_id - See if a pci device matches a given pci_id table 286 - * @ids: array of PCI device id structures to search in 287 - * @dev: the PCI device structure to match against. 288 - * 289 - * Used by a driver to check whether a PCI device present in the 290 - * system is in its list of supported devices. Returns the matching 291 - * pci_device_id structure or %NULL if there is no match. 292 - * 293 - * Deprecated, don't use this as it will not catch any dynamic ids 294 - * that a driver might want to check for. 295 - */ 296 - const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 297 - struct pci_dev *dev) 298 - { 299 - if (ids) { 300 - while (ids->vendor || ids->subvendor || ids->class_mask) { 301 - if (pci_match_one_device(ids, dev)) 302 - return ids; 303 - ids++; 304 - } 305 - } 306 - return NULL; 307 - } 308 - EXPORT_SYMBOL(pci_match_id); 309 - 310 - static const struct pci_device_id pci_device_id_any = { 311 - .vendor = PCI_ANY_ID, 312 - .device = PCI_ANY_ID, 313 - .subvendor = PCI_ANY_ID, 314 - .subdevice = PCI_ANY_ID, 315 - }; 316 - 317 - /** 318 - * pci_match_device - Tell if a PCI device structure has a matching PCI device id structure 319 - * @drv: the PCI driver to match against 320 - * @dev: the PCI device structure to match against 321 - * 322 - * Used by a driver to check whether a PCI device present in the 323 - * system is in its list of supported devices. Returns the matching 324 - * pci_device_id structure or %NULL if there is no match. 325 - */ 326 - static const struct pci_device_id *pci_match_device(struct pci_driver *drv, 327 - struct pci_dev *dev) 328 - { 329 - struct pci_dynid *dynid; 330 - const struct pci_device_id *found_id = NULL; 331 - 332 - /* When driver_override is set, only bind to the matching driver */ 333 - if (dev->driver_override && strcmp(dev->driver_override, drv->name)) 334 - return NULL; 335 - 336 - /* Look at the dynamic ids first, before the static ones */ 337 - spin_lock(&drv->dynids.lock); 338 - list_for_each_entry(dynid, &drv->dynids.list, node) { 339 - if (pci_match_one_device(&dynid->id, dev)) { 340 - found_id = &dynid->id; 341 - break; 342 - } 343 - } 344 - spin_unlock(&drv->dynids.lock); 345 - 346 - if (!found_id) 347 - found_id = pci_match_id(drv->id_table, dev); 348 - 349 - /* driver_override will always match, send a dummy id */ 350 - if (!found_id && dev->driver_override) 351 - found_id = &pci_device_id_any; 352 - 353 - return found_id; 354 - } 355 210 356 211 struct drv_dev_and_id { 357 212 struct pci_driver *drv;

+10

drivers/pci/pci-sysfs.c

··· 124 124 } 125 125 static DEVICE_ATTR_RO(cpulistaffinity); 126 126 127 + static ssize_t power_state_show(struct device *dev, 128 + struct device_attribute *attr, char *buf) 129 + { 130 + struct pci_dev *pdev = to_pci_dev(dev); 131 + 132 + return sprintf(buf, "%s\n", pci_power_name(pdev->current_state)); 133 + } 134 + static DEVICE_ATTR_RO(power_state); 135 + 127 136 /* show resources */ 128 137 static ssize_t resource_show(struct device *dev, struct device_attribute *attr, 129 138 char *buf) ··· 590 581 static DEVICE_ATTR_RW(driver_override); 591 582 592 583 static struct attribute *pci_dev_attrs[] = { 584 + &dev_attr_power_state.attr, 593 585 &dev_attr_resource.attr, 594 586 &dev_attr_vendor.attr, 595 587 &dev_attr_device.attr,

+80 -45

drivers/pci/pci.c

··· 399 399 return 1; 400 400 } 401 401 402 - static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 403 - u8 pos, int cap, int *ttl) 402 + static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 403 + u8 pos, int cap, int *ttl) 404 404 { 405 405 u8 id; 406 406 u16 ent; ··· 423 423 return 0; 424 424 } 425 425 426 - static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 427 - u8 pos, int cap) 426 + static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 427 + u8 pos, int cap) 428 428 { 429 429 int ttl = PCI_FIND_CAP_TTL; 430 430 431 431 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 432 432 } 433 433 434 - int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 434 + u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 435 435 { 436 436 return __pci_find_next_cap(dev->bus, dev->devfn, 437 437 pos + PCI_CAP_LIST_NEXT, cap); 438 438 } 439 439 EXPORT_SYMBOL_GPL(pci_find_next_capability); 440 440 441 - static int __pci_bus_find_cap_start(struct pci_bus *bus, 441 + static u8 __pci_bus_find_cap_start(struct pci_bus *bus, 442 442 unsigned int devfn, u8 hdr_type) 443 443 { 444 444 u16 status; ··· 477 477 * %PCI_CAP_ID_PCIX PCI-X 478 478 * %PCI_CAP_ID_EXP PCI Express 479 479 */ 480 - int pci_find_capability(struct pci_dev *dev, int cap) 480 + u8 pci_find_capability(struct pci_dev *dev, int cap) 481 481 { 482 - int pos; 482 + u8 pos; 483 483 484 484 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 485 485 if (pos) ··· 502 502 * device's PCI configuration space or 0 in case the device does not 503 503 * support it. 504 504 */ 505 - int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 505 + u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 506 506 { 507 - int pos; 508 - u8 hdr_type; 507 + u8 hdr_type, pos; 509 508 510 509 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 511 510 ··· 527 528 * not support it. Some capabilities can occur several times, e.g., the 528 529 * vendor-specific capability, and this provides a way to find them all. 529 530 */ 530 - int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) 531 + u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) 531 532 { 532 533 u32 header; 533 534 int ttl; 534 - int pos = PCI_CFG_SPACE_SIZE; 535 + u16 pos = PCI_CFG_SPACE_SIZE; 535 536 536 537 /* minimum 8 bytes per capability */ 537 538 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; ··· 582 583 * %PCI_EXT_CAP_ID_DSN Device Serial Number 583 584 * %PCI_EXT_CAP_ID_PWR Power Budgeting 584 585 */ 585 - int pci_find_ext_capability(struct pci_dev *dev, int cap) 586 + u16 pci_find_ext_capability(struct pci_dev *dev, int cap) 586 587 { 587 588 return pci_find_next_ext_capability(dev, 0, cap); 588 589 } ··· 622 623 } 623 624 EXPORT_SYMBOL_GPL(pci_get_dsn); 624 625 625 - static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 626 + static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) 626 627 { 627 628 int rc, ttl = PCI_FIND_CAP_TTL; 628 629 u8 cap, mask; ··· 649 650 650 651 return 0; 651 652 } 653 + 652 654 /** 653 - * pci_find_next_ht_capability - query a device's Hypertransport capabilities 655 + * pci_find_next_ht_capability - query a device's HyperTransport capabilities 654 656 * @dev: PCI device to query 655 657 * @pos: Position from which to continue searching 656 - * @ht_cap: Hypertransport capability code 658 + * @ht_cap: HyperTransport capability code 657 659 * 658 660 * To be used in conjunction with pci_find_ht_capability() to search for 659 661 * all capabilities matching @ht_cap. @pos should always be a value returned ··· 663 663 * NB. To be 100% safe against broken PCI devices, the caller should take 664 664 * steps to avoid an infinite loop. 665 665 */ 666 - int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 666 + u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap) 667 667 { 668 668 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 669 669 } 670 670 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 671 671 672 672 /** 673 - * pci_find_ht_capability - query a device's Hypertransport capabilities 673 + * pci_find_ht_capability - query a device's HyperTransport capabilities 674 674 * @dev: PCI device to query 675 - * @ht_cap: Hypertransport capability code 675 + * @ht_cap: HyperTransport capability code 676 676 * 677 - * Tell if a device supports a given Hypertransport capability. 677 + * Tell if a device supports a given HyperTransport capability. 678 678 * Returns an address within the device's PCI configuration space 679 679 * or 0 in case the device does not support the request capability. 680 680 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 681 - * which has a Hypertransport capability matching @ht_cap. 681 + * which has a HyperTransport capability matching @ht_cap. 682 682 */ 683 - int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 683 + u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 684 684 { 685 - int pos; 685 + u8 pos; 686 686 687 687 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 688 688 if (pos) ··· 1174 1174 } 1175 1175 EXPORT_SYMBOL_GPL(pci_platform_power_transition); 1176 1176 1177 - /** 1178 - * pci_wakeup - Wake up a PCI device 1179 - * @pci_dev: Device to handle. 1180 - * @ign: ignored parameter 1181 - */ 1182 - static int pci_wakeup(struct pci_dev *pci_dev, void *ign) 1177 + static int pci_resume_one(struct pci_dev *pci_dev, void *ign) 1183 1178 { 1184 - pci_wakeup_event(pci_dev); 1185 1179 pm_request_resume(&pci_dev->dev); 1186 1180 return 0; 1187 1181 } 1188 1182 1189 1183 /** 1190 - * pci_wakeup_bus - Walk given bus and wake up devices on it 1184 + * pci_resume_bus - Walk given bus and runtime resume devices on it 1191 1185 * @bus: Top bus of the subtree to walk. 1192 1186 */ 1193 - void pci_wakeup_bus(struct pci_bus *bus) 1187 + void pci_resume_bus(struct pci_bus *bus) 1194 1188 { 1195 1189 if (bus) 1196 - pci_walk_bus(bus, pci_wakeup, NULL); 1190 + pci_walk_bus(bus, pci_resume_one, NULL); 1197 1191 } 1198 1192 1199 1193 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) ··· 1250 1256 * may be powered on into D0uninitialized state, resume them to 1251 1257 * give them a chance to suspend again 1252 1258 */ 1253 - pci_wakeup_bus(dev->subordinate); 1259 + pci_resume_bus(dev->subordinate); 1254 1260 } 1255 1261 1256 1262 return pci_raw_set_power_state(dev, PCI_D0); ··· 1558 1564 return i; 1559 1565 1560 1566 pci_save_ltr_state(dev); 1567 + pci_save_aspm_l1ss_state(dev); 1561 1568 pci_save_dpc_state(dev); 1562 1569 pci_save_aer_state(dev); 1570 + pci_save_ptm_state(dev); 1563 1571 return pci_save_vc_state(dev); 1564 1572 } 1565 1573 EXPORT_SYMBOL(pci_save_state); ··· 1665 1669 * LTR itself (in the PCIe capability). 1666 1670 */ 1667 1671 pci_restore_ltr_state(dev); 1672 + pci_restore_aspm_l1ss_state(dev); 1668 1673 1669 1674 pci_restore_pcie_state(dev); 1670 1675 pci_restore_pasid_state(dev); ··· 1674 1677 pci_restore_vc_state(dev); 1675 1678 pci_restore_rebar_state(dev); 1676 1679 pci_restore_dpc_state(dev); 1680 + pci_restore_ptm_state(dev); 1677 1681 1678 1682 pci_aer_clear_status(dev); 1679 1683 pci_restore_aer_state(dev); ··· 2604 2606 if (target_state == PCI_POWER_ERROR) 2605 2607 return -EIO; 2606 2608 2609 + /* 2610 + * There are systems (for example, Intel mobile chips since Coffee 2611 + * Lake) where the power drawn while suspended can be significantly 2612 + * reduced by disabling PTM on PCIe root ports as this allows the 2613 + * port to enter a lower-power PM state and the SoC to reach a 2614 + * lower-power idle state as a whole. 2615 + */ 2616 + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2617 + pci_disable_ptm(dev); 2618 + 2607 2619 pci_enable_wake(dev, target_state, wakeup); 2608 2620 2609 2621 error = pci_set_power_state(dev, target_state); 2610 2622 2611 - if (error) 2623 + if (error) { 2612 2624 pci_enable_wake(dev, target_state, false); 2625 + pci_restore_ptm_state(dev); 2626 + } 2613 2627 2614 2628 return error; 2615 2629 } ··· 2659 2649 2660 2650 dev->runtime_d3cold = target_state == PCI_D3cold; 2661 2651 2652 + /* 2653 + * There are systems (for example, Intel mobile chips since Coffee 2654 + * Lake) where the power drawn while suspended can be significantly 2655 + * reduced by disabling PTM on PCIe root ports as this allows the 2656 + * port to enter a lower-power PM state and the SoC to reach a 2657 + * lower-power idle state as a whole. 2658 + */ 2659 + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2660 + pci_disable_ptm(dev); 2661 + 2662 2662 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); 2663 2663 2664 2664 error = pci_set_power_state(dev, target_state); 2665 2665 2666 2666 if (error) { 2667 2667 pci_enable_wake(dev, target_state, false); 2668 + pci_restore_ptm_state(dev); 2668 2669 dev->runtime_d3cold = false; 2669 2670 } 2670 2671 ··· 3353 3332 if (error) 3354 3333 pci_err(dev, "unable to allocate suspend buffer for LTR\n"); 3355 3334 3335 + error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS, 3336 + 2 * sizeof(u32)); 3337 + if (error) 3338 + pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n"); 3339 + 3356 3340 pci_allocate_vc_save_buffers(dev); 3357 3341 } 3358 3342 ··· 3506 3480 } 3507 3481 3508 3482 /** 3509 - * pci_acs_path_enable - test ACS flags from start to end in a hierarchy 3483 + * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy 3510 3484 * @start: starting downstream device 3511 3485 * @end: ending upstream device or NULL to search to the root bus 3512 3486 * @acs_flags: required flags ··· 4214 4188 } 4215 4189 4216 4190 size = resource_size(res); 4217 - name = res->name ?: dev_name(dev); 4191 + 4192 + if (res->name) 4193 + name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev), 4194 + res->name); 4195 + else 4196 + name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 4197 + if (!name) 4198 + return IOMEM_ERR_PTR(-ENOMEM); 4218 4199 4219 4200 if (!devm_request_mem_region(dev, res->start, size, name)) { 4220 4201 dev_err(dev, "can't request region for resource %pR\n", res); ··· 4350 4317 if (cacheline_size == pci_cache_line_size) 4351 4318 return 0; 4352 4319 4353 - pci_info(dev, "cache line size of %d is not supported\n", 4320 + pci_dbg(dev, "cache line size of %d is not supported\n", 4354 4321 pci_cache_line_size << 2); 4355 4322 4356 4323 return -EINVAL; ··· 6235 6202 while (*p) { 6236 6203 count = 0; 6237 6204 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 6238 - p[count] == '@') { 6205 + p[count] == '@') { 6239 6206 p += count + 1; 6207 + if (align_order > 63) { 6208 + pr_err("PCI: Invalid requested alignment (order %d)\n", 6209 + align_order); 6210 + align_order = PAGE_SHIFT; 6211 + } 6240 6212 } else { 6241 - align_order = -1; 6213 + align_order = PAGE_SHIFT; 6242 6214 } 6243 6215 6244 6216 ret = pci_dev_str_match(dev, p, &p); 6245 6217 if (ret == 1) { 6246 6218 *resize = true; 6247 - if (align_order == -1) 6248 - align = PAGE_SIZE; 6249 - else 6250 - align = 1 << align_order; 6219 + align = 1ULL << align_order; 6251 6220 break; 6252 6221 } else if (ret < 0) { 6253 6222 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",

+47 -25

drivers/pci/pci.h

··· 104 104 void pci_config_pm_runtime_put(struct pci_dev *dev); 105 105 void pci_pm_init(struct pci_dev *dev); 106 106 void pci_ea_init(struct pci_dev *dev); 107 + void pci_msi_init(struct pci_dev *dev); 108 + void pci_msix_init(struct pci_dev *dev); 107 109 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 108 110 void pci_free_cap_save_buffers(struct pci_dev *dev); 109 111 bool pci_bridge_d3_possible(struct pci_dev *dev); ··· 186 184 #else 187 185 static inline void pci_no_msi(void) { } 188 186 #endif 189 - 190 - static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) 191 - { 192 - u16 control; 193 - 194 - pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 195 - control &= ~PCI_MSI_FLAGS_ENABLE; 196 - if (enable) 197 - control |= PCI_MSI_FLAGS_ENABLE; 198 - pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 199 - } 200 - 201 - static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) 202 - { 203 - u16 ctrl; 204 - 205 - pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 206 - ctrl &= ~clear; 207 - ctrl |= set; 208 - pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); 209 - } 210 187 211 188 void pci_realloc_get_opt(char *); 212 189 ··· 275 294 276 295 /* PCIe link information from Link Capabilities 2 */ 277 296 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 278 - ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 297 + ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 298 + (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 279 299 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 280 300 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 281 301 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ ··· 285 303 286 304 /* PCIe speed to Mb/s reduced by encoding overhead */ 287 305 #define PCIE_SPEED2MBS_ENC(speed) \ 288 - ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 306 + ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ 307 + (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 289 308 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 290 309 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 291 310 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ ··· 431 448 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 432 449 #endif /* CONFIG_PCIEAER */ 433 450 451 + #ifdef CONFIG_PCIEPORTBUS 452 + /* Cached RCEC Endpoint Association */ 453 + struct rcec_ea { 454 + u8 nextbusn; 455 + u8 lastbusn; 456 + u32 bitmap; 457 + }; 458 + #endif 459 + 434 460 #ifdef CONFIG_PCIE_DPC 435 461 void pci_save_dpc_state(struct pci_dev *dev); 436 462 void pci_restore_dpc_state(struct pci_dev *dev); ··· 450 458 static inline void pci_save_dpc_state(struct pci_dev *dev) {} 451 459 static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 452 460 static inline void pci_dpc_init(struct pci_dev *pdev) {} 461 + #endif 462 + 463 + #ifdef CONFIG_PCIEPORTBUS 464 + void pci_rcec_init(struct pci_dev *dev); 465 + void pci_rcec_exit(struct pci_dev *dev); 466 + void pcie_link_rcec(struct pci_dev *rcec); 467 + void pcie_walk_rcec(struct pci_dev *rcec, 468 + int (*cb)(struct pci_dev *, void *), 469 + void *userdata); 470 + #else 471 + static inline void pci_rcec_init(struct pci_dev *dev) {} 472 + static inline void pci_rcec_exit(struct pci_dev *dev) {} 473 + static inline void pcie_link_rcec(struct pci_dev *rcec) {} 474 + static inline void pcie_walk_rcec(struct pci_dev *rcec, 475 + int (*cb)(struct pci_dev *, void *), 476 + void *userdata) {} 453 477 #endif 454 478 455 479 #ifdef CONFIG_PCI_ATS ··· 524 516 525 517 #endif /* CONFIG_PCI_IOV */ 526 518 519 + #ifdef CONFIG_PCIE_PTM 520 + void pci_save_ptm_state(struct pci_dev *dev); 521 + void pci_restore_ptm_state(struct pci_dev *dev); 522 + void pci_disable_ptm(struct pci_dev *dev); 523 + #else 524 + static inline void pci_save_ptm_state(struct pci_dev *dev) { } 525 + static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 526 + static inline void pci_disable_ptm(struct pci_dev *dev) { } 527 + #endif 528 + 527 529 unsigned long pci_cardbus_resource_alignment(struct resource *); 528 530 529 531 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, ··· 573 555 574 556 /* PCI error reporting and recovery */ 575 557 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 576 - pci_channel_state_t state, 577 - pci_ers_result_t (*reset_link)(struct pci_dev *pdev)); 558 + pci_channel_state_t state, 559 + pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 578 560 579 561 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 580 562 #ifdef CONFIG_PCIEASPM ··· 582 564 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 583 565 void pcie_aspm_pm_state_change(struct pci_dev *pdev); 584 566 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 567 + void pci_save_aspm_l1ss_state(struct pci_dev *dev); 568 + void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 585 569 #else 586 570 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 587 571 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 588 572 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 589 573 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 574 + static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { } 575 + static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { } 590 576 #endif 591 577 592 578 #ifdef CONFIG_PCIE_ECRC

+1 -1

drivers/pci/pcie/Makefile

··· 2 2 # 3 3 # Makefile for PCI Express features and port driver 4 4 5 - pcieportdrv-y := portdrv_core.o portdrv_pci.o err.o 5 + pcieportdrv-y := portdrv_core.o portdrv_pci.o err.o rcec.o 6 6 7 7 obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o 8 8

+75 -26

drivers/pci/pcie/aer.c

··· 300 300 return -EIO; 301 301 302 302 port_type = pci_pcie_type(dev); 303 - if (port_type == PCI_EXP_TYPE_ROOT_PORT) { 303 + if (port_type == PCI_EXP_TYPE_ROOT_PORT || 304 + port_type == PCI_EXP_TYPE_RC_EC) { 304 305 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status); 305 306 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status); 306 307 } ··· 596 595 if ((a == &dev_attr_aer_rootport_total_err_cor.attr || 597 596 a == &dev_attr_aer_rootport_total_err_fatal.attr || 598 597 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) && 599 - pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) 598 + ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && 599 + (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC))) 600 600 return 0; 601 601 602 602 return a->mode; ··· 918 916 if (result) 919 917 return true; 920 918 921 - pci_walk_bus(parent->subordinate, find_device_iter, e_info); 919 + if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC) 920 + pcie_walk_rcec(parent, find_device_iter, e_info); 921 + else 922 + pci_walk_bus(parent->subordinate, find_device_iter, e_info); 922 923 923 924 if (!e_info->error_dev_num) { 924 925 pci_info(parent, "can't find device of ID%04x\n", e_info->id); ··· 1039 1034 */ 1040 1035 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) 1041 1036 { 1037 + int type = pci_pcie_type(dev); 1042 1038 int aer = dev->aer_cap; 1043 1039 int temp; 1044 1040 ··· 1058 1052 &info->mask); 1059 1053 if (!(info->status & ~info->mask)) 1060 1054 return 0; 1061 - } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 1062 - pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM || 1055 + } else if (type == PCI_EXP_TYPE_ROOT_PORT || 1056 + type == PCI_EXP_TYPE_RC_EC || 1057 + type == PCI_EXP_TYPE_DOWNSTREAM || 1063 1058 info->severity == AER_NONFATAL) { 1064 1059 1065 1060 /* Link is still healthy for IO reads */ ··· 1212 1205 int type = pci_pcie_type(dev); 1213 1206 1214 1207 if ((type == PCI_EXP_TYPE_ROOT_PORT) || 1208 + (type == PCI_EXP_TYPE_RC_EC) || 1215 1209 (type == PCI_EXP_TYPE_UPSTREAM) || 1216 1210 (type == PCI_EXP_TYPE_DOWNSTREAM)) { 1217 1211 if (enable) ··· 1237 1229 { 1238 1230 set_device_error_reporting(dev, &enable); 1239 1231 1240 - if (!dev->subordinate) 1241 - return; 1242 - pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable); 1232 + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) 1233 + pcie_walk_rcec(dev, set_device_error_reporting, &enable); 1234 + else if (dev->subordinate) 1235 + pci_walk_bus(dev->subordinate, set_device_error_reporting, 1236 + &enable); 1237 + 1243 1238 } 1244 1239 1245 1240 /** ··· 1340 1329 struct device *device = &dev->device; 1341 1330 struct pci_dev *port = dev->port; 1342 1331 1332 + /* Limit to Root Ports or Root Complex Event Collectors */ 1333 + if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) && 1334 + (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT)) 1335 + return -ENODEV; 1336 + 1343 1337 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL); 1344 1338 if (!rpc) 1345 1339 return -ENOMEM; ··· 1366 1350 } 1367 1351 1368 1352 /** 1369 - * aer_root_reset - reset link on Root Port 1370 - * @dev: pointer to Root Port's pci_dev data structure 1353 + * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP 1354 + * @dev: pointer to Root Port, RCEC, or RCiEP 1371 1355 * 1372 - * Invoked by Port Bus driver when performing link reset at Root Port. 1356 + * Invoked by Port Bus driver when performing reset. 1373 1357 */ 1374 1358 static pci_ers_result_t aer_root_reset(struct pci_dev *dev) 1375 1359 { 1376 - int aer = dev->aer_cap; 1360 + int type = pci_pcie_type(dev); 1361 + struct pci_dev *root; 1362 + int aer; 1363 + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 1377 1364 u32 reg32; 1378 1365 int rc; 1379 1366 1367 + /* 1368 + * Only Root Ports and RCECs have AER Root Command and Root Status 1369 + * registers. If "dev" is an RCiEP, the relevant registers are in 1370 + * the RCEC. 1371 + */ 1372 + if (type == PCI_EXP_TYPE_RC_END) 1373 + root = dev->rcec; 1374 + else 1375 + root = dev; 1380 1376 1381 - /* Disable Root's interrupt in response to error messages */ 1382 - pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, &reg32); 1383 - reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1384 - pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1377 + /* 1378 + * If the platform retained control of AER, an RCiEP may not have 1379 + * an RCEC visible to us, so dev->rcec ("root") may be NULL. In 1380 + * that case, firmware is responsible for these registers. 1381 + */ 1382 + aer = root ? root->aer_cap : 0; 1385 1383 1386 - rc = pci_bus_error_reset(dev); 1387 - pci_info(dev, "Root Port link has been reset\n"); 1384 + if ((host->native_aer || pcie_ports_native) && aer) { 1385 + /* Disable Root's interrupt in response to error messages */ 1386 + pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32); 1387 + reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1388 + pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32); 1389 + } 1388 1390 1389 - /* Clear Root Error Status */ 1390 - pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &reg32); 1391 - pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, reg32); 1391 + if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { 1392 + if (pcie_has_flr(dev)) { 1393 + rc = pcie_flr(dev); 1394 + pci_info(dev, "has been reset (%d)\n", rc); 1395 + } else { 1396 + pci_info(dev, "not reset (no FLR support)\n"); 1397 + rc = -ENOTTY; 1398 + } 1399 + } else { 1400 + rc = pci_bus_error_reset(dev); 1401 + pci_info(dev, "Root Port link has been reset (%d)\n", rc); 1402 + } 1392 1403 1393 - /* Enable Root Port's interrupt in response to error messages */ 1394 - pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, &reg32); 1395 - reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1396 - pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1404 + if ((host->native_aer || pcie_ports_native) && aer) { 1405 + /* Clear Root Error Status */ 1406 + pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, &reg32); 1407 + pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32); 1408 + 1409 + /* Enable Root Port's interrupt in response to error messages */ 1410 + pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32); 1411 + reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1412 + pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32); 1413 + } 1397 1414 1398 1415 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1399 1416 } 1400 1417 1401 1418 static struct pcie_port_service_driver aerdriver = { 1402 1419 .name = "aer", 1403 - .port_type = PCI_EXP_TYPE_ROOT_PORT, 1420 + .port_type = PCIE_ANY_PORT, 1404 1421 .service = PCIE_PORT_SERVICE_AER, 1405 1422 1406 1423 .probe = aer_probe,

+4 -1

drivers/pci/pcie/aer_inject.c

··· 333 333 if (!dev) 334 334 return -ENODEV; 335 335 rpdev = pcie_find_root_port(dev); 336 + /* If Root Port not found, try to find an RCEC */ 337 + if (!rpdev) 338 + rpdev = dev->rcec; 336 339 if (!rpdev) { 337 - pci_err(dev, "Root port not found\n"); 340 + pci_err(dev, "Neither Root Port nor RCEC found\n"); 338 341 ret = -ENODEV; 339 342 goto out_put; 340 343 }

+44

drivers/pci/pcie/aspm.c

··· 734 734 PCI_L1SS_CTL1_L1SS_MASK, val); 735 735 } 736 736 737 + void pci_save_aspm_l1ss_state(struct pci_dev *dev) 738 + { 739 + int aspm_l1ss; 740 + struct pci_cap_saved_state *save_state; 741 + u32 *cap; 742 + 743 + if (!pci_is_pcie(dev)) 744 + return; 745 + 746 + aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); 747 + if (!aspm_l1ss) 748 + return; 749 + 750 + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS); 751 + if (!save_state) 752 + return; 753 + 754 + cap = (u32 *)&save_state->cap.data[0]; 755 + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap++); 756 + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, cap++); 757 + } 758 + 759 + void pci_restore_aspm_l1ss_state(struct pci_dev *dev) 760 + { 761 + int aspm_l1ss; 762 + struct pci_cap_saved_state *save_state; 763 + u32 *cap; 764 + 765 + if (!pci_is_pcie(dev)) 766 + return; 767 + 768 + aspm_l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); 769 + if (!aspm_l1ss) 770 + return; 771 + 772 + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS); 773 + if (!save_state) 774 + return; 775 + 776 + cap = (u32 *)&save_state->cap.data[0]; 777 + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap++); 778 + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, *cap++); 779 + } 780 + 737 781 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) 738 782 { 739 783 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,

+68 -27

drivers/pci/pcie/err.c

··· 146 146 return 0; 147 147 } 148 148 149 - pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 150 - pci_channel_state_t state, 151 - pci_ers_result_t (*reset_link)(struct pci_dev *pdev)) 149 + /** 150 + * pci_walk_bridge - walk bridges potentially AER affected 151 + * @bridge: bridge which may be a Port, an RCEC, or an RCiEP 152 + * @cb: callback to be called for each device found 153 + * @userdata: arbitrary pointer to be passed to callback 154 + * 155 + * If the device provided is a bridge, walk the subordinate bus, including 156 + * any bridged devices on buses under this bus. Call the provided callback 157 + * on each device found. 158 + * 159 + * If the device provided has no subordinate bus, e.g., an RCEC or RCiEP, 160 + * call the callback on the device itself. 161 + */ 162 + static void pci_walk_bridge(struct pci_dev *bridge, 163 + int (*cb)(struct pci_dev *, void *), 164 + void *userdata) 152 165 { 166 + if (bridge->subordinate) 167 + pci_walk_bus(bridge->subordinate, cb, userdata); 168 + else 169 + cb(bridge, userdata); 170 + } 171 + 172 + pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 173 + pci_channel_state_t state, 174 + pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)) 175 + { 176 + int type = pci_pcie_type(dev); 177 + struct pci_dev *bridge; 153 178 pci_ers_result_t status = PCI_ERS_RESULT_CAN_RECOVER; 154 - struct pci_bus *bus; 179 + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 155 180 156 181 /* 157 - * Error recovery runs on all subordinates of the first downstream port. 158 - * If the downstream port detected the error, it is cleared at the end. 182 + * If the error was detected by a Root Port, Downstream Port, RCEC, 183 + * or RCiEP, recovery runs on the device itself. For Ports, that 184 + * also includes any subordinate devices. 185 + * 186 + * If it was detected by another device (Endpoint, etc), recovery 187 + * runs on the device and anything else under the same Port, i.e., 188 + * everything under "bridge". 159 189 */ 160 - if (!(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 161 - pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)) 162 - dev = dev->bus->self; 163 - bus = dev->subordinate; 190 + if (type == PCI_EXP_TYPE_ROOT_PORT || 191 + type == PCI_EXP_TYPE_DOWNSTREAM || 192 + type == PCI_EXP_TYPE_RC_EC || 193 + type == PCI_EXP_TYPE_RC_END) 194 + bridge = dev; 195 + else 196 + bridge = pci_upstream_bridge(dev); 164 197 165 - pci_dbg(dev, "broadcast error_detected message\n"); 198 + pci_dbg(bridge, "broadcast error_detected message\n"); 166 199 if (state == pci_channel_io_frozen) { 167 - pci_walk_bus(bus, report_frozen_detected, &status); 168 - status = reset_link(dev); 200 + pci_walk_bridge(bridge, report_frozen_detected, &status); 201 + status = reset_subordinates(bridge); 169 202 if (status != PCI_ERS_RESULT_RECOVERED) { 170 - pci_warn(dev, "link reset failed\n"); 203 + pci_warn(bridge, "subordinate device reset failed\n"); 171 204 goto failed; 172 205 } 173 206 } else { 174 - pci_walk_bus(bus, report_normal_detected, &status); 207 + pci_walk_bridge(bridge, report_normal_detected, &status); 175 208 } 176 209 177 210 if (status == PCI_ERS_RESULT_CAN_RECOVER) { 178 211 status = PCI_ERS_RESULT_RECOVERED; 179 - pci_dbg(dev, "broadcast mmio_enabled message\n"); 180 - pci_walk_bus(bus, report_mmio_enabled, &status); 212 + pci_dbg(bridge, "broadcast mmio_enabled message\n"); 213 + pci_walk_bridge(bridge, report_mmio_enabled, &status); 181 214 } 182 215 183 216 if (status == PCI_ERS_RESULT_NEED_RESET) { ··· 220 187 * drivers' slot_reset callbacks? 221 188 */ 222 189 status = PCI_ERS_RESULT_RECOVERED; 223 - pci_dbg(dev, "broadcast slot_reset message\n"); 224 - pci_walk_bus(bus, report_slot_reset, &status); 190 + pci_dbg(bridge, "broadcast slot_reset message\n"); 191 + pci_walk_bridge(bridge, report_slot_reset, &status); 225 192 } 226 193 227 194 if (status != PCI_ERS_RESULT_RECOVERED) 228 195 goto failed; 229 196 230 - pci_dbg(dev, "broadcast resume message\n"); 231 - pci_walk_bus(bus, report_resume, &status); 197 + pci_dbg(bridge, "broadcast resume message\n"); 198 + pci_walk_bridge(bridge, report_resume, &status); 232 199 233 - if (pcie_aer_is_native(dev)) 234 - pcie_clear_device_status(dev); 235 - pci_aer_clear_nonfatal_status(dev); 236 - pci_info(dev, "device recovery successful\n"); 200 + /* 201 + * If we have native control of AER, clear error status in the Root 202 + * Port or Downstream Port that signaled the error. If the 203 + * platform retained control of AER, it is responsible for clearing 204 + * this status. In that case, the signaling device may not even be 205 + * visible to the OS. 206 + */ 207 + if (host->native_aer || pcie_ports_native) { 208 + pcie_clear_device_status(bridge); 209 + pci_aer_clear_nonfatal_status(bridge); 210 + } 211 + pci_info(bridge, "device recovery successful\n"); 237 212 return status; 238 213 239 214 failed: 240 - pci_uevent_ers(dev, PCI_ERS_RESULT_DISCONNECT); 215 + pci_uevent_ers(bridge, PCI_ERS_RESULT_DISCONNECT); 241 216 242 217 /* TODO: Should kernel panic here? */ 243 - pci_info(dev, "device recovery failed\n"); 218 + pci_info(bridge, "device recovery failed\n"); 244 219 245 220 return status; 246 221 }

+12 -4

drivers/pci/pcie/pme.c

··· 310 310 static void pcie_pme_mark_devices(struct pci_dev *port) 311 311 { 312 312 pcie_pme_can_wakeup(port, NULL); 313 - if (port->subordinate) 313 + 314 + if (pci_pcie_type(port) == PCI_EXP_TYPE_RC_EC) 315 + pcie_walk_rcec(port, pcie_pme_can_wakeup, NULL); 316 + else if (port->subordinate) 314 317 pci_walk_bus(port->subordinate, pcie_pme_can_wakeup, NULL); 315 318 } 316 319 ··· 323 320 */ 324 321 static int pcie_pme_probe(struct pcie_device *srv) 325 322 { 326 - struct pci_dev *port; 323 + struct pci_dev *port = srv->port; 327 324 struct pcie_pme_service_data *data; 325 + int type = pci_pcie_type(port); 328 326 int ret; 327 + 328 + /* Limit to Root Ports or Root Complex Event Collectors */ 329 + if (type != PCI_EXP_TYPE_RC_EC && 330 + type != PCI_EXP_TYPE_ROOT_PORT) 331 + return -ENODEV; 329 332 330 333 data = kzalloc(sizeof(*data), GFP_KERNEL); 331 334 if (!data) ··· 342 333 data->srv = srv; 343 334 set_service_data(srv, data); 344 335 345 - port = srv->port; 346 336 pcie_pme_interrupt_enable(port, false); 347 337 pcie_clear_root_pme_status(port); 348 338 ··· 453 445 454 446 static struct pcie_port_service_driver pcie_pme_driver = { 455 447 .name = "pcie_pme", 456 - .port_type = PCI_EXP_TYPE_ROOT_PORT, 448 + .port_type = PCIE_ANY_PORT, 457 449 .service = PCIE_PORT_SERVICE_PME, 458 450 459 451 .probe = pcie_pme_probe,

+3 -6

drivers/pci/pcie/portdrv_core.c

··· 233 233 } 234 234 #endif 235 235 236 - /* 237 - * Root ports are capable of generating PME too. Root Complex 238 - * Event Collectors can also generate PMEs, but we don't handle 239 - * those yet. 240 - */ 241 - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && 236 + /* Root Ports and Root Complex Event Collectors may generate PMEs */ 237 + if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 238 + pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) && 242 239 (pcie_ports_native || host->native_pme)) { 243 240 services |= PCIE_PORT_SERVICE_PME; 244 241

+10 -3

drivers/pci/pcie/portdrv_pci.c

··· 101 101 static int pcie_portdrv_probe(struct pci_dev *dev, 102 102 const struct pci_device_id *id) 103 103 { 104 + int type = pci_pcie_type(dev); 104 105 int status; 105 106 106 107 if (!pci_is_pcie(dev) || 107 - ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 108 - (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) && 109 - (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 108 + ((type != PCI_EXP_TYPE_ROOT_PORT) && 109 + (type != PCI_EXP_TYPE_UPSTREAM) && 110 + (type != PCI_EXP_TYPE_DOWNSTREAM) && 111 + (type != PCI_EXP_TYPE_RC_EC))) 110 112 return -ENODEV; 113 + 114 + if (type == PCI_EXP_TYPE_RC_EC) 115 + pcie_link_rcec(dev); 111 116 112 117 status = pcie_port_device_register(dev); 113 118 if (status) ··· 200 195 { PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0) }, 201 196 /* subtractive decode PCI-to-PCI bridge, class type is 060401h */ 202 197 { PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x01), ~0) }, 198 + /* handle any Root Complex Event Collector */ 199 + { PCI_DEVICE_CLASS(((PCI_CLASS_SYSTEM_RCEC << 8) | 0x00), ~0) }, 203 200 { }, 204 201 }; 205 202

+60

drivers/pci/pcie/ptm.c

··· 29 29 dev->ptm_root ? " (root)" : "", clock_desc); 30 30 } 31 31 32 + void pci_disable_ptm(struct pci_dev *dev) 33 + { 34 + int ptm; 35 + u16 ctrl; 36 + 37 + if (!pci_is_pcie(dev)) 38 + return; 39 + 40 + ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 41 + if (!ptm) 42 + return; 43 + 44 + pci_read_config_word(dev, ptm + PCI_PTM_CTRL, &ctrl); 45 + ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT); 46 + pci_write_config_word(dev, ptm + PCI_PTM_CTRL, ctrl); 47 + } 48 + 49 + void pci_save_ptm_state(struct pci_dev *dev) 50 + { 51 + int ptm; 52 + struct pci_cap_saved_state *save_state; 53 + u16 *cap; 54 + 55 + if (!pci_is_pcie(dev)) 56 + return; 57 + 58 + ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 59 + if (!ptm) 60 + return; 61 + 62 + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM); 63 + if (!save_state) { 64 + pci_err(dev, "no suspend buffer for PTM\n"); 65 + return; 66 + } 67 + 68 + cap = (u16 *)&save_state->cap.data[0]; 69 + pci_read_config_word(dev, ptm + PCI_PTM_CTRL, cap); 70 + } 71 + 72 + void pci_restore_ptm_state(struct pci_dev *dev) 73 + { 74 + struct pci_cap_saved_state *save_state; 75 + int ptm; 76 + u16 *cap; 77 + 78 + if (!pci_is_pcie(dev)) 79 + return; 80 + 81 + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM); 82 + ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 83 + if (!save_state || !ptm) 84 + return; 85 + 86 + cap = (u16 *)&save_state->cap.data[0]; 87 + pci_write_config_word(dev, ptm + PCI_PTM_CTRL, *cap); 88 + } 89 + 32 90 void pci_ptm_init(struct pci_dev *dev) 33 91 { 34 92 int pos; ··· 122 64 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 123 65 if (!pos) 124 66 return; 67 + 68 + pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u16)); 125 69 126 70 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap); 127 71 local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;

+190

drivers/pci/pcie/rcec.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Root Complex Event Collector Support 4 + * 5 + * Authors: 6 + * Sean V Kelley <sean.v.kelley@intel.com> 7 + * Qiuxu Zhuo <qiuxu.zhuo@intel.com> 8 + * 9 + * Copyright (C) 2020 Intel Corp. 10 + */ 11 + 12 + #include <linux/kernel.h> 13 + #include <linux/pci.h> 14 + #include <linux/pci_regs.h> 15 + 16 + #include "../pci.h" 17 + 18 + struct walk_rcec_data { 19 + struct pci_dev *rcec; 20 + int (*user_callback)(struct pci_dev *dev, void *data); 21 + void *user_data; 22 + }; 23 + 24 + static bool rcec_assoc_rciep(struct pci_dev *rcec, struct pci_dev *rciep) 25 + { 26 + unsigned long bitmap = rcec->rcec_ea->bitmap; 27 + unsigned int devn; 28 + 29 + /* An RCiEP found on a different bus in range */ 30 + if (rcec->bus->number != rciep->bus->number) 31 + return true; 32 + 33 + /* Same bus, so check bitmap */ 34 + for_each_set_bit(devn, &bitmap, 32) 35 + if (devn == rciep->devfn) 36 + return true; 37 + 38 + return false; 39 + } 40 + 41 + static int link_rcec_helper(struct pci_dev *dev, void *data) 42 + { 43 + struct walk_rcec_data *rcec_data = data; 44 + struct pci_dev *rcec = rcec_data->rcec; 45 + 46 + if ((pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) && 47 + rcec_assoc_rciep(rcec, dev)) { 48 + dev->rcec = rcec; 49 + pci_dbg(dev, "PME & error events signaled via %s\n", 50 + pci_name(rcec)); 51 + } 52 + 53 + return 0; 54 + } 55 + 56 + static int walk_rcec_helper(struct pci_dev *dev, void *data) 57 + { 58 + struct walk_rcec_data *rcec_data = data; 59 + struct pci_dev *rcec = rcec_data->rcec; 60 + 61 + if ((pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) && 62 + rcec_assoc_rciep(rcec, dev)) 63 + rcec_data->user_callback(dev, rcec_data->user_data); 64 + 65 + return 0; 66 + } 67 + 68 + static void walk_rcec(int (*cb)(struct pci_dev *dev, void *data), 69 + void *userdata) 70 + { 71 + struct walk_rcec_data *rcec_data = userdata; 72 + struct pci_dev *rcec = rcec_data->rcec; 73 + u8 nextbusn, lastbusn; 74 + struct pci_bus *bus; 75 + unsigned int bnr; 76 + 77 + if (!rcec->rcec_ea) 78 + return; 79 + 80 + /* Walk own bus for bitmap based association */ 81 + pci_walk_bus(rcec->bus, cb, rcec_data); 82 + 83 + nextbusn = rcec->rcec_ea->nextbusn; 84 + lastbusn = rcec->rcec_ea->lastbusn; 85 + 86 + /* All RCiEP devices are on the same bus as the RCEC */ 87 + if (nextbusn == 0xff && lastbusn == 0x00) 88 + return; 89 + 90 + for (bnr = nextbusn; bnr <= lastbusn; bnr++) { 91 + /* No association indicated (PCIe 5.0-1, 7.9.10.3) */ 92 + if (bnr == rcec->bus->number) 93 + continue; 94 + 95 + bus = pci_find_bus(pci_domain_nr(rcec->bus), bnr); 96 + if (!bus) 97 + continue; 98 + 99 + /* Find RCiEP devices on the given bus ranges */ 100 + pci_walk_bus(bus, cb, rcec_data); 101 + } 102 + } 103 + 104 + /** 105 + * pcie_link_rcec - Link RCiEP devices associated with RCEC. 106 + * @rcec: RCEC whose RCiEP devices should be linked. 107 + * 108 + * Link the given RCEC to each RCiEP device found. 109 + */ 110 + void pcie_link_rcec(struct pci_dev *rcec) 111 + { 112 + struct walk_rcec_data rcec_data; 113 + 114 + if (!rcec->rcec_ea) 115 + return; 116 + 117 + rcec_data.rcec = rcec; 118 + rcec_data.user_callback = NULL; 119 + rcec_data.user_data = NULL; 120 + 121 + walk_rcec(link_rcec_helper, &rcec_data); 122 + } 123 + 124 + /** 125 + * pcie_walk_rcec - Walk RCiEP devices associating with RCEC and call callback. 126 + * @rcec: RCEC whose RCiEP devices should be walked 127 + * @cb: Callback to be called for each RCiEP device found 128 + * @userdata: Arbitrary pointer to be passed to callback 129 + * 130 + * Walk the given RCEC. Call the callback on each RCiEP found. 131 + * 132 + * If @cb returns anything other than 0, break out. 133 + */ 134 + void pcie_walk_rcec(struct pci_dev *rcec, int (*cb)(struct pci_dev *, void *), 135 + void *userdata) 136 + { 137 + struct walk_rcec_data rcec_data; 138 + 139 + if (!rcec->rcec_ea) 140 + return; 141 + 142 + rcec_data.rcec = rcec; 143 + rcec_data.user_callback = cb; 144 + rcec_data.user_data = userdata; 145 + 146 + walk_rcec(walk_rcec_helper, &rcec_data); 147 + } 148 + 149 + void pci_rcec_init(struct pci_dev *dev) 150 + { 151 + struct rcec_ea *rcec_ea; 152 + u32 rcec, hdr, busn; 153 + u8 ver; 154 + 155 + /* Only for Root Complex Event Collectors */ 156 + if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_EC) 157 + return; 158 + 159 + rcec = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_RCEC); 160 + if (!rcec) 161 + return; 162 + 163 + rcec_ea = kzalloc(sizeof(*rcec_ea), GFP_KERNEL); 164 + if (!rcec_ea) 165 + return; 166 + 167 + pci_read_config_dword(dev, rcec + PCI_RCEC_RCIEP_BITMAP, 168 + &rcec_ea->bitmap); 169 + 170 + /* Check whether RCEC BUSN register is present */ 171 + pci_read_config_dword(dev, rcec, &hdr); 172 + ver = PCI_EXT_CAP_VER(hdr); 173 + if (ver >= PCI_RCEC_BUSN_REG_VER) { 174 + pci_read_config_dword(dev, rcec + PCI_RCEC_BUSN, &busn); 175 + rcec_ea->nextbusn = PCI_RCEC_BUSN_NEXT(busn); 176 + rcec_ea->lastbusn = PCI_RCEC_BUSN_LAST(busn); 177 + } else { 178 + /* Avoid later ver check by setting nextbusn */ 179 + rcec_ea->nextbusn = 0xff; 180 + rcec_ea->lastbusn = 0x00; 181 + } 182 + 183 + dev->rcec_ea = rcec_ea; 184 + } 185 + 186 + void pci_rcec_exit(struct pci_dev *dev) 187 + { 188 + kfree(dev->rcec_ea); 189 + dev->rcec_ea = NULL; 190 + }

+8 -22

drivers/pci/probe.c

··· 165 165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 166 166 167 167 /** 168 - * pci_read_base - Read a PCI BAR 168 + * __pci_read_base - Read a PCI BAR 169 169 * @dev: the PCI device 170 170 * @type: type of the BAR 171 171 * @res: resource buffer to be filled in ··· 677 677 PCIE_SPEED_8_0GT, /* 3 */ 678 678 PCIE_SPEED_16_0GT, /* 4 */ 679 679 PCIE_SPEED_32_0GT, /* 5 */ 680 - PCI_SPEED_UNKNOWN, /* 6 */ 680 + PCIE_SPEED_64_0GT, /* 6 */ 681 681 PCI_SPEED_UNKNOWN, /* 7 */ 682 682 PCI_SPEED_UNKNOWN, /* 8 */ 683 683 PCI_SPEED_UNKNOWN, /* 9 */ ··· 719 719 "8.0 GT/s PCIe", /* 0x16 */ 720 720 "16.0 GT/s PCIe", /* 0x17 */ 721 721 "32.0 GT/s PCIe", /* 0x18 */ 722 + "64.0 GT/s PCIe", /* 0x19 */ 722 723 }; 723 724 724 725 if (speed < ARRAY_SIZE(speed_strings)) ··· 1613 1612 } 1614 1613 1615 1614 /** 1616 - * pci_cfg_space_size - Get the configuration space size of the PCI device 1615 + * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1617 1616 * @dev: PCI device 1618 1617 * 1619 1618 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices ··· 1716 1715 } 1717 1716 1718 1717 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1719 - 1720 - static void pci_msi_setup_pci_dev(struct pci_dev *dev) 1721 - { 1722 - /* 1723 - * Disable the MSI hardware to avoid screaming interrupts 1724 - * during boot. This is the power on reset default so 1725 - * usually this should be a noop. 1726 - */ 1727 - dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); 1728 - if (dev->msi_cap) 1729 - pci_msi_set_enable(dev, 0); 1730 - 1731 - dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1732 - if (dev->msix_cap) 1733 - pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); 1734 - } 1735 1718 1736 1719 /** 1737 1720 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability ··· 2201 2216 static void pci_release_capabilities(struct pci_dev *dev) 2202 2217 { 2203 2218 pci_aer_exit(dev); 2219 + pci_rcec_exit(dev); 2204 2220 pci_vpd_release(dev); 2205 2221 pci_iov_release(dev); 2206 2222 pci_free_cap_save_buffers(dev); ··· 2383 2397 static void pci_init_capabilities(struct pci_dev *dev) 2384 2398 { 2385 2399 pci_ea_init(dev); /* Enhanced Allocation */ 2386 - 2387 - /* Setup MSI caps & disable MSI/MSI-X interrupts */ 2388 - pci_msi_setup_pci_dev(dev); 2400 + pci_msi_init(dev); /* Disable MSI */ 2401 + pci_msix_init(dev); /* Disable MSI-X */ 2389 2402 2390 2403 /* Buffers for saving PCIe and PCI-X capabilities */ 2391 2404 pci_allocate_cap_save_buffers(dev); ··· 2400 2415 pci_ptm_init(dev); /* Precision Time Measurement */ 2401 2416 pci_aer_init(dev); /* Advanced Error Reporting */ 2402 2417 pci_dpc_init(dev); /* Downstream Port Containment */ 2418 + pci_rcec_init(dev); /* Root Complex Event Collector */ 2403 2419 2404 2420 pcie_report_downtraining(dev); 2405 2421

+34 -7

drivers/pci/quirks.c

··· 2356 2356 dev->clear_retrain_link = 1; 2357 2357 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2358 2358 } 2359 - DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link); 2360 - DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link); 2361 - DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link); 2359 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2360 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2361 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2362 2362 2363 2363 static void fixup_rev1_53c810(struct pci_dev *dev) 2364 2364 { ··· 2522 2522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2523 2523 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2524 2524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2525 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2525 2526 2526 2527 /* Disable MSI on chipsets that are known to not support it */ 2527 2528 static void quirk_disable_msi(struct pci_dev *dev) ··· 3999 3998 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4000 3999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4001 4000 quirk_dma_func1_alias); 4001 + /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4002 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4003 + quirk_dma_func1_alias); 4002 4004 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4003 4005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4004 4006 quirk_dma_func1_alias); ··· 5168 5164 (pdev->device == 0x7340 && pdev->revision != 0xc5)) 5169 5165 return; 5170 5166 5167 + if (pdev->device == 0x15d8) { 5168 + if (pdev->revision == 0xcf && 5169 + pdev->subsystem_vendor == 0xea50 && 5170 + (pdev->subsystem_device == 0xce19 || 5171 + pdev->subsystem_device == 0xcc10 || 5172 + pdev->subsystem_device == 0xcc08)) 5173 + goto no_ats; 5174 + else 5175 + return; 5176 + } 5177 + 5178 + no_ats: 5171 5179 pci_info(pdev, "disabling ATS\n"); 5172 5180 pdev->ats_cap = 0; 5173 5181 } ··· 5192 5176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5193 5177 /* AMD Navi14 dGPU */ 5194 5178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5179 + /* AMD Raven platform iGPU */ 5180 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5195 5181 #endif /* CONFIG_PCI_ATS */ 5196 5182 5197 5183 /* Freescale PCIe doesn't support MSI in RC mode */ ··· 5585 5567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 5586 5568 5587 5569 /* 5588 - * Device [12d8:0x400e] and [12d8:0x400f] 5570 + * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 5571 + * 5589 5572 * These devices advertise PME# support in all power states but don't 5590 5573 * reliably assert it. 5574 + * 5575 + * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 5576 + * says "The MSI Function is not implemented on this device" in chapters 5577 + * 7.3.27, 7.3.29-7.3.31. 5591 5578 */ 5592 - static void pci_fixup_no_pme(struct pci_dev *dev) 5579 + static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 5593 5580 { 5581 + #ifdef CONFIG_PCI_MSI 5582 + pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 5583 + dev->no_msi = 1; 5584 + #endif 5594 5585 pci_info(dev, "PME# is unreliable, disabling it\n"); 5595 5586 dev->pme_support = 0; 5596 5587 } 5597 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_pme); 5598 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_pme); 5588 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 5589 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 5599 5590 5600 5591 static void apex_pci_fixup_class(struct pci_dev *pdev) 5601 5592 {

+6 -5

drivers/pci/slot.c

··· 272 272 goto err; 273 273 } 274 274 275 + INIT_LIST_HEAD(&slot->list); 276 + list_add(&slot->list, &parent->slots); 277 + 275 278 err = kobject_init_and_add(&slot->kobj, &pci_slot_ktype, NULL, 276 279 "%s", slot_name); 277 280 if (err) { 278 281 kobject_put(&slot->kobj); 279 282 goto err; 280 283 } 281 - 282 - INIT_LIST_HEAD(&slot->list); 283 - list_add(&slot->list, &parent->slots); 284 284 285 285 down_read(&pci_bus_sem); 286 286 list_for_each_entry(dev, &parent->devices, bus_list) ··· 323 323 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 324 324 #include <linux/pci_hotplug.h> 325 325 /** 326 - * pci_hp_create_link - create symbolic link to the hotplug driver module. 326 + * pci_hp_create_module_link - create symbolic link to hotplug driver module 327 327 * @pci_slot: struct pci_slot 328 328 * 329 329 * Helper function for pci_hotplug_core.c to create symbolic link to ··· 349 349 EXPORT_SYMBOL_GPL(pci_hp_create_module_link); 350 350 351 351 /** 352 - * pci_hp_remove_link - remove symbolic link to the hotplug driver module. 352 + * pci_hp_remove_module_link - remove symbolic link to the hotplug driver 353 + * module. 353 354 * @pci_slot: struct pci_slot 354 355 * 355 356 * Helper function for pci_hotplug_core.c to remove symbolic link to

+27

include/linux/pci-ecam.h

··· 10 10 #include <linux/platform_device.h> 11 11 12 12 /* 13 + * Memory address shift values for the byte-level address that 14 + * can be used when accessing the PCI Express Configuration Space. 15 + */ 16 + 17 + /* 18 + * Enhanced Configuration Access Mechanism (ECAM) 19 + * 20 + * See PCI Express Base Specification, Revision 5.0, Version 1.0, 21 + * Section 7.2.2, Table 7-1, p. 677. 22 + */ 23 + #define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */ 24 + #define PCIE_ECAM_DEVFN_SHIFT 12 /* Device and Function number */ 25 + 26 + #define PCIE_ECAM_BUS_MASK 0xff 27 + #define PCIE_ECAM_DEVFN_MASK 0xff 28 + #define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */ 29 + 30 + #define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT) 31 + #define PCIE_ECAM_DEVFN(x) (((x) & PCIE_ECAM_DEVFN_MASK) << PCIE_ECAM_DEVFN_SHIFT) 32 + #define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK) 33 + 34 + #define PCIE_ECAM_OFFSET(bus, devfn, where) \ 35 + (PCIE_ECAM_BUS(bus) | \ 36 + PCIE_ECAM_DEVFN(devfn) | \ 37 + PCIE_ECAM_REG(where)) 38 + 39 + /* 13 40 * struct to hold pci ops and bus shift of the config window 14 41 * for a PCI controller. 15 42 */

+16 -11

include/linux/pci.h

··· 281 281 PCIE_SPEED_8_0GT = 0x16, 282 282 PCIE_SPEED_16_0GT = 0x17, 283 283 PCIE_SPEED_32_0GT = 0x18, 284 + PCIE_SPEED_64_0GT = 0x19, 284 285 PCI_SPEED_UNKNOWN = 0xff, 285 286 }; 286 287 ··· 305 304 struct pci_vpd; 306 305 struct pci_sriov; 307 306 struct pci_p2pdma; 307 + struct rcec_ea; 308 308 309 309 /* The pci_dev structure describes PCI devices */ 310 310 struct pci_dev { ··· 328 326 #ifdef CONFIG_PCIEAER 329 327 u16 aer_cap; /* AER capability offset */ 330 328 struct aer_stats *aer_stats; /* AER stats for this device */ 329 + #endif 330 + #ifdef CONFIG_PCIEPORTBUS 331 + struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 332 + struct pci_dev *rcec; /* Associated RCEC device */ 331 333 #endif 332 334 u8 pcie_cap; /* PCIe capability offset */ 333 335 u8 msi_cap; /* MSI capability offset */ ··· 386 380 struct pcie_link_state *link_state; /* ASPM link state */ 387 381 unsigned int ltr_path:1; /* Latency Tolerance Reporting 388 382 supported from root to here */ 389 - int l1ss; /* L1SS Capability pointer */ 383 + u16 l1ss; /* L1SS Capability pointer */ 390 384 #endif 391 385 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 392 386 ··· 1069 1063 1070 1064 /* Generic PCI functions exported to card drivers */ 1071 1065 1072 - int pci_find_capability(struct pci_dev *dev, int cap); 1073 - int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1074 - int pci_find_ext_capability(struct pci_dev *dev, int cap); 1075 - int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 1076 - int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1077 - int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 1066 + u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1067 + u8 pci_find_capability(struct pci_dev *dev, int cap); 1068 + u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1069 + u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1070 + u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1071 + u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1072 + u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1078 1073 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1079 1074 1080 1075 u64 pci_get_dsn(struct pci_dev *dev); ··· 1197 1190 1198 1191 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1199 1192 int pci_set_cacheline_size(struct pci_dev *dev); 1200 - #define HAVE_PCI_SET_MWI 1201 1193 int __must_check pci_set_mwi(struct pci_dev *dev); 1202 1194 int __must_check pcim_set_mwi(struct pci_dev *dev); 1203 1195 int pci_try_set_mwi(struct pci_dev *dev); ··· 1277 1271 void pci_d3cold_enable(struct pci_dev *dev); 1278 1272 void pci_d3cold_disable(struct pci_dev *dev); 1279 1273 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1280 - void pci_wakeup_bus(struct pci_bus *bus); 1274 + void pci_resume_bus(struct pci_bus *bus); 1281 1275 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1282 1276 1283 1277 /* For use by arch with custom probe code */ ··· 1285 1279 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1286 1280 1287 1281 /* Functions for PCI Hotplug drivers to use */ 1288 - int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1289 1282 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1290 1283 unsigned int pci_rescan_bus(struct pci_bus *bus); 1291 1284 void pci_lock_rescan_remove(void); ··· 1724 1719 static inline int pci_register_driver(struct pci_driver *drv) 1725 1720 { return 0; } 1726 1721 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1727 - static inline int pci_find_capability(struct pci_dev *dev, int cap) 1722 + static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1728 1723 { return 0; } 1729 1724 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1730 1725 int cap)

+1

include/linux/pci_ids.h

··· 81 81 #define PCI_CLASS_SYSTEM_RTC 0x0803 82 82 #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 83 83 #define PCI_CLASS_SYSTEM_SDHCI 0x0805 84 + #define PCI_CLASS_SYSTEM_RCEC 0x0807 84 85 #define PCI_CLASS_SYSTEM_OTHER 0x0880 85 86 86 87 #define PCI_BASE_CLASS_INPUT 0x09

+11

include/uapi/linux/pci_regs.h

··· 531 531 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ 532 532 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ 533 533 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ 534 + #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */ 534 535 #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ 535 536 #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ 536 537 #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ ··· 563 562 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 564 563 #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ 565 564 #define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ 565 + #define PCI_EXP_LNKSTA_CLS_64_0GB 0x0006 /* Current Link Speed 64.0GT/s */ 566 566 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 567 567 #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ 568 568 #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ ··· 672 670 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ 673 671 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ 674 672 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ 673 + #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */ 675 674 #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ 676 675 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 677 676 #define PCI_EXP_LNKCTL2_TLS 0x000f ··· 681 678 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 682 679 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 683 680 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 681 + #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 684 682 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 685 683 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 686 684 #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ ··· 835 831 #define PCI_PWR_CAP 12 /* Capability */ 836 832 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 837 833 #define PCI_EXT_CAP_PWR_SIZEOF 16 834 + 835 + /* Root Complex Event Collector Endpoint Association */ 836 + #define PCI_RCEC_RCIEP_BITMAP 4 /* Associated Bitmap for RCiEPs */ 837 + #define PCI_RCEC_BUSN 8 /* RCEC Associated Bus Numbers */ 838 + #define PCI_RCEC_BUSN_REG_VER 0x02 /* Least version with BUSN present */ 839 + #define PCI_RCEC_BUSN_NEXT(x) (((x) >> 8) & 0xff) 840 + #define PCI_RCEC_BUSN_LAST(x) (((x) >> 16) & 0xff) 838 841 839 842 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ 840 843 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */

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