Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2018-06-29' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Nothing too major this round:
- small set of mali-dp fixes
- single meson fix
- a bunch of amdgpu fixes (one makes non-4k page sizes not be a bad
experience)"
* tag 'drm-fixes-2018-06-29' of git://anongit.freedesktop.org/drm/drm:
drm/amd/display: release spinlock before committing updates to stream
drm/amdgpu:Support new VCN FW version naming convention
drm/amdgpu: fix UBSAN: Undefined behaviour for amdgpu_fence.c
drm/meson: Fix an un-handled error path in 'meson_drv_bind_master()'
drm/amdgpu: GPU vs CPU page size fixes in amdgpu_vm_bo_split_mapping
drm/amdgpu: Count disabled CRTCs in commit tail earlier
drm/mali-dp: Rectify the width and height passed to rotmem_required()
drm/arm/malidp: Preserve LAYER_FORMAT contents when setting format
drm: mali-dp: Enable Global SE interrupts mask for DP500
drm/arm/malidp: Ensure that the crtcs are shutdown before removing any encoder/connector
+59
-27
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
···
376
376
struct amdgpu_device *adev = ring->adev;
377
377
uint64_t index;
378
378
379
-
if (ring != &adev->uvd.inst[ring->me].ring) {
379
+
if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
380
380
ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
381
381
ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
382
382
} else {
+27
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+27
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
···
52
52
unsigned long bo_size;
53
53
const char *fw_name;
54
54
const struct common_firmware_header *hdr;
55
-
unsigned version_major, version_minor, family_id;
55
+
unsigned char fw_check;
56
56
int r;
57
57
58
58
INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
···
83
83
84
84
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
85
85
adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
86
-
family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
87
-
version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
88
-
version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
89
-
DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
90
-
version_major, version_minor, family_id);
91
86
87
+
/* Bit 20-23, it is encode major and non-zero for new naming convention.
88
+
* This field is part of version minor and DRM_DISABLED_FLAG in old naming
89
+
* convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
90
+
* is zero in old naming convention, this field is always zero so far.
91
+
* These four bits are used to tell which naming convention is present.
92
+
*/
93
+
fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
94
+
if (fw_check) {
95
+
unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
96
+
97
+
fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
98
+
enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
99
+
enc_major = fw_check;
100
+
dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
101
+
vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
102
+
DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
103
+
enc_major, enc_minor, dec_ver, vep, fw_rev);
104
+
} else {
105
+
unsigned int version_major, version_minor, family_id;
106
+
107
+
family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
108
+
version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
109
+
version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
110
+
DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
111
+
version_major, version_minor, family_id);
112
+
}
92
113
93
114
bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
94
115
+ AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
+5
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+5
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
1463
1463
uint64_t count;
1464
1464
1465
1465
max_entries = min(max_entries, 16ull * 1024ull);
1466
-
for (count = 1; count < max_entries; ++count) {
1466
+
for (count = 1;
1467
+
count < max_entries / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1468
+
++count) {
1467
1469
uint64_t idx = pfn + count;
1468
1470
1469
1471
if (pages_addr[idx] !=
···
1478
1476
dma_addr = pages_addr;
1479
1477
} else {
1480
1478
addr = pages_addr[pfn];
1481
-
max_entries = count;
1479
+
max_entries = count * (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1482
1480
}
1483
1481
1484
1482
} else if (flags & AMDGPU_PTE_VALID) {
···
1493
1491
if (r)
1494
1492
return r;
1495
1493
1496
-
pfn += last - start + 1;
1494
+
pfn += (last - start + 1) / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1497
1495
if (nodes && nodes->size == pfn) {
1498
1496
pfn = 0;
1499
1497
++nodes;
+8
-8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+8
-8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
3928
3928
if (acrtc->base.state->event)
3929
3929
prepare_flip_isr(acrtc);
3930
3930
3931
+
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3932
+
3931
3933
surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
3932
3934
surface_updates->flip_addr = &addr;
3933
-
3934
3935
3935
3936
dc_commit_updates_for_stream(adev->dm.dc,
3936
3937
surface_updates,
···
3945
3944
__func__,
3946
3945
addr.address.grph.addr.high_part,
3947
3946
addr.address.grph.addr.low_part);
3948
-
3949
-
3950
-
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3951
3947
}
3952
3948
3953
3949
/*
···
4204
4206
struct drm_connector *connector;
4205
4207
struct drm_connector_state *old_con_state, *new_con_state;
4206
4208
struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4209
+
int crtc_disable_count = 0;
4207
4210
4208
4211
drm_atomic_helper_update_legacy_modeset_state(dev, state);
4209
4212
···
4409
4410
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4410
4411
bool modeset_needed;
4411
4412
4413
+
if (old_crtc_state->active && !new_crtc_state->active)
4414
+
crtc_disable_count++;
4415
+
4412
4416
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4413
4417
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4414
4418
modeset_needed = modeset_required(
···
4465
4463
* so we can put the GPU into runtime suspend if we're not driving any
4466
4464
* displays anymore
4467
4465
*/
4466
+
for (i = 0; i < crtc_disable_count; i++)
4467
+
pm_runtime_put_autosuspend(dev->dev);
4468
4468
pm_runtime_mark_last_busy(dev->dev);
4469
-
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4470
-
if (old_crtc_state->active && !new_crtc_state->active)
4471
-
pm_runtime_put_autosuspend(dev->dev);
4472
-
}
4473
4469
}
4474
4470
4475
4471
+2
-1
drivers/gpu/drm/arm/malidp_drv.c
+2
-1
drivers/gpu/drm/arm/malidp_drv.c
···
278
278
279
279
static void malidp_fini(struct drm_device *drm)
280
280
{
281
-
drm_atomic_helper_shutdown(drm);
282
281
drm_mode_config_cleanup(drm);
283
282
}
284
283
···
645
646
malidp_de_irq_fini(drm);
646
647
drm->irq_enabled = false;
647
648
irq_init_fail:
649
+
drm_atomic_helper_shutdown(drm);
648
650
component_unbind_all(dev, drm);
649
651
bind_fail:
650
652
of_node_put(malidp->crtc.port);
···
681
681
malidp_se_irq_fini(drm);
682
682
malidp_de_irq_fini(drm);
683
683
drm->irq_enabled = false;
684
+
drm_atomic_helper_shutdown(drm);
684
685
component_unbind_all(dev, drm);
685
686
of_node_put(malidp->crtc.port);
686
687
malidp->crtc.port = NULL;
+2
-1
drivers/gpu/drm/arm/malidp_hw.c
+2
-1
drivers/gpu/drm/arm/malidp_hw.c
+6
-3
drivers/gpu/drm/arm/malidp_planes.c
+6
-3
drivers/gpu/drm/arm/malidp_planes.c
···
23
23
24
24
/* Layer specific register offsets */
25
25
#define MALIDP_LAYER_FORMAT 0x000
26
+
#define LAYER_FORMAT_MASK 0x3f
26
27
#define MALIDP_LAYER_CONTROL 0x004
27
28
#define LAYER_ENABLE (1 << 0)
28
29
#define LAYER_FLOWCFG_MASK 7
···
236
235
if (state->rotation & MALIDP_ROTATED_MASK) {
237
236
int val;
238
237
239
-
val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_h,
240
-
state->crtc_w,
238
+
val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w,
239
+
state->crtc_h,
241
240
fb->format->format);
242
241
if (val < 0)
243
242
return val;
···
338
337
dest_w = plane->state->crtc_w;
339
338
dest_h = plane->state->crtc_h;
340
339
341
-
malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
340
+
val = malidp_hw_read(mp->hwdev, mp->layer->base);
341
+
val = (val & ~LAYER_FORMAT_MASK) | ms->format;
342
+
malidp_hw_write(mp->hwdev, val, mp->layer->base);
342
343
343
344
for (i = 0; i < ms->n_planes; i++) {
344
345
/* calculate the offset for the layer's plane registers */
+8
-4
drivers/gpu/drm/meson/meson_drv.c
+8
-4
drivers/gpu/drm/meson/meson_drv.c
···
197
197
priv->io_base = regs;
198
198
199
199
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
200
-
if (!res)
201
-
return -EINVAL;
200
+
if (!res) {
201
+
ret = -EINVAL;
202
+
goto free_drm;
203
+
}
202
204
/* Simply ioremap since it may be a shared register zone */
203
205
regs = devm_ioremap(dev, res->start, resource_size(res));
204
206
if (!regs) {
···
217
215
}
218
216
219
217
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmc");
220
-
if (!res)
221
-
return -EINVAL;
218
+
if (!res) {
219
+
ret = -EINVAL;
220
+
goto free_drm;
221
+
}
222
222
/* Simply ioremap since it may be a shared register zone */
223
223
regs = devm_ioremap(dev, res->start, resource_size(res));
224
224
if (!regs) {