Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'staging-3.7-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging driver fixes from Greg Kroah-Hartman:
"Here are some staging driver fixes for your 3.7-rc tree.
Nothing major here, a number of iio driver fixups that were causing
problems, some comedi driver bugfixes, and a bunch of tidspbridge
warning squashing and other regressions fixed from the 3.6 release.
All have been in the linux-next releases for a bit.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>"
* tag 'staging-3.7-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (32 commits)
staging: tidspbridge: delete unused mmu functions
staging: tidspbridge: ioremap physical address of the stack segment in shm
staging: tidspbridge: ioremap dsp sync addr
staging: tidspbridge: change type to __iomem for per and core addresses
staging: tidspbridge: drop const from custom mmu implementation
staging: tidspbridge: request the right irq for mmu
staging: ipack: add missing include (implicit declaration of function 'kfree')
staging: ramster: depends on NET
staging: omapdrm: fix allocation size for page addresses array
staging: zram: Fix handling of incompressible pages
Staging: android: binder: Allow using highmem for binder buffers
Staging: android: binder: Fix memory leak on thread/process exit
staging: comedi: ni_labpc: fix possible NULL deref during detach
staging: comedi: das08: fix possible NULL deref during detach
staging: comedi: amplc_pc263: fix possible NULL deref during detach
staging: comedi: amplc_pc236: fix possible NULL deref during detach
staging: comedi: amplc_pc236: fix invalid register access during detach
staging: comedi: amplc_dio200: fix possible NULL deref during detach
staging: comedi: 8255_pci: fix possible NULL deref during detach
staging: comedi: ni_daq_700: fix dio subdevice regression
...
+287
-243
-1
drivers/iio/Kconfig
-1
drivers/iio/Kconfig
-1
drivers/iio/Makefile
-1
drivers/iio/Makefile
+28
-2
drivers/staging/android/binder.c
+28
-2
drivers/staging/android/binder.c
···
567
567
page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE];
568
568
569
569
BUG_ON(*page);
570
-
*page = alloc_page(GFP_KERNEL | __GFP_ZERO);
570
+
*page = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO);
571
571
if (*page == NULL) {
572
572
pr_err("binder: %d: binder_alloc_buf failed "
573
573
"for page at %p\n", proc->pid, page_addr);
···
2419
2419
struct binder_transaction *t;
2420
2420
2421
2421
t = container_of(w, struct binder_transaction, work);
2422
-
if (t->buffer->target_node && !(t->flags & TF_ONE_WAY))
2422
+
if (t->buffer->target_node &&
2423
+
!(t->flags & TF_ONE_WAY)) {
2423
2424
binder_send_failed_reply(t, BR_DEAD_REPLY);
2425
+
} else {
2426
+
binder_debug(BINDER_DEBUG_DEAD_TRANSACTION,
2427
+
"binder: undelivered transaction %d\n",
2428
+
t->debug_id);
2429
+
t->buffer->transaction = NULL;
2430
+
kfree(t);
2431
+
binder_stats_deleted(BINDER_STAT_TRANSACTION);
2432
+
}
2424
2433
} break;
2425
2434
case BINDER_WORK_TRANSACTION_COMPLETE: {
2435
+
binder_debug(BINDER_DEBUG_DEAD_TRANSACTION,
2436
+
"binder: undelivered TRANSACTION_COMPLETE\n");
2426
2437
kfree(w);
2427
2438
binder_stats_deleted(BINDER_STAT_TRANSACTION_COMPLETE);
2428
2439
} break;
2440
+
case BINDER_WORK_DEAD_BINDER_AND_CLEAR:
2441
+
case BINDER_WORK_CLEAR_DEATH_NOTIFICATION: {
2442
+
struct binder_ref_death *death;
2443
+
2444
+
death = container_of(w, struct binder_ref_death, work);
2445
+
binder_debug(BINDER_DEBUG_DEAD_TRANSACTION,
2446
+
"binder: undelivered death notification, %p\n",
2447
+
death->cookie);
2448
+
kfree(death);
2449
+
binder_stats_deleted(BINDER_STAT_DEATH);
2450
+
} break;
2429
2451
default:
2452
+
pr_err("binder: unexpected work type, %d, not freed\n",
2453
+
w->type);
2430
2454
break;
2431
2455
}
2432
2456
}
···
2923
2899
nodes++;
2924
2900
rb_erase(&node->rb_node, &proc->nodes);
2925
2901
list_del_init(&node->work.entry);
2902
+
binder_release_work(&node->async_todo);
2926
2903
if (hlist_empty(&node->refs)) {
2927
2904
kfree(node);
2928
2905
binder_stats_deleted(BINDER_STAT_NODE);
···
2962
2937
binder_delete_ref(ref);
2963
2938
}
2964
2939
binder_release_work(&proc->todo);
2940
+
binder_release_work(&proc->delivered_death);
2965
2941
buffers = 0;
2966
2942
2967
2943
while ((n = rb_first(&proc->allocated_buffers))) {
+2
drivers/staging/comedi/drivers/8255_pci.c
+2
drivers/staging/comedi/drivers/8255_pci.c
+2
drivers/staging/comedi/drivers/amplc_dio200.c
+2
drivers/staging/comedi/drivers/amplc_dio200.c
+3
-2
drivers/staging/comedi/drivers/amplc_pc236.c
+3
-2
drivers/staging/comedi/drivers/amplc_pc236.c
···
573
573
static void pc236_detach(struct comedi_device *dev)
574
574
{
575
575
const struct pc236_board *thisboard = comedi_board(dev);
576
-
struct pc236_private *devpriv = dev->private;
577
576
578
-
if (devpriv)
577
+
if (!thisboard)
578
+
return;
579
+
if (dev->iobase)
579
580
pc236_intr_disable(dev);
580
581
if (dev->irq)
581
582
free_irq(dev->irq, dev);
+2
drivers/staging/comedi/drivers/amplc_pc263.c
+2
drivers/staging/comedi/drivers/amplc_pc263.c
+2
drivers/staging/comedi/drivers/das08.c
+2
drivers/staging/comedi/drivers/das08.c
+1
-1
drivers/staging/comedi/drivers/ni_daq_700.c
+1
-1
drivers/staging/comedi/drivers/ni_daq_700.c
+2
drivers/staging/comedi/drivers/ni_labpc.c
+2
drivers/staging/comedi/drivers/ni_labpc.c
+13
-11
drivers/staging/iio/accel/adis16201_core.c
+13
-11
drivers/staging/iio/accel/adis16201_core.c
···
310
310
case IIO_CHAN_INFO_SCALE:
311
311
switch (chan->type) {
312
312
case IIO_VOLTAGE:
313
-
*val = 0;
314
-
if (chan->channel == 0)
315
-
*val2 = 1220;
316
-
else
317
-
*val2 = 610;
313
+
if (chan->channel == 0) {
314
+
*val = 1;
315
+
*val2 = 220000; /* 1.22 mV */
316
+
} else {
317
+
*val = 0;
318
+
*val2 = 610000; /* 0.610 mV */
319
+
}
318
320
return IIO_VAL_INT_PLUS_MICRO;
319
321
case IIO_TEMP:
320
-
*val = 0;
321
-
*val2 = -470000;
322
+
*val = -470; /* 0.47 C */
323
+
*val2 = 0;
322
324
return IIO_VAL_INT_PLUS_MICRO;
323
325
case IIO_ACCEL:
324
326
*val = 0;
325
-
*val2 = 462500;
326
-
return IIO_VAL_INT_PLUS_MICRO;
327
+
*val2 = IIO_G_TO_M_S_2(462400); /* 0.4624 mg */
328
+
return IIO_VAL_INT_PLUS_NANO;
327
329
case IIO_INCLI:
328
330
*val = 0;
329
-
*val2 = 100000;
331
+
*val2 = 100000; /* 0.1 degree */
330
332
return IIO_VAL_INT_PLUS_MICRO;
331
333
default:
332
334
return -EINVAL;
333
335
}
334
336
break;
335
337
case IIO_CHAN_INFO_OFFSET:
336
-
*val = 25;
338
+
*val = 25000 / -470 - 1278; /* 25 C = 1278 */
337
339
return IIO_VAL_INT;
338
340
case IIO_CHAN_INFO_CALIBBIAS:
339
341
switch (chan->type) {
+11
-9
drivers/staging/iio/accel/adis16203_core.c
+11
-9
drivers/staging/iio/accel/adis16203_core.c
···
316
316
case IIO_CHAN_INFO_SCALE:
317
317
switch (chan->type) {
318
318
case IIO_VOLTAGE:
319
-
*val = 0;
320
-
if (chan->channel == 0)
321
-
*val2 = 1220;
322
-
else
323
-
*val2 = 610;
319
+
if (chan->channel == 0) {
320
+
*val = 1;
321
+
*val2 = 220000; /* 1.22 mV */
322
+
} else {
323
+
*val = 0;
324
+
*val2 = 610000; /* 0.61 mV */
325
+
}
324
326
return IIO_VAL_INT_PLUS_MICRO;
325
327
case IIO_TEMP:
326
-
*val = 0;
327
-
*val2 = -470000;
328
+
*val = -470; /* -0.47 C */
329
+
*val2 = 0;
328
330
return IIO_VAL_INT_PLUS_MICRO;
329
331
case IIO_INCLI:
330
332
*val = 0;
331
-
*val2 = 25000;
333
+
*val2 = 25000; /* 0.025 degree */
332
334
return IIO_VAL_INT_PLUS_MICRO;
333
335
default:
334
336
return -EINVAL;
335
337
}
336
338
case IIO_CHAN_INFO_OFFSET:
337
-
*val = 25;
339
+
*val = 25000 / -470 - 1278; /* 25 C = 1278 */
338
340
return IIO_VAL_INT;
339
341
case IIO_CHAN_INFO_CALIBBIAS:
340
342
bits = 14;
+12
-10
drivers/staging/iio/accel/adis16204_core.c
+12
-10
drivers/staging/iio/accel/adis16204_core.c
···
317
317
case IIO_CHAN_INFO_SCALE:
318
318
switch (chan->type) {
319
319
case IIO_VOLTAGE:
320
-
*val = 0;
321
-
if (chan->channel == 0)
322
-
*val2 = 1220;
323
-
else
324
-
*val2 = 610;
320
+
if (chan->channel == 0) {
321
+
*val = 1;
322
+
*val2 = 220000; /* 1.22 mV */
323
+
} else {
324
+
*val = 0;
325
+
*val2 = 610000; /* 0.61 mV */
326
+
}
325
327
return IIO_VAL_INT_PLUS_MICRO;
326
328
case IIO_TEMP:
327
-
*val = 0;
328
-
*val2 = -470000;
329
+
*val = -470; /* 0.47 C */
330
+
*val2 = 0;
329
331
return IIO_VAL_INT_PLUS_MICRO;
330
332
case IIO_ACCEL:
331
333
*val = 0;
332
334
switch (chan->channel2) {
333
335
case IIO_MOD_X:
334
336
case IIO_MOD_ROOT_SUM_SQUARED_X_Y:
335
-
*val2 = 17125;
337
+
*val2 = IIO_G_TO_M_S_2(17125); /* 17.125 mg */
336
338
break;
337
339
case IIO_MOD_Y:
338
340
case IIO_MOD_Z:
339
-
*val2 = 8407;
341
+
*val2 = IIO_G_TO_M_S_2(8407); /* 8.407 mg */
340
342
break;
341
343
}
342
344
return IIO_VAL_INT_PLUS_MICRO;
···
347
345
}
348
346
break;
349
347
case IIO_CHAN_INFO_OFFSET:
350
-
*val = 25;
348
+
*val = 25000 / -470 - 1278; /* 25 C = 1278 */
351
349
return IIO_VAL_INT;
352
350
case IIO_CHAN_INFO_CALIBBIAS:
353
351
case IIO_CHAN_INFO_PEAK:
+10
-8
drivers/staging/iio/accel/adis16209_core.c
+10
-8
drivers/staging/iio/accel/adis16209_core.c
···
343
343
case IIO_VOLTAGE:
344
344
*val = 0;
345
345
if (chan->channel == 0)
346
-
*val2 = 305180;
346
+
*val2 = 305180; /* 0.30518 mV */
347
347
else
348
-
*val2 = 610500;
348
+
*val2 = 610500; /* 0.6105 mV */
349
349
return IIO_VAL_INT_PLUS_MICRO;
350
350
case IIO_TEMP:
351
-
*val = 0;
352
-
*val2 = -470000;
351
+
*val = -470; /* -0.47 C */
352
+
*val2 = 0;
353
353
return IIO_VAL_INT_PLUS_MICRO;
354
354
case IIO_ACCEL:
355
355
*val = 0;
356
-
*val2 = 2394;
357
-
return IIO_VAL_INT_PLUS_MICRO;
356
+
*val2 = IIO_G_TO_M_S_2(244140); /* 0.244140 mg */
357
+
return IIO_VAL_INT_PLUS_NANO;
358
358
case IIO_INCLI:
359
+
case IIO_ROT:
359
360
*val = 0;
360
-
*val2 = 436;
361
+
*val2 = 25000; /* 0.025 degree */
361
362
return IIO_VAL_INT_PLUS_MICRO;
362
363
default:
363
364
return -EINVAL;
364
365
}
365
366
break;
366
367
case IIO_CHAN_INFO_OFFSET:
367
-
*val = 25;
368
+
*val = 25000 / -470 - 0x4FE; /* 25 C = 0x4FE */
368
369
return IIO_VAL_INT;
369
370
case IIO_CHAN_INFO_CALIBBIAS:
370
371
switch (chan->type) {
···
492
491
.modified = 1,
493
492
.channel2 = IIO_MOD_X,
494
493
.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT,
494
+
IIO_CHAN_INFO_SCALE_SHARED_BIT,
495
495
.address = rot,
496
496
.scan_index = ADIS16209_SCAN_ROT,
497
497
.scan_type = {
+11
-8
drivers/staging/iio/accel/adis16220_core.c
+11
-8
drivers/staging/iio/accel/adis16220_core.c
···
486
486
break;
487
487
case IIO_CHAN_INFO_OFFSET:
488
488
if (chan->type == IIO_TEMP) {
489
-
*val = 25;
489
+
*val = 25000 / -470 - 1278; /* 25 C = 1278 */
490
490
return IIO_VAL_INT;
491
491
}
492
492
addrind = 1;
···
495
495
addrind = 2;
496
496
break;
497
497
case IIO_CHAN_INFO_SCALE:
498
-
*val = 0;
499
498
switch (chan->type) {
500
499
case IIO_TEMP:
501
-
*val2 = -470000;
500
+
*val = -470; /* -0.47 C */
501
+
*val2 = 0;
502
502
return IIO_VAL_INT_PLUS_MICRO;
503
503
case IIO_ACCEL:
504
-
*val2 = 1887042;
504
+
*val2 = IIO_G_TO_M_S_2(19073); /* 19.073 g */
505
505
return IIO_VAL_INT_PLUS_MICRO;
506
506
case IIO_VOLTAGE:
507
-
if (chan->channel == 0)
508
-
*val2 = 0012221;
509
-
else /* Should really be dependent on VDD */
510
-
*val2 = 305;
507
+
if (chan->channel == 0) {
508
+
*val = 1;
509
+
*val2 = 220700; /* 1.2207 mV */
510
+
} else {
511
+
/* Should really be dependent on VDD */
512
+
*val2 = 305180; /* 305.18 uV */
513
+
}
511
514
return IIO_VAL_INT_PLUS_MICRO;
512
515
default:
513
516
return -EINVAL;
+12
-11
drivers/staging/iio/accel/adis16240_core.c
+12
-11
drivers/staging/iio/accel/adis16240_core.c
···
373
373
case IIO_CHAN_INFO_SCALE:
374
374
switch (chan->type) {
375
375
case IIO_VOLTAGE:
376
-
*val = 0;
377
-
if (chan->channel == 0)
378
-
*val2 = 4880;
379
-
else
376
+
if (chan->channel == 0) {
377
+
*val = 4;
378
+
*val2 = 880000; /* 4.88 mV */
379
+
return IIO_VAL_INT_PLUS_MICRO;
380
+
} else {
380
381
return -EINVAL;
381
-
return IIO_VAL_INT_PLUS_MICRO;
382
+
}
382
383
case IIO_TEMP:
383
-
*val = 0;
384
-
*val2 = 244000;
384
+
*val = 244; /* 0.244 C */
385
+
*val2 = 0;
385
386
return IIO_VAL_INT_PLUS_MICRO;
386
387
case IIO_ACCEL:
387
388
*val = 0;
388
-
*val2 = 504062;
389
+
*val2 = IIO_G_TO_M_S_2(51400); /* 51.4 mg */
389
390
return IIO_VAL_INT_PLUS_MICRO;
390
391
default:
391
392
return -EINVAL;
392
393
}
393
394
break;
394
395
case IIO_CHAN_INFO_PEAK_SCALE:
395
-
*val = 6;
396
-
*val2 = 629295;
396
+
*val = 0;
397
+
*val2 = IIO_G_TO_M_S_2(51400); /* 51.4 mg */
397
398
return IIO_VAL_INT_PLUS_MICRO;
398
399
case IIO_CHAN_INFO_OFFSET:
399
-
*val = 25;
400
+
*val = 25000 / 244 - 0x133; /* 25 C = 0x133 */
400
401
return IIO_VAL_INT;
401
402
case IIO_CHAN_INFO_CALIBBIAS:
402
403
bits = 10;
+17
-12
drivers/staging/iio/gyro/adis16260_core.c
+17
-12
drivers/staging/iio/gyro/adis16260_core.c
···
498
498
switch (chan->type) {
499
499
case IIO_ANGL_VEL:
500
500
*val = 0;
501
-
if (spi_get_device_id(st->us)->driver_data)
502
-
*val2 = 320;
503
-
else
504
-
*val2 = 1278;
501
+
if (spi_get_device_id(st->us)->driver_data) {
502
+
/* 0.01832 degree / sec */
503
+
*val2 = IIO_DEGREE_TO_RAD(18320);
504
+
} else {
505
+
/* 0.07326 degree / sec */
506
+
*val2 = IIO_DEGREE_TO_RAD(73260);
507
+
}
505
508
return IIO_VAL_INT_PLUS_MICRO;
506
509
case IIO_VOLTAGE:
507
-
*val = 0;
508
-
if (chan->channel == 0)
509
-
*val2 = 18315;
510
-
else
511
-
*val2 = 610500;
510
+
if (chan->channel == 0) {
511
+
*val = 1;
512
+
*val2 = 831500; /* 1.8315 mV */
513
+
} else {
514
+
*val = 0;
515
+
*val2 = 610500; /* 610.5 uV */
516
+
}
512
517
return IIO_VAL_INT_PLUS_MICRO;
513
518
case IIO_TEMP:
514
-
*val = 0;
515
-
*val2 = 145300;
519
+
*val = 145;
520
+
*val2 = 300000; /* 0.1453 C */
516
521
return IIO_VAL_INT_PLUS_MICRO;
517
522
default:
518
523
return -EINVAL;
519
524
}
520
525
break;
521
526
case IIO_CHAN_INFO_OFFSET:
522
-
*val = 25;
527
+
*val = 250000 / 1453; /* 25 C = 0x00 */
523
528
return IIO_VAL_INT;
524
529
case IIO_CHAN_INFO_CALIBBIAS:
525
530
switch (chan->type) {
+2
drivers/staging/iio/imu/adis16400.h
+2
drivers/staging/iio/imu/adis16400.h
+44
-26
drivers/staging/iio/imu/adis16400_core.c
+44
-26
drivers/staging/iio/imu/adis16400_core.c
···
553
553
return IIO_VAL_INT_PLUS_MICRO;
554
554
case IIO_VOLTAGE:
555
555
*val = 0;
556
-
if (chan->channel == 0)
557
-
*val2 = 2418;
558
-
else
559
-
*val2 = 806;
556
+
if (chan->channel == 0) {
557
+
*val = 2;
558
+
*val2 = 418000; /* 2.418 mV */
559
+
} else {
560
+
*val = 0;
561
+
*val2 = 805800; /* 805.8 uV */
562
+
}
560
563
return IIO_VAL_INT_PLUS_MICRO;
561
564
case IIO_ACCEL:
562
565
*val = 0;
···
567
564
return IIO_VAL_INT_PLUS_MICRO;
568
565
case IIO_MAGN:
569
566
*val = 0;
570
-
*val2 = 500;
567
+
*val2 = 500; /* 0.5 mgauss */
571
568
return IIO_VAL_INT_PLUS_MICRO;
572
569
case IIO_TEMP:
573
-
*val = 0;
574
-
*val2 = 140000;
570
+
*val = st->variant->temp_scale_nano / 1000000;
571
+
*val2 = (st->variant->temp_scale_nano % 1000000);
575
572
return IIO_VAL_INT_PLUS_MICRO;
576
573
default:
577
574
return -EINVAL;
···
589
586
return IIO_VAL_INT;
590
587
case IIO_CHAN_INFO_OFFSET:
591
588
/* currently only temperature */
592
-
*val = 198;
593
-
*val2 = 160000;
594
-
return IIO_VAL_INT_PLUS_MICRO;
589
+
*val = st->variant->temp_offset;
590
+
return IIO_VAL_INT;
595
591
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
596
592
mutex_lock(&indio_dev->mlock);
597
593
/* Need both the number of taps and the sampling frequency */
···
1037
1035
.indexed = 1,
1038
1036
.channel = 0,
1039
1037
.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
1040
-
IIO_CHAN_INFO_CALIBBIAS_SEPARATE_BIT |
1038
+
IIO_CHAN_INFO_OFFSET_SEPARATE_BIT |
1041
1039
IIO_CHAN_INFO_SCALE_SHARED_BIT,
1042
1040
.address = temp0,
1043
1041
.scan_index = ADIS16400_SCAN_TEMP,
···
1060
1058
[ADIS16300] = {
1061
1059
.channels = adis16300_channels,
1062
1060
.num_channels = ARRAY_SIZE(adis16300_channels),
1063
-
.gyro_scale_micro = 873,
1061
+
.gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1064
1062
.accel_scale_micro = 5884,
1063
+
.temp_scale_nano = 140000000, /* 0.14 C */
1064
+
.temp_offset = 25000000 / 140000, /* 25 C = 0x00 */
1065
1065
.default_scan_mask = (1 << ADIS16400_SCAN_SUPPLY) |
1066
1066
(1 << ADIS16400_SCAN_GYRO_X) | (1 << ADIS16400_SCAN_ACC_X) |
1067
1067
(1 << ADIS16400_SCAN_ACC_Y) | (1 << ADIS16400_SCAN_ACC_Z) |
···
1074
1070
[ADIS16334] = {
1075
1071
.channels = adis16334_channels,
1076
1072
.num_channels = ARRAY_SIZE(adis16334_channels),
1077
-
.gyro_scale_micro = 873,
1078
-
.accel_scale_micro = 981,
1073
+
.gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1074
+
.accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */
1075
+
.temp_scale_nano = 67850000, /* 0.06785 C */
1076
+
.temp_offset = 25000000 / 67850, /* 25 C = 0x00 */
1079
1077
.default_scan_mask = (1 << ADIS16400_SCAN_GYRO_X) |
1080
1078
(1 << ADIS16400_SCAN_GYRO_Y) | (1 << ADIS16400_SCAN_GYRO_Z) |
1081
1079
(1 << ADIS16400_SCAN_ACC_X) | (1 << ADIS16400_SCAN_ACC_Y) |
···
1086
1080
[ADIS16350] = {
1087
1081
.channels = adis16350_channels,
1088
1082
.num_channels = ARRAY_SIZE(adis16350_channels),
1089
-
.gyro_scale_micro = 872664,
1090
-
.accel_scale_micro = 24732,
1083
+
.gyro_scale_micro = IIO_DEGREE_TO_RAD(73260), /* 0.07326 deg/s */
1084
+
.accel_scale_micro = IIO_G_TO_M_S_2(2522), /* 0.002522 g */
1085
+
.temp_scale_nano = 145300000, /* 0.1453 C */
1086
+
.temp_offset = 25000000 / 145300, /* 25 C = 0x00 */
1091
1087
.default_scan_mask = 0x7FF,
1092
1088
.flags = ADIS16400_NO_BURST,
1093
1089
},
···
1098
1090
.num_channels = ARRAY_SIZE(adis16350_channels),
1099
1091
.flags = ADIS16400_HAS_PROD_ID,
1100
1092
.product_id = 0x3FE8,
1101
-
.gyro_scale_micro = 1279,
1102
-
.accel_scale_micro = 24732,
1093
+
.gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1094
+
.accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */
1095
+
.temp_scale_nano = 136000000, /* 0.136 C */
1096
+
.temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1103
1097
.default_scan_mask = 0x7FF,
1104
1098
},
1105
1099
[ADIS16362] = {
···
1109
1099
.num_channels = ARRAY_SIZE(adis16350_channels),
1110
1100
.flags = ADIS16400_HAS_PROD_ID,
1111
1101
.product_id = 0x3FEA,
1112
-
.gyro_scale_micro = 1279,
1113
-
.accel_scale_micro = 24732,
1102
+
.gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1103
+
.accel_scale_micro = IIO_G_TO_M_S_2(333), /* 0.333 mg */
1104
+
.temp_scale_nano = 136000000, /* 0.136 C */
1105
+
.temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1114
1106
.default_scan_mask = 0x7FF,
1115
1107
},
1116
1108
[ADIS16364] = {
···
1120
1108
.num_channels = ARRAY_SIZE(adis16350_channels),
1121
1109
.flags = ADIS16400_HAS_PROD_ID,
1122
1110
.product_id = 0x3FEC,
1123
-
.gyro_scale_micro = 1279,
1124
-
.accel_scale_micro = 24732,
1111
+
.gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1112
+
.accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */
1113
+
.temp_scale_nano = 136000000, /* 0.136 C */
1114
+
.temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1125
1115
.default_scan_mask = 0x7FF,
1126
1116
},
1127
1117
[ADIS16365] = {
···
1131
1117
.num_channels = ARRAY_SIZE(adis16350_channels),
1132
1118
.flags = ADIS16400_HAS_PROD_ID,
1133
1119
.product_id = 0x3FED,
1134
-
.gyro_scale_micro = 1279,
1135
-
.accel_scale_micro = 24732,
1120
+
.gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1121
+
.accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */
1122
+
.temp_scale_nano = 136000000, /* 0.136 C */
1123
+
.temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1136
1124
.default_scan_mask = 0x7FF,
1137
1125
},
1138
1126
[ADIS16400] = {
···
1142
1126
.num_channels = ARRAY_SIZE(adis16400_channels),
1143
1127
.flags = ADIS16400_HAS_PROD_ID,
1144
1128
.product_id = 0x4015,
1145
-
.gyro_scale_micro = 873,
1146
-
.accel_scale_micro = 32656,
1129
+
.gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1130
+
.accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */
1147
1131
.default_scan_mask = 0xFFF,
1132
+
.temp_scale_nano = 140000000, /* 0.14 C */
1133
+
.temp_offset = 25000000 / 140000, /* 25 C = 0x00 */
1148
1134
}
1149
1135
};
1150
1136
+1
drivers/staging/ipack/bridges/tpci200.c
+1
drivers/staging/ipack/bridges/tpci200.c
+2
-2
drivers/staging/omapdrm/omap_gem.c
+2
-2
drivers/staging/omapdrm/omap_gem.c
···
246
246
* DSS, GPU, etc. are not cache coherent:
247
247
*/
248
248
if (omap_obj->flags & (OMAP_BO_WC|OMAP_BO_UNCACHED)) {
249
-
addrs = kmalloc(npages * sizeof(addrs), GFP_KERNEL);
249
+
addrs = kmalloc(npages * sizeof(*addrs), GFP_KERNEL);
250
250
if (!addrs) {
251
251
ret = -ENOMEM;
252
252
goto free_pages;
···
257
257
0, PAGE_SIZE, DMA_BIDIRECTIONAL);
258
258
}
259
259
} else {
260
-
addrs = kzalloc(npages * sizeof(addrs), GFP_KERNEL);
260
+
addrs = kzalloc(npages * sizeof(*addrs), GFP_KERNEL);
261
261
if (!addrs) {
262
262
ret = -ENOMEM;
263
263
goto free_pages;
+1
drivers/staging/ramster/Kconfig
+1
drivers/staging/ramster/Kconfig
+26
-11
drivers/staging/tidspbridge/core/tiomap3430.c
+26
-11
drivers/staging/tidspbridge/core/tiomap3430.c
···
126
126
u32 ul_num_bytes,
127
127
struct hw_mmu_map_attrs_t *hw_attrs);
128
128
129
-
bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
129
+
bool wait_for_start(struct bridge_dev_context *dev_context,
130
+
void __iomem *sync_addr);
130
131
131
132
/* ----------------------------------- Globals */
132
133
···
364
363
{
365
364
int status = 0;
366
365
struct bridge_dev_context *dev_context = dev_ctxt;
367
-
u32 dw_sync_addr = 0;
366
+
void __iomem *sync_addr;
368
367
u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
369
368
u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
370
369
u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
370
+
u32 shm_sync_pa;
371
371
/* Offset of shm_base_virt from tlb_base_virt */
372
372
u32 ul_shm_offset_virt;
373
373
s32 entry_ndx;
···
399
397
/* Kernel logical address */
400
398
ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
401
399
400
+
/* SHM physical sync address */
401
+
shm_sync_pa = dev_context->atlb_entry[0].gpp_pa + ul_shm_offset_virt +
402
+
SHMSYNCOFFSET;
403
+
402
404
/* 2nd wd is used as sync field */
403
-
dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
405
+
sync_addr = ioremap(shm_sync_pa, SZ_32);
406
+
if (!sync_addr)
407
+
return -ENOMEM;
408
+
404
409
/* Write a signature into the shm base + offset; this will
405
410
* get cleared when the DSP program starts. */
406
411
if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
407
412
pr_err("%s: Illegal SM base\n", __func__);
408
413
status = -EPERM;
409
414
} else
410
-
__raw_writel(0xffffffff, dw_sync_addr);
415
+
__raw_writel(0xffffffff, sync_addr);
411
416
412
417
if (!status) {
413
418
resources = dev_context->resources;
···
428
419
* function is made available.
429
420
*/
430
421
void __iomem *ctrl = ioremap(0x48002000, SZ_4K);
431
-
if (!ctrl)
422
+
if (!ctrl) {
423
+
iounmap(sync_addr);
432
424
return -ENOMEM;
425
+
}
433
426
434
427
(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
435
428
OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
···
599
588
(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
600
589
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
601
590
602
-
dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
591
+
dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", *(u32 *)sync_addr);
603
592
dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
604
593
if (dsp_debug)
605
-
while (__raw_readw(dw_sync_addr))
594
+
while (__raw_readw(sync_addr))
606
595
;
607
596
608
597
/* Wait for DSP to clear word in shared memory */
609
598
/* Read the Location */
610
-
if (!wait_for_start(dev_context, dw_sync_addr))
599
+
if (!wait_for_start(dev_context, sync_addr))
611
600
status = -ETIMEDOUT;
612
601
613
602
dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
···
623
612
/* Write the synchronization bit to indicate the
624
613
* completion of OPP table update to DSP
625
614
*/
626
-
__raw_writel(0XCAFECAFE, dw_sync_addr);
615
+
__raw_writel(0XCAFECAFE, sync_addr);
627
616
628
617
/* update board state */
629
618
dev_context->brd_state = BRD_RUNNING;
···
632
621
dev_context->brd_state = BRD_UNKNOWN;
633
622
}
634
623
}
624
+
625
+
iounmap(sync_addr);
626
+
635
627
return status;
636
628
}
637
629
···
1810
1796
* ======== wait_for_start ========
1811
1797
* Wait for the singal from DSP that it has started, or time out.
1812
1798
*/
1813
-
bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr)
1799
+
bool wait_for_start(struct bridge_dev_context *dev_context,
1800
+
void __iomem *sync_addr)
1814
1801
{
1815
1802
u16 timeout = TIHELEN_ACKTIMEOUT;
1816
1803
1817
1804
/* Wait for response from board */
1818
-
while (__raw_readw(dw_sync_addr) && --timeout)
1805
+
while (__raw_readw(sync_addr) && --timeout)
1819
1806
udelay(10);
1820
1807
1821
1808
/* If timed out: return false */
+20
-95
drivers/staging/tidspbridge/hw/hw_mmu.c
+20
-95
drivers/staging/tidspbridge/hw/hw_mmu.c
···
48
48
};
49
49
50
50
/*
51
-
* FUNCTION : mmu_flush_entry
52
-
*
53
-
* INPUTS:
54
-
*
55
-
* Identifier : base_address
56
-
* Type : const u32
57
-
* Description : Base Address of instance of MMU module
58
-
*
59
-
* RETURNS:
60
-
*
61
-
* Type : hw_status
62
-
* Description : 0 -- No errors occurred
63
-
* RET_BAD_NULL_PARAM -- A Pointer
64
-
* Parameter was set to NULL
65
-
*
66
-
* PURPOSE: : Flush the TLB entry pointed by the
67
-
* lock counter register
68
-
* even if this entry is set protected
69
-
*
70
-
* METHOD: : Check the Input parameter and Flush a
71
-
* single entry in the TLB.
72
-
*/
73
-
static hw_status mmu_flush_entry(const void __iomem *base_address);
74
-
75
-
/*
76
51
* FUNCTION : mmu_set_cam_entry
77
52
*
78
53
* INPUTS:
79
54
*
80
55
* Identifier : base_address
81
-
* TypE : const u32
56
+
* Type : void __iomem *
82
57
* Description : Base Address of instance of MMU module
83
58
*
84
59
* Identifier : page_sz
···
87
112
*
88
113
* METHOD: : Check the Input parameters and set the CAM entry.
89
114
*/
90
-
static hw_status mmu_set_cam_entry(const void __iomem *base_address,
115
+
static hw_status mmu_set_cam_entry(void __iomem *base_address,
91
116
const u32 page_sz,
92
117
const u32 preserved_bit,
93
118
const u32 valid_bit,
···
99
124
* INPUTS:
100
125
*
101
126
* Identifier : base_address
102
-
* Type : const u32
127
+
* Type : void __iomem *
103
128
* Description : Base Address of instance of MMU module
104
129
*
105
130
* Identifier : physical_addr
···
132
157
*
133
158
* METHOD: : Check the Input parameters and set the RAM entry.
134
159
*/
135
-
static hw_status mmu_set_ram_entry(const void __iomem *base_address,
160
+
static hw_status mmu_set_ram_entry(void __iomem *base_address,
136
161
const u32 physical_addr,
137
162
enum hw_endianism_t endianism,
138
163
enum hw_element_size_t element_size,
···
140
165
141
166
/* HW FUNCTIONS */
142
167
143
-
hw_status hw_mmu_enable(const void __iomem *base_address)
168
+
hw_status hw_mmu_enable(void __iomem *base_address)
144
169
{
145
170
hw_status status = 0;
146
171
···
149
174
return status;
150
175
}
151
176
152
-
hw_status hw_mmu_disable(const void __iomem *base_address)
177
+
hw_status hw_mmu_disable(void __iomem *base_address)
153
178
{
154
179
hw_status status = 0;
155
180
···
158
183
return status;
159
184
}
160
185
161
-
hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
186
+
hw_status hw_mmu_num_locked_set(void __iomem *base_address,
162
187
u32 num_locked_entries)
163
188
{
164
189
hw_status status = 0;
···
168
193
return status;
169
194
}
170
195
171
-
hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
196
+
hw_status hw_mmu_victim_num_set(void __iomem *base_address,
172
197
u32 victim_entry_num)
173
198
{
174
199
hw_status status = 0;
···
178
203
return status;
179
204
}
180
205
181
-
hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)
206
+
hw_status hw_mmu_event_ack(void __iomem *base_address, u32 irq_mask)
182
207
{
183
208
hw_status status = 0;
184
209
···
187
212
return status;
188
213
}
189
214
190
-
hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)
215
+
hw_status hw_mmu_event_disable(void __iomem *base_address, u32 irq_mask)
191
216
{
192
217
hw_status status = 0;
193
218
u32 irq_reg;
···
199
224
return status;
200
225
}
201
226
202
-
hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)
227
+
hw_status hw_mmu_event_enable(void __iomem *base_address, u32 irq_mask)
203
228
{
204
229
hw_status status = 0;
205
230
u32 irq_reg;
···
211
236
return status;
212
237
}
213
238
214
-
hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)
239
+
hw_status hw_mmu_event_status(void __iomem *base_address, u32 *irq_mask)
215
240
{
216
241
hw_status status = 0;
217
242
···
220
245
return status;
221
246
}
222
247
223
-
hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
248
+
hw_status hw_mmu_fault_addr_read(void __iomem *base_address, u32 *addr)
224
249
{
225
250
hw_status status = 0;
226
251
···
230
255
return status;
231
256
}
232
257
233
-
hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
258
+
hw_status hw_mmu_ttb_set(void __iomem *base_address, u32 ttb_phys_addr)
234
259
{
235
260
hw_status status = 0;
236
261
u32 load_ttb;
···
242
267
return status;
243
268
}
244
269
245
-
hw_status hw_mmu_twl_enable(const void __iomem *base_address)
270
+
hw_status hw_mmu_twl_enable(void __iomem *base_address)
246
271
{
247
272
hw_status status = 0;
248
273
···
251
276
return status;
252
277
}
253
278
254
-
hw_status hw_mmu_twl_disable(const void __iomem *base_address)
279
+
hw_status hw_mmu_twl_disable(void __iomem *base_address)
255
280
{
256
281
hw_status status = 0;
257
282
···
260
285
return status;
261
286
}
262
287
263
-
hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtual_addr,
264
-
u32 page_sz)
265
-
{
266
-
hw_status status = 0;
267
-
u32 virtual_addr_tag;
268
-
enum hw_mmu_page_size_t pg_size_bits;
269
-
270
-
switch (page_sz) {
271
-
case HW_PAGE_SIZE4KB:
272
-
pg_size_bits = HW_MMU_SMALL_PAGE;
273
-
break;
274
-
275
-
case HW_PAGE_SIZE64KB:
276
-
pg_size_bits = HW_MMU_LARGE_PAGE;
277
-
break;
278
-
279
-
case HW_PAGE_SIZE1MB:
280
-
pg_size_bits = HW_MMU_SECTION;
281
-
break;
282
-
283
-
case HW_PAGE_SIZE16MB:
284
-
pg_size_bits = HW_MMU_SUPERSECTION;
285
-
break;
286
-
287
-
default:
288
-
return -EINVAL;
289
-
}
290
-
291
-
/* Generate the 20-bit tag from virtual address */
292
-
virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
293
-
294
-
mmu_set_cam_entry(base_address, pg_size_bits, 0, 0, virtual_addr_tag);
295
-
296
-
mmu_flush_entry(base_address);
297
-
298
-
return status;
299
-
}
300
-
301
-
hw_status hw_mmu_tlb_add(const void __iomem *base_address,
288
+
hw_status hw_mmu_tlb_add(void __iomem *base_address,
302
289
u32 physical_addr,
303
290
u32 virtual_addr,
304
291
u32 page_sz,
···
440
503
return status;
441
504
}
442
505
443
-
/* mmu_flush_entry */
444
-
static hw_status mmu_flush_entry(const void __iomem *base_address)
445
-
{
446
-
hw_status status = 0;
447
-
u32 flush_entry_data = 0x1;
448
-
449
-
/* write values to register */
450
-
MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, flush_entry_data);
451
-
452
-
return status;
453
-
}
454
-
455
506
/* mmu_set_cam_entry */
456
-
static hw_status mmu_set_cam_entry(const void __iomem *base_address,
507
+
static hw_status mmu_set_cam_entry(void __iomem *base_address,
457
508
const u32 page_sz,
458
509
const u32 preserved_bit,
459
510
const u32 valid_bit,
···
461
536
}
462
537
463
538
/* mmu_set_ram_entry */
464
-
static hw_status mmu_set_ram_entry(const void __iomem *base_address,
539
+
static hw_status mmu_set_ram_entry(void __iomem *base_address,
465
540
const u32 physical_addr,
466
541
enum hw_endianism_t endianism,
467
542
enum hw_element_size_t element_size,
···
481
556
482
557
}
483
558
484
-
void hw_mmu_tlb_flush_all(const void __iomem *base)
559
+
void hw_mmu_tlb_flush_all(void __iomem *base)
485
560
{
486
561
__raw_writel(1, base + MMU_GFLUSH);
487
562
}
+14
-17
drivers/staging/tidspbridge/hw/hw_mmu.h
+14
-17
drivers/staging/tidspbridge/hw/hw_mmu.h
···
42
42
bool donotlockmpupage;
43
43
};
44
44
45
-
extern hw_status hw_mmu_enable(const void __iomem *base_address);
45
+
extern hw_status hw_mmu_enable(void __iomem *base_address);
46
46
47
-
extern hw_status hw_mmu_disable(const void __iomem *base_address);
47
+
extern hw_status hw_mmu_disable(void __iomem *base_address);
48
48
49
-
extern hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
49
+
extern hw_status hw_mmu_num_locked_set(void __iomem *base_address,
50
50
u32 num_locked_entries);
51
51
52
-
extern hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
52
+
extern hw_status hw_mmu_victim_num_set(void __iomem *base_address,
53
53
u32 victim_entry_num);
54
54
55
55
/* For MMU faults */
56
-
extern hw_status hw_mmu_event_ack(const void __iomem *base_address,
56
+
extern hw_status hw_mmu_event_ack(void __iomem *base_address,
57
57
u32 irq_mask);
58
58
59
-
extern hw_status hw_mmu_event_disable(const void __iomem *base_address,
59
+
extern hw_status hw_mmu_event_disable(void __iomem *base_address,
60
60
u32 irq_mask);
61
61
62
-
extern hw_status hw_mmu_event_enable(const void __iomem *base_address,
62
+
extern hw_status hw_mmu_event_enable(void __iomem *base_address,
63
63
u32 irq_mask);
64
64
65
-
extern hw_status hw_mmu_event_status(const void __iomem *base_address,
65
+
extern hw_status hw_mmu_event_status(void __iomem *base_address,
66
66
u32 *irq_mask);
67
67
68
-
extern hw_status hw_mmu_fault_addr_read(const void __iomem *base_address,
68
+
extern hw_status hw_mmu_fault_addr_read(void __iomem *base_address,
69
69
u32 *addr);
70
70
71
71
/* Set the TT base address */
72
-
extern hw_status hw_mmu_ttb_set(const void __iomem *base_address,
72
+
extern hw_status hw_mmu_ttb_set(void __iomem *base_address,
73
73
u32 ttb_phys_addr);
74
74
75
-
extern hw_status hw_mmu_twl_enable(const void __iomem *base_address);
75
+
extern hw_status hw_mmu_twl_enable(void __iomem *base_address);
76
76
77
-
extern hw_status hw_mmu_twl_disable(const void __iomem *base_address);
77
+
extern hw_status hw_mmu_twl_disable(void __iomem *base_address);
78
78
79
-
extern hw_status hw_mmu_tlb_flush(const void __iomem *base_address,
80
-
u32 virtual_addr, u32 page_sz);
81
-
82
-
extern hw_status hw_mmu_tlb_add(const void __iomem *base_address,
79
+
extern hw_status hw_mmu_tlb_add(void __iomem *base_address,
83
80
u32 physical_addr,
84
81
u32 virtual_addr,
85
82
u32 page_sz,
···
94
97
extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va,
95
98
u32 virtual_addr, u32 page_size);
96
99
97
-
void hw_mmu_tlb_flush_all(const void __iomem *base);
100
+
void hw_mmu_tlb_flush_all(void __iomem *base);
98
101
99
102
static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va)
100
103
{
+2
-2
drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
+2
-2
drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
+2
-2
drivers/staging/tidspbridge/include/dspbridge/host_os.h
+2
-2
drivers/staging/tidspbridge/include/dspbridge/host_os.h
+4
-4
drivers/staging/tidspbridge/rmgr/drv.c
+4
-4
drivers/staging/tidspbridge/rmgr/drv.c
···
667
667
OMAP_DSP_MEM3_SIZE);
668
668
host_res->per_base = ioremap(OMAP_PER_CM_BASE,
669
669
OMAP_PER_CM_SIZE);
670
-
host_res->per_pm_base = (u32) ioremap(OMAP_PER_PRM_BASE,
671
-
OMAP_PER_PRM_SIZE);
672
-
host_res->core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE,
673
-
OMAP_CORE_PRM_SIZE);
670
+
host_res->per_pm_base = ioremap(OMAP_PER_PRM_BASE,
671
+
OMAP_PER_PRM_SIZE);
672
+
host_res->core_pm_base = ioremap(OMAP_CORE_PRM_BASE,
673
+
OMAP_CORE_PRM_SIZE);
674
674
host_res->dmmu_base = ioremap(OMAP_DMMU_BASE,
675
675
OMAP_DMMU_SIZE);
676
676
+15
-6
drivers/staging/tidspbridge/rmgr/node.c
+15
-6
drivers/staging/tidspbridge/rmgr/node.c
···
304
304
u32 pul_value;
305
305
u32 dynext_base;
306
306
u32 off_set = 0;
307
-
u32 ul_stack_seg_addr, ul_stack_seg_val;
308
-
u32 ul_gpp_mem_base;
307
+
u32 ul_stack_seg_val;
309
308
struct cfg_hostres *host_res;
310
309
struct bridge_dev_context *pbridge_context;
311
310
u32 mapped_addr = 0;
···
580
581
if (strcmp((char *)
581
582
pnode->dcd_props.obj_data.node_obj.ndb_props.
582
583
stack_seg_name, STACKSEGLABEL) == 0) {
584
+
void __iomem *stack_seg;
585
+
u32 stack_seg_pa;
586
+
583
587
status =
584
588
hnode_mgr->nldr_fxns.
585
589
get_fxn_addr(pnode->nldr_node_obj, "DYNEXT_BEG",
···
610
608
goto func_end;
611
609
}
612
610
613
-
ul_gpp_mem_base = (u32) host_res->mem_base[1];
614
611
off_set = pul_value - dynext_base;
615
-
ul_stack_seg_addr = ul_gpp_mem_base + off_set;
616
-
ul_stack_seg_val = readl(ul_stack_seg_addr);
612
+
stack_seg_pa = host_res->mem_phys[1] + off_set;
613
+
stack_seg = ioremap(stack_seg_pa, SZ_32);
614
+
if (!stack_seg) {
615
+
status = -ENOMEM;
616
+
goto func_end;
617
+
}
618
+
619
+
ul_stack_seg_val = readl(stack_seg);
620
+
621
+
iounmap(stack_seg);
617
622
618
623
dev_dbg(bridge, "%s: StackSegVal = 0x%x, StackSegAddr ="
619
624
" 0x%x\n", __func__, ul_stack_seg_val,
620
-
ul_stack_seg_addr);
625
+
host_res->mem_base[1] + off_set);
621
626
622
627
pnode->create_args.asa.task_arg_obj.stack_seg =
623
628
ul_stack_seg_val;
+10
-2
drivers/staging/zram/zram_drv.c
+10
-2
drivers/staging/zram/zram_drv.c
···
223
223
cmem = zs_map_object(zram->mem_pool, zram->table[index].handle,
224
224
ZS_MM_RO);
225
225
226
-
ret = lzo1x_decompress_safe(cmem, zram->table[index].size,
226
+
if (zram->table[index].size == PAGE_SIZE) {
227
+
memcpy(uncmem, cmem, PAGE_SIZE);
228
+
ret = LZO_E_OK;
229
+
} else {
230
+
ret = lzo1x_decompress_safe(cmem, zram->table[index].size,
227
231
uncmem, &clen);
232
+
}
228
233
229
234
if (is_partial_io(bvec)) {
230
235
memcpy(user_mem + bvec->bv_offset, uncmem + offset,
···
347
342
goto out;
348
343
}
349
344
350
-
if (unlikely(clen > max_zpage_size))
345
+
if (unlikely(clen > max_zpage_size)) {
351
346
zram_stat_inc(&zram->stats.bad_compress);
347
+
src = uncmem;
348
+
clen = PAGE_SIZE;
349
+
}
352
350
353
351
handle = zs_malloc(zram->mem_pool, clen);
354
352
if (!handle) {
+16
include/linux/iio/iio.h
+16
include/linux/iio/iio.h
···
618
618
};
619
619
#endif
620
620
621
+
/**
622
+
* IIO_DEGREE_TO_RAD() - Convert degree to rad
623
+
* @deg: A value in degree
624
+
*
625
+
* Returns the given value converted from degree to rad
626
+
*/
627
+
#define IIO_DEGREE_TO_RAD(deg) (((deg) * 314159ULL + 9000000ULL) / 18000000ULL)
628
+
629
+
/**
630
+
* IIO_G_TO_M_S_2() - Convert g to meter / second**2
631
+
* @g: A value in g
632
+
*
633
+
* Returns the given value converted from g to meter / second**2
634
+
*/
635
+
#define IIO_G_TO_M_S_2(g) ((g) * 980665ULL / 100000ULL)
636
+
621
637
#endif /* _INDUSTRIAL_IO_H_ */