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ntb: intel: Add Intel Gen6 NTB support for DiamondRapids

Add DiamondRapids NTB support by adding the DID and adjust the changed
PPD0 offset.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>

authored by

Dave Jiang and committed by
Jon Mason
49218116 7bd27439

+35 -9
+10 -4
drivers/ntb/hw/intel/ntb_hw_gen1.c
··· 763 763 return ndev_ntb_debugfs_read(filp, ubuf, count, offp); 764 764 else if (pdev_is_gen3(ndev->ntb.pdev)) 765 765 return ndev_ntb3_debugfs_read(filp, ubuf, count, offp); 766 - else if (pdev_is_gen4(ndev->ntb.pdev) || pdev_is_gen5(ndev->ntb.pdev)) 766 + else if (pdev_is_gen4(ndev->ntb.pdev) || pdev_is_gen5(ndev->ntb.pdev) || 767 + pdev_is_gen6(ndev->ntb.pdev)) 767 768 return ndev_ntb4_debugfs_read(filp, ubuf, count, offp); 768 769 769 770 return -ENXIO; ··· 1873 1872 rc = gen3_init_dev(ndev); 1874 1873 if (rc) 1875 1874 goto err_init_dev; 1876 - } else if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) { 1875 + } else if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev) || 1876 + pdev_is_gen6(pdev)) { 1877 1877 ndev->ntb.ops = &intel_ntb4_ops; 1878 1878 rc = intel_ntb_init_pci(ndev, pdev); 1879 1879 if (rc) ··· 1905 1903 err_register: 1906 1904 ndev_deinit_debugfs(ndev); 1907 1905 if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || 1908 - pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) 1906 + pdev_is_gen4(pdev) || pdev_is_gen5(pdev) || 1907 + pdev_is_gen6(pdev)) 1909 1908 xeon_deinit_dev(ndev); 1910 1909 err_init_dev: 1911 1910 intel_ntb_deinit_pci(ndev); ··· 1923 1920 ntb_unregister_device(&ndev->ntb); 1924 1921 ndev_deinit_debugfs(ndev); 1925 1922 if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || 1926 - pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) 1923 + pdev_is_gen4(pdev) || pdev_is_gen5(pdev) || 1924 + pdev_is_gen6(pdev)) 1927 1925 xeon_deinit_dev(ndev); 1928 1926 intel_ntb_deinit_pci(ndev); 1929 1927 kfree(ndev); ··· 2053 2049 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)}, 2054 2050 /* GEN5 PCIe */ 2055 2051 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)}, 2052 + /* GEN6 PCIe */ 2053 + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_DMR)}, 2056 2054 {0} 2057 2055 }; 2058 2056 MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl);
+17 -5
drivers/ntb/hw/intel/ntb_hw_gen4.c
··· 46 46 .spad = GEN4_EM_SPAD_OFFSET, 47 47 }; 48 48 49 + static u64 get_ppd0(struct pci_dev *pdev) 50 + { 51 + if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) 52 + return GEN4_PPD0_OFFSET; 53 + else if (pdev_is_gen6(pdev)) 54 + return GEN6_PPD0_OFFSET; 55 + 56 + return ULLONG_MAX; 57 + } 58 + 49 59 static int gen4_poll_link(struct intel_ntb_dev *ndev) 50 60 { 51 61 u16 reg_val; ··· 193 183 int gen4_init_dev(struct intel_ntb_dev *ndev) 194 184 { 195 185 struct pci_dev *pdev = ndev->ntb.pdev; 196 - u32 ppd1/*, ppd0*/; 186 + u32 ppd1; 197 187 u16 lnkctl; 198 188 int rc; 199 189 ··· 207 197 ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET); 208 198 if (pdev_is_ICX(pdev)) 209 199 ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1); 210 - else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev)) 200 + else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev) || pdev_is_gen6(pdev)) 211 201 ndev->ntb.topo = spr_ppd_topo(ndev, ppd1); 212 202 dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1, 213 203 ntb_topo_string(ndev->ntb.topo)); ··· 442 432 enum ntb_speed max_speed, enum ntb_width max_width) 443 433 { 444 434 struct intel_ntb_dev *ndev; 435 + struct pci_dev *pdev; 445 436 u32 ntb_ctl, ppd0; 446 437 u16 lnkctl; 447 438 448 439 ndev = container_of(ntb, struct intel_ntb_dev, ntb); 440 + pdev = ntb->pdev; 449 441 450 442 dev_dbg(&ntb->pdev->dev, 451 443 "Enabling link with max_speed %d max_width %d\n", ··· 488 476 iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET); 489 477 490 478 /* start link training in PPD0 */ 491 - ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET); 479 + ppd0 = ioread32(ndev->self_mmio + get_ppd0(pdev)); 492 480 ppd0 |= GEN4_PPD_LINKTRN; 493 - iowrite32(ppd0, ndev->self_mmio + GEN4_PPD0_OFFSET); 481 + iowrite32(ppd0, ndev->self_mmio + get_ppd0(pdev)); 494 482 495 483 /* make sure link training has started */ 496 - ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET); 484 + ppd0 = ioread32(ndev->self_mmio + get_ppd0(pdev)); 497 485 if (!(ppd0 & GEN4_PPD_LINKTRN)) { 498 486 dev_warn(&ntb->pdev->dev, "Link is not training\n"); 499 487 return -ENXIO;
+2
drivers/ntb/hw/intel/ntb_hw_gen4.h
··· 103 103 #define NTB_LTR_IDLE_LATSCALE 0x0800 /* 1us scale */ 104 104 #define NTB_LTR_IDLE_REQMNT 0x8000 /* snoop req enable */ 105 105 106 + #define GEN6_PPD0_OFFSET 0xf0d4 107 + 106 108 ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf, 107 109 size_t count, loff_t *offp); 108 110 int gen4_init_dev(struct intel_ntb_dev *ndev);
+6
drivers/ntb/hw/intel/ntb_hw_intel.h
··· 71 71 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C 72 72 #define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e 73 73 #define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4 74 + #define PCI_DEVICE_ID_INTEL_NTB_B2B_DMR 0x7868 74 75 75 76 /* Ntb control and link status */ 76 77 #define NTB_CTL_CFG_LOCK BIT(0) ··· 234 233 static inline int pdev_is_gen5(struct pci_dev *pdev) 235 234 { 236 235 return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR; 236 + } 237 + 238 + static inline int pdev_is_gen6(struct pci_dev *pdev) 239 + { 240 + return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_DMR; 237 241 } 238 242 239 243 #endif