Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mtd/fixes-for-5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD fixes from Miquel Raynal:
"MTD:
- sm_ftl: Fix NULL pointer warning.
Raw NAND:
- Cadence: fix compile testing.
- STM32: Avoid locking.
Onenand:
- Fix several sparse/build warnings.
SPI-NOR:
- Add a flag to fix interaction with Micron parts"
* tag 'mtd/fixes-for-5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
mtd: spi-nor: Fix the writing of the Status Register on micron flashes
mtd: sm_ftl: fix NULL pointer warning
mtd: onenand: omap2: Pass correct flags for prep_dma_memcpy
mtd: onenand: samsung: Fix iomem access with regular memcpy
mtd: onenand: omap2: Fix errors in style
mtd: cadence: Fix cast to pointer from integer of different size warning
mtd: rawnand: stm32_fmc2: avoid to lock the CPU bus
+65
-28
+8
-6
drivers/mtd/nand/onenand/omap2.c
+8
-6
drivers/mtd/nand/onenand/omap2.c
···
148
148
unsigned long timeout;
149
149
u32 syscfg;
150
150
151
-
if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
151
+
if (state == FL_RESETTING || state == FL_PREPARING_ERASE ||
152
152
state == FL_VERIFYING_ERASE) {
153
153
int i = 21;
154
154
unsigned int intr_flags = ONENAND_INT_MASTER;
155
155
156
156
switch (state) {
157
-
case FL_RESETING:
157
+
case FL_RESETTING:
158
158
intr_flags |= ONENAND_INT_RESET;
159
159
break;
160
160
case FL_PREPARING_ERASE:
···
328
328
struct dma_async_tx_descriptor *tx;
329
329
dma_cookie_t cookie;
330
330
331
-
tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
331
+
tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count,
332
+
DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
332
333
if (!tx) {
333
334
dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
334
335
return -EIO;
···
376
375
* context fallback to PIO mode.
377
376
*/
378
377
if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
379
-
count < 384 || in_interrupt() || oops_in_progress )
378
+
count < 384 || in_interrupt() || oops_in_progress)
380
379
goto out_copy;
381
380
382
381
xtra = count & 3;
···
423
422
* context fallback to PIO mode.
424
423
*/
425
424
if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
426
-
count < 384 || in_interrupt() || oops_in_progress )
425
+
count < 384 || in_interrupt() || oops_in_progress)
427
426
goto out_copy;
428
427
429
428
dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);
···
529
528
c->gpmc_cs, c->phys_base, c->onenand.base,
530
529
c->dma_chan ? "DMA" : "PIO");
531
530
532
-
if ((r = onenand_scan(&c->mtd, 1)) < 0)
531
+
r = onenand_scan(&c->mtd, 1);
532
+
if (r < 0)
533
533
goto err_release_dma;
534
534
535
535
freq = omap2_onenand_get_freq(c->onenand.version_id);
+7
-7
drivers/mtd/nand/onenand/onenand_base.c
+7
-7
drivers/mtd/nand/onenand/onenand_base.c
···
2853
2853
2854
2854
/* Exit OTP access mode */
2855
2855
this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2856
-
this->wait(mtd, FL_RESETING);
2856
+
this->wait(mtd, FL_RESETTING);
2857
2857
2858
2858
status = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
2859
2859
status &= 0x60;
···
2924
2924
2925
2925
/* Exit OTP access mode */
2926
2926
this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2927
-
this->wait(mtd, FL_RESETING);
2927
+
this->wait(mtd, FL_RESETTING);
2928
2928
2929
2929
return ret;
2930
2930
}
···
2968
2968
2969
2969
/* Exit OTP access mode */
2970
2970
this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2971
-
this->wait(mtd, FL_RESETING);
2971
+
this->wait(mtd, FL_RESETTING);
2972
2972
2973
2973
return ret;
2974
2974
}
···
3008
3008
3009
3009
/* Exit OTP access mode */
3010
3010
this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3011
-
this->wait(mtd, FL_RESETING);
3011
+
this->wait(mtd, FL_RESETTING);
3012
3012
} else {
3013
3013
ops.mode = MTD_OPS_PLACE_OOB;
3014
3014
ops.ooblen = len;
···
3413
3413
this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
3414
3414
3415
3415
this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3416
-
this->wait(mtd, FL_RESETING);
3416
+
this->wait(mtd, FL_RESETTING);
3417
3417
3418
3418
printk(KERN_INFO "Die %d boundary: %d%s\n", die,
3419
3419
this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
···
3635
3635
ret = this->wait(mtd, FL_WRITING);
3636
3636
out:
3637
3637
this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
3638
-
this->wait(mtd, FL_RESETING);
3638
+
this->wait(mtd, FL_RESETTING);
3639
3639
if (!ret)
3640
3640
/* Recalculate device size on boundary change*/
3641
3641
flexonenand_get_size(mtd);
···
3671
3671
/* Reset OneNAND to read default register values */
3672
3672
this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
3673
3673
/* Wait reset */
3674
-
this->wait(mtd, FL_RESETING);
3674
+
this->wait(mtd, FL_RESETTING);
3675
3675
3676
3676
/* Restore system configuration 1 */
3677
3677
this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
+4
-4
drivers/mtd/nand/onenand/samsung_mtd.c
+4
-4
drivers/mtd/nand/onenand/samsung_mtd.c
···
675
675
normal:
676
676
if (count != mtd->writesize) {
677
677
/* Copy the bufferram to memory to prevent unaligned access */
678
-
memcpy(this->page_buf, p, mtd->writesize);
679
-
p = this->page_buf + offset;
678
+
memcpy_fromio(this->page_buf, p, mtd->writesize);
679
+
memcpy(buffer, this->page_buf + offset, count);
680
+
} else {
681
+
memcpy_fromio(buffer, p, count);
680
682
}
681
-
682
-
memcpy(buffer, p, count);
683
683
684
684
return 0;
685
685
}
+6
-7
drivers/mtd/nand/raw/cadence-nand-controller.c
+6
-7
drivers/mtd/nand/raw/cadence-nand-controller.c
···
914
914
/* Prepare CDMA descriptor. */
915
915
static void
916
916
cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,
917
-
char nf_mem, u32 flash_ptr, char *mem_ptr,
918
-
char *ctrl_data_ptr, u16 ctype)
917
+
char nf_mem, u32 flash_ptr, dma_addr_t mem_ptr,
918
+
dma_addr_t ctrl_data_ptr, u16 ctype)
919
919
{
920
920
struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc;
921
921
···
931
931
cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;
932
932
cdma_desc->command_flags |= CDMA_CF_INT;
933
933
934
-
cdma_desc->memory_pointer = (uintptr_t)mem_ptr;
934
+
cdma_desc->memory_pointer = mem_ptr;
935
935
cdma_desc->status = 0;
936
936
cdma_desc->sync_flag_pointer = 0;
937
937
cdma_desc->sync_arguments = 0;
938
938
939
939
cdma_desc->command_type = ctype;
940
-
cdma_desc->ctrl_data_ptr = (uintptr_t)ctrl_data_ptr;
940
+
cdma_desc->ctrl_data_ptr = ctrl_data_ptr;
941
941
}
942
942
943
943
static u8 cadence_nand_check_desc_error(struct cdns_nand_ctrl *cdns_ctrl,
···
1280
1280
}
1281
1281
1282
1282
cadence_nand_cdma_desc_prepare(cdns_ctrl, chip_nr, page,
1283
-
(void *)dma_buf, (void *)dma_ctrl_dat,
1284
-
ctype);
1283
+
dma_buf, dma_ctrl_dat, ctype);
1285
1284
1286
1285
status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
1287
1286
···
1359
1360
1360
1361
cadence_nand_cdma_desc_prepare(cdns_ctrl,
1361
1362
cdns_chip->cs[chip->cur_cs],
1362
-
page, NULL, NULL,
1363
+
page, 0, 0,
1363
1364
CDMA_CT_ERASE);
1364
1365
status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
1365
1366
if (status) {
+36
-2
drivers/mtd/nand/raw/stm32_fmc2_nand.c
+36
-2
drivers/mtd/nand/raw/stm32_fmc2_nand.c
···
37
37
/* Max ECC buffer length */
38
38
#define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
39
39
40
+
#define FMC2_TIMEOUT_US 1000
40
41
#define FMC2_TIMEOUT_MS 1000
41
42
42
43
/* Timings */
···
54
53
#define FMC2_PMEM 0x88
55
54
#define FMC2_PATT 0x8c
56
55
#define FMC2_HECCR 0x94
56
+
#define FMC2_ISR 0x184
57
+
#define FMC2_ICR 0x188
57
58
#define FMC2_CSQCR 0x200
58
59
#define FMC2_CSQCFGR1 0x204
59
60
#define FMC2_CSQCFGR2 0x208
···
120
117
#define FMC2_PATT_ATTHOLD(x) (((x) & 0xff) << 16)
121
118
#define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24)
122
119
#define FMC2_PATT_DEFAULT 0x0a0a0a0a
120
+
121
+
/* Register: FMC2_ISR */
122
+
#define FMC2_ISR_IHLF BIT(1)
123
+
124
+
/* Register: FMC2_ICR */
125
+
#define FMC2_ICR_CIHLF BIT(1)
123
126
124
127
/* Register: FMC2_CSQCR */
125
128
#define FMC2_CSQCR_CSQSTART BIT(0)
···
1331
1322
stm32_fmc2_set_buswidth_16(fmc2, true);
1332
1323
}
1333
1324
1325
+
static int stm32_fmc2_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
1326
+
{
1327
+
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
1328
+
const struct nand_sdr_timings *timings;
1329
+
u32 isr, sr;
1330
+
1331
+
/* Check if there is no pending requests to the NAND flash */
1332
+
if (readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_SR, sr,
1333
+
sr & FMC2_SR_NWRF, 1,
1334
+
FMC2_TIMEOUT_US))
1335
+
dev_warn(fmc2->dev, "Waitrdy timeout\n");
1336
+
1337
+
/* Wait tWB before R/B# signal is low */
1338
+
timings = nand_get_sdr_timings(&chip->data_interface);
1339
+
ndelay(PSEC_TO_NSEC(timings->tWB_max));
1340
+
1341
+
/* R/B# signal is low, clear high level flag */
1342
+
writel_relaxed(FMC2_ICR_CIHLF, fmc2->io_base + FMC2_ICR);
1343
+
1344
+
/* Wait R/B# signal is high */
1345
+
return readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_ISR,
1346
+
isr, isr & FMC2_ISR_IHLF,
1347
+
5, 1000 * timeout_ms);
1348
+
}
1349
+
1334
1350
static int stm32_fmc2_exec_op(struct nand_chip *chip,
1335
1351
const struct nand_operation *op,
1336
1352
bool check_only)
···
1400
1366
break;
1401
1367
1402
1368
case NAND_OP_WAITRDY_INSTR:
1403
-
ret = nand_soft_waitrdy(chip,
1404
-
instr->ctx.waitrdy.timeout_ms);
1369
+
ret = stm32_fmc2_waitrdy(chip,
1370
+
instr->ctx.waitrdy.timeout_ms);
1405
1371
break;
1406
1372
}
1407
1373
}
+2
-1
drivers/mtd/sm_ftl.c
+2
-1
drivers/mtd/sm_ftl.c
+1
drivers/mtd/spi-nor/spi-nor.c
+1
drivers/mtd/spi-nor/spi-nor.c