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dmaengine: mmp_pdma: fix DMA mask handling

The driver's existing logic for setting the DMA mask for "marvell,pdma-1.0"
was flawed. It incorrectly relied on pdev->dev->coherent_dma_mask instead
of declaring the hardware's fixed addressing capability. A cleaner and
more correct approach is to define the mask directly based on the hardware
limitations.

The MMP/PXA PDMA controller is a 32-bit DMA engine. This is supported by
datasheets and various dtsi files for PXA25x, PXA27x, PXA3xx, and MMP2,
all of which are 32-bit systems.

This patch simplifies the driver's logic by replacing the 'u64 dma_mask'
field with a simpler 'u32 dma_width' to store the addressing capability
in bits. The complex if/else block in probe() is then replaced with a
single, clear call to dma_set_mask_and_coherent(). This sets a fixed
32-bit DMA mask for "marvell,pdma-1.0" and a 64-bit mask for
"spacemit,k1-pdma," matching each device's hardware capabilities.

Finally, this change also works around a specific build error encountered
with clang-20 on x86_64 allyesconfig. The shift-count-overflow error is
caused by a known clang compiler issue where the DMA_BIT_MASK(n) macro's
ternary operator is not correctly evaluated in static initializers. By
moving the macro's evaluation into the probe() function, the driver avoids
this compiler bug.

Fixes: 5cfe585d8624 ("dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing")
Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Closes: https://lore.kernel.org/lkml/CA+G9fYsPcMfW-e_0_TRqu4cnwqOqYF3aJOeKUYk6Z4qRStdFvg@mail.gmail.com
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Nathan Chancellor <nathan@kernel.org> # build
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Guodong Xu and committed by
Vinod Koul 49400b70 8f0b4cce

+8 -12
+8 -12
drivers/dma/mmp_pdma.c
··· 152 152 * 153 153 * Controller Configuration: 154 154 * @run_bits: Control bits in DCSR register for channel start/stop 155 - * @dma_mask: DMA addressing capability of controller. 0 to use OF/platform 156 - * settings, or explicit mask like DMA_BIT_MASK(32/64) 155 + * @dma_width: DMA addressing width in bits (32 or 64). Determines the 156 + * DMA mask capability of the controller hardware. 157 157 */ 158 158 struct mmp_pdma_ops { 159 159 /* Hardware Register Operations */ ··· 173 173 174 174 /* Controller Configuration */ 175 175 u32 run_bits; 176 - u64 dma_mask; 176 + u32 dma_width; 177 177 }; 178 178 179 179 struct mmp_pdma_device { ··· 1172 1172 .get_desc_src_addr = get_desc_src_addr_32, 1173 1173 .get_desc_dst_addr = get_desc_dst_addr_32, 1174 1174 .run_bits = (DCSR_RUN), 1175 - .dma_mask = 0, /* let OF/platform set DMA mask */ 1175 + .dma_width = 32, 1176 1176 }; 1177 1177 1178 1178 static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { ··· 1185 1185 .get_desc_src_addr = get_desc_src_addr_64, 1186 1186 .get_desc_dst_addr = get_desc_dst_addr_64, 1187 1187 .run_bits = (DCSR_RUN | DCSR_LPAEEN), 1188 - .dma_mask = DMA_BIT_MASK(64), /* force 64-bit DMA addr capability */ 1188 + .dma_width = 64, 1189 1189 }; 1190 1190 1191 1191 static const struct of_device_id mmp_pdma_dt_ids[] = { ··· 1314 1314 pdev->device.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); 1315 1315 pdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 1316 1316 1317 - /* Set DMA mask based on ops->dma_mask, or OF/platform */ 1318 - if (pdev->ops->dma_mask) 1319 - dma_set_mask(pdev->dev, pdev->ops->dma_mask); 1320 - else if (pdev->dev->coherent_dma_mask) 1321 - dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask); 1322 - else 1323 - dma_set_mask(pdev->dev, DMA_BIT_MASK(64)); 1317 + /* Set DMA mask based on controller hardware capabilities */ 1318 + dma_set_mask_and_coherent(pdev->dev, 1319 + DMA_BIT_MASK(pdev->ops->dma_width)); 1324 1320 1325 1321 ret = dma_async_device_register(&pdev->device); 1326 1322 if (ret) {