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arm64: dts: qcom: sc8180x: Add display and gpu nodes

This patch adds gpu, gmu, gpucc, dispcc and finally the mdss node with
dsi0/1, dp0/1 and edp subnodes as found in this SoC

Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230530162454.51708-13-vkoul@kernel.org

authored by

Vinod Koul and committed by
Bjorn Andersson 494dec9b b080f53a

+658
+658
arch/arm64/boot/dts/qcom/sc8180x.dtsi
··· 4 4 * Copyright (c) 2020-2023, Linaro Limited 5 5 */ 6 6 7 + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 7 8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h> 9 + #include <dt-bindings/clock/qcom,gpucc-sm8150.h> 8 10 #include <dt-bindings/clock/qcom,rpmh.h> 9 11 #include <dt-bindings/interconnect/qcom,osm-l3.h> 10 12 #include <dt-bindings/interconnect/qcom,sc8180x.h> ··· 2192 2190 #hwlock-cells = <1>; 2193 2191 }; 2194 2192 2193 + gpu: gpu@2c00000 { 2194 + compatible = "qcom,adreno-680.1", "qcom,adreno"; 2195 + #stream-id-cells = <16>; 2196 + 2197 + reg = <0 0x02c00000 0 0x40000>; 2198 + reg-names = "kgsl_3d0_reg_memory"; 2199 + 2200 + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2201 + 2202 + iommus = <&adreno_smmu 0 0xc01>; 2203 + 2204 + operating-points-v2 = <&gpu_opp_table>; 2205 + 2206 + interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2207 + interconnect-names = "gfx-mem"; 2208 + 2209 + qcom,gmu = <&gmu>; 2210 + status = "disabled"; 2211 + 2212 + gpu_opp_table: opp-table { 2213 + compatible = "operating-points-v2"; 2214 + 2215 + opp-514000000 { 2216 + opp-hz = /bits/ 64 <514000000>; 2217 + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2218 + }; 2219 + 2220 + opp-500000000 { 2221 + opp-hz = /bits/ 64 <500000000>; 2222 + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2223 + }; 2224 + 2225 + opp-461000000 { 2226 + opp-hz = /bits/ 64 <461000000>; 2227 + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2228 + }; 2229 + 2230 + opp-405000000 { 2231 + opp-hz = /bits/ 64 <405000000>; 2232 + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2233 + }; 2234 + 2235 + opp-315000000 { 2236 + opp-hz = /bits/ 64 <315000000>; 2237 + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2238 + }; 2239 + 2240 + opp-256000000 { 2241 + opp-hz = /bits/ 64 <256000000>; 2242 + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2243 + }; 2244 + 2245 + opp-177000000 { 2246 + opp-hz = /bits/ 64 <177000000>; 2247 + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2248 + }; 2249 + }; 2250 + }; 2251 + 2252 + gmu: gmu@2c6a000 { 2253 + compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2254 + 2255 + reg = <0 0x02c6a000 0 0x30000>, 2256 + <0 0x0b290000 0 0x10000>, 2257 + <0 0x0b490000 0 0x10000>; 2258 + reg-names = "gmu", 2259 + "gmu_pdc", 2260 + "gmu_pdc_seq"; 2261 + 2262 + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2263 + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2264 + interrupt-names = "hfi", "gmu"; 2265 + 2266 + clocks = <&gpucc GPU_CC_AHB_CLK>, 2267 + <&gpucc GPU_CC_CX_GMU_CLK>, 2268 + <&gpucc GPU_CC_CXO_CLK>, 2269 + <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2270 + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2271 + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2272 + 2273 + power-domains = <&gpucc GPU_CX_GDSC>, 2274 + <&gpucc GPU_GX_GDSC>; 2275 + power-domain-names = "cx", "gx"; 2276 + 2277 + iommus = <&adreno_smmu 5 0xc00>; 2278 + 2279 + operating-points-v2 = <&gmu_opp_table>; 2280 + 2281 + gmu_opp_table: opp-table { 2282 + compatible = "operating-points-v2"; 2283 + 2284 + opp-200000000 { 2285 + opp-hz = /bits/ 64 <200000000>; 2286 + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2287 + }; 2288 + 2289 + opp-500000000 { 2290 + opp-hz = /bits/ 64 <500000000>; 2291 + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2292 + }; 2293 + }; 2294 + }; 2295 + 2296 + gpucc: clock-controller@2c90000 { 2297 + compatible = "qcom,sc8180x-gpucc"; 2298 + reg = <0 0x02c90000 0 0x9000>; 2299 + clocks = <&rpmhcc RPMH_CXO_CLK>, 2300 + <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2301 + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2302 + clock-names = "bi_tcxo", 2303 + "gcc_gpu_gpll0_clk_src", 2304 + "gcc_gpu_gpll0_div_clk_src"; 2305 + #clock-cells = <1>; 2306 + #reset-cells = <1>; 2307 + #power-domain-cells = <1>; 2308 + }; 2309 + 2195 2310 adreno_smmu: iommu@2ca0000 { 2196 2311 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 2197 2312 reg = <0 0x02ca0000 0 0x10000>; ··· 2656 2537 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; 2657 2538 phy-names = "usb2-phy", "usb3-phy"; 2658 2539 }; 2540 + }; 2541 + 2542 + mdss: mdss@ae00000 { 2543 + compatible = "qcom,sc8180x-mdss"; 2544 + reg = <0 0x0ae00000 0 0x1000>; 2545 + reg-names = "mdss"; 2546 + 2547 + power-domains = <&dispcc MDSS_GDSC>; 2548 + 2549 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2550 + <&gcc GCC_DISP_HF_AXI_CLK>, 2551 + <&gcc GCC_DISP_SF_AXI_CLK>, 2552 + <&dispcc DISP_CC_MDSS_MDP_CLK>; 2553 + clock-names = "iface", 2554 + "bus", 2555 + "nrt_bus", 2556 + "core"; 2557 + 2558 + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2559 + 2560 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2561 + interrupt-controller; 2562 + #interrupt-cells = <1>; 2563 + 2564 + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 2565 + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 2566 + interconnect-names = "mdp0-mem", "mdp1-mem"; 2567 + 2568 + iommus = <&apps_smmu 0x800 0x420>; 2569 + 2570 + #address-cells = <2>; 2571 + #size-cells = <2>; 2572 + ranges; 2573 + 2574 + status = "disabled"; 2575 + 2576 + mdss_mdp: mdp@ae01000 { 2577 + compatible = "qcom,sc8180x-dpu"; 2578 + reg = <0 0x0ae01000 0 0x8f000>, 2579 + <0 0x0aeb0000 0 0x2008>; 2580 + reg-names = "mdp", "vbif"; 2581 + 2582 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2583 + <&gcc GCC_DISP_HF_AXI_CLK>, 2584 + <&dispcc DISP_CC_MDSS_MDP_CLK>, 2585 + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2586 + clock-names = "iface", 2587 + "bus", 2588 + "core", 2589 + "vsync"; 2590 + 2591 + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2592 + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2593 + assigned-clock-rates = <460000000>, 2594 + <19200000>; 2595 + 2596 + operating-points-v2 = <&mdp_opp_table>; 2597 + power-domains = <&rpmhpd SC8180X_MMCX>; 2598 + 2599 + interrupt-parent = <&mdss>; 2600 + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2601 + 2602 + ports { 2603 + #address-cells = <1>; 2604 + #size-cells = <0>; 2605 + 2606 + port@0 { 2607 + reg = <0>; 2608 + dpu_intf0_out: endpoint { 2609 + remote-endpoint = <&dp0_in>; 2610 + }; 2611 + }; 2612 + 2613 + port@1 { 2614 + reg = <1>; 2615 + dpu_intf1_out: endpoint { 2616 + remote-endpoint = <&dsi0_in>; 2617 + }; 2618 + }; 2619 + 2620 + port@2 { 2621 + reg = <2>; 2622 + dpu_intf2_out: endpoint { 2623 + remote-endpoint = <&dsi1_in>; 2624 + }; 2625 + }; 2626 + 2627 + port@4 { 2628 + reg = <4>; 2629 + dpu_intf4_out: endpoint { 2630 + remote-endpoint = <&dp1_in>; 2631 + }; 2632 + }; 2633 + 2634 + port@5 { 2635 + reg = <5>; 2636 + dpu_intf5_out: endpoint { 2637 + remote-endpoint = <&edp_in>; 2638 + }; 2639 + }; 2640 + }; 2641 + 2642 + mdp_opp_table: opp-table { 2643 + compatible = "operating-points-v2"; 2644 + 2645 + opp-200000000 { 2646 + opp-hz = /bits/ 64 <200000000>; 2647 + required-opps = <&rpmhpd_opp_low_svs>; 2648 + }; 2649 + 2650 + opp-300000000 { 2651 + opp-hz = /bits/ 64 <300000000>; 2652 + required-opps = <&rpmhpd_opp_svs>; 2653 + }; 2654 + 2655 + opp-345000000 { 2656 + opp-hz = /bits/ 64 <345000000>; 2657 + required-opps = <&rpmhpd_opp_svs_l1>; 2658 + }; 2659 + 2660 + opp-460000000 { 2661 + opp-hz = /bits/ 64 <460000000>; 2662 + required-opps = <&rpmhpd_opp_nom>; 2663 + }; 2664 + }; 2665 + }; 2666 + 2667 + dsi0: dsi@ae94000 { 2668 + compatible = "qcom,mdss-dsi-ctrl"; 2669 + reg = <0 0x0ae94000 0 0x400>; 2670 + reg-names = "dsi_ctrl"; 2671 + 2672 + interrupt-parent = <&mdss>; 2673 + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2674 + 2675 + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2676 + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2677 + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2678 + <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2679 + <&dispcc DISP_CC_MDSS_AHB_CLK>, 2680 + <&gcc GCC_DISP_HF_AXI_CLK>; 2681 + clock-names = "byte", 2682 + "byte_intf", 2683 + "pixel", 2684 + "core", 2685 + "iface", 2686 + "bus"; 2687 + 2688 + operating-points-v2 = <&dsi_opp_table>; 2689 + power-domains = <&rpmhpd SC8180X_MMCX>; 2690 + 2691 + phys = <&dsi0_phy>; 2692 + phy-names = "dsi"; 2693 + 2694 + status = "disabled"; 2695 + 2696 + ports { 2697 + #address-cells = <1>; 2698 + #size-cells = <0>; 2699 + 2700 + port@0 { 2701 + reg = <0>; 2702 + dsi0_in: endpoint { 2703 + remote-endpoint = <&dpu_intf1_out>; 2704 + }; 2705 + }; 2706 + 2707 + port@1 { 2708 + reg = <1>; 2709 + dsi0_out: endpoint { 2710 + }; 2711 + }; 2712 + }; 2713 + 2714 + dsi_opp_table: opp-table { 2715 + compatible = "operating-points-v2"; 2716 + 2717 + opp-187500000 { 2718 + opp-hz = /bits/ 64 <187500000>; 2719 + required-opps = <&rpmhpd_opp_low_svs>; 2720 + }; 2721 + 2722 + opp-300000000 { 2723 + opp-hz = /bits/ 64 <300000000>; 2724 + required-opps = <&rpmhpd_opp_svs>; 2725 + }; 2726 + 2727 + opp-358000000 { 2728 + opp-hz = /bits/ 64 <358000000>; 2729 + required-opps = <&rpmhpd_opp_svs_l1>; 2730 + }; 2731 + }; 2732 + }; 2733 + 2734 + dsi0_phy: dsi-phy@ae94400 { 2735 + compatible = "qcom,dsi-phy-7nm"; 2736 + reg = <0 0x0ae94400 0 0x200>, 2737 + <0 0x0ae94600 0 0x280>, 2738 + <0 0x0ae94900 0 0x260>; 2739 + reg-names = "dsi_phy", 2740 + "dsi_phy_lane", 2741 + "dsi_pll"; 2742 + 2743 + #clock-cells = <1>; 2744 + #phy-cells = <0>; 2745 + 2746 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2747 + <&rpmhcc RPMH_CXO_CLK>; 2748 + clock-names = "iface", "ref"; 2749 + 2750 + status = "disabled"; 2751 + }; 2752 + 2753 + dsi1: dsi@ae96000 { 2754 + compatible = "qcom,mdss-dsi-ctrl"; 2755 + reg = <0 0x0ae96000 0 0x400>; 2756 + reg-names = "dsi_ctrl"; 2757 + 2758 + interrupt-parent = <&mdss>; 2759 + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2760 + 2761 + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2762 + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2763 + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2764 + <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2765 + <&dispcc DISP_CC_MDSS_AHB_CLK>, 2766 + <&gcc GCC_DISP_HF_AXI_CLK>; 2767 + clock-names = "byte", 2768 + "byte_intf", 2769 + "pixel", 2770 + "core", 2771 + "iface", 2772 + "bus"; 2773 + 2774 + operating-points-v2 = <&dsi_opp_table>; 2775 + power-domains = <&rpmhpd SC8180X_MMCX>; 2776 + 2777 + phys = <&dsi1_phy>; 2778 + phy-names = "dsi"; 2779 + 2780 + status = "disabled"; 2781 + 2782 + ports { 2783 + #address-cells = <1>; 2784 + #size-cells = <0>; 2785 + 2786 + port@0 { 2787 + reg = <0>; 2788 + dsi1_in: endpoint { 2789 + remote-endpoint = <&dpu_intf2_out>; 2790 + }; 2791 + }; 2792 + 2793 + port@1 { 2794 + reg = <1>; 2795 + dsi1_out: endpoint { 2796 + }; 2797 + }; 2798 + }; 2799 + }; 2800 + 2801 + dsi1_phy: dsi-phy@ae96400 { 2802 + compatible = "qcom,dsi-phy-7nm"; 2803 + reg = <0 0x0ae96400 0 0x200>, 2804 + <0 0x0ae96600 0 0x280>, 2805 + <0 0x0ae96900 0 0x260>; 2806 + reg-names = "dsi_phy", 2807 + "dsi_phy_lane", 2808 + "dsi_pll"; 2809 + 2810 + #clock-cells = <1>; 2811 + #phy-cells = <0>; 2812 + 2813 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2814 + <&rpmhcc RPMH_CXO_CLK>; 2815 + clock-names = "iface", "ref"; 2816 + 2817 + status = "disabled"; 2818 + }; 2819 + 2820 + mdss_dp0: displayport-controller@ae90000 { 2821 + compatible = "qcom,sc8180x-dp"; 2822 + reg = <0 0xae90000 0 0x200>, 2823 + <0 0xae90200 0 0x200>, 2824 + <0 0xae90400 0 0x600>, 2825 + <0 0xae90a00 0 0x400>; 2826 + interrupt-parent = <&mdss>; 2827 + interrupts = <12>; 2828 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2829 + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2830 + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2831 + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2832 + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2833 + clock-names = "core_iface", 2834 + "core_aux", 2835 + "ctrl_link", 2836 + "ctrl_link_iface", 2837 + "stream_pixel"; 2838 + 2839 + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2840 + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2841 + assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; 2842 + 2843 + phys = <&usb_prim_dpphy>; 2844 + phy-names = "dp"; 2845 + 2846 + #sound-dai-cells = <0>; 2847 + 2848 + operating-points-v2 = <&dp0_opp_table>; 2849 + power-domains = <&rpmhpd SC8180X_CX>; 2850 + 2851 + status = "disabled"; 2852 + 2853 + ports { 2854 + #address-cells = <1>; 2855 + #size-cells = <0>; 2856 + 2857 + port@0 { 2858 + reg = <0>; 2859 + dp0_in: endpoint { 2860 + remote-endpoint = <&dpu_intf0_out>; 2861 + }; 2862 + }; 2863 + 2864 + port@1 { 2865 + reg = <1>; 2866 + }; 2867 + }; 2868 + 2869 + dp0_opp_table: opp-table { 2870 + compatible = "operating-points-v2"; 2871 + 2872 + opp-160000000 { 2873 + opp-hz = /bits/ 64 <160000000>; 2874 + required-opps = <&rpmhpd_opp_low_svs>; 2875 + }; 2876 + 2877 + opp-270000000 { 2878 + opp-hz = /bits/ 64 <270000000>; 2879 + required-opps = <&rpmhpd_opp_svs>; 2880 + }; 2881 + 2882 + opp-540000000 { 2883 + opp-hz = /bits/ 64 <540000000>; 2884 + required-opps = <&rpmhpd_opp_svs_l1>; 2885 + }; 2886 + 2887 + opp-810000000 { 2888 + opp-hz = /bits/ 64 <810000000>; 2889 + required-opps = <&rpmhpd_opp_nom>; 2890 + }; 2891 + }; 2892 + }; 2893 + 2894 + mdss_dp1: displayport-controller@ae98000 { 2895 + compatible = "qcom,sc8180x-dp"; 2896 + reg = <0 0xae98000 0 0x200>, 2897 + <0 0xae98200 0 0x200>, 2898 + <0 0xae98400 0 0x600>, 2899 + <0 0xae98a00 0 0x400>; 2900 + interrupt-parent = <&mdss>; 2901 + interrupts = <13>; 2902 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2903 + <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 2904 + <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 2905 + <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 2906 + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 2907 + clock-names = "core_iface", 2908 + "core_aux", 2909 + "ctrl_link", 2910 + "ctrl_link_iface", 2911 + "stream_pixel"; 2912 + 2913 + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 2914 + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 2915 + assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; 2916 + 2917 + phys = <&usb_sec_dpphy>; 2918 + phy-names = "dp"; 2919 + 2920 + #sound-dai-cells = <0>; 2921 + 2922 + operating-points-v2 = <&dp0_opp_table>; 2923 + power-domains = <&rpmhpd SC8180X_CX>; 2924 + 2925 + status = "disabled"; 2926 + 2927 + ports { 2928 + #address-cells = <1>; 2929 + #size-cells = <0>; 2930 + 2931 + port@0 { 2932 + reg = <0>; 2933 + dp1_in: endpoint { 2934 + remote-endpoint = <&dpu_intf4_out>; 2935 + }; 2936 + }; 2937 + 2938 + port@1 { 2939 + reg = <1>; 2940 + }; 2941 + }; 2942 + 2943 + dp1_opp_table: opp-table { 2944 + compatible = "operating-points-v2"; 2945 + 2946 + opp-160000000 { 2947 + opp-hz = /bits/ 64 <160000000>; 2948 + required-opps = <&rpmhpd_opp_low_svs>; 2949 + }; 2950 + 2951 + opp-270000000 { 2952 + opp-hz = /bits/ 64 <270000000>; 2953 + required-opps = <&rpmhpd_opp_svs>; 2954 + }; 2955 + 2956 + opp-540000000 { 2957 + opp-hz = /bits/ 64 <540000000>; 2958 + required-opps = <&rpmhpd_opp_svs_l1>; 2959 + }; 2960 + 2961 + opp-810000000 { 2962 + opp-hz = /bits/ 64 <810000000>; 2963 + required-opps = <&rpmhpd_opp_nom>; 2964 + }; 2965 + }; 2966 + }; 2967 + 2968 + mdss_edp: displayport-controller@ae9a000 { 2969 + compatible = "qcom,sc8180x-edp"; 2970 + reg = <0 0xae9a000 0 0x200>, 2971 + <0 0xae9a200 0 0x200>, 2972 + <0 0xae9a400 0 0x600>, 2973 + <0 0xae9aa00 0 0x400>; 2974 + interrupt-parent = <&mdss>; 2975 + interrupts = <14>; 2976 + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2977 + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 2978 + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 2979 + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 2980 + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 2981 + clock-names = "core_iface", 2982 + "core_aux", 2983 + "ctrl_link", 2984 + "ctrl_link_iface", 2985 + "stream_pixel"; 2986 + 2987 + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 2988 + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 2989 + assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 2990 + 2991 + phys = <&edp_phy>; 2992 + phy-names = "dp"; 2993 + 2994 + #sound-dai-cells = <0>; 2995 + 2996 + operating-points-v2 = <&edp_opp_table>; 2997 + power-domains = <&rpmhpd SC8180X_CX>; 2998 + 2999 + status = "disabled"; 3000 + 3001 + ports { 3002 + #address-cells = <1>; 3003 + #size-cells = <0>; 3004 + 3005 + port@0 { 3006 + reg = <0>; 3007 + edp_in: endpoint { 3008 + remote-endpoint = <&dpu_intf5_out>; 3009 + }; 3010 + }; 3011 + }; 3012 + 3013 + edp_opp_table: opp-table { 3014 + compatible = "operating-points-v2"; 3015 + 3016 + opp-160000000 { 3017 + opp-hz = /bits/ 64 <160000000>; 3018 + required-opps = <&rpmhpd_opp_low_svs>; 3019 + }; 3020 + 3021 + opp-270000000 { 3022 + opp-hz = /bits/ 64 <270000000>; 3023 + required-opps = <&rpmhpd_opp_svs>; 3024 + }; 3025 + 3026 + opp-540000000 { 3027 + opp-hz = /bits/ 64 <540000000>; 3028 + required-opps = <&rpmhpd_opp_svs_l1>; 3029 + }; 3030 + 3031 + opp-810000000 { 3032 + opp-hz = /bits/ 64 <810000000>; 3033 + required-opps = <&rpmhpd_opp_nom>; 3034 + }; 3035 + }; 3036 + }; 3037 + }; 3038 + 3039 + edp_phy: phy@aec2a00 { 3040 + compatible = "qcom,sc8180x-edp-phy"; 3041 + reg = <0 0x0aec2a00 0 0x1c0>, 3042 + <0 0x0aec2200 0 0xa0>, 3043 + <0 0x0aec2600 0 0xa0>, 3044 + <0 0x0aec2000 0 0x19c>; 3045 + 3046 + clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3047 + <&dispcc DISP_CC_MDSS_AHB_CLK>; 3048 + clock-names = "aux", "cfg_ahb"; 3049 + 3050 + power-domains = <&dispcc MDSS_GDSC>; 3051 + 3052 + #clock-cells = <1>; 3053 + #phy-cells = <0>; 3054 + }; 3055 + 3056 + dispcc: clock-controller@af00000 { 3057 + compatible = "qcom,sc8180x-dispcc"; 3058 + reg = <0 0x0af00000 0 0x20000>; 3059 + clocks = <&rpmhcc RPMH_CXO_CLK>, 3060 + <&sleep_clk>, 3061 + <&usb_prim_dpphy 0>, 3062 + <&usb_prim_dpphy 1>, 3063 + <&usb_sec_dpphy 0>, 3064 + <&usb_sec_dpphy 1>, 3065 + <&edp_phy 0>, 3066 + <&edp_phy 1>; 3067 + clock-names = "bi_tcxo", 3068 + "sleep_clk", 3069 + "dp_phy_pll_link_clk", 3070 + "dp_phy_pll_vco_div_clk", 3071 + "dptx1_phy_pll_link_clk", 3072 + "dptx1_phy_pll_vco_div_clk", 3073 + "edp_phy_pll_link_clk", 3074 + "edp_phy_pll_vco_div_clk"; 3075 + power-domains = <&rpmhpd SC8180X_MMCX>; 3076 + #clock-cells = <1>; 3077 + #reset-cells = <1>; 3078 + #power-domain-cells = <1>; 2659 3079 }; 2660 3080 2661 3081 pdc: interrupt-controller@b220000 {