Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20251003-topic-hamoa_gcc_usb4-v2-1-61d27a14ee65@oss.qualcomm.com' into clk-for-6.19
Merge the addition of missing USB4 clocks and resets in the Hamoa global
clock controller binding, to allow sharing them with the DeviceTree
branch.
+119
-4
+58
-4
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
+58
-4
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
···
32
32
- description: PCIe 5 pipe clock
33
33
- description: PCIe 6a pipe clock
34
34
- description: PCIe 6b pipe clock
35
-
- description: USB QMP Phy 0 clock source
36
-
- description: USB QMP Phy 1 clock source
37
-
- description: USB QMP Phy 2 clock source
35
+
- description: USB4_0 QMPPHY clock source
36
+
- description: USB4_1 QMPPHY clock source
37
+
- description: USB4_2 QMPPHY clock source
38
+
- description: USB4_0 PHY DP0 GMUX clock source
39
+
- description: USB4_0 PHY DP1 GMUX clock source
40
+
- description: USB4_0 PHY PCIE PIPEGMUX clock source
41
+
- description: USB4_0 PHY PIPEGMUX clock source
42
+
- description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
43
+
- description: USB4_1 PHY DP0 GMUX 2 clock source
44
+
- description: USB4_1 PHY DP1 GMUX 2 clock source
45
+
- description: USB4_1 PHY PCIE PIPEGMUX clock source
46
+
- description: USB4_1 PHY PIPEGMUX clock source
47
+
- description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
48
+
- description: USB4_2 PHY DP0 GMUX 2 clock source
49
+
- description: USB4_2 PHY DP1 GMUX 2 clock source
50
+
- description: USB4_2 PHY PCIE PIPEGMUX clock source
51
+
- description: USB4_2 PHY PIPEGMUX clock source
52
+
- description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
53
+
- description: USB4_0 PHY RX 0 clock source
54
+
- description: USB4_0 PHY RX 1 clock source
55
+
- description: USB4_1 PHY RX 0 clock source
56
+
- description: USB4_1 PHY RX 1 clock source
57
+
- description: USB4_2 PHY RX 0 clock source
58
+
- description: USB4_2 PHY RX 1 clock source
59
+
- description: USB4_0 PHY PCIE PIPE clock source
60
+
- description: USB4_0 PHY max PIPE clock source
61
+
- description: USB4_1 PHY PCIE PIPE clock source
62
+
- description: USB4_1 PHY max PIPE clock source
63
+
- description: USB4_2 PHY PCIE PIPE clock source
64
+
- description: USB4_2 PHY max PIPE clock source
38
65
39
66
power-domains:
40
67
description:
···
94
67
<&pcie6b_phy>,
95
68
<&usb_1_ss0_qmpphy 0>,
96
69
<&usb_1_ss1_qmpphy 1>,
97
-
<&usb_1_ss2_qmpphy 2>;
70
+
<&usb_1_ss2_qmpphy 2>,
71
+
<&usb4_0_phy_dp0_gmux_clk>,
72
+
<&usb4_0_phy_dp1_gmux_clk>,
73
+
<&usb4_0_phy_pcie_pipegmux_clk>,
74
+
<&usb4_0_phy_pipegmux_clk>,
75
+
<&usb4_0_phy_sys_pcie_pipegmux_clk>,
76
+
<&usb4_1_phy_dp0_gmux_2_clk>,
77
+
<&usb4_1_phy_dp1_gmux_2_clk>,
78
+
<&usb4_1_phy_pcie_pipegmux_clk>,
79
+
<&usb4_1_phy_pipegmux_clk>,
80
+
<&usb4_1_phy_sys_pcie_pipegmux_clk>,
81
+
<&usb4_2_phy_dp0_gmux_2_clk>,
82
+
<&usb4_2_phy_dp1_gmux_2_clk>,
83
+
<&usb4_2_phy_pcie_pipegmux_clk>,
84
+
<&usb4_2_phy_pipegmux_clk>,
85
+
<&usb4_2_phy_sys_pcie_pipegmux_clk>,
86
+
<&usb4_0_phy_rx_0_clk>,
87
+
<&usb4_0_phy_rx_1_clk>,
88
+
<&usb4_1_phy_rx_0_clk>,
89
+
<&usb4_1_phy_rx_1_clk>,
90
+
<&usb4_2_phy_rx_0_clk>,
91
+
<&usb4_2_phy_rx_1_clk>,
92
+
<&usb4_0_phy_pcie_pipe_clk>,
93
+
<&usb4_0_phy_max_pipe_clk>,
94
+
<&usb4_1_phy_pcie_pipe_clk>,
95
+
<&usb4_1_phy_max_pipe_clk>,
96
+
<&usb4_2_phy_pcie_pipe_clk>,
97
+
<&usb4_2_phy_max_pipe_clk>;
98
98
power-domains = <&rpmhpd RPMHPD_CX>;
99
99
#clock-cells = <1>;
100
100
#reset-cells = <1>;
+61
include/dt-bindings/clock/qcom,x1e80100-gcc.h
+61
include/dt-bindings/clock/qcom,x1e80100-gcc.h
···
363
363
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353
364
364
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354
365
365
#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355
366
+
#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 356
367
+
#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 357
368
+
#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 358
369
+
#define GCC_USB4_0_PHY_DP0_CLK_SRC 359
370
+
#define GCC_USB4_0_PHY_DP1_CLK_SRC 360
371
+
#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361
372
+
#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 362
373
+
#define GCC_USB4_0_PHY_RX0_CLK_SRC 363
374
+
#define GCC_USB4_0_PHY_RX1_CLK_SRC 364
375
+
#define GCC_USB4_0_PHY_SYS_CLK_SRC 365
376
+
#define GCC_USB4_1_PHY_DP0_CLK_SRC 366
377
+
#define GCC_USB4_1_PHY_DP1_CLK_SRC 367
378
+
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 368
379
+
#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 369
380
+
#define GCC_USB4_1_PHY_RX0_CLK_SRC 370
381
+
#define GCC_USB4_1_PHY_RX1_CLK_SRC 371
382
+
#define GCC_USB4_1_PHY_SYS_CLK_SRC 372
383
+
#define GCC_USB4_2_PHY_DP0_CLK_SRC 373
384
+
#define GCC_USB4_2_PHY_DP1_CLK_SRC 374
385
+
#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 375
386
+
#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 376
387
+
#define GCC_USB4_2_PHY_RX0_CLK_SRC 377
388
+
#define GCC_USB4_2_PHY_RX1_CLK_SRC 378
389
+
#define GCC_USB4_2_PHY_SYS_CLK_SRC 379
366
390
367
391
/* GCC power domains */
368
392
#define GCC_PCIE_0_TUNNEL_GDSC 0
···
508
484
#define GCC_VIDEO_BCR 87
509
485
#define GCC_VIDEO_AXI0_CLK_ARES 88
510
486
#define GCC_VIDEO_AXI1_CLK_ARES 89
487
+
#define GCC_USB4_0_MISC_USB4_SYS_BCR 90
488
+
#define GCC_USB4_0_MISC_RX_CLK_0_BCR 91
489
+
#define GCC_USB4_0_MISC_RX_CLK_1_BCR 92
490
+
#define GCC_USB4_0_MISC_USB_PIPE_BCR 93
491
+
#define GCC_USB4_0_MISC_PCIE_PIPE_BCR 94
492
+
#define GCC_USB4_0_MISC_TMU_BCR 95
493
+
#define GCC_USB4_0_MISC_SB_IF_BCR 96
494
+
#define GCC_USB4_0_MISC_HIA_MSTR_BCR 97
495
+
#define GCC_USB4_0_MISC_AHB_BCR 98
496
+
#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR 99
497
+
#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR 100
498
+
#define GCC_USB4_1_MISC_USB4_SYS_BCR 101
499
+
#define GCC_USB4_1_MISC_RX_CLK_0_BCR 102
500
+
#define GCC_USB4_1_MISC_RX_CLK_1_BCR 103
501
+
#define GCC_USB4_1_MISC_USB_PIPE_BCR 104
502
+
#define GCC_USB4_1_MISC_PCIE_PIPE_BCR 105
503
+
#define GCC_USB4_1_MISC_TMU_BCR 106
504
+
#define GCC_USB4_1_MISC_SB_IF_BCR 107
505
+
#define GCC_USB4_1_MISC_HIA_MSTR_BCR 108
506
+
#define GCC_USB4_1_MISC_AHB_BCR 109
507
+
#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR 110
508
+
#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR 111
509
+
#define GCC_USB4_2_MISC_USB4_SYS_BCR 112
510
+
#define GCC_USB4_2_MISC_RX_CLK_0_BCR 113
511
+
#define GCC_USB4_2_MISC_RX_CLK_1_BCR 114
512
+
#define GCC_USB4_2_MISC_USB_PIPE_BCR 115
513
+
#define GCC_USB4_2_MISC_PCIE_PIPE_BCR 116
514
+
#define GCC_USB4_2_MISC_TMU_BCR 117
515
+
#define GCC_USB4_2_MISC_SB_IF_BCR 118
516
+
#define GCC_USB4_2_MISC_HIA_MSTR_BCR 119
517
+
#define GCC_USB4_2_MISC_AHB_BCR 120
518
+
#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR 121
519
+
#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR 122
520
+
#define GCC_USB4PHY_PHY_PRIM_BCR 123
521
+
#define GCC_USB4PHY_PHY_SEC_BCR 124
522
+
#define GCC_USB4PHY_PHY_TERT_BCR 125
523
+
511
524
#endif