Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"Pretty much all across the field so with this we should be in
reasonable shape for the upcoming -rc2"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: OCTEON: make get_system_type() thread-safe
MIPS: CPS: Initialize EVA before bringing up VPEs from secondary cores
MIPS: Malta: EVA: Rename 'eva_entry' to 'platform_eva_init'
MIPS: EVA: Add new EVA header
MIPS: scall64-o32: Fix indirect syscall detection
MIPS: syscall: Fix AUDIT value for O32 processes on MIPS64
MIPS: Loongson: Fix COP2 usage for preemptible kernel
MIPS: NL: Fix nlm_xlp_defconfig build error
MIPS: Remove race window in page fault handling
MIPS: Malta: Improve system memory detection for '{e, }memsize' >= 2G
MIPS: Alchemy: Fix db1200 PSC clock enablement
MIPS: BCM47XX: Fix reboot problem on BCM4705/BCM4785
MIPS: Remove duplicated include from numa.c
MIPS: Add common plat_irq_dispatch declaration
MIPS: MSP71xx: remove unused plat_irq_dispatch() argument
MIPS: GIC: Remove useless parens from GICBIS().
MIPS: perf: Mark pmu interupt IRQF_NO_THREAD
+142
-59
+1
-5
arch/mips/alchemy/devboards/db1200.c
+1
-5
arch/mips/alchemy/devboards/db1200.c
···
847
847
pr_warn("DB1200: cant get I2C close to 50MHz\n");
848
848
else
849
849
clk_set_rate(c, pfc);
850
+
clk_prepare_enable(c);
850
851
clk_put(c);
851
852
}
852
853
···
923
922
}
924
923
925
924
/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
926
-
c = clk_get(NULL, "psc1_intclk");
927
-
if (!IS_ERR(c)) {
928
-
clk_prepare_enable(c);
929
-
clk_put(c);
930
-
}
931
925
__raw_writel(PSC_SEL_CLK_SERCLK,
932
926
(void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
933
927
wmb();
+11
-2
arch/mips/bcm47xx/setup.c
+11
-2
arch/mips/bcm47xx/setup.c
···
59
59
switch (bcm47xx_bus_type) {
60
60
#ifdef CONFIG_BCM47XX_SSB
61
61
case BCM47XX_BUS_TYPE_SSB:
62
-
ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 3);
62
+
if (bcm47xx_bus.ssb.chip_id == 0x4785)
63
+
write_c0_diag4(1 << 22);
64
+
ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
65
+
if (bcm47xx_bus.ssb.chip_id == 0x4785) {
66
+
__asm__ __volatile__(
67
+
".set\tmips3\n\t"
68
+
"sync\n\t"
69
+
"wait\n\t"
70
+
".set\tmips0");
71
+
}
63
72
break;
64
73
#endif
65
74
#ifdef CONFIG_BCM47XX_BCMA
66
75
case BCM47XX_BUS_TYPE_BCMA:
67
-
bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 3);
76
+
bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
68
77
break;
69
78
#endif
70
79
}
+13
-6
arch/mips/cavium-octeon/setup.c
+13
-6
arch/mips/cavium-octeon/setup.c
···
263
263
static int octeon_uart;
264
264
265
265
extern asmlinkage void handle_int(void);
266
-
extern asmlinkage void plat_irq_dispatch(void);
267
266
268
267
/**
269
268
* Return non zero if we are currently running in the Octeon simulator
···
457
458
octeon_kill_core(NULL);
458
459
}
459
460
461
+
static char __read_mostly octeon_system_type[80];
462
+
463
+
static int __init init_octeon_system_type(void)
464
+
{
465
+
snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
466
+
cvmx_board_type_to_string(octeon_bootinfo->board_type),
467
+
octeon_model_get_string(read_c0_prid()));
468
+
469
+
return 0;
470
+
}
471
+
early_initcall(init_octeon_system_type);
472
+
460
473
/**
461
474
* Return a string representing the system type
462
475
*
···
476
465
*/
477
466
const char *octeon_board_type_string(void)
478
467
{
479
-
static char name[80];
480
-
sprintf(name, "%s (%s)",
481
-
cvmx_board_type_to_string(octeon_bootinfo->board_type),
482
-
octeon_model_get_string(read_c0_prid()));
483
-
return name;
468
+
return octeon_system_type;
484
469
}
485
470
486
471
const char *get_system_type(void)
+43
arch/mips/include/asm/eva.h
+43
arch/mips/include/asm/eva.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2014, Imagination Technologies Ltd.
7
+
*
8
+
* EVA functions for generic code
9
+
*/
10
+
11
+
#ifndef _ASM_EVA_H
12
+
#define _ASM_EVA_H
13
+
14
+
#include <kernel-entry-init.h>
15
+
16
+
#ifdef __ASSEMBLY__
17
+
18
+
#ifdef CONFIG_EVA
19
+
20
+
/*
21
+
* EVA early init code
22
+
*
23
+
* Platforms must define their own 'platform_eva_init' macro in
24
+
* their kernel-entry-init.h header. This macro usually does the
25
+
* platform specific configuration of the segmentation registers,
26
+
* and it is normally called from assembly code.
27
+
*
28
+
*/
29
+
30
+
.macro eva_init
31
+
platform_eva_init
32
+
.endm
33
+
34
+
#else
35
+
36
+
.macro eva_init
37
+
.endm
38
+
39
+
#endif /* CONFIG_EVA */
40
+
41
+
#endif /* __ASSEMBLY__ */
42
+
43
+
#endif
+1
-1
arch/mips/include/asm/gic.h
+1
-1
arch/mips/include/asm/gic.h
+2
arch/mips/include/asm/irq.h
+2
arch/mips/include/asm/irq.h
+16
-6
arch/mips/include/asm/mach-malta/kernel-entry-init.h
+16
-6
arch/mips/include/asm/mach-malta/kernel-entry-init.h
···
10
10
#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
11
11
#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
12
12
13
+
#include <asm/regdef.h>
14
+
#include <asm/mipsregs.h>
15
+
13
16
/*
14
17
* Prepare segments for EVA boot:
15
18
*
16
19
* This is in case the processor boots in legacy configuration
17
20
* (SI_EVAReset is de-asserted and CONFIG5.K == 0)
18
-
*
19
-
* On entry, t1 is loaded with CP0_CONFIG
20
21
*
21
22
* ========================= Mappings =============================
22
23
* Virtual memory Physical memory Mapping
···
31
30
*
32
31
*
33
32
* Lowmem is expanded to 2GB
33
+
*
34
+
* The following code uses the t0, t1, t2 and ra registers without
35
+
* previously preserving them.
36
+
*
34
37
*/
35
-
.macro eva_entry
38
+
.macro platform_eva_init
39
+
40
+
.set push
41
+
.set reorder
36
42
/*
37
43
* Get Config.K0 value and use it to program
38
44
* the segmentation registers
39
45
*/
46
+
mfc0 t1, CP0_CONFIG
40
47
andi t1, 0x7 /* CCA */
41
48
move t2, t1
42
49
ins t2, t1, 16, 3
···
86
77
mtc0 t0, $16, 5
87
78
sync
88
79
jal mips_ihb
80
+
81
+
.set pop
89
82
.endm
90
83
91
84
.macro kernel_entry_setup
···
106
95
sll t0, t0, 6 /* SC bit */
107
96
bgez t0, 9f
108
97
109
-
eva_entry
98
+
platform_eva_init
110
99
b 0f
111
100
9:
112
101
/* Assume we came from YAMON... */
···
138
127
#ifdef CONFIG_EVA
139
128
sync
140
129
ehb
141
-
mfc0 t1, CP0_CONFIG
142
-
eva_entry
130
+
platform_eva_init
143
131
#endif
144
132
.endm
145
133
-7
arch/mips/include/asm/mach-netlogic/topology.h
-7
arch/mips/include/asm/mach-netlogic/topology.h
···
10
10
11
11
#include <asm/mach-netlogic/multi-node.h>
12
12
13
-
#ifdef CONFIG_SMP
14
-
#define topology_physical_package_id(cpu) cpu_to_node(cpu)
15
-
#define topology_core_id(cpu) (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
16
-
#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu])
17
-
#define topology_core_cpumask(cpu) cpumask_of_node(cpu_to_node(cpu))
18
-
#endif
19
-
20
13
#include <asm-generic/topology.h>
21
14
22
15
#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
+3
-5
arch/mips/include/asm/pgtable.h
+3
-5
arch/mips/include/asm/pgtable.h
···
122
122
} \
123
123
} while(0)
124
124
125
+
extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
126
+
pte_t pteval);
127
+
125
128
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
126
129
127
130
#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
···
148
145
}
149
146
}
150
147
}
151
-
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
152
148
153
149
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
154
150
{
···
185
183
}
186
184
#endif
187
185
}
188
-
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
189
186
190
187
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
191
188
{
···
391
390
392
391
extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
393
392
pte_t pte);
394
-
extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
395
-
pte_t pte);
396
393
397
394
static inline void update_mmu_cache(struct vm_area_struct *vma,
398
395
unsigned long address, pte_t *ptep)
399
396
{
400
397
pte_t pte = *ptep;
401
398
__update_tlb(vma, address, pte);
402
-
__update_cache(vma, address, pte);
403
399
}
404
400
405
401
static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
+5
-3
arch/mips/include/asm/syscall.h
+5
-3
arch/mips/include/asm/syscall.h
···
131
131
{
132
132
int arch = EM_MIPS;
133
133
#ifdef CONFIG_64BIT
134
-
if (!test_thread_flag(TIF_32BIT_REGS))
134
+
if (!test_thread_flag(TIF_32BIT_REGS)) {
135
135
arch |= __AUDIT_ARCH_64BIT;
136
-
if (test_thread_flag(TIF_32BIT_ADDR))
137
-
arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
136
+
/* N32 sets only TIF_32BIT_ADDR */
137
+
if (test_thread_flag(TIF_32BIT_ADDR))
138
+
arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
139
+
}
138
140
#endif
139
141
#if defined(__LITTLE_ENDIAN)
140
142
arch |= __AUDIT_ARCH_LE;
+4
arch/mips/kernel/cps-vec.S
+4
arch/mips/kernel/cps-vec.S
···
13
13
#include <asm/asm-offsets.h>
14
14
#include <asm/asmmacro.h>
15
15
#include <asm/cacheops.h>
16
+
#include <asm/eva.h>
16
17
#include <asm/mipsregs.h>
17
18
#include <asm/mipsmtregs.h>
18
19
#include <asm/pm.h>
···
166
165
*/
167
166
1: jal mips_cps_core_init
168
167
nop
168
+
169
+
/* Do any EVA initialization if necessary */
170
+
eva_init
169
171
170
172
/*
171
173
* Boot any other VPEs within this core that should be online, and
+1
-1
arch/mips/kernel/perf_event_mipsxx.c
+1
-1
arch/mips/kernel/perf_event_mipsxx.c
···
558
558
if (mipspmu.irq >= 0) {
559
559
/* Request my own irq handler. */
560
560
err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
561
-
IRQF_PERCPU | IRQF_NOBALANCING,
561
+
IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD,
562
562
"mips_perf_pmu", NULL);
563
563
if (err) {
564
564
pr_warning("Unable to request IRQ%d for MIPS "
+8
-4
arch/mips/kernel/scall64-o32.S
+8
-4
arch/mips/kernel/scall64-o32.S
···
113
113
move s0, t2 # Save syscall pointer
114
114
move a0, sp
115
115
/*
116
-
* syscall number is in v0 unless we called syscall(__NR_###)
116
+
* absolute syscall number is in v0 unless we called syscall(__NR_###)
117
117
* where the real syscall number is in a0
118
118
* note: NR_syscall is the first O32 syscall but the macro is
119
119
* only defined when compiling with -mabi=32 (CONFIG_32BIT)
120
120
* therefore __NR_O32_Linux is used (4000)
121
121
*/
122
-
addiu a1, v0, __NR_O32_Linux
123
-
bnez v0, 1f /* __NR_syscall at offset 0 */
124
-
lw a1, PT_R4(sp)
122
+
.set push
123
+
.set reorder
124
+
subu t1, v0, __NR_O32_Linux
125
+
move a1, v0
126
+
bnez t1, 1f /* __NR_syscall at offset 0 */
127
+
lw a1, PT_R4(sp) /* Arg1 for __NR_syscall case */
128
+
.set pop
125
129
126
130
1: jal syscall_trace_enter
127
131
+4
-4
arch/mips/loongson/loongson-3/cop2-ex.c
+4
-4
arch/mips/loongson/loongson-3/cop2-ex.c
···
22
22
static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
23
23
void *data)
24
24
{
25
-
int fpu_enabled;
25
+
int fpu_owned;
26
26
int fr = !test_thread_flag(TIF_32BIT_FPREGS);
27
27
28
28
switch (action) {
29
29
case CU2_EXCEPTION:
30
30
preempt_disable();
31
-
fpu_enabled = read_c0_status() & ST0_CU1;
31
+
fpu_owned = __is_fpu_owner();
32
32
if (!fr)
33
33
set_c0_status(ST0_CU1 | ST0_CU2);
34
34
else
···
39
39
KSTK_STATUS(current) |= ST0_FR;
40
40
else
41
41
KSTK_STATUS(current) &= ~ST0_FR;
42
-
/* If FPU is enabled, we needn't init or restore fp */
43
-
if(!fpu_enabled) {
42
+
/* If FPU is owned, we needn't init or restore fp */
43
+
if (!fpu_owned) {
44
44
set_thread_flag(TIF_USEDFPU);
45
45
if (!used_math()) {
46
46
_init_fpu();
-2
arch/mips/loongson/loongson-3/numa.c
-2
arch/mips/loongson/loongson-3/numa.c
+19
-8
arch/mips/mm/cache.c
+19
-8
arch/mips/mm/cache.c
···
119
119
120
120
EXPORT_SYMBOL(__flush_anon_page);
121
121
122
-
void __update_cache(struct vm_area_struct *vma, unsigned long address,
123
-
pte_t pte)
122
+
static void mips_flush_dcache_from_pte(pte_t pteval, unsigned long address)
124
123
{
125
124
struct page *page;
126
-
unsigned long pfn, addr;
127
-
int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc;
125
+
unsigned long pfn = pte_pfn(pteval);
128
126
129
-
pfn = pte_pfn(pte);
130
127
if (unlikely(!pfn_valid(pfn)))
131
128
return;
129
+
132
130
page = pfn_to_page(pfn);
133
131
if (page_mapping(page) && Page_dcache_dirty(page)) {
134
-
addr = (unsigned long) page_address(page);
135
-
if (exec || pages_do_alias(addr, address & PAGE_MASK))
136
-
flush_data_cache_page(addr);
132
+
unsigned long page_addr = (unsigned long) page_address(page);
133
+
134
+
if (!cpu_has_ic_fills_f_dc ||
135
+
pages_do_alias(page_addr, address & PAGE_MASK))
136
+
flush_data_cache_page(page_addr);
137
137
ClearPageDcacheDirty(page);
138
138
}
139
+
}
140
+
141
+
void set_pte_at(struct mm_struct *mm, unsigned long addr,
142
+
pte_t *ptep, pte_t pteval)
143
+
{
144
+
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
145
+
if (pte_present(pteval))
146
+
mips_flush_dcache_from_pte(pteval, addr);
147
+
}
148
+
149
+
set_pte(ptep, pteval);
139
150
}
140
151
141
152
unsigned long _page_cachable_default;
+10
-4
arch/mips/mti-malta/malta-memory.c
+10
-4
arch/mips/mti-malta/malta-memory.c
···
35
35
/* otherwise look in the environment */
36
36
37
37
memsize_str = fw_getenv("memsize");
38
-
if (memsize_str)
39
-
tmp = kstrtol(memsize_str, 0, &memsize);
38
+
if (memsize_str) {
39
+
tmp = kstrtoul(memsize_str, 0, &memsize);
40
+
if (tmp)
41
+
pr_warn("Failed to read the 'memsize' env variable.\n");
42
+
}
40
43
if (eva) {
41
44
/* Look for ememsize for EVA */
42
45
ememsize_str = fw_getenv("ememsize");
43
-
if (ememsize_str)
44
-
tmp = kstrtol(ememsize_str, 0, &ememsize);
46
+
if (ememsize_str) {
47
+
tmp = kstrtoul(ememsize_str, 0, &ememsize);
48
+
if (tmp)
49
+
pr_warn("Failed to read the 'ememsize' env variable.\n");
50
+
}
45
51
}
46
52
if (!memsize && !ememsize) {
47
53
pr_warn("memsize not set in YAMON, set to default (32Mb)\n");