Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rtw-next-2025-11-21-v2' of https://github.com/pkshih/rtw
Ping-Ke Shih says:
==================
rtw-next patches for v6.19
Main changes are about rtw89 USB support, which two USB devices are added
with proper TX status, and other notable items are listed below.
rtl8xxxu:
- fix 40MHz bandwidth connection
rtw89:
- support USB devices RTL8852AU and RTL8852CU
- report TX status from air for USB devices
- resolve racing between processes of TX and TX report
- resolve racing of skb queue of C2H events
- support injected packets with bandwidth and data rate
- more materials for coming RTL8922DE
==================
Link: https://patch.msgid.link/45eed1763a354460acba15a8e69f9e3e@realtek.com
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+2375
-889
+2
-7
drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c
+2
-7
drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c
···
1023
1023
dma_addr_t *mapping;
1024
1024
entry = priv->rx_ring + priv->rx_ring_sz*i;
1025
1025
if (!skb) {
1026
-
dma_free_coherent(&priv->pdev->dev,
1027
-
priv->rx_ring_sz * 32,
1028
-
priv->rx_ring, priv->rx_ring_dma);
1029
1026
wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
1030
1027
return -ENOMEM;
1031
1028
}
···
1034
1037
1035
1038
if (dma_mapping_error(&priv->pdev->dev, *mapping)) {
1036
1039
kfree_skb(skb);
1037
-
dma_free_coherent(&priv->pdev->dev,
1038
-
priv->rx_ring_sz * 32,
1039
-
priv->rx_ring, priv->rx_ring_dma);
1040
+
priv->rx_buf[i] = NULL;
1040
1041
wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
1041
1042
return -ENOMEM;
1042
1043
}
···
1125
1130
1126
1131
ret = rtl8180_init_rx_ring(dev);
1127
1132
if (ret)
1128
-
return ret;
1133
+
goto err_free_rings;
1129
1134
1130
1135
for (i = 0; i < (dev->queues + 1); i++)
1131
1136
if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
+19
-8
drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c
+19
-8
drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c
···
338
338
spin_unlock_irqrestore(&priv->rx_queue.lock, f);
339
339
skb_put(skb, urb->actual_length);
340
340
341
-
if (unlikely(urb->status)) {
342
-
dev_kfree_skb_irq(skb);
343
-
return;
344
-
}
341
+
if (unlikely(urb->status))
342
+
goto free_skb;
345
343
346
344
if (!priv->is_rtl8187b) {
347
-
struct rtl8187_rx_hdr *hdr =
348
-
(typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
345
+
struct rtl8187_rx_hdr *hdr;
346
+
347
+
if (skb->len < sizeof(struct rtl8187_rx_hdr))
348
+
goto free_skb;
349
+
350
+
hdr = (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
349
351
flags = le32_to_cpu(hdr->flags);
350
352
/* As with the RTL8187B below, the AGC is used to calculate
351
353
* signal strength. In this case, the scaling
···
357
355
rx_status.antenna = (hdr->signal >> 7) & 1;
358
356
rx_status.mactime = le64_to_cpu(hdr->mac_time);
359
357
} else {
360
-
struct rtl8187b_rx_hdr *hdr =
361
-
(typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
358
+
struct rtl8187b_rx_hdr *hdr;
359
+
360
+
if (skb->len < sizeof(struct rtl8187b_rx_hdr))
361
+
goto free_skb;
362
+
363
+
hdr = (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
362
364
/* The Realtek datasheet for the RTL8187B shows that the RX
363
365
* header contains the following quantities: signal quality,
364
366
* RSSI, AGC, the received power in dB, and the measured SNR.
···
415
409
skb_unlink(skb, &priv->rx_queue);
416
410
dev_kfree_skb_irq(skb);
417
411
}
412
+
return;
413
+
414
+
free_skb:
415
+
dev_kfree_skb_irq(skb);
416
+
return;
418
417
}
419
418
420
419
static int rtl8187_init_urbs(struct ieee80211_hw *dev)
+79
-1
drivers/net/wireless/realtek/rtl8xxxu/8192c.c
+79
-1
drivers/net/wireless/realtek/rtl8xxxu/8192c.c
···
593
593
return 0;
594
594
}
595
595
596
+
static void rtl8192cu_power_off(struct rtl8xxxu_priv *priv)
597
+
{
598
+
u32 val32;
599
+
u16 val16;
600
+
u8 val8;
601
+
int i;
602
+
603
+
/*
604
+
* Workaround for 8188RU LNA power leakage problem.
605
+
*/
606
+
if (priv->rtl_chip == RTL8188R) {
607
+
val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
608
+
val32 |= BIT(1);
609
+
rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
610
+
}
611
+
612
+
/* _DisableRFAFEAndResetBB */
613
+
rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
614
+
rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_AC, 0xff, 0);
615
+
616
+
rtl8xxxu_write8_set(priv, REG_APSD_CTRL, APSD_CTRL_OFF);
617
+
rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, FPGA0_RF_PARM_CLK_GATE);
618
+
619
+
rtl8xxxu_write8(priv, REG_SYS_FUNC,
620
+
SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_BB_GLB_RSTN);
621
+
rtl8xxxu_write8(priv, REG_SYS_FUNC, SYS_FUNC_USBA | SYS_FUNC_USBD);
622
+
623
+
/* _ResetDigitalProcedure1 */
624
+
if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_DL_READY) {
625
+
rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
626
+
627
+
rtl8xxxu_write8(priv, REG_FWIMR, 0x20);
628
+
629
+
rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
630
+
631
+
for (i = 0; i < 100; i++) {
632
+
val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
633
+
if (!(val16 & SYS_FUNC_CPU_ENABLE))
634
+
break;
635
+
636
+
fsleep(50);
637
+
}
638
+
639
+
if (i == 100) {
640
+
rtl8xxxu_write8(priv, REG_SYS_FUNC + 1,
641
+
(SYS_FUNC_HWPDN | SYS_FUNC_ELDR) >> 8);
642
+
msleep(10);
643
+
}
644
+
}
645
+
646
+
val8 = (SYS_FUNC_HWPDN | SYS_FUNC_ELDR | SYS_FUNC_CPU_ENABLE) >> 8;
647
+
rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
648
+
649
+
/* _DisableGPIO */
650
+
rtl8xxxu_write16(priv, REG_GPIO_PIN_CTRL + 2, 0);
651
+
val32 = rtl8xxxu_read32(priv, REG_GPIO_PIN_CTRL) & 0xffff00ff;
652
+
val32 |= (val32 & 0xff) << 8;
653
+
val32 |= 0x00ff0000;
654
+
rtl8xxxu_write32(priv, REG_GPIO_PIN_CTRL, val32);
655
+
656
+
rtl8xxxu_write8(priv, REG_GPIO_MUXCFG + 3, 0);
657
+
val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG + 2) & 0xff0f;
658
+
val16 |= (val16 & 0xf) << 4;
659
+
val16 |= 0x0780;
660
+
rtl8xxxu_write16(priv, REG_GPIO_MUXCFG + 2, val16);
661
+
662
+
/* _DisableAnalog */
663
+
val8 = 0x23;
664
+
if (priv->vendor_umc && priv->chip_cut == 1)
665
+
val8 |= BIT(3);
666
+
rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
667
+
668
+
val16 = APS_FSMCO_HOST | APS_FSMCO_HW_SUSPEND | APS_FSMCO_PFM_ALDN;
669
+
rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
670
+
671
+
rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
672
+
}
673
+
596
674
static int rtl8192cu_led_brightness_set(struct led_classdev *led_cdev,
597
675
enum led_brightness brightness)
598
676
{
···
696
618
.parse_efuse = rtl8192cu_parse_efuse,
697
619
.load_firmware = rtl8192cu_load_firmware,
698
620
.power_on = rtl8192cu_power_on,
699
-
.power_off = rtl8xxxu_power_off,
621
+
.power_off = rtl8192cu_power_off,
700
622
.read_efuse = rtl8xxxu_read_efuse,
701
623
.reset_8051 = rtl8xxxu_reset_8051,
702
624
.llt_init = rtl8xxxu_init_llt_table,
+114
-1
drivers/net/wireless/realtek/rtl8xxxu/8723a.c
+114
-1
drivers/net/wireless/realtek/rtl8xxxu/8723a.c
···
411
411
return ret;
412
412
}
413
413
414
+
static int rtl8723au_active_to_emu(struct rtl8xxxu_priv *priv)
415
+
{
416
+
u8 val8;
417
+
int count, ret = 0;
418
+
419
+
/* Start of rtl8723AU_card_enable_flow */
420
+
/* Act to Cardemu sequence*/
421
+
/* Turn off RF */
422
+
rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
423
+
424
+
/* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
425
+
val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
426
+
val8 &= ~LEDCFG2_DPDT_SELECT;
427
+
rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
428
+
429
+
/* 0x0005[1] = 1 turn off MAC by HW state machine*/
430
+
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
431
+
val8 |= BIT(1);
432
+
rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
433
+
434
+
for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
435
+
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
436
+
if ((val8 & BIT(1)) == 0)
437
+
break;
438
+
udelay(10);
439
+
}
440
+
441
+
if (!count) {
442
+
dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
443
+
__func__);
444
+
ret = -EBUSY;
445
+
goto exit;
446
+
}
447
+
448
+
/* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
449
+
val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
450
+
val8 |= SYS_ISO_ANALOG_IPS;
451
+
rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
452
+
453
+
/* 0x0020[0] = 0 disable LDOA12 MACRO block*/
454
+
val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
455
+
val8 &= ~LDOA15_ENABLE;
456
+
rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
457
+
458
+
exit:
459
+
return ret;
460
+
}
461
+
462
+
static int rtl8723au_emu_to_disabled(struct rtl8xxxu_priv *priv)
463
+
{
464
+
u8 val8;
465
+
466
+
/* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
467
+
rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
468
+
469
+
/* 0x04[12:11] = 01 enable WL suspend */
470
+
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
471
+
val8 &= ~BIT(4);
472
+
val8 |= BIT(3);
473
+
rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
474
+
475
+
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
476
+
val8 |= BIT(7);
477
+
rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
478
+
479
+
/* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
480
+
val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
481
+
val8 |= BIT(0);
482
+
rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
483
+
484
+
return 0;
485
+
}
486
+
487
+
static void rtl8723au_power_off(struct rtl8xxxu_priv *priv)
488
+
{
489
+
u8 val8;
490
+
u16 val16;
491
+
492
+
rtl8xxxu_flush_fifo(priv);
493
+
494
+
rtl8xxxu_active_to_lps(priv);
495
+
496
+
/* Turn off RF */
497
+
rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
498
+
499
+
/* Reset Firmware if running in RAM */
500
+
if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
501
+
rtl8xxxu_firmware_self_reset(priv);
502
+
503
+
/* Reset MCU */
504
+
val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
505
+
val16 &= ~SYS_FUNC_CPU_ENABLE;
506
+
rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
507
+
508
+
/* Reset MCU ready status */
509
+
rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
510
+
511
+
rtl8723au_active_to_emu(priv);
512
+
rtl8723au_emu_to_disabled(priv);
513
+
514
+
/* Reset MCU IO Wrapper */
515
+
val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
516
+
val8 &= ~BIT(0);
517
+
rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
518
+
519
+
val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
520
+
val8 |= BIT(0);
521
+
rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
522
+
523
+
/* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
524
+
rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
525
+
}
526
+
414
527
#define XTAL1 GENMASK(23, 18)
415
528
#define XTAL0 GENMASK(17, 12)
416
529
···
605
492
.parse_efuse = rtl8723au_parse_efuse,
606
493
.load_firmware = rtl8723au_load_firmware,
607
494
.power_on = rtl8723au_power_on,
608
-
.power_off = rtl8xxxu_power_off,
495
+
.power_off = rtl8723au_power_off,
609
496
.read_efuse = rtl8xxxu_read_efuse,
610
497
.reset_8051 = rtl8xxxu_reset_8051,
611
498
.llt_init = rtl8xxxu_init_llt_table,
+41
-147
drivers/net/wireless/realtek/rtl8xxxu/core.c
+41
-147
drivers/net/wireless/realtek/rtl8xxxu/core.c
···
20
20
#define DRIVER_NAME "rtl8xxxu"
21
21
22
22
int rtl8xxxu_debug;
23
-
static bool rtl8xxxu_ht40_2g;
24
23
static bool rtl8xxxu_dma_aggregation;
25
24
static int rtl8xxxu_dma_agg_timeout = -1;
26
25
static int rtl8xxxu_dma_agg_pages = -1;
···
44
45
45
46
module_param_named(debug, rtl8xxxu_debug, int, 0600);
46
47
MODULE_PARM_DESC(debug, "Set debug mask");
47
-
module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
48
-
MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
49
48
module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
50
49
MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
51
50
module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
···
1249
1252
opmode &= ~BW_OPMODE_20MHZ;
1250
1253
rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1251
1254
rsr &= ~RSR_RSC_BANDWIDTH_40M;
1252
-
if (sec_ch_above)
1255
+
if (!sec_ch_above)
1253
1256
rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1254
1257
else
1255
1258
rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
···
1318
1321
1319
1322
for (i = RF_A; i < priv->rf_paths; i++) {
1320
1323
val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1321
-
if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1322
-
val32 &= ~MODE_AG_CHANNEL_20MHZ;
1323
-
else
1324
+
val32 &= ~MODE_AG_BW_MASK;
1325
+
if (hw->conf.chandef.width != NL80211_CHAN_WIDTH_40)
1324
1326
val32 |= MODE_AG_CHANNEL_20MHZ;
1325
1327
rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1326
1328
}
···
1370
1374
hw->conf.chandef.chan->center_freq) {
1371
1375
sec_ch_above = 1;
1372
1376
channel += 2;
1377
+
subchannel = 2;
1373
1378
} else {
1374
1379
sec_ch_above = 0;
1375
1380
channel -= 2;
1381
+
subchannel = 1;
1376
1382
}
1377
1383
1378
1384
val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
···
3635
3637
rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3636
3638
}
3637
3639
3638
-
static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3639
-
{
3640
-
u8 val8;
3641
-
int count, ret = 0;
3642
-
3643
-
/* Start of rtl8723AU_card_enable_flow */
3644
-
/* Act to Cardemu sequence*/
3645
-
/* Turn off RF */
3646
-
rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3647
-
3648
-
/* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3649
-
val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3650
-
val8 &= ~LEDCFG2_DPDT_SELECT;
3651
-
rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3652
-
3653
-
/* 0x0005[1] = 1 turn off MAC by HW state machine*/
3654
-
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3655
-
val8 |= BIT(1);
3656
-
rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3657
-
3658
-
for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3659
-
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3660
-
if ((val8 & BIT(1)) == 0)
3661
-
break;
3662
-
udelay(10);
3663
-
}
3664
-
3665
-
if (!count) {
3666
-
dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3667
-
__func__);
3668
-
ret = -EBUSY;
3669
-
goto exit;
3670
-
}
3671
-
3672
-
/* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3673
-
val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3674
-
val8 |= SYS_ISO_ANALOG_IPS;
3675
-
rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3676
-
3677
-
/* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3678
-
val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3679
-
val8 &= ~LDOA15_ENABLE;
3680
-
rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3681
-
3682
-
exit:
3683
-
return ret;
3684
-
}
3685
-
3686
3640
int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3687
3641
{
3688
3642
u8 val8;
···
3709
3759
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3710
3760
val8 &= ~(BIT(3) | BIT(4));
3711
3761
rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3712
-
}
3713
-
3714
-
static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3715
-
{
3716
-
u8 val8;
3717
-
3718
-
/* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3719
-
rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3720
-
3721
-
/* 0x04[12:11] = 01 enable WL suspend */
3722
-
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3723
-
val8 &= ~BIT(4);
3724
-
val8 |= BIT(3);
3725
-
rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3726
-
3727
-
val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3728
-
val8 |= BIT(7);
3729
-
rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3730
-
3731
-
/* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3732
-
val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3733
-
val8 |= BIT(0);
3734
-
rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3735
-
3736
-
return 0;
3737
3762
}
3738
3763
3739
3764
int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
···
3786
3861
val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3787
3862
val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3788
3863
rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3789
-
}
3790
-
3791
-
void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3792
-
{
3793
-
u8 val8;
3794
-
u16 val16;
3795
-
u32 val32;
3796
-
3797
-
/*
3798
-
* Workaround for 8188RU LNA power leakage problem.
3799
-
*/
3800
-
if (priv->rtl_chip == RTL8188R) {
3801
-
val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3802
-
val32 |= BIT(1);
3803
-
rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3804
-
}
3805
-
3806
-
rtl8xxxu_flush_fifo(priv);
3807
-
3808
-
rtl8xxxu_active_to_lps(priv);
3809
-
3810
-
/* Turn off RF */
3811
-
rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3812
-
3813
-
/* Reset Firmware if running in RAM */
3814
-
if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3815
-
rtl8xxxu_firmware_self_reset(priv);
3816
-
3817
-
/* Reset MCU */
3818
-
val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3819
-
val16 &= ~SYS_FUNC_CPU_ENABLE;
3820
-
rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3821
-
3822
-
/* Reset MCU ready status */
3823
-
rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3824
-
3825
-
rtl8xxxu_active_to_emu(priv);
3826
-
rtl8xxxu_emu_to_disabled(priv);
3827
-
3828
-
/* Reset MCU IO Wrapper */
3829
-
val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3830
-
val8 &= ~BIT(0);
3831
-
rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3832
-
3833
-
val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3834
-
val8 |= BIT(0);
3835
-
rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3836
-
3837
-
/* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
3838
-
rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3839
3864
}
3840
3865
3841
3866
void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
···
4893
5018
sgi = 1;
4894
5019
4895
5020
highest_rate = fls(ramask) - 1;
4896
-
if (rtl8xxxu_ht40_2g &&
4897
-
(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
5021
+
if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
4898
5022
bw = RATE_INFO_BW_40;
4899
5023
else
4900
5024
bw = RATE_INFO_BW_20;
···
5219
5345
tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5220
5346
}
5221
5347
5222
-
if (ieee80211_is_data_qos(hdr->frame_control))
5348
+
if (ieee80211_is_data_qos(hdr->frame_control)) {
5223
5349
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5350
+
5351
+
if (conf_is_ht40(&hw->conf)) {
5352
+
tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW);
5353
+
5354
+
if (conf_is_ht40_minus(&hw->conf))
5355
+
tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER);
5356
+
else
5357
+
tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER);
5358
+
}
5359
+
}
5224
5360
5225
5361
if (short_preamble)
5226
5362
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
···
5697
5813
!rtl8xxxu_is_sta_sta(priv) &&
5698
5814
(rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) ||
5699
5815
rtl8xxxu_is_packet_match_bssid(priv, hdr, 1));
5700
-
u8 pwdb_max = 0;
5816
+
u8 pwdb_max = 0, rxsc;
5701
5817
int rx_path;
5702
5818
5703
5819
if (parse_cfo) {
···
5712
5828
pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]);
5713
5829
5714
5830
rx_status->signal = pwdb_max - 110;
5831
+
5832
+
if (rxmcs >= DESC_RATE_6M && rxmcs <= DESC_RATE_54M)
5833
+
rxsc = phy_stats1->l_rxsc;
5834
+
else
5835
+
rxsc = phy_stats1->ht_rxsc;
5836
+
5837
+
if (phy_stats1->rf_mode == 0 || rxsc == 1 || rxsc == 2)
5838
+
rx_status->bw = RATE_INFO_BW_20;
5839
+
else
5840
+
rx_status->bw = RATE_INFO_BW_40;
5715
5841
}
5716
5842
5717
5843
static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv,
···
6348
6454
rtl8xxxu_rx_update_rssi(priv,
6349
6455
rx_status,
6350
6456
hdr);
6457
+
} else {
6458
+
rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
6351
6459
}
6352
6460
6353
6461
rx_status->mactime = rx_desc->tsfl;
···
6456
6560
rtl8xxxu_rx_update_rssi(priv,
6457
6561
rx_status,
6458
6562
hdr);
6563
+
} else {
6564
+
rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
6459
6565
}
6460
6566
6461
6567
rx_status->mactime = rx_desc->tsfl;
···
7804
7906
goto err_set_intfdata;
7805
7907
}
7806
7908
7909
+
if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE)
7910
+
rtl8xxxu_dump_efuse(priv);
7911
+
7807
7912
ret = priv->fops->parse_efuse(priv);
7808
7913
if (ret) {
7809
7914
dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7810
7915
goto err_set_intfdata;
7811
7916
}
7812
-
7813
-
if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE)
7814
-
rtl8xxxu_dump_efuse(priv);
7815
7917
7816
7918
rtl8xxxu_print_chipinfo(priv);
7817
7919
···
7847
7949
sband->ht_cap.ht_supported = true;
7848
7950
sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7849
7951
sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7850
-
sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7952
+
sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
7953
+
IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7851
7954
memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7852
7955
sband->ht_cap.mcs.rx_mask[0] = 0xff;
7853
7956
sband->ht_cap.mcs.rx_mask[4] = 0x01;
···
7857
7958
sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7858
7959
}
7859
7960
sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7860
-
/*
7861
-
* Some APs will negotiate HT20_40 in a noisy environment leading
7862
-
* to miserable performance. Rather than defaulting to this, only
7863
-
* enable it if explicitly requested at module load time.
7864
-
*/
7865
-
if (rtl8xxxu_ht40_2g) {
7866
-
dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7867
-
sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7868
-
}
7961
+
7869
7962
hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
7870
7963
7871
7964
hw->wiphy->rts_threshold = 2347;
···
8026
8135
.driver_info = (unsigned long)&rtl8192fu_fops},
8027
8136
/* TP-Link TL-WN823N V2 */
8028
8137
{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0135, 0xff, 0xff, 0xff),
8138
+
.driver_info = (unsigned long)&rtl8192fu_fops},
8139
+
/* D-Link AN3U rev. A1 */
8140
+
{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3328, 0xff, 0xff, 0xff),
8029
8141
.driver_info = (unsigned long)&rtl8192fu_fops},
8030
8142
#ifdef CONFIG_RTL8XXXU_UNTESTED
8031
8143
/* Still supported by rtlwifi */
+1
drivers/net/wireless/realtek/rtl8xxxu/regs.h
+1
drivers/net/wireless/realtek/rtl8xxxu/regs.h
-1
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
-1
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
···
2078
2078
const struct rtl8xxxu_reg32val *array);
2079
2079
int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name);
2080
2080
void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv);
2081
-
void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv);
2082
2081
void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor);
2083
2082
void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor);
2084
2083
void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv);
+1
-1
drivers/net/wireless/realtek/rtlwifi/base.c
+1
-1
drivers/net/wireless/realtek/rtlwifi/base.c
+1
-1
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.c
+1
-1
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.c
+7
-1
drivers/net/wireless/realtek/rtw88/bf.c
+7
-1
drivers/net/wireless/realtek/rtw88/bf.c
···
124
124
void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
125
125
enum rtw_trx_desc_rate rate)
126
126
{
127
+
u8 csi_rsc = CSI_RSC_FOLLOW_RX_PACKET_BW;
127
128
u32 psf_ctl = 0;
128
-
u8 csi_rsc = 0x1;
129
+
130
+
if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
131
+
csi_rsc = CSI_RSC_PRIMARY_20M_BW;
129
132
130
133
psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
131
134
BIT_WMAC_USE_NDPARATE |
···
389
386
390
387
csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE;
391
388
cur_rrsr = rtw_read16(rtwdev, REG_RRSR);
389
+
390
+
if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
391
+
csi_cfg |= BIT_CSI_FORCE_RATE;
392
392
393
393
if (rssi >= 40) {
394
394
if (cur_rate != DESC_RATE54M) {
+7
drivers/net/wireless/realtek/rtw88/bf.h
+7
drivers/net/wireless/realtek/rtw88/bf.h
···
33
33
#define BIT_SHIFT_R_MU_RL 12
34
34
#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4
35
35
#define BIT_SHIFT_CSI_RATE 24
36
+
#define BIT_CSI_FORCE_RATE BIT(15)
36
37
37
38
#define BIT_MASK_R_MU_RL (R_MU_RL << BIT_SHIFT_R_MU_RL)
38
39
#define BIT_MASK_R_MU_TABLE_VALID 0x3f
···
48
47
#define RTW_NDP_RX_STANDBY_TIME 0x70
49
48
#define RTW_SND_CTRL_REMOVE 0x98
50
49
#define RTW_SND_CTRL_SOUNDING 0x9B
50
+
51
+
enum csi_rsc {
52
+
CSI_RSC_PRIMARY_20M_BW = 0,
53
+
CSI_RSC_FOLLOW_RX_PACKET_BW = 1,
54
+
CSI_RSC_DUPLICATE_MODE = 2,
55
+
};
51
56
52
57
enum csi_seg_len {
53
58
HAL_CSI_SEG_4K = 0,
+2
drivers/net/wireless/realtek/rtw88/rtw8822bu.c
+2
drivers/net/wireless/realtek/rtw88/rtw8822bu.c
···
79
79
.driver_info = (kernel_ulong_t)&(rtw8822b_hw_spec) }, /* D-Link DWA-T185 rev. A1 */
80
80
{ USB_DEVICE_AND_INTERFACE_INFO(0x0411, 0x03d1, 0xff, 0xff, 0xff),
81
81
.driver_info = (kernel_ulong_t)&(rtw8822b_hw_spec) }, /* BUFFALO WI-U2-866DM */
82
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0411, 0x03d0, 0xff, 0xff, 0xff),
83
+
.driver_info = (kernel_ulong_t)&(rtw8822b_hw_spec) }, /* BUFFALO WI-U3-866DHP */
82
84
{},
83
85
};
84
86
MODULE_DEVICE_TABLE(usb, rtw_8822bu_id_table);
+2
drivers/net/wireless/realtek/rtw88/rtw8822cu.c
+2
drivers/net/wireless/realtek/rtw88/rtw8822cu.c
···
21
21
.driver_info = (kernel_ulong_t)&(rtw8822c_hw_spec) },
22
22
{ USB_DEVICE_AND_INTERFACE_INFO(0x13b1, 0x0043, 0xff, 0xff, 0xff),
23
23
.driver_info = (kernel_ulong_t)&(rtw8822c_hw_spec) }, /* Alpha - Alpha */
24
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3329, 0xff, 0xff, 0xff),
25
+
.driver_info = (kernel_ulong_t)&(rtw8822c_hw_spec) }, /* D-Link AC13U rev. A1 */
24
26
{},
25
27
};
26
28
MODULE_DEVICE_TABLE(usb, rtw_8822cu_id_table);
+2
-1
drivers/net/wireless/realtek/rtw88/usb.c
+2
-1
drivers/net/wireless/realtek/rtw88/usb.c
···
965
965
struct sk_buff *rx_skb;
966
966
int i;
967
967
968
-
rtwusb->rxwq = alloc_workqueue("rtw88_usb: rx wq", WQ_BH, 0);
968
+
rtwusb->rxwq = alloc_workqueue("rtw88_usb: rx wq", WQ_BH | WQ_UNBOUND,
969
+
0);
969
970
if (!rtwusb->rxwq) {
970
971
rtw_err(rtwdev, "failed to create RX work queue\n");
971
972
return -ENOMEM;
+22
drivers/net/wireless/realtek/rtw89/Kconfig
+22
drivers/net/wireless/realtek/rtw89/Kconfig
···
74
74
75
75
802.11ax PCIe wireless network (Wi-Fi 6) adapter
76
76
77
+
config RTW89_8852AU
78
+
tristate "Realtek 8852AU USB wireless network (Wi-Fi 6) adapter"
79
+
depends on USB
80
+
select RTW89_CORE
81
+
select RTW89_USB
82
+
select RTW89_8852A
83
+
help
84
+
Select this option will enable support for 8852AU chipset
85
+
86
+
802.11ax USB wireless network (Wi-Fi 6) adapter
87
+
77
88
config RTW89_8852BE
78
89
tristate "Realtek 8852BE PCI wireless network (Wi-Fi 6) adapter"
79
90
depends on PCI
···
131
120
Select this option will enable support for 8852CE chipset
132
121
133
122
802.11ax PCIe wireless network (Wi-Fi 6E) adapter
123
+
124
+
config RTW89_8852CU
125
+
tristate "Realtek 8852CU USB wireless network (Wi-Fi 6E) adapter"
126
+
depends on USB
127
+
select RTW89_CORE
128
+
select RTW89_USB
129
+
select RTW89_8852C
130
+
help
131
+
Select this option will enable support for 8852CU chipset
132
+
133
+
802.11ax USB wireless network (Wi-Fi 6E) adapter
134
134
135
135
config RTW89_8922AE
136
136
tristate "Realtek 8922AE/8922AE-VS PCI wireless network (Wi-Fi 7) adapter"
+6
drivers/net/wireless/realtek/rtw89/Makefile
+6
drivers/net/wireless/realtek/rtw89/Makefile
···
43
43
obj-$(CONFIG_RTW89_8852AE) += rtw89_8852ae.o
44
44
rtw89_8852ae-objs := rtw8852ae.o
45
45
46
+
obj-$(CONFIG_RTW89_8852AU) += rtw89_8852au.o
47
+
rtw89_8852au-objs := rtw8852au.o
48
+
46
49
obj-$(CONFIG_RTW89_8852B_COMMON) += rtw89_8852b_common.o
47
50
rtw89_8852b_common-objs := rtw8852b_common.o
48
51
···
77
74
78
75
obj-$(CONFIG_RTW89_8852CE) += rtw89_8852ce.o
79
76
rtw89_8852ce-objs := rtw8852ce.o
77
+
78
+
obj-$(CONFIG_RTW89_8852CU) += rtw89_8852cu.o
79
+
rtw89_8852cu-objs := rtw8852cu.o
80
80
81
81
obj-$(CONFIG_RTW89_8922A) += rtw89_8922a.o
82
82
rtw89_8922a-objs := rtw8922a.o \
+90
-75
drivers/net/wireless/realtek/rtw89/cam.c
+90
-75
drivers/net/wireless/realtek/rtw89/cam.c
···
236
236
if (ret)
237
237
rtw89_err(rtwdev,
238
238
"failed to update dctl cam del key: %d\n", ret);
239
-
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
239
+
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
240
+
RTW89_ROLE_INFO_CHANGE);
240
241
if (ret)
241
242
rtw89_err(rtwdev, "failed to update cam del key: %d\n", ret);
242
243
}
···
277
276
ret);
278
277
return ret;
279
278
}
280
-
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
279
+
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
280
+
RTW89_ROLE_INFO_CHANGE);
281
281
if (ret) {
282
282
rtw89_err(rtwdev, "failed to update addr cam sec entry: %d\n",
283
283
ret);
···
762
760
763
761
int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev,
764
762
struct rtw89_vif_link *rtwvif_link,
765
-
struct rtw89_sta_link *rtwsta_link, u8 *cmd)
763
+
struct rtw89_sta_link *rtwsta_link,
764
+
struct rtw89_h2c_addr_cam_v0 *h2c)
766
765
{
767
766
struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link,
768
767
rtwsta_link);
···
783
780
784
781
rcu_read_unlock();
785
782
786
-
FWCMD_SET_ADDR_BSSID_IDX(cmd, bssid_cam->bssid_cam_idx);
787
-
FWCMD_SET_ADDR_BSSID_OFFSET(cmd, bssid_cam->offset);
788
-
FWCMD_SET_ADDR_BSSID_LEN(cmd, bssid_cam->len);
789
-
FWCMD_SET_ADDR_BSSID_VALID(cmd, bssid_cam->valid);
790
-
FWCMD_SET_ADDR_BSSID_MASK(cmd, bss_mask);
791
-
FWCMD_SET_ADDR_BSSID_BB_SEL(cmd, bssid_cam->phy_idx);
792
-
FWCMD_SET_ADDR_BSSID_BSS_COLOR(cmd, bss_color);
793
-
794
-
FWCMD_SET_ADDR_BSSID_BSSID0(cmd, bssid_cam->bssid[0]);
795
-
FWCMD_SET_ADDR_BSSID_BSSID1(cmd, bssid_cam->bssid[1]);
796
-
FWCMD_SET_ADDR_BSSID_BSSID2(cmd, bssid_cam->bssid[2]);
797
-
FWCMD_SET_ADDR_BSSID_BSSID3(cmd, bssid_cam->bssid[3]);
798
-
FWCMD_SET_ADDR_BSSID_BSSID4(cmd, bssid_cam->bssid[4]);
799
-
FWCMD_SET_ADDR_BSSID_BSSID5(cmd, bssid_cam->bssid[5]);
783
+
h2c->w12 = le32_encode_bits(bssid_cam->bssid_cam_idx, ADDR_CAM_W12_BSSID_IDX) |
784
+
le32_encode_bits(bssid_cam->offset, ADDR_CAM_W12_BSSID_OFFSET) |
785
+
le32_encode_bits(bssid_cam->len, ADDR_CAM_W12_BSSID_LEN);
786
+
h2c->w13 = le32_encode_bits(bssid_cam->valid, ADDR_CAM_W13_BSSID_VALID) |
787
+
le32_encode_bits(bss_mask, ADDR_CAM_W13_BSSID_MASK) |
788
+
le32_encode_bits(bssid_cam->phy_idx, ADDR_CAM_W13_BSSID_BB_SEL) |
789
+
le32_encode_bits(bss_color, ADDR_CAM_W13_BSSID_BSS_COLOR) |
790
+
le32_encode_bits(bssid_cam->bssid[0], ADDR_CAM_W13_BSSID_BSSID0) |
791
+
le32_encode_bits(bssid_cam->bssid[1], ADDR_CAM_W13_BSSID_BSSID1);
792
+
h2c->w14 = le32_encode_bits(bssid_cam->bssid[2], ADDR_CAM_W14_BSSID_BSSID2) |
793
+
le32_encode_bits(bssid_cam->bssid[3], ADDR_CAM_W14_BSSID_BSSID3) |
794
+
le32_encode_bits(bssid_cam->bssid[4], ADDR_CAM_W14_BSSID_BSSID4) |
795
+
le32_encode_bits(bssid_cam->bssid[5], ADDR_CAM_W14_BSSID_BSSID5);
800
796
801
797
return 0;
802
798
}
···
815
813
struct rtw89_vif_link *rtwvif_link,
816
814
struct rtw89_sta_link *rtwsta_link,
817
815
const u8 *scan_mac_addr,
818
-
u8 *cmd)
816
+
struct rtw89_h2c_addr_cam_v0 *h2c)
819
817
{
820
818
struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
821
819
struct rtw89_addr_cam_entry *addr_cam =
822
820
rtw89_get_addr_cam_of(rtwvif_link, rtwsta_link);
823
821
struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link);
822
+
const struct rtw89_chip_info *chip = rtwdev->chip;
824
823
struct ieee80211_link_sta *link_sta;
825
824
const u8 *sma = scan_mac_addr ? scan_mac_addr : rtwvif_link->mac_addr;
826
825
u8 sma_hash, tma_hash, addr_msk_start;
826
+
u8 ver = chip->addrcam_ver;
827
827
u8 sma_start = 0;
828
828
u8 tma_start = 0;
829
829
const u8 *tma;
830
+
u8 mac_id;
830
831
831
832
rcu_read_lock();
832
833
···
850
845
sma_hash = rtw89_cam_addr_hash(sma_start, sma);
851
846
tma_hash = rtw89_cam_addr_hash(tma_start, tma);
852
847
853
-
FWCMD_SET_ADDR_IDX(cmd, addr_cam->addr_cam_idx);
854
-
FWCMD_SET_ADDR_OFFSET(cmd, addr_cam->offset);
855
-
FWCMD_SET_ADDR_LEN(cmd, addr_cam->len);
848
+
mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
856
849
857
-
FWCMD_SET_ADDR_VALID(cmd, addr_cam->valid);
858
-
FWCMD_SET_ADDR_NET_TYPE(cmd, rtwvif_link->net_type);
859
-
FWCMD_SET_ADDR_BCN_HIT_COND(cmd, rtwvif_link->bcn_hit_cond);
860
-
FWCMD_SET_ADDR_HIT_RULE(cmd, rtwvif_link->hit_rule);
861
-
FWCMD_SET_ADDR_BB_SEL(cmd, rtwvif_link->phy_idx);
862
-
FWCMD_SET_ADDR_ADDR_MASK(cmd, addr_cam->addr_mask);
863
-
FWCMD_SET_ADDR_MASK_SEL(cmd, addr_cam->mask_sel);
864
-
FWCMD_SET_ADDR_SMA_HASH(cmd, sma_hash);
865
-
FWCMD_SET_ADDR_TMA_HASH(cmd, tma_hash);
850
+
if (ver == 0)
851
+
h2c->w1 = le32_encode_bits(addr_cam->addr_cam_idx, ADDR_CAM_W1_IDX) |
852
+
le32_encode_bits(addr_cam->offset, ADDR_CAM_W1_OFFSET) |
853
+
le32_encode_bits(addr_cam->len, ADDR_CAM_W1_LEN);
854
+
else
855
+
h2c->w1 = le32_encode_bits(addr_cam->addr_cam_idx, ADDR_CAM_W1_V1_IDX) |
856
+
le32_encode_bits(addr_cam->offset, ADDR_CAM_W1_V1_OFFSET) |
857
+
le32_encode_bits(addr_cam->len, ADDR_CAM_W1_V1_LEN);
866
858
867
-
FWCMD_SET_ADDR_BSSID_CAM_IDX(cmd, addr_cam->bssid_cam_idx);
859
+
h2c->w2 = le32_encode_bits(addr_cam->valid, ADDR_CAM_W2_VALID) |
860
+
le32_encode_bits(rtwvif_link->net_type, ADDR_CAM_W2_NET_TYPE) |
861
+
le32_encode_bits(rtwvif_link->bcn_hit_cond, ADDR_CAM_W2_BCN_HIT_COND) |
862
+
le32_encode_bits(rtwvif_link->hit_rule, ADDR_CAM_W2_HIT_RULE) |
863
+
le32_encode_bits(rtwvif_link->phy_idx, ADDR_CAM_W2_BB_SEL) |
864
+
le32_encode_bits(addr_cam->addr_mask, ADDR_CAM_W2_ADDR_MASK) |
865
+
le32_encode_bits(addr_cam->mask_sel, ADDR_CAM_W2_MASK_SEL) |
866
+
le32_encode_bits(sma_hash, ADDR_CAM_W2_SMA_HASH) |
867
+
le32_encode_bits(tma_hash, ADDR_CAM_W2_TMA_HASH);
868
+
h2c->w3 = le32_encode_bits(addr_cam->bssid_cam_idx, ADDR_CAM_W3_BSSID_CAM_IDX);
869
+
h2c->w4 = le32_encode_bits(sma[0], ADDR_CAM_W4_SMA0) |
870
+
le32_encode_bits(sma[1], ADDR_CAM_W4_SMA1) |
871
+
le32_encode_bits(sma[2], ADDR_CAM_W4_SMA2) |
872
+
le32_encode_bits(sma[3], ADDR_CAM_W4_SMA3);
873
+
h2c->w5 = le32_encode_bits(sma[4], ADDR_CAM_W5_SMA4) |
874
+
le32_encode_bits(sma[5], ADDR_CAM_W5_SMA5) |
875
+
le32_encode_bits(tma[0], ADDR_CAM_W5_TMA0) |
876
+
le32_encode_bits(tma[1], ADDR_CAM_W5_TMA1);
877
+
h2c->w6 = le32_encode_bits(tma[2], ADDR_CAM_W6_TMA2) |
878
+
le32_encode_bits(tma[3], ADDR_CAM_W6_TMA3) |
879
+
le32_encode_bits(tma[4], ADDR_CAM_W6_TMA4) |
880
+
le32_encode_bits(tma[5], ADDR_CAM_W6_TMA5);
881
+
if (ver == 0)
882
+
h2c->w8 = le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_PORT_INT) |
883
+
le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_TSF_SYNC) |
884
+
le32_encode_bits(rtwvif_link->trigger, ADDR_CAM_W8_TF_TRS) |
885
+
le32_encode_bits(rtwvif_link->lsig_txop, ADDR_CAM_W8_LSIG_TXOP) |
886
+
le32_encode_bits(rtwvif_link->tgt_ind, ADDR_CAM_W8_TGT_IND) |
887
+
le32_encode_bits(rtwvif_link->frm_tgt_ind, ADDR_CAM_W8_FRM_TGT_IND) |
888
+
le32_encode_bits(mac_id, ADDR_CAM_W8_MACID);
889
+
else
890
+
h2c->w8 = le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_V1_PORT_INT) |
891
+
le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_V1_TSF_SYNC) |
892
+
le32_encode_bits(rtwvif_link->trigger, ADDR_CAM_W8_V1_TF_TRS) |
893
+
le32_encode_bits(rtwvif_link->lsig_txop, ADDR_CAM_W8_V1_LSIG_TXOP) |
894
+
le32_encode_bits(mac_id, ADDR_CAM_W8_V1_MACID);
868
895
869
-
FWCMD_SET_ADDR_SMA0(cmd, sma[0]);
870
-
FWCMD_SET_ADDR_SMA1(cmd, sma[1]);
871
-
FWCMD_SET_ADDR_SMA2(cmd, sma[2]);
872
-
FWCMD_SET_ADDR_SMA3(cmd, sma[3]);
873
-
FWCMD_SET_ADDR_SMA4(cmd, sma[4]);
874
-
FWCMD_SET_ADDR_SMA5(cmd, sma[5]);
875
-
876
-
FWCMD_SET_ADDR_TMA0(cmd, tma[0]);
877
-
FWCMD_SET_ADDR_TMA1(cmd, tma[1]);
878
-
FWCMD_SET_ADDR_TMA2(cmd, tma[2]);
879
-
FWCMD_SET_ADDR_TMA3(cmd, tma[3]);
880
-
FWCMD_SET_ADDR_TMA4(cmd, tma[4]);
881
-
FWCMD_SET_ADDR_TMA5(cmd, tma[5]);
882
-
883
-
FWCMD_SET_ADDR_PORT_INT(cmd, rtwvif_link->port);
884
-
FWCMD_SET_ADDR_TSF_SYNC(cmd, rtwvif_link->port);
885
-
FWCMD_SET_ADDR_TF_TRS(cmd, rtwvif_link->trigger);
886
-
FWCMD_SET_ADDR_LSIG_TXOP(cmd, rtwvif_link->lsig_txop);
887
-
FWCMD_SET_ADDR_TGT_IND(cmd, rtwvif_link->tgt_ind);
888
-
FWCMD_SET_ADDR_FRM_TGT_IND(cmd, rtwvif_link->frm_tgt_ind);
889
-
FWCMD_SET_ADDR_MACID(cmd, rtwsta_link ? rtwsta_link->mac_id :
890
-
rtwvif_link->mac_id);
891
896
if (rtwvif_link->net_type == RTW89_NET_TYPE_INFRA)
892
-
FWCMD_SET_ADDR_AID12(cmd, vif->cfg.aid & 0xfff);
897
+
h2c->w9 = le32_encode_bits(vif->cfg.aid & 0xfff, ADDR_CAM_W9_AID12);
893
898
else if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE)
894
-
FWCMD_SET_ADDR_AID12(cmd, sta ? sta->aid & 0xfff : 0);
895
-
FWCMD_SET_ADDR_WOL_PATTERN(cmd, rtwvif_link->wowlan_pattern);
896
-
FWCMD_SET_ADDR_WOL_UC(cmd, rtwvif_link->wowlan_uc);
897
-
FWCMD_SET_ADDR_WOL_MAGIC(cmd, rtwvif_link->wowlan_magic);
898
-
FWCMD_SET_ADDR_WAPI(cmd, addr_cam->wapi);
899
-
FWCMD_SET_ADDR_SEC_ENT_MODE(cmd, addr_cam->sec_ent_mode);
900
-
FWCMD_SET_ADDR_SEC_ENT0_KEYID(cmd, addr_cam->sec_ent_keyid[0]);
901
-
FWCMD_SET_ADDR_SEC_ENT1_KEYID(cmd, addr_cam->sec_ent_keyid[1]);
902
-
FWCMD_SET_ADDR_SEC_ENT2_KEYID(cmd, addr_cam->sec_ent_keyid[2]);
903
-
FWCMD_SET_ADDR_SEC_ENT3_KEYID(cmd, addr_cam->sec_ent_keyid[3]);
904
-
FWCMD_SET_ADDR_SEC_ENT4_KEYID(cmd, addr_cam->sec_ent_keyid[4]);
905
-
FWCMD_SET_ADDR_SEC_ENT5_KEYID(cmd, addr_cam->sec_ent_keyid[5]);
906
-
FWCMD_SET_ADDR_SEC_ENT6_KEYID(cmd, addr_cam->sec_ent_keyid[6]);
899
+
h2c->w9 = le32_encode_bits(sta ? sta->aid & 0xfff : 0, ADDR_CAM_W9_AID12);
907
900
908
-
FWCMD_SET_ADDR_SEC_ENT_VALID(cmd, addr_cam->sec_cam_map[0] & 0xff);
909
-
FWCMD_SET_ADDR_SEC_ENT0(cmd, addr_cam->sec_ent[0]);
910
-
FWCMD_SET_ADDR_SEC_ENT1(cmd, addr_cam->sec_ent[1]);
911
-
FWCMD_SET_ADDR_SEC_ENT2(cmd, addr_cam->sec_ent[2]);
912
-
FWCMD_SET_ADDR_SEC_ENT3(cmd, addr_cam->sec_ent[3]);
913
-
FWCMD_SET_ADDR_SEC_ENT4(cmd, addr_cam->sec_ent[4]);
914
-
FWCMD_SET_ADDR_SEC_ENT5(cmd, addr_cam->sec_ent[5]);
915
-
FWCMD_SET_ADDR_SEC_ENT6(cmd, addr_cam->sec_ent[6]);
901
+
h2c->w9 |= le32_encode_bits(rtwvif_link->wowlan_pattern, ADDR_CAM_W9_WOL_PATTERN) |
902
+
le32_encode_bits(rtwvif_link->wowlan_uc, ADDR_CAM_W9_WOL_UC) |
903
+
le32_encode_bits(rtwvif_link->wowlan_magic, ADDR_CAM_W9_WOL_MAGIC) |
904
+
le32_encode_bits(addr_cam->wapi, ADDR_CAM_W9_WAPI) |
905
+
le32_encode_bits(addr_cam->sec_ent_mode, ADDR_CAM_W9_SEC_ENT_MODE) |
906
+
le32_encode_bits(addr_cam->sec_ent_keyid[0], ADDR_CAM_W9_SEC_ENT0_KEYID) |
907
+
le32_encode_bits(addr_cam->sec_ent_keyid[1], ADDR_CAM_W9_SEC_ENT1_KEYID) |
908
+
le32_encode_bits(addr_cam->sec_ent_keyid[2], ADDR_CAM_W9_SEC_ENT2_KEYID) |
909
+
le32_encode_bits(addr_cam->sec_ent_keyid[3], ADDR_CAM_W9_SEC_ENT3_KEYID) |
910
+
le32_encode_bits(addr_cam->sec_ent_keyid[4], ADDR_CAM_W9_SEC_ENT4_KEYID) |
911
+
le32_encode_bits(addr_cam->sec_ent_keyid[5], ADDR_CAM_W9_SEC_ENT5_KEYID) |
912
+
le32_encode_bits(addr_cam->sec_ent_keyid[6], ADDR_CAM_W9_SEC_ENT6_KEYID);
913
+
h2c->w10 = le32_encode_bits(addr_cam->sec_cam_map[0] & 0xff, ADDR_CAM_W10_SEC_ENT_VALID) |
914
+
le32_encode_bits(addr_cam->sec_ent[0], ADDR_CAM_W10_SEC_ENT0) |
915
+
le32_encode_bits(addr_cam->sec_ent[1], ADDR_CAM_W10_SEC_ENT1) |
916
+
le32_encode_bits(addr_cam->sec_ent[2], ADDR_CAM_W10_SEC_ENT2);
917
+
h2c->w11 = le32_encode_bits(addr_cam->sec_ent[3], ADDR_CAM_W11_SEC_ENT3) |
918
+
le32_encode_bits(addr_cam->sec_ent[4], ADDR_CAM_W11_SEC_ENT4) |
919
+
le32_encode_bits(addr_cam->sec_ent[5], ADDR_CAM_W11_SEC_ENT5) |
920
+
le32_encode_bits(addr_cam->sec_ent[6], ADDR_CAM_W11_SEC_ENT6);
916
921
917
922
rcu_read_unlock();
918
923
}
+108
-342
drivers/net/wireless/realtek/rtw89/cam.h
+108
-342
drivers/net/wireless/realtek/rtw89/cam.h
···
12
12
#define RTW89_BSSID_MATCH_ALL GENMASK(5, 0)
13
13
#define RTW89_BSSID_MATCH_5_BYTES GENMASK(4, 0)
14
14
15
-
static inline void FWCMD_SET_ADDR_IDX(void *cmd, u32 value)
16
-
{
17
-
le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0));
18
-
}
19
-
20
-
static inline void FWCMD_SET_ADDR_OFFSET(void *cmd, u32 value)
21
-
{
22
-
le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8));
23
-
}
24
-
25
-
static inline void FWCMD_SET_ADDR_LEN(void *cmd, u32 value)
26
-
{
27
-
le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16));
28
-
}
29
-
30
-
static inline void FWCMD_SET_ADDR_VALID(void *cmd, u32 value)
31
-
{
32
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(0));
33
-
}
34
-
35
-
static inline void FWCMD_SET_ADDR_NET_TYPE(void *cmd, u32 value)
36
-
{
37
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1));
38
-
}
39
-
40
-
static inline void FWCMD_SET_ADDR_BCN_HIT_COND(void *cmd, u32 value)
41
-
{
42
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(4, 3));
43
-
}
44
-
45
-
static inline void FWCMD_SET_ADDR_HIT_RULE(void *cmd, u32 value)
46
-
{
47
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(6, 5));
48
-
}
49
-
50
-
static inline void FWCMD_SET_ADDR_BB_SEL(void *cmd, u32 value)
51
-
{
52
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(7));
53
-
}
54
-
55
-
static inline void FWCMD_SET_ADDR_ADDR_MASK(void *cmd, u32 value)
56
-
{
57
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(13, 8));
58
-
}
59
-
60
-
static inline void FWCMD_SET_ADDR_MASK_SEL(void *cmd, u32 value)
61
-
{
62
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(15, 14));
63
-
}
64
-
65
-
static inline void FWCMD_SET_ADDR_SMA_HASH(void *cmd, u32 value)
66
-
{
67
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(23, 16));
68
-
}
69
-
70
-
static inline void FWCMD_SET_ADDR_TMA_HASH(void *cmd, u32 value)
71
-
{
72
-
le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(31, 24));
73
-
}
74
-
75
-
static inline void FWCMD_SET_ADDR_BSSID_CAM_IDX(void *cmd, u32 value)
76
-
{
77
-
le32p_replace_bits((__le32 *)(cmd) + 3, value, GENMASK(5, 0));
78
-
}
79
-
80
-
static inline void FWCMD_SET_ADDR_SMA0(void *cmd, u32 value)
81
-
{
82
-
le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(7, 0));
83
-
}
84
-
85
-
static inline void FWCMD_SET_ADDR_SMA1(void *cmd, u32 value)
86
-
{
87
-
le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(15, 8));
88
-
}
89
-
90
-
static inline void FWCMD_SET_ADDR_SMA2(void *cmd, u32 value)
91
-
{
92
-
le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(23, 16));
93
-
}
94
-
95
-
static inline void FWCMD_SET_ADDR_SMA3(void *cmd, u32 value)
96
-
{
97
-
le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(31, 24));
98
-
}
99
-
100
-
static inline void FWCMD_SET_ADDR_SMA4(void *cmd, u32 value)
101
-
{
102
-
le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(7, 0));
103
-
}
104
-
105
-
static inline void FWCMD_SET_ADDR_SMA5(void *cmd, u32 value)
106
-
{
107
-
le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(15, 8));
108
-
}
109
-
110
-
static inline void FWCMD_SET_ADDR_TMA0(void *cmd, u32 value)
111
-
{
112
-
le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(23, 16));
113
-
}
114
-
115
-
static inline void FWCMD_SET_ADDR_TMA1(void *cmd, u32 value)
116
-
{
117
-
le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(31, 24));
118
-
}
119
-
120
-
static inline void FWCMD_SET_ADDR_TMA2(void *cmd, u32 value)
121
-
{
122
-
le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(7, 0));
123
-
}
124
-
125
-
static inline void FWCMD_SET_ADDR_TMA3(void *cmd, u32 value)
126
-
{
127
-
le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(15, 8));
128
-
}
129
-
130
-
static inline void FWCMD_SET_ADDR_TMA4(void *cmd, u32 value)
131
-
{
132
-
le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(23, 16));
133
-
}
134
-
135
-
static inline void FWCMD_SET_ADDR_TMA5(void *cmd, u32 value)
136
-
{
137
-
le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(31, 24));
138
-
}
139
-
140
-
static inline void FWCMD_SET_ADDR_MACID(void *cmd, u32 value)
141
-
{
142
-
le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(7, 0));
143
-
}
144
-
145
-
static inline void FWCMD_SET_ADDR_PORT_INT(void *cmd, u32 value)
146
-
{
147
-
le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(10, 8));
148
-
}
149
-
150
-
static inline void FWCMD_SET_ADDR_TSF_SYNC(void *cmd, u32 value)
151
-
{
152
-
le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(13, 11));
153
-
}
154
-
155
-
static inline void FWCMD_SET_ADDR_TF_TRS(void *cmd, u32 value)
156
-
{
157
-
le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(14));
158
-
}
159
-
160
-
static inline void FWCMD_SET_ADDR_LSIG_TXOP(void *cmd, u32 value)
161
-
{
162
-
le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(15));
163
-
}
164
-
165
-
static inline void FWCMD_SET_ADDR_TGT_IND(void *cmd, u32 value)
166
-
{
167
-
le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(26, 24));
168
-
}
169
-
170
-
static inline void FWCMD_SET_ADDR_FRM_TGT_IND(void *cmd, u32 value)
171
-
{
172
-
le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(29, 27));
173
-
}
174
-
175
-
static inline void FWCMD_SET_ADDR_AID12(void *cmd, u32 value)
176
-
{
177
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 0));
178
-
}
179
-
180
-
static inline void FWCMD_SET_ADDR_AID12_0(void *cmd, u32 value)
181
-
{
182
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(7, 0));
183
-
}
184
-
185
-
static inline void FWCMD_SET_ADDR_AID12_1(void *cmd, u32 value)
186
-
{
187
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 8));
188
-
}
189
-
190
-
static inline void FWCMD_SET_ADDR_WOL_PATTERN(void *cmd, u32 value)
191
-
{
192
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(12));
193
-
}
194
-
195
-
static inline void FWCMD_SET_ADDR_WOL_UC(void *cmd, u32 value)
196
-
{
197
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(13));
198
-
}
199
-
200
-
static inline void FWCMD_SET_ADDR_WOL_MAGIC(void *cmd, u32 value)
201
-
{
202
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(14));
203
-
}
204
-
205
-
static inline void FWCMD_SET_ADDR_WAPI(void *cmd, u32 value)
206
-
{
207
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(15));
208
-
}
209
-
210
-
static inline void FWCMD_SET_ADDR_SEC_ENT_MODE(void *cmd, u32 value)
211
-
{
212
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(17, 16));
213
-
}
214
-
215
-
static inline void FWCMD_SET_ADDR_SEC_ENT0_KEYID(void *cmd, u32 value)
216
-
{
217
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(19, 18));
218
-
}
219
-
220
-
static inline void FWCMD_SET_ADDR_SEC_ENT1_KEYID(void *cmd, u32 value)
221
-
{
222
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(21, 20));
223
-
}
224
-
225
-
static inline void FWCMD_SET_ADDR_SEC_ENT2_KEYID(void *cmd, u32 value)
226
-
{
227
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(23, 22));
228
-
}
229
-
230
-
static inline void FWCMD_SET_ADDR_SEC_ENT3_KEYID(void *cmd, u32 value)
231
-
{
232
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(25, 24));
233
-
}
234
-
235
-
static inline void FWCMD_SET_ADDR_SEC_ENT4_KEYID(void *cmd, u32 value)
236
-
{
237
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(27, 26));
238
-
}
239
-
240
-
static inline void FWCMD_SET_ADDR_SEC_ENT5_KEYID(void *cmd, u32 value)
241
-
{
242
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(29, 28));
243
-
}
244
-
245
-
static inline void FWCMD_SET_ADDR_SEC_ENT6_KEYID(void *cmd, u32 value)
246
-
{
247
-
le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(31, 30));
248
-
}
249
-
250
-
static inline void FWCMD_SET_ADDR_SEC_ENT_VALID(void *cmd, u32 value)
251
-
{
252
-
le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(7, 0));
253
-
}
254
-
255
-
static inline void FWCMD_SET_ADDR_SEC_ENT0(void *cmd, u32 value)
256
-
{
257
-
le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(15, 8));
258
-
}
259
-
260
-
static inline void FWCMD_SET_ADDR_SEC_ENT1(void *cmd, u32 value)
261
-
{
262
-
le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(23, 16));
263
-
}
264
-
265
-
static inline void FWCMD_SET_ADDR_SEC_ENT2(void *cmd, u32 value)
266
-
{
267
-
le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(31, 24));
268
-
}
269
-
270
-
static inline void FWCMD_SET_ADDR_SEC_ENT3(void *cmd, u32 value)
271
-
{
272
-
le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(7, 0));
273
-
}
274
-
275
-
static inline void FWCMD_SET_ADDR_SEC_ENT4(void *cmd, u32 value)
276
-
{
277
-
le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(15, 8));
278
-
}
279
-
280
-
static inline void FWCMD_SET_ADDR_SEC_ENT5(void *cmd, u32 value)
281
-
{
282
-
le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(23, 16));
283
-
}
284
-
285
-
static inline void FWCMD_SET_ADDR_SEC_ENT6(void *cmd, u32 value)
286
-
{
287
-
le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(31, 24));
288
-
}
289
-
290
-
static inline void FWCMD_SET_ADDR_BSSID_IDX(void *cmd, u32 value)
291
-
{
292
-
le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(7, 0));
293
-
}
294
-
295
-
static inline void FWCMD_SET_ADDR_BSSID_OFFSET(void *cmd, u32 value)
296
-
{
297
-
le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(15, 8));
298
-
}
299
-
300
-
static inline void FWCMD_SET_ADDR_BSSID_LEN(void *cmd, u32 value)
301
-
{
302
-
le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(23, 16));
303
-
}
304
-
305
-
static inline void FWCMD_SET_ADDR_BSSID_VALID(void *cmd, u32 value)
306
-
{
307
-
le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(0));
308
-
}
309
-
310
-
static inline void FWCMD_SET_ADDR_BSSID_BB_SEL(void *cmd, u32 value)
311
-
{
312
-
le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(1));
313
-
}
314
-
315
-
static inline void FWCMD_SET_ADDR_BSSID_MASK(void *cmd, u32 value)
316
-
{
317
-
le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(7, 2));
318
-
}
319
-
320
-
static inline void FWCMD_SET_ADDR_BSSID_BSS_COLOR(void *cmd, u32 value)
321
-
{
322
-
le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(13, 8));
323
-
}
324
-
325
-
static inline void FWCMD_SET_ADDR_BSSID_BSSID0(void *cmd, u32 value)
326
-
{
327
-
le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(23, 16));
328
-
}
329
-
330
-
static inline void FWCMD_SET_ADDR_BSSID_BSSID1(void *cmd, u32 value)
331
-
{
332
-
le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(31, 24));
333
-
}
334
-
335
-
static inline void FWCMD_SET_ADDR_BSSID_BSSID2(void *cmd, u32 value)
336
-
{
337
-
le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(7, 0));
338
-
}
339
-
340
-
static inline void FWCMD_SET_ADDR_BSSID_BSSID3(void *cmd, u32 value)
341
-
{
342
-
le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(15, 8));
343
-
}
344
-
345
-
static inline void FWCMD_SET_ADDR_BSSID_BSSID4(void *cmd, u32 value)
346
-
{
347
-
le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(23, 16));
348
-
}
349
-
350
-
static inline void FWCMD_SET_ADDR_BSSID_BSSID5(void *cmd, u32 value)
351
-
{
352
-
le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(31, 24));
353
-
}
15
+
struct rtw89_h2c_addr_cam_v0 {
16
+
__le32 w0;
17
+
__le32 w1;
18
+
__le32 w2;
19
+
__le32 w3;
20
+
__le32 w4;
21
+
__le32 w5;
22
+
__le32 w6;
23
+
__le32 w7;
24
+
__le32 w8;
25
+
__le32 w9;
26
+
__le32 w10;
27
+
__le32 w11;
28
+
__le32 w12;
29
+
__le32 w13;
30
+
__le32 w14;
31
+
} __packed;
32
+
33
+
struct rtw89_h2c_addr_cam {
34
+
struct rtw89_h2c_addr_cam_v0 v0;
35
+
__le32 w15;
36
+
} __packed;
37
+
38
+
#define ADDR_CAM_W1_IDX GENMASK(7, 0)
39
+
#define ADDR_CAM_W1_OFFSET GENMASK(15, 8)
40
+
#define ADDR_CAM_W1_LEN GENMASK(23, 16)
41
+
#define ADDR_CAM_W1_V1_IDX GENMASK(9, 0)
42
+
#define ADDR_CAM_W1_V1_OFFSET GENMASK(23, 16)
43
+
#define ADDR_CAM_W1_V1_LEN GENMASK(31, 24)
44
+
#define ADDR_CAM_W2_VALID BIT(0)
45
+
#define ADDR_CAM_W2_NET_TYPE GENMASK(2, 1)
46
+
#define ADDR_CAM_W2_BCN_HIT_COND GENMASK(4, 3)
47
+
#define ADDR_CAM_W2_HIT_RULE GENMASK(6, 5)
48
+
#define ADDR_CAM_W2_BB_SEL BIT(7)
49
+
#define ADDR_CAM_W2_ADDR_MASK GENMASK(13, 8)
50
+
#define ADDR_CAM_W2_MASK_SEL GENMASK(15, 14)
51
+
#define ADDR_CAM_W2_SMA_HASH GENMASK(23, 16)
52
+
#define ADDR_CAM_W2_TMA_HASH GENMASK(31, 24)
53
+
#define ADDR_CAM_W3_BSSID_CAM_IDX GENMASK(5, 0)
54
+
#define ADDR_CAM_W4_SMA0 GENMASK(7, 0)
55
+
#define ADDR_CAM_W4_SMA1 GENMASK(15, 8)
56
+
#define ADDR_CAM_W4_SMA2 GENMASK(23, 16)
57
+
#define ADDR_CAM_W4_SMA3 GENMASK(31, 24)
58
+
#define ADDR_CAM_W5_SMA4 GENMASK(7, 0)
59
+
#define ADDR_CAM_W5_SMA5 GENMASK(15, 8)
60
+
#define ADDR_CAM_W5_TMA0 GENMASK(23, 16)
61
+
#define ADDR_CAM_W5_TMA1 GENMASK(31, 24)
62
+
#define ADDR_CAM_W6_TMA2 GENMASK(7, 0)
63
+
#define ADDR_CAM_W6_TMA3 GENMASK(15, 8)
64
+
#define ADDR_CAM_W6_TMA4 GENMASK(23, 16)
65
+
#define ADDR_CAM_W6_TMA5 GENMASK(31, 24)
66
+
#define ADDR_CAM_W8_MACID GENMASK(7, 0)
67
+
#define ADDR_CAM_W8_PORT_INT GENMASK(10, 8)
68
+
#define ADDR_CAM_W8_TSF_SYNC GENMASK(13, 11)
69
+
#define ADDR_CAM_W8_TF_TRS BIT(14)
70
+
#define ADDR_CAM_W8_LSIG_TXOP BIT(15)
71
+
#define ADDR_CAM_W8_TGT_IND GENMASK(26, 24)
72
+
#define ADDR_CAM_W8_FRM_TGT_IND GENMASK(29, 27)
73
+
#define ADDR_CAM_W8_V1_MACID GENMASK(9, 0)
74
+
#define ADDR_CAM_W8_V1_PORT_INT GENMASK(18, 16)
75
+
#define ADDR_CAM_W8_V1_TSF_SYNC GENMASK(21, 19)
76
+
#define ADDR_CAM_W8_V1_TF_TRS BIT(22)
77
+
#define ADDR_CAM_W8_V1_LSIG_TXOP BIT(23)
78
+
#define ADDR_CAM_W8_V1_TB_RANGING BIT(24)
79
+
#define ADDR_CAM_W8_V1_TB_SENSING BIT(25)
80
+
#define ADDR_CAM_W8_V1_SENS_EN BIT(26)
81
+
#define ADDR_CAM_W9_AID12 GENMASK(11, 0)
82
+
#define ADDR_CAM_W9_AID12_0 GENMASK(7, 0)
83
+
#define ADDR_CAM_W9_AID12_1 GENMASK(11, 8)
84
+
#define ADDR_CAM_W9_WOL_PATTERN BIT(12)
85
+
#define ADDR_CAM_W9_WOL_UC BIT(13)
86
+
#define ADDR_CAM_W9_WOL_MAGIC BIT(14)
87
+
#define ADDR_CAM_W9_WAPI BIT(15)
88
+
#define ADDR_CAM_W9_SEC_ENT_MODE GENMASK(17, 16)
89
+
#define ADDR_CAM_W9_SEC_ENT0_KEYID GENMASK(19, 18)
90
+
#define ADDR_CAM_W9_SEC_ENT1_KEYID GENMASK(21, 20)
91
+
#define ADDR_CAM_W9_SEC_ENT2_KEYID GENMASK(23, 22)
92
+
#define ADDR_CAM_W9_SEC_ENT3_KEYID GENMASK(25, 24)
93
+
#define ADDR_CAM_W9_SEC_ENT4_KEYID GENMASK(27, 26)
94
+
#define ADDR_CAM_W9_SEC_ENT5_KEYID GENMASK(29, 28)
95
+
#define ADDR_CAM_W9_SEC_ENT6_KEYID GENMASK(31, 30)
96
+
#define ADDR_CAM_W10_SEC_ENT_VALID GENMASK(7, 0)
97
+
#define ADDR_CAM_W10_SEC_ENT0 GENMASK(15, 8)
98
+
#define ADDR_CAM_W10_SEC_ENT1 GENMASK(23, 16)
99
+
#define ADDR_CAM_W10_SEC_ENT2 GENMASK(31, 24)
100
+
#define ADDR_CAM_W11_SEC_ENT3 GENMASK(7, 0)
101
+
#define ADDR_CAM_W11_SEC_ENT4 GENMASK(15, 8)
102
+
#define ADDR_CAM_W11_SEC_ENT5 GENMASK(23, 16)
103
+
#define ADDR_CAM_W11_SEC_ENT6 GENMASK(31, 24)
104
+
#define ADDR_CAM_W12_BSSID_IDX GENMASK(7, 0)
105
+
#define ADDR_CAM_W12_BSSID_OFFSET GENMASK(15, 8)
106
+
#define ADDR_CAM_W12_BSSID_LEN GENMASK(23, 16)
107
+
#define ADDR_CAM_W13_BSSID_VALID BIT(0)
108
+
#define ADDR_CAM_W13_BSSID_BB_SEL BIT(1)
109
+
#define ADDR_CAM_W13_BSSID_MASK GENMASK(7, 2)
110
+
#define ADDR_CAM_W13_BSSID_BSS_COLOR GENMASK(13, 8)
111
+
#define ADDR_CAM_W13_BSSID_BSSID0 GENMASK(23, 16)
112
+
#define ADDR_CAM_W13_BSSID_BSSID1 GENMASK(31, 24)
113
+
#define ADDR_CAM_W14_BSSID_BSSID2 GENMASK(7, 0)
114
+
#define ADDR_CAM_W14_BSSID_BSSID3 GENMASK(15, 8)
115
+
#define ADDR_CAM_W14_BSSID_BSSID4 GENMASK(23, 16)
116
+
#define ADDR_CAM_W14_BSSID_BSSID5 GENMASK(31, 24)
117
+
#define ADDR_CAM_W15_UPD_MODE GENMASK(2, 0)
354
118
355
119
struct rtw89_h2c_dctlinfo_ud_v1 {
356
120
__le32 c0;
···
316
552
void rtw89_cam_deinit_bssid_cam(struct rtw89_dev *rtwdev,
317
553
struct rtw89_bssid_cam_entry *bssid_cam);
318
554
void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev,
319
-
struct rtw89_vif_link *vif,
555
+
struct rtw89_vif_link *rtwvif_link,
320
556
struct rtw89_sta_link *rtwsta_link,
321
-
const u8 *scan_mac_addr, u8 *cmd);
557
+
const u8 *scan_mac_addr,
558
+
struct rtw89_h2c_addr_cam_v0 *h2c);
322
559
void rtw89_cam_fill_dctl_sec_cam_info_v1(struct rtw89_dev *rtwdev,
323
560
struct rtw89_vif_link *rtwvif_link,
324
561
struct rtw89_sta_link *rtwsta_link,
···
330
565
struct rtw89_h2c_dctlinfo_ud_v2 *h2c);
331
566
int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev,
332
567
struct rtw89_vif_link *rtwvif_link,
333
-
struct rtw89_sta_link *rtwsta_link, u8 *cmd);
568
+
struct rtw89_sta_link *rtwsta_link,
569
+
struct rtw89_h2c_addr_cam_v0 *h2c);
334
570
int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev,
335
571
struct ieee80211_vif *vif,
336
572
struct ieee80211_sta *sta,
+180
-51
drivers/net/wireless/realtek/rtw89/core.c
+180
-51
drivers/net/wireless/realtek/rtw89/core.c
···
321
321
.n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
322
322
};
323
323
324
+
static const struct rtw89_hw_rate_def {
325
+
enum rtw89_hw_rate ht;
326
+
enum rtw89_hw_rate vht[RTW89_NSS_NUM];
327
+
} rtw89_hw_rate[RTW89_CHIP_GEN_NUM] = {
328
+
[RTW89_CHIP_AX] = {
329
+
.ht = RTW89_HW_RATE_MCS0,
330
+
.vht = {RTW89_HW_RATE_VHT_NSS1_MCS0,
331
+
RTW89_HW_RATE_VHT_NSS2_MCS0,
332
+
RTW89_HW_RATE_VHT_NSS3_MCS0,
333
+
RTW89_HW_RATE_VHT_NSS4_MCS0},
334
+
},
335
+
[RTW89_CHIP_BE] = {
336
+
.ht = RTW89_HW_RATE_V1_MCS0,
337
+
.vht = {RTW89_HW_RATE_V1_VHT_NSS1_MCS0,
338
+
RTW89_HW_RATE_V1_VHT_NSS2_MCS0,
339
+
RTW89_HW_RATE_V1_VHT_NSS3_MCS0,
340
+
RTW89_HW_RATE_V1_VHT_NSS4_MCS0},
341
+
},
342
+
};
343
+
324
344
static void __rtw89_traffic_stats_accu(struct rtw89_traffic_stats *stats,
325
345
struct sk_buff *skb, bool tx)
326
346
{
···
470
450
__rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1);
471
451
}
472
452
453
+
static void rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev *rtwdev,
454
+
enum rtw89_phy_idx phy_idx)
455
+
{
456
+
struct rtw89_vif *rtwvif = rtwdev->pure_monitor_mode_vif;
457
+
struct rtw89_vif_link *rtwvif_link;
458
+
459
+
if (!rtwvif)
460
+
return;
461
+
462
+
rtwvif_link = rtw89_vif_get_link_inst(rtwvif, phy_idx);
463
+
if (!rtwvif_link)
464
+
return;
465
+
466
+
rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
467
+
}
468
+
473
469
static void __rtw89_set_channel(struct rtw89_dev *rtwdev,
474
470
const struct rtw89_chan *chan,
475
471
enum rtw89_mac_idx mac_idx,
···
514
478
}
515
479
516
480
rtw89_set_entity_state(rtwdev, phy_idx, true);
481
+
482
+
rtw89_chip_rfk_channel_for_pure_mon_vif(rtwdev, phy_idx);
517
483
}
518
484
519
485
int rtw89_set_channel(struct rtw89_dev *rtwdev)
···
796
758
}
797
759
}
798
760
EXPORT_SYMBOL(rtw89_core_get_ch_dma_v1);
761
+
762
+
u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel)
763
+
{
764
+
switch (qsel) {
765
+
default:
766
+
rtw89_warn(rtwdev, "Cannot map qsel to dma v2: %d\n", qsel);
767
+
fallthrough;
768
+
case RTW89_TX_QSEL_BE_0:
769
+
case RTW89_TX_QSEL_VO_0:
770
+
return RTW89_TXCH_ACH0;
771
+
case RTW89_TX_QSEL_BK_0:
772
+
case RTW89_TX_QSEL_VI_0:
773
+
return RTW89_TXCH_ACH2;
774
+
case RTW89_TX_QSEL_B0_MGMT:
775
+
case RTW89_TX_QSEL_B0_HI:
776
+
return RTW89_TXCH_CH8;
777
+
}
778
+
}
779
+
EXPORT_SYMBOL(rtw89_core_get_ch_dma_v2);
799
780
800
781
static void
801
782
rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
···
1135
1078
rtw89_mac_notify_wake(rtwdev);
1136
1079
}
1137
1080
1081
+
static void rtw89_core_tx_update_injection(struct rtw89_dev *rtwdev,
1082
+
struct rtw89_core_tx_request *tx_req,
1083
+
struct ieee80211_tx_info *info)
1084
+
{
1085
+
const struct rtw89_hw_rate_def *hw_rate = &rtw89_hw_rate[rtwdev->chip->chip_gen];
1086
+
enum mac80211_rate_control_flags flags = info->control.rates[0].flags;
1087
+
struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1088
+
const struct rtw89_chan *chan;
1089
+
u8 idx = info->control.rates[0].idx;
1090
+
u8 nss, mcs;
1091
+
1092
+
desc_info->use_rate = true;
1093
+
desc_info->dis_data_fb = true;
1094
+
1095
+
if (flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
1096
+
desc_info->data_bw = 3;
1097
+
else if (flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
1098
+
desc_info->data_bw = 2;
1099
+
else if (flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1100
+
desc_info->data_bw = 1;
1101
+
1102
+
if (flags & IEEE80211_TX_RC_SHORT_GI)
1103
+
desc_info->gi_ltf = 1;
1104
+
1105
+
if (flags & IEEE80211_TX_RC_VHT_MCS) {
1106
+
nss = umin(idx >> 4, ARRAY_SIZE(hw_rate->vht) - 1);
1107
+
mcs = idx & 0xf;
1108
+
desc_info->data_rate = hw_rate->vht[nss] + mcs;
1109
+
} else if (flags & IEEE80211_TX_RC_MCS) {
1110
+
desc_info->data_rate = hw_rate->ht + idx;
1111
+
} else {
1112
+
chan = rtw89_chan_get(rtwdev, tx_req->rtwvif_link->chanctx_idx);
1113
+
1114
+
desc_info->data_rate = idx + (chan->band_type == RTW89_BAND_2G ?
1115
+
RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6);
1116
+
}
1117
+
}
1118
+
1138
1119
static void
1139
1120
rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
1140
1121
struct rtw89_core_tx_request *tx_req)
···
1182
1087
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1183
1088
struct ieee80211_hdr *hdr = (void *)skb->data;
1184
1089
struct rtw89_addr_cam_entry *addr_cam;
1185
-
enum rtw89_core_tx_type tx_type;
1186
1090
enum btc_pkt_type pkt_type;
1187
1091
bool upd_wlan_hdr = false;
1188
1092
bool is_bmc;
1189
1093
u16 seq;
1094
+
1095
+
desc_info->pkt_size = skb->len;
1096
+
1097
+
if (unlikely(tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD)) {
1098
+
rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
1099
+
return;
1100
+
}
1101
+
1102
+
tx_req->tx_type = rtw89_core_get_tx_type(rtwdev, skb);
1190
1103
1191
1104
if (tx_req->sta)
1192
1105
desc_info->mlo = tx_req->sta->mlo;
···
1202
1099
desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif);
1203
1100
1204
1101
seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
1205
-
if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) {
1206
-
tx_type = rtw89_core_get_tx_type(rtwdev, skb);
1207
-
tx_req->tx_type = tx_type;
1102
+
addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link,
1103
+
tx_req->rtwsta_link);
1104
+
if (addr_cam->valid && desc_info->mlo)
1105
+
upd_wlan_hdr = true;
1208
1106
1209
-
addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link,
1210
-
tx_req->rtwsta_link);
1211
-
if (addr_cam->valid && desc_info->mlo)
1212
-
upd_wlan_hdr = true;
1213
-
}
1107
+
if (rtw89_is_tx_rpt_skb(rtwdev, tx_req->skb))
1108
+
rtw89_tx_rpt_init(rtwdev, tx_req);
1109
+
1214
1110
is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
1215
1111
is_multicast_ether_addr(hdr->addr1));
1216
1112
1217
1113
desc_info->seq = seq;
1218
-
desc_info->pkt_size = skb->len;
1219
1114
desc_info->is_bmc = is_bmc;
1220
1115
desc_info->wd_page = true;
1221
1116
desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
···
1230
1129
rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
1231
1130
rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
1232
1131
break;
1233
-
case RTW89_CORE_TX_TYPE_FWCMD:
1234
-
rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
1132
+
default:
1235
1133
break;
1236
1134
}
1135
+
1136
+
if (unlikely(info->flags & IEEE80211_TX_CTL_INJECTED))
1137
+
rtw89_core_tx_update_injection(rtwdev, tx_req, info);
1237
1138
}
1238
1139
1239
1140
static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work)
···
1342
1239
tx_req.rtwvif_link = rtwvif_link;
1343
1240
tx_req.rtwsta_link = rtwsta_link;
1344
1241
tx_req.desc_info.sw_mld = sw_mld;
1242
+
rcu_assign_pointer(skb_data->wait, wait);
1345
1243
1346
1244
rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true);
1347
1245
rtw89_wow_parse_akm(rtwdev, skb);
1348
1246
rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1349
1247
rtw89_core_tx_wake(rtwdev, &tx_req);
1350
-
1351
-
rcu_assign_pointer(skb_data->wait, wait);
1352
1248
1353
1249
ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1354
1250
if (ret) {
···
1464
1362
static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1465
1363
{
1466
1364
u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1365
+
FIELD_PREP(RTW89_TXWD_BODY7_DATA_BW, desc_info->data_bw) |
1366
+
FIELD_PREP(RTW89_TXWD_BODY7_GI_LTF, desc_info->gi_ltf) |
1467
1367
FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1468
1368
1469
1369
return cpu_to_le32(dword);
···
1474
1370
static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1475
1371
{
1476
1372
u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1373
+
FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW, desc_info->data_bw) |
1374
+
FIELD_PREP(RTW89_TXWD_INFO0_GI_LTF, desc_info->gi_ltf) |
1477
1375
FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1478
1376
FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1479
1377
FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
···
1502
1396
u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1503
1397
FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1504
1398
FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1505
-
desc_info->data_retry_lowest_rate);
1399
+
desc_info->data_retry_lowest_rate) |
1400
+
FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL,
1401
+
desc_info->tx_cnt_lmt_en) |
1402
+
FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt);
1506
1403
1507
1404
return cpu_to_le32(dword);
1508
1405
}
···
1529
1420
return cpu_to_le32(dword);
1530
1421
}
1531
1422
1423
+
static __le32 rtw89_build_txwd_info3(struct rtw89_tx_desc_info *desc_info)
1424
+
{
1425
+
u32 dword = FIELD_PREP(RTW89_TXWD_INFO3_SPE_RPT, desc_info->report);
1426
+
1427
+
return cpu_to_le32(dword);
1428
+
}
1429
+
1532
1430
static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1533
1431
{
1534
1432
bool rts_en = !desc_info->is_bmc;
1535
1433
u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1536
-
FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1);
1434
+
FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1) |
1435
+
FIELD_PREP(RTW89_TXWD_INFO4_SW_DEFINE, desc_info->sn);
1537
1436
1538
1437
return cpu_to_le32(dword);
1539
1438
}
···
1564
1447
txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1565
1448
txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1566
1449
txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1450
+
txwd_info->dword3 = rtw89_build_txwd_info3(desc_info);
1567
1451
txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1568
1452
1569
1453
}
···
1594
1476
txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1595
1477
txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1596
1478
txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1479
+
txwd_info->dword3 = rtw89_build_txwd_info3(desc_info);
1597
1480
txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1598
1481
}
1599
1482
EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
···
1668
1549
static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1669
1550
{
1670
1551
u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1552
+
FIELD_PREP(BE_TXD_BODY7_DATA_BW, desc_info->data_bw) |
1553
+
FIELD_PREP(BE_TXD_BODY7_GI_LTF, desc_info->gi_ltf) |
1671
1554
FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1672
1555
FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1673
1556
FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
···
1682
1561
u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1683
1562
FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1684
1563
FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1685
-
FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port);
1564
+
FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port) |
1565
+
FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT_SEL,
1566
+
desc_info->tx_cnt_lmt_en) |
1567
+
FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt);
1686
1568
1687
1569
return cpu_to_le32(dword);
1688
1570
}
···
1695
1571
u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1696
1572
FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1697
1573
FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1698
-
desc_info->data_retry_lowest_rate);
1574
+
desc_info->data_retry_lowest_rate) |
1575
+
FIELD_PREP(BE_TXD_INFO1_SW_DEFINE, desc_info->sn);
1699
1576
1700
1577
return cpu_to_le32(dword);
1701
1578
}
···
1705
1580
{
1706
1581
u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1707
1582
FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1708
-
FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1583
+
FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx) |
1584
+
FIELD_PREP(BE_TXD_INFO2_SPE_RPT_V1, desc_info->report);
1709
1585
1710
1586
return cpu_to_le32(dword);
1711
1587
}
···
1834
1708
/* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set
1835
1709
* by hardware, so update mac_id by rxinfo_user[].mac_id.
1836
1710
*/
1837
-
if (chip_gen == RTW89_CHIP_BE)
1711
+
if (chip->chip_id == RTL8922A)
1838
1712
phy_ppdu->mac_id =
1839
1713
le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1714
+
else if (chip->chip_id == RTL8922D)
1715
+
phy_ppdu->mac_id =
1716
+
le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID_V1);
1717
+
1840
1718
phy_ppdu->has_data =
1841
1719
le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA);
1842
1720
phy_ppdu->has_bcn =
···
3762
3632
struct ieee80211_sta *sta)
3763
3633
{
3764
3634
struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3765
-
struct sk_buff *skb, *tmp;
3635
+
struct sk_buff *skb;
3766
3636
3767
-
skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
3768
-
skb_unlink(skb, &rtwsta->roc_queue);
3637
+
while ((skb = skb_dequeue(&rtwsta->roc_queue)))
3769
3638
dev_kfree_skb_any(skb);
3770
-
}
3771
3639
}
3772
3640
3773
3641
static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
···
4009
3881
struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
4010
3882
struct rtw89_vif_link *target = data;
4011
3883
struct rtw89_vif_link *rtwvif_link;
4012
-
struct sk_buff *skb, *tmp;
4013
3884
unsigned int link_id;
3885
+
struct sk_buff *skb;
4014
3886
int qsel, ret;
4015
3887
4016
3888
rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
···
4023
3895
if (skb_queue_len(&rtwsta->roc_queue) == 0)
4024
3896
return;
4025
3897
4026
-
skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
4027
-
skb_unlink(skb, &rtwsta->roc_queue);
4028
-
3898
+
while ((skb = skb_dequeue(&rtwsta->roc_queue))) {
4029
3899
ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
4030
3900
if (ret) {
4031
3901
rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
···
4173
4047
4174
4048
void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4175
4049
{
4176
-
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4177
4050
struct ieee80211_hw *hw = rtwdev->hw;
4178
4051
struct rtw89_roc *roc = &rtwvif->roc;
4179
4052
struct rtw89_vif_link *rtwvif_link;
4180
4053
struct rtw89_vif *tmp_vif;
4181
-
u32 reg;
4182
4054
int ret;
4183
4055
4184
4056
lockdep_assert_wiphy(hw->wiphy);
···
4193
4069
return;
4194
4070
}
4195
4071
4196
-
reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
4197
-
rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr);
4072
+
rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr);
4198
4073
4199
4074
roc->state = RTW89_ROC_IDLE;
4200
4075
rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL);
···
4824
4701
}
4825
4702
4826
4703
/* update cam aid mac_id net_type */
4827
-
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
4704
+
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
4705
+
RTW89_ROLE_CON_DISCONN);
4828
4706
if (ret) {
4829
4707
rtw89_warn(rtwdev, "failed to send h2c cam\n");
4830
4708
return ret;
···
4899
4775
}
4900
4776
4901
4777
/* update cam aid mac_id net_type */
4902
-
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
4778
+
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
4779
+
RTW89_ROLE_CON_DISCONN);
4903
4780
if (ret) {
4904
4781
rtw89_warn(rtwdev, "failed to send h2c cam\n");
4905
4782
return ret;
···
5618
5493
5619
5494
int rtw89_core_start(struct rtw89_dev *rtwdev)
5620
5495
{
5496
+
bool no_bbmcu = !rtwdev->chip->bbmcu_nr;
5621
5497
int ret;
5622
5498
5499
+
ret = rtw89_mac_preinit(rtwdev);
5500
+
if (ret) {
5501
+
rtw89_err(rtwdev, "mac preinit fail, ret: %d\n", ret);
5502
+
return ret;
5503
+
}
5504
+
5505
+
if (no_bbmcu)
5506
+
rtw89_chip_bb_preinit(rtwdev);
5507
+
5623
5508
rtw89_phy_init_bb_afe(rtwdev);
5509
+
5510
+
/* above do preinit before downloading firmware */
5624
5511
5625
5512
ret = rtw89_mac_init(rtwdev);
5626
5513
if (ret) {
···
5679
5542
rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
5680
5543
rtw89_fw_h2c_init_ba_cam(rtwdev);
5681
5544
rtw89_tas_fw_timer_enable(rtwdev, true);
5545
+
rtwdev->ps_hang_cnt = 0;
5682
5546
5683
5547
return 0;
5684
5548
}
···
5967
5829
wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
5968
5830
INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
5969
5831
5832
+
spin_lock_init(&rtwdev->tx_rpt.skb_lock);
5970
5833
skb_queue_head_init(&rtwdev->c2h_queue);
5971
5834
rtw89_core_ppdu_sts_init(rtwdev);
5972
5835
rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
···
6032
5893
rtw89_phy_config_edcca(rtwdev, bb, true);
6033
5894
rtw89_tas_scan(rtwdev, true);
6034
5895
6035
-
rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr);
5896
+
rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr,
5897
+
RTW89_ROLE_INFO_CHANGE);
6036
5898
}
6037
5899
6038
5900
void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
···
6053
5913
6054
5914
rcu_read_unlock();
6055
5915
6056
-
rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
5916
+
rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL,
5917
+
RTW89_ROLE_INFO_CHANGE);
6057
5918
6058
5919
rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false);
6059
5920
rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx);
···
6155
6014
struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
6156
6015
u16 usable_links = ieee80211_vif_usable_links(vif);
6157
6016
u16 active_links = vif->active_links;
6158
-
struct rtw89_vif_link *target, *cur;
6017
+
struct rtw89_vif_link *target;
6159
6018
int ret;
6160
6019
6161
6020
lockdep_assert_wiphy(rtwdev->hw->wiphy);
···
6181
6040
ieee80211_stop_queues(rtwdev->hw);
6182
6041
flush_work(&rtwdev->txq_work);
6183
6042
6184
-
cur = rtw89_get_designated_link(rtwvif);
6185
-
6186
-
ret = ieee80211_set_active_links(vif, active_links | BIT(link_id));
6043
+
ret = ieee80211_set_active_links(vif, BIT(link_id));
6187
6044
if (ret) {
6188
-
rtw89_err(rtwdev, "%s: failed to activate link id %u\n",
6045
+
rtw89_err(rtwdev, "%s: failed to work on link id %u\n",
6189
6046
__func__, link_id);
6190
6047
goto wake_queue;
6191
6048
}
···
6197
6058
ret = -EFAULT;
6198
6059
goto wake_queue;
6199
6060
}
6200
-
6201
-
if (likely(cur))
6202
-
rtw89_fw_h2c_mlo_link_cfg(rtwdev, cur, false);
6203
-
6204
-
rtw89_fw_h2c_mlo_link_cfg(rtwdev, target, true);
6205
-
6206
-
ret = ieee80211_set_active_links(vif, BIT(link_id));
6207
-
if (ret)
6208
-
rtw89_err(rtwdev, "%s: failed to inactivate links 0x%x\n",
6209
-
__func__, active_links);
6210
6061
6211
6062
rtw89_chip_rfk_channel(rtwdev, target);
6212
6063
+88
-16
drivers/net/wireless/realtek/rtw89/core.h
+88
-16
drivers/net/wireless/realtek/rtw89/core.h
···
15
15
16
16
struct rtw89_dev;
17
17
struct rtw89_pci_info;
18
+
struct rtw89_usb_info;
18
19
struct rtw89_mac_gen_def;
19
20
struct rtw89_phy_gen_def;
20
21
struct rtw89_fw_blacklist;
···
39
38
#define RFREG_MASK 0xfffff
40
39
#define INV_RF_DATA 0xffffffff
41
40
#define BYPASS_CR_DATA 0xbabecafe
41
+
#define RTW89_R32_EA 0xEAEAEAEA
42
+
#define RTW89_R32_DEAD 0xDEADBEEF
42
43
43
44
#define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
44
45
#define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100)
45
46
#define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
47
+
#define RTW89_PS_HANG_MAX_CNT 3
46
48
#define CFO_TRACK_MAX_USER 64
47
49
#define MAX_RSSI 110
48
50
#define RSSI_FACTOR 1
···
155
151
RTL8852C,
156
152
RTL8851B,
157
153
RTL8922A,
154
+
RTL8922D,
158
155
};
159
156
160
157
enum rtw89_chip_gen {
···
1172
1167
u8 ampdu_density;
1173
1168
u8 ampdu_num;
1174
1169
bool sec_en;
1170
+
bool report;
1171
+
bool tx_cnt_lmt_en;
1172
+
u8 sn: 4;
1173
+
u8 tx_cnt_lmt: 6;
1175
1174
u8 addr_info_nr;
1176
1175
u8 sec_keyid;
1177
1176
u8 sec_type;
···
1183
1174
u8 sec_seq[6];
1184
1175
u16 data_rate;
1185
1176
u16 data_retry_lowest_rate;
1177
+
u8 data_bw;
1178
+
u8 gi_ltf;
1186
1179
bool fw_dl;
1187
1180
u16 seq;
1188
1181
bool a_ctrl_bsr;
···
3385
3374
u8 cr_tbl_sel:1;
3386
3375
u8 fix_giltf_en:1;
3387
3376
u8 fix_giltf:3;
3388
-
u8 rsvd2:1;
3377
+
u8 partial_bw_er:1;
3389
3378
u8 csi_mcs_ss_idx;
3390
3379
u8 csi_mode:2;
3391
3380
u8 csi_gi_ltf:3;
3392
3381
u8 csi_bw:3;
3382
+
/* after v1 */
3383
+
u8 is_noisy:1;
3384
+
u8 psra_en:1;
3385
+
u8 rsvd0:1;
3386
+
u8 macid_msb:2;
3387
+
u8 band:2; /* enum rtw89_band */
3388
+
u8 is_new_dbgreg:1;
3393
3389
};
3394
3390
3395
3391
#define RTW89_PPDU_MAC_INFO_USR_SIZE 4
···
3525
3507
bool enable;
3526
3508
};
3527
3509
3510
+
#define RTW89_TX_DONE 0x0
3511
+
#define RTW89_TX_RETRY_LIMIT 0x1
3512
+
#define RTW89_TX_LIFE_TIME 0x2
3513
+
#define RTW89_TX_MACID_DROP 0x3
3514
+
3515
+
#define RTW89_MAX_TX_RPTS 16
3516
+
#define RTW89_MAX_TX_RPTS_MASK (RTW89_MAX_TX_RPTS - 1)
3517
+
struct rtw89_tx_rpt {
3518
+
struct sk_buff *skbs[RTW89_MAX_TX_RPTS];
3519
+
/* protect skbs array access/modification */
3520
+
spinlock_t skb_lock;
3521
+
atomic_t sn;
3522
+
};
3523
+
3528
3524
#define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500)
3529
3525
struct rtw89_tx_wait_info {
3530
3526
struct rcu_head rcu_head;
···
3550
3518
3551
3519
struct rtw89_tx_skb_data {
3552
3520
struct rtw89_tx_wait_info __rcu *wait;
3521
+
u8 tx_rpt_sn;
3522
+
u8 tx_pkt_cnt_lmt;
3553
3523
u8 hci_priv[];
3554
3524
};
3555
3525
···
3686
3652
void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3687
3653
void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3688
3654
3655
+
u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr);
3656
+
3689
3657
int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3690
3658
int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3691
3659
int (*mac_post_init)(struct rtw89_dev *rtwdev);
···
3723
3687
u32 rpwm_addr;
3724
3688
u32 cpwm_addr;
3725
3689
bool paused;
3690
+
bool tx_rpt_enabled;
3726
3691
};
3727
3692
3728
3693
struct rtw89_chip_ops {
···
3800
3763
void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3801
3764
struct rtw89_tx_desc_info *desc_info,
3802
3765
void *txdesc);
3803
-
u8 (*get_ch_dma)(struct rtw89_dev *rtwdev, u8 qsel);
3766
+
u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel);
3804
3767
int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3805
3768
int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3806
3769
const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
···
4459
4422
u8 bacam_num;
4460
4423
u8 bacam_dynamic_num;
4461
4424
enum rtw89_bacam_ver bacam_ver;
4425
+
u8 addrcam_ver;
4462
4426
u8 ppdu_max_usr;
4463
4427
4464
4428
u8 sec_ctrl_efuse_size;
···
4551
4513
4552
4514
union rtw89_bus_info {
4553
4515
const struct rtw89_pci_info *pci;
4516
+
const struct rtw89_usb_info *usb;
4554
4517
};
4555
4518
4556
4519
struct rtw89_driver_info {
···
4679
4640
RTW89_FW_FEATURE_RFK_NTFY_MCC_V0,
4680
4641
RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG,
4681
4642
RTW89_FW_FEATURE_BEACON_TRACKING,
4643
+
RTW89_FW_FEATURE_ADDR_CAM_V0,
4682
4644
};
4683
4645
4684
4646
struct rtw89_fw_suit {
···
4740
4700
struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4741
4701
const struct rtw89_regd_data *regd;
4742
4702
const struct rtw89_fw_element_hdr *afe;
4703
+
const struct rtw89_fw_element_hdr *diag_mac;
4743
4704
};
4744
4705
4745
4706
enum rtw89_fw_mss_dev_type {
···
5490
5449
struct rtw89_regulatory_info {
5491
5450
struct rtw89_regd_ctrl ctrl;
5492
5451
const struct rtw89_regd *regd;
5452
+
bool programmed;
5453
+
5493
5454
enum rtw89_reg_6ghz_power reg_6ghz_power;
5494
5455
struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
5495
5456
bool txpwr_uk_follow_etsi;
···
5976
5933
5977
5934
enum rtw89_mlo_mode {
5978
5935
RTW89_MLO_MODE_MLSR = 0,
5936
+
RTW89_MLO_MODE_EMLSR = 1,
5979
5937
5980
5938
NUM_OF_RTW89_MLO_MODE,
5981
5939
};
···
6049
6005
6050
6006
struct list_head tx_waits;
6051
6007
struct wiphy_delayed_work tx_wait_work;
6008
+
6009
+
struct rtw89_tx_rpt tx_rpt;
6052
6010
6053
6011
struct rtw89_cam_info cam_info;
6054
6012
···
6125
6079
struct rtw89_btc btc;
6126
6080
enum rtw89_ps_mode ps_mode;
6127
6081
bool lps_enabled;
6082
+
u8 ps_hang_cnt;
6128
6083
6129
6084
struct rtw89_wow_param wow;
6130
6085
···
6135
6088
int napi_budget_countdown;
6136
6089
6137
6090
struct rtw89_debugfs *debugfs;
6091
+
struct rtw89_vif *pure_monitor_mode_vif;
6138
6092
6139
6093
/* HCI related data, keep last */
6140
6094
u8 priv[] __aligned(sizeof(void *));
···
6143
6095
6144
6096
struct rtw89_link_conf_container {
6145
6097
struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS];
6098
+
};
6099
+
6100
+
struct rtw89_vif_ml_trans {
6101
+
u16 mediate_links;
6102
+
u16 links_to_del;
6103
+
u16 links_to_add;
6146
6104
};
6147
6105
6148
6106
#define RTW89_VIF_IDLE_LINK_ID 0
···
6173
6119
bool offchan;
6174
6120
6175
6121
enum rtw89_mlo_mode mlo_mode;
6122
+
struct rtw89_vif_ml_trans ml_trans;
6176
6123
6177
6124
struct list_head dlink_pool;
6178
6125
u8 links_inst_valid_num;
···
6346
6291
static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
6347
6292
{
6348
6293
rtwdev->hci.ops->reset(rtwdev);
6294
+
/* hci.ops->reset must complete all pending TX wait SKBs */
6349
6295
rtw89_tx_wait_list_clear(rtwdev);
6350
6296
}
6351
6297
···
6674
6618
mutex_lock(&rtwdev->rf_mutex);
6675
6619
rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
6676
6620
mutex_unlock(&rtwdev->rf_mutex);
6621
+
}
6622
+
6623
+
static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr)
6624
+
{
6625
+
if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE ||
6626
+
!rtwdev->hci.ops->read32_pci_cfg)
6627
+
return RTW89_R32_EA;
6628
+
6629
+
return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr);
6677
6630
}
6678
6631
6679
6632
static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
···
7049
6984
}
7050
6985
7051
6986
static inline
7052
-
void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6987
+
void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev)
7053
6988
{
7054
6989
const struct rtw89_chip_info *chip = rtwdev->chip;
7055
6990
7056
-
if (chip->ops->bb_preinit)
7057
-
chip->ops->bb_preinit(rtwdev, phy_idx);
6991
+
if (!chip->ops->bb_preinit)
6992
+
return;
6993
+
6994
+
chip->ops->bb_preinit(rtwdev, RTW89_PHY_0);
6995
+
6996
+
if (rtwdev->dbcc_en)
6997
+
chip->ops->bb_preinit(rtwdev, RTW89_PHY_1);
7058
6998
}
7059
6999
7060
7000
static inline
···
7311
7241
{
7312
7242
const struct rtw89_chip_info *chip = rtwdev->chip;
7313
7243
7314
-
return chip->ops->get_ch_dma(rtwdev, qsel);
7244
+
return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel);
7315
7245
}
7316
7246
7317
7247
static inline
···
7442
7372
return dev_alloc_skb(length);
7443
7373
}
7444
7374
7375
+
static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev,
7376
+
struct rtw89_tx_skb_data *skb_data)
7377
+
{
7378
+
return rcu_access_pointer(skb_data->wait);
7379
+
}
7380
+
7445
7381
static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
7446
7382
struct rtw89_tx_skb_data *skb_data,
7447
-
bool tx_done)
7383
+
u8 tx_status)
7448
7384
{
7449
7385
struct rtw89_tx_wait_info *wait;
7450
-
bool ret = false;
7451
7386
7452
-
rcu_read_lock();
7387
+
guard(rcu)();
7453
7388
7454
7389
wait = rcu_dereference(skb_data->wait);
7455
7390
if (!wait)
7456
-
goto out;
7391
+
return false;
7457
7392
7458
-
ret = true;
7459
-
wait->tx_done = tx_done;
7393
+
wait->tx_done = tx_status == RTW89_TX_DONE;
7460
7394
/* Don't access skb anymore after completion */
7461
7395
complete_all(&wait->completion);
7462
-
7463
-
out:
7464
-
rcu_read_unlock();
7465
-
return ret;
7396
+
return true;
7466
7397
}
7467
7398
7468
7399
static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
···
7566
7495
void *txdesc);
7567
7496
u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel);
7568
7497
u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel);
7498
+
u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel);
7569
7499
void rtw89_core_rx(struct rtw89_dev *rtwdev,
7570
7500
struct rtw89_rx_desc_info *desc_info,
7571
7501
struct sk_buff *skb);
+299
drivers/net/wireless/realtek/rtw89/debug.c
+299
drivers/net/wireless/realtek/rtw89/debug.c
···
87
87
struct rtw89_debugfs_priv disable_dm;
88
88
struct rtw89_debugfs_priv mlo_mode;
89
89
struct rtw89_debugfs_priv beacon_info;
90
+
struct rtw89_debugfs_priv diag_mac;
90
91
};
91
92
92
93
struct rtw89_debugfs_iter_data {
···
4362
4361
return count;
4363
4362
}
4364
4363
4364
+
enum __diag_mac_cmd {
4365
+
__CMD_EQUALV,
4366
+
__CMD_EQUALO,
4367
+
__CMD_NEQUALV,
4368
+
__CMD_NEQUALO,
4369
+
__CMD_SETEQUALV,
4370
+
__CMD_SETEQUALO,
4371
+
__CMD_CMPWCR,
4372
+
__CMD_CMPWWD,
4373
+
__CMD_NEQ_CMPWCR,
4374
+
__CMD_NEQ_CMPWWD,
4375
+
__CMD_INCREMENT,
4376
+
__CMD_MESSAGE,
4377
+
};
4378
+
4379
+
enum __diag_mac_io {
4380
+
__IO_NORMAL,
4381
+
__IO_NORMAL_PCIE,
4382
+
__IO_NORMAL_USB,
4383
+
__IO_NORMAL_SDIO,
4384
+
__IO_PCIE_CFG,
4385
+
__IO_SDIO_CCCR,
4386
+
};
4387
+
4388
+
struct __diag_mac_rule_header {
4389
+
u8 sheet;
4390
+
u8 cmd;
4391
+
u8 seq_major;
4392
+
u8 seq_minor;
4393
+
u8 io_band;
4394
+
#define __DIAG_MAC_IO GENMASK(3, 0)
4395
+
#define __DIAG_MAC_N_BAND BIT(4)
4396
+
#define __DIAG_MAC_HAS_BAND BIT(5)
4397
+
u8 len; /* include header. Unit: 4 bytes */
4398
+
u8 rsvd[2];
4399
+
} __packed;
4400
+
4401
+
struct __diag_mac_rule_equal {
4402
+
struct __diag_mac_rule_header header;
4403
+
__le32 addr;
4404
+
__le32 addr_name_offset;
4405
+
__le32 mask;
4406
+
__le32 val;
4407
+
__le32 msg_offset;
4408
+
u8 rsvd[4];
4409
+
} __packed;
4410
+
4411
+
struct __diag_mac_rule_increment {
4412
+
struct __diag_mac_rule_header header;
4413
+
__le32 addr;
4414
+
__le32 addr_name_offset;
4415
+
__le32 mask;
4416
+
__le16 sel;
4417
+
__le16 delay;
4418
+
__le32 msg_offset;
4419
+
u8 rsvd[4];
4420
+
} __packed;
4421
+
4422
+
struct __diag_mac_msg_buf {
4423
+
__le16 len;
4424
+
char string[];
4425
+
} __packed;
4426
+
4427
+
static ssize_t rtw89_mac_diag_do_equalv(struct rtw89_dev *rtwdev,
4428
+
char *buf, size_t bufsz,
4429
+
const struct __diag_mac_rule_equal *r,
4430
+
const void *msg_start,
4431
+
u64 *positive_bmp)
4432
+
{
4433
+
const struct __diag_mac_msg_buf *name = msg_start +
4434
+
le32_to_cpu(r->addr_name_offset);
4435
+
const struct __diag_mac_msg_buf *msg = msg_start +
4436
+
le32_to_cpu(r->msg_offset);
4437
+
bool want_eq = r->header.cmd == __CMD_EQUALV;
4438
+
char *p = buf, *end = buf + bufsz;
4439
+
bool equal = false;
4440
+
u32 val;
4441
+
4442
+
*positive_bmp <<= 1;
4443
+
4444
+
if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG)
4445
+
val = rtw89_read32_pci_cfg(rtwdev, le32_to_cpu(r->addr));
4446
+
else
4447
+
val = rtw89_read32(rtwdev, le32_to_cpu(r->addr));
4448
+
4449
+
if ((val & le32_to_cpu(r->mask)) == le32_to_cpu(r->val))
4450
+
equal = true;
4451
+
4452
+
if (want_eq == equal) {
4453
+
*positive_bmp |= BIT(0);
4454
+
return p - buf;
4455
+
}
4456
+
4457
+
p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s => %x, %.*s\n",
4458
+
r->header.sheet, r->header.cmd, le16_to_cpu(name->len),
4459
+
name->string, val, le16_to_cpu(msg->len), msg->string);
4460
+
4461
+
return p - buf;
4462
+
}
4463
+
4464
+
static ssize_t rtw89_mac_diag_do_increment(struct rtw89_dev *rtwdev,
4465
+
char *buf, size_t bufsz,
4466
+
const struct __diag_mac_rule_increment *r,
4467
+
const void *msg_start,
4468
+
u64 *positive_bmp)
4469
+
{
4470
+
const struct __diag_mac_msg_buf *name = msg_start +
4471
+
le32_to_cpu(r->addr_name_offset);
4472
+
const struct __diag_mac_msg_buf *msg = msg_start +
4473
+
le32_to_cpu(r->msg_offset);
4474
+
char *p = buf, *end = buf + bufsz;
4475
+
u32 addr = le32_to_cpu(r->addr);
4476
+
u32 mask = le32_to_cpu(r->mask);
4477
+
u16 sel = le16_to_cpu(r->sel);
4478
+
u32 val1, val2;
4479
+
4480
+
*positive_bmp <<= 1;
4481
+
4482
+
rtw89_write32(rtwdev, addr, sel);
4483
+
4484
+
if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG)
4485
+
val1 = rtw89_read32_pci_cfg(rtwdev, addr);
4486
+
else
4487
+
val1 = rtw89_read32(rtwdev, addr);
4488
+
4489
+
mdelay(le16_to_cpu(r->delay));
4490
+
4491
+
if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG)
4492
+
val2 = rtw89_read32_pci_cfg(rtwdev, addr);
4493
+
else
4494
+
val2 = rtw89_read32(rtwdev, addr);
4495
+
4496
+
if ((val2 & mask) > (val1 & mask)) {
4497
+
*positive_bmp |= BIT(0);
4498
+
return p - buf;
4499
+
}
4500
+
4501
+
p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s [%d]=> %x, %.*s\n",
4502
+
r->header.sheet, r->header.cmd, le16_to_cpu(name->len),
4503
+
name->string, le16_to_cpu(r->sel), val1,
4504
+
le16_to_cpu(msg->len), msg->string);
4505
+
4506
+
return p - buf;
4507
+
}
4508
+
4509
+
static bool rtw89_mac_diag_match_hci(struct rtw89_dev *rtwdev,
4510
+
const struct __diag_mac_rule_header *rh)
4511
+
{
4512
+
switch (u8_get_bits(rh->io_band, __DIAG_MAC_IO)) {
4513
+
case __IO_NORMAL:
4514
+
default:
4515
+
return true;
4516
+
case __IO_NORMAL_PCIE:
4517
+
case __IO_PCIE_CFG:
4518
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
4519
+
return true;
4520
+
break;
4521
+
case __IO_NORMAL_USB:
4522
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
4523
+
return true;
4524
+
break;
4525
+
case __IO_NORMAL_SDIO:
4526
+
case __IO_SDIO_CCCR:
4527
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_SDIO)
4528
+
return true;
4529
+
break;
4530
+
}
4531
+
4532
+
return false;
4533
+
}
4534
+
4535
+
static bool rtw89_mac_diag_match_band(struct rtw89_dev *rtwdev,
4536
+
const struct __diag_mac_rule_header *rh)
4537
+
{
4538
+
u8 active_bands;
4539
+
bool has_band;
4540
+
u8 band;
4541
+
4542
+
has_band = u8_get_bits(rh->io_band, __DIAG_MAC_HAS_BAND);
4543
+
if (!has_band)
4544
+
return true;
4545
+
4546
+
band = u8_get_bits(rh->io_band, __DIAG_MAC_N_BAND);
4547
+
active_bands = rtw89_get_active_phy_bitmap(rtwdev);
4548
+
4549
+
if (active_bands & BIT(band))
4550
+
return true;
4551
+
4552
+
return false;
4553
+
}
4554
+
4555
+
static ssize_t rtw89_mac_diag_iter_all(struct rtw89_dev *rtwdev,
4556
+
char *buf, size_t bufsz)
4557
+
{
4558
+
const struct rtw89_fw_element_hdr *elm = rtwdev->fw.elm_info.diag_mac;
4559
+
u32 n_plains = 0, n_rules = 0, n_positive = 0, n_ignore = 0;
4560
+
char *p = buf, *end = buf + bufsz, *p_rewind;
4561
+
const void *rule, *rule_end;
4562
+
u32 elm_size, rule_size;
4563
+
const void *msg_start;
4564
+
u64 positive_bmp = 0;
4565
+
u8 prev_sheet = 0;
4566
+
u8 prev_seq = 0;
4567
+
int limit;
4568
+
4569
+
if (!elm) {
4570
+
p += scnprintf(p, end - p, "No diag_mac entry\n");
4571
+
goto out;
4572
+
}
4573
+
4574
+
rule_size = le32_to_cpu(elm->u.diag_mac.rule_size);
4575
+
elm_size = le32_to_cpu(elm->size);
4576
+
4577
+
if (ALIGN(rule_size, 16) > elm_size) {
4578
+
p += scnprintf(p, end - p, "rule size (%u) exceed elm_size (%u)\n",
4579
+
ALIGN(rule_size, 16), elm_size);
4580
+
goto out;
4581
+
}
4582
+
4583
+
rule = &elm->u.diag_mac.rules_and_msgs[0];
4584
+
rule_end = &elm->u.diag_mac.rules_and_msgs[rule_size];
4585
+
msg_start = &elm->u.diag_mac.rules_and_msgs[ALIGN(rule_size, 16)];
4586
+
4587
+
for (limit = 0; limit < 5000 && rule < rule_end; limit++) {
4588
+
const struct __diag_mac_rule_header *rh = rule;
4589
+
u8 sheet = rh->sheet;
4590
+
u8 seq = rh->seq_major;
4591
+
4592
+
if (!rtw89_mac_diag_match_hci(rtwdev, rh) ||
4593
+
!rtw89_mac_diag_match_band(rtwdev, rh)) {
4594
+
n_ignore++;
4595
+
goto next;
4596
+
}
4597
+
4598
+
if (!seq || prev_sheet != sheet || prev_seq != seq) {
4599
+
if (positive_bmp) {
4600
+
n_positive++;
4601
+
/*
4602
+
* discard output for negative results if one in
4603
+
* a sequence set is positive.
4604
+
*/
4605
+
if (p_rewind)
4606
+
p = p_rewind;
4607
+
}
4608
+
p_rewind = seq ? p : NULL;
4609
+
positive_bmp = 0;
4610
+
n_rules++;
4611
+
}
4612
+
4613
+
switch (rh->cmd) {
4614
+
case __CMD_EQUALV:
4615
+
case __CMD_NEQUALV:
4616
+
p += rtw89_mac_diag_do_equalv(rtwdev, p, end - p, rule,
4617
+
msg_start, &positive_bmp);
4618
+
break;
4619
+
case __CMD_INCREMENT:
4620
+
p += rtw89_mac_diag_do_increment(rtwdev, p, end - p, rule,
4621
+
msg_start, &positive_bmp);
4622
+
break;
4623
+
default:
4624
+
p += scnprintf(p, end - p, "unknown rule cmd %u\n", rh->cmd);
4625
+
break;
4626
+
}
4627
+
4628
+
next:
4629
+
n_plains++;
4630
+
rule += rh->len * 4;
4631
+
prev_seq = seq;
4632
+
prev_sheet = sheet;
4633
+
}
4634
+
4635
+
if (positive_bmp) {
4636
+
n_positive++;
4637
+
if (p_rewind)
4638
+
p = p_rewind;
4639
+
}
4640
+
4641
+
p += scnprintf(p, end - p, "\nPlain(Ignore)/Rules/Positive: %u(%u)/%u/%u\n",
4642
+
n_plains, n_ignore, n_rules, n_positive);
4643
+
4644
+
out:
4645
+
return p - buf;
4646
+
}
4647
+
4648
+
static ssize_t
4649
+
rtw89_debug_priv_diag_mac_get(struct rtw89_dev *rtwdev,
4650
+
struct rtw89_debugfs_priv *debugfs_priv,
4651
+
char *buf, size_t bufsz)
4652
+
{
4653
+
lockdep_assert_wiphy(rtwdev->hw->wiphy);
4654
+
4655
+
rtw89_leave_lps(rtwdev);
4656
+
4657
+
return rtw89_mac_diag_iter_all(rtwdev, buf, bufsz);
4658
+
}
4659
+
4365
4660
static ssize_t
4366
4661
rtw89_debug_priv_beacon_info_get(struct rtw89_dev *rtwdev,
4367
4662
struct rtw89_debugfs_priv *debugfs_priv,
···
4775
4478
.disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK),
4776
4479
.mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK),
4777
4480
.beacon_info = rtw89_debug_priv_get(beacon_info),
4481
+
.diag_mac = rtw89_debug_priv_get(diag_mac, RSIZE_16K, RLOCK),
4778
4482
};
4779
4483
4780
4484
#define rtw89_debugfs_add(name, mode, fopname, parent) \
···
4822
4524
rtw89_debugfs_add_rw(disable_dm);
4823
4525
rtw89_debugfs_add_rw(mlo_mode);
4824
4526
rtw89_debugfs_add_r(beacon_info);
4527
+
rtw89_debugfs_add_r(diag_mac);
4825
4528
}
4826
4529
4827
4530
void rtw89_debugfs_init(struct rtw89_dev *rtwdev)
+118
-51
drivers/net/wireless/realtek/rtw89/fw.c
+118
-51
drivers/net/wireless/realtek/rtw89/fw.c
···
161
161
info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_W7_DYN_HDR);
162
162
info->idmem_share_mode = le32_get_bits(fw_hdr->w7, FW_HDR_W7_IDMEM_SHARE_MODE);
163
163
164
+
if (chip->chip_gen == RTW89_CHIP_AX)
165
+
info->part_size = FWDL_SECTION_PER_PKT_LEN;
166
+
else
167
+
info->part_size = le32_get_bits(fw_hdr->w7, FW_HDR_W7_PART_SIZE);
168
+
164
169
if (info->dynamic_hdr_en) {
165
170
info->hdr_len = le32_get_bits(fw_hdr->w3, FW_HDR_W3_LEN);
166
171
info->dynamic_hdr_len = info->hdr_len - base_hdr_len;
···
444
439
struct rtw89_fw_bin_info *info)
445
440
{
446
441
const struct rtw89_fw_hdr_v1 *fw_hdr = (const struct rtw89_fw_hdr_v1 *)fw;
442
+
const struct rtw89_chip_info *chip = rtwdev->chip;
447
443
struct rtw89_fw_hdr_section_info *section_info;
448
444
const struct rtw89_fw_dynhdr_hdr *fwdynhdr;
449
445
const struct rtw89_fw_hdr_section_v1 *section;
···
460
454
base_hdr_len = struct_size(fw_hdr, sections, info->section_num);
461
455
info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_V1_W7_DYN_HDR);
462
456
info->idmem_share_mode = le32_get_bits(fw_hdr->w7, FW_HDR_V1_W7_IDMEM_SHARE_MODE);
457
+
458
+
if (chip->chip_gen == RTW89_CHIP_AX)
459
+
info->part_size = FWDL_SECTION_PER_PKT_LEN;
460
+
else
461
+
info->part_size = le32_get_bits(fw_hdr->w7, FW_HDR_V1_W7_PART_SIZE);
463
462
464
463
if (info->dynamic_hdr_en) {
465
464
info->hdr_len = le32_get_bits(fw_hdr->w5, FW_HDR_V1_W5_HDR_SIZE);
···
881
870
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 76, 0, LPS_DACK_BY_C2H_REG),
882
871
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 79, 0, CRASH_TRIGGER_TYPE_1),
883
872
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 80, 0, BEACON_TRACKING),
873
+
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0),
884
874
};
885
875
886
876
static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
···
1310
1298
return 0;
1311
1299
}
1312
1300
1301
+
static
1302
+
int rtw89_recognize_diag_mac_from_elm(struct rtw89_dev *rtwdev,
1303
+
const struct rtw89_fw_element_hdr *elm,
1304
+
const union rtw89_fw_element_arg arg)
1305
+
{
1306
+
struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1307
+
1308
+
elm_info->diag_mac = elm;
1309
+
1310
+
return 0;
1311
+
}
1312
+
1313
1313
static const struct rtw89_fw_element_handler __fw_element_handlers[] = {
1314
1314
[RTW89_FW_ELEMENT_ID_BBMCU0] = {__rtw89_fw_recognize_from_elm,
1315
1315
{ .fw_type = RTW89_FW_BBMCU0 }, NULL},
···
1409
1385
},
1410
1386
[RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ] = {
1411
1387
rtw89_build_afe_pwr_seq_from_elm, {}, "AFE",
1388
+
},
1389
+
[RTW89_FW_ELEMENT_ID_DIAG_MAC] = {
1390
+
rtw89_recognize_diag_mac_from_elm, {}, NULL,
1412
1391
},
1413
1392
};
1414
1393
···
1528
1501
struct rtw89_fw_hdr_section *section;
1529
1502
int i;
1530
1503
1531
-
le32p_replace_bits(&fw_hdr->w7, FWDL_SECTION_PER_PKT_LEN,
1532
-
FW_HDR_W7_PART_SIZE);
1504
+
le32p_replace_bits(&fw_hdr->w7, info->part_size, FW_HDR_W7_PART_SIZE);
1533
1505
1534
1506
for (i = 0; i < info->section_num; i++) {
1535
1507
section_info = &info->section_info[i];
···
1553
1527
u8 dst_sec_idx = 0;
1554
1528
u8 sec_idx;
1555
1529
1556
-
le32p_replace_bits(&fw_hdr->w7, FWDL_SECTION_PER_PKT_LEN,
1557
-
FW_HDR_V1_W7_PART_SIZE);
1530
+
le32p_replace_bits(&fw_hdr->w7, info->part_size, FW_HDR_V1_W7_PART_SIZE);
1558
1531
1559
1532
for (sec_idx = 0; sec_idx < info->section_num; sec_idx++) {
1560
1533
section_info = &info->section_info[sec_idx];
···
1655
1630
}
1656
1631
1657
1632
static int __rtw89_fw_download_main(struct rtw89_dev *rtwdev,
1658
-
struct rtw89_fw_hdr_section_info *info)
1633
+
struct rtw89_fw_hdr_section_info *info,
1634
+
u32 part_size)
1659
1635
{
1660
1636
struct sk_buff *skb;
1661
1637
const u8 *section = info->addr;
···
1677
1651
}
1678
1652
1679
1653
if (info->key_addr && info->key_len) {
1680
-
if (residue_len > FWDL_SECTION_PER_PKT_LEN || info->len < info->key_len)
1654
+
if (residue_len > part_size || info->len < info->key_len)
1681
1655
rtw89_warn(rtwdev,
1682
1656
"ignore to copy key data because of len %d, %d, %d, %d\n",
1683
-
info->len, FWDL_SECTION_PER_PKT_LEN,
1657
+
info->len, part_size,
1684
1658
info->key_len, residue_len);
1685
1659
else
1686
1660
copy_key = true;
1687
1661
}
1688
1662
1689
1663
while (residue_len) {
1690
-
if (residue_len >= FWDL_SECTION_PER_PKT_LEN)
1691
-
pkt_len = FWDL_SECTION_PER_PKT_LEN;
1692
-
else
1693
-
pkt_len = residue_len;
1664
+
pkt_len = min(residue_len, part_size);
1694
1665
1695
1666
skb = rtw89_fw_h2c_alloc_skb_no_hdr(rtwdev, pkt_len);
1696
1667
if (!skb) {
···
1742
1719
int ret;
1743
1720
1744
1721
while (section_num--) {
1745
-
ret = __rtw89_fw_download_main(rtwdev, section_info);
1722
+
ret = __rtw89_fw_download_main(rtwdev, section_info, info->part_size);
1746
1723
if (ret)
1747
1724
return ret;
1748
1725
section_info++;
···
2133
2110
2134
2111
}
2135
2112
2136
-
#define H2C_CAM_LEN 60
2137
2113
int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
2138
-
struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr)
2114
+
struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr,
2115
+
enum rtw89_upd_mode upd_mode)
2139
2116
{
2117
+
const struct rtw89_chip_info *chip = rtwdev->chip;
2118
+
struct rtw89_h2c_addr_cam_v0 *h2c_v0;
2119
+
struct rtw89_h2c_addr_cam *h2c;
2120
+
u32 len = sizeof(*h2c);
2140
2121
struct sk_buff *skb;
2122
+
u8 ver = U8_MAX;
2141
2123
int ret;
2142
2124
2143
-
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_CAM_LEN);
2125
+
if (RTW89_CHK_FW_FEATURE(ADDR_CAM_V0, &rtwdev->fw) ||
2126
+
chip->chip_gen == RTW89_CHIP_AX) {
2127
+
len = sizeof(*h2c_v0);
2128
+
ver = 0;
2129
+
}
2130
+
2131
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
2144
2132
if (!skb) {
2145
2133
rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
2146
2134
return -ENOMEM;
2147
2135
}
2148
-
skb_put(skb, H2C_CAM_LEN);
2149
-
rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif_link, rtwsta_link, scan_mac_addr,
2150
-
skb->data);
2151
-
rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif_link, rtwsta_link, skb->data);
2136
+
skb_put(skb, len);
2137
+
h2c_v0 = (struct rtw89_h2c_addr_cam_v0 *)skb->data;
2152
2138
2139
+
rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif_link, rtwsta_link,
2140
+
scan_mac_addr, h2c_v0);
2141
+
rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif_link, rtwsta_link, h2c_v0);
2142
+
2143
+
if (ver == 0)
2144
+
goto hdr;
2145
+
2146
+
h2c = (struct rtw89_h2c_addr_cam *)skb->data;
2147
+
h2c->w15 = le32_encode_bits(upd_mode, ADDR_CAM_W15_UPD_MODE);
2148
+
2149
+
hdr:
2153
2150
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
2154
2151
H2C_CAT_MAC,
2155
2152
H2C_CL_MAC_ADDR_CAM_UPDATE,
2156
2153
H2C_FUNC_MAC_ADDR_CAM_UPD, 0, 1,
2157
-
H2C_CAM_LEN);
2154
+
len);
2158
2155
2159
2156
ret = rtw89_h2c_tx(rtwdev, skb, false);
2160
2157
if (ret) {
···
3208
3165
SET_CMC_TBL_ANTSEL_C(skb->data, 0);
3209
3166
SET_CMC_TBL_ANTSEL_D(skb->data, 0);
3210
3167
}
3168
+
SET_CMC_TBL_MGQ_RPT_EN(skb->data, rtwdev->hci.tx_rpt_enabled);
3211
3169
SET_CMC_TBL_DOPPLER_CTRL(skb->data, 0);
3212
3170
SET_CMC_TBL_TXPWR_TOLERENCE(skb->data, 0);
3213
3171
if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE)
···
3254
3210
h2c->c0 = le32_encode_bits(mac_id, CCTLINFO_G7_C0_MACID) |
3255
3211
le32_encode_bits(1, CCTLINFO_G7_C0_OP);
3256
3212
3257
-
h2c->w0 = le32_encode_bits(4, CCTLINFO_G7_W0_DATARATE);
3213
+
h2c->w0 = le32_encode_bits(4, CCTLINFO_G7_W0_DATARATE) |
3214
+
le32_encode_bits(rtwdev->hci.tx_rpt_enabled, CCTLINFO_G7_W0_MGQ_RPT_EN);
3258
3215
h2c->m0 = cpu_to_le32(CCTLINFO_G7_W0_ALL);
3259
3216
3260
3217
h2c->w1 = le32_encode_bits(4, CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE) |
···
4760
4715
struct rtw89_h2c_ra_v1 *h2c_v1;
4761
4716
struct rtw89_h2c_ra *h2c;
4762
4717
u32 len = sizeof(*h2c);
4763
-
bool format_v1 = false;
4764
4718
struct sk_buff *skb;
4719
+
u8 ver = U8_MAX;
4765
4720
int ret;
4766
4721
4767
-
if (chip->chip_gen == RTW89_CHIP_BE) {
4722
+
if (chip->chip_gen == RTW89_CHIP_AX) {
4723
+
len = sizeof(*h2c);
4724
+
ver = 0;
4725
+
} else {
4768
4726
len = sizeof(*h2c_v1);
4769
-
format_v1 = true;
4727
+
ver = 1;
4770
4728
}
4771
4729
4772
4730
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
···
4801
4753
h2c->w3 = le32_encode_bits(ra->fix_giltf_en, RTW89_H2C_RA_W3_FIX_GILTF_EN) |
4802
4754
le32_encode_bits(ra->fix_giltf, RTW89_H2C_RA_W3_FIX_GILTF);
4803
4755
4804
-
if (!format_v1)
4805
-
goto csi;
4806
-
4807
-
h2c_v1 = (struct rtw89_h2c_ra_v1 *)h2c;
4808
-
h2c_v1->w4 = le32_encode_bits(ra->mode_ctrl, RTW89_H2C_RA_V1_W4_MODE_EHT) |
4809
-
le32_encode_bits(ra->bw_cap, RTW89_H2C_RA_V1_W4_BW_EHT);
4810
-
4811
-
csi:
4812
-
if (!csi)
4813
-
goto done;
4756
+
if (!csi || ver >= 1)
4757
+
goto next_v1;
4814
4758
4815
4759
h2c->w2 |= le32_encode_bits(1, RTW89_H2C_RA_W2_BFEE_CSI_CTL);
4816
4760
h2c->w3 |= le32_encode_bits(ra->band_num, RTW89_H2C_RA_W3_BAND_NUM) |
···
4813
4773
le32_encode_bits(ra->csi_mode, RTW89_H2C_RA_W3_FIXED_CSI_MODE) |
4814
4774
le32_encode_bits(ra->csi_gi_ltf, RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF) |
4815
4775
le32_encode_bits(ra->csi_bw, RTW89_H2C_RA_W3_FIXED_CSI_BW);
4776
+
4777
+
next_v1:
4778
+
if (ver < 1)
4779
+
goto done;
4780
+
4781
+
h2c->w3 |= le32_encode_bits(ra->partial_bw_er,
4782
+
RTW89_H2C_RA_V1_W3_PARTIAL_BW_SU_ER) |
4783
+
le32_encode_bits(ra->band, RTW89_H2C_RA_V1_W3_BAND);
4784
+
4785
+
h2c_v1 = (struct rtw89_h2c_ra_v1 *)h2c;
4786
+
h2c_v1->w4 = le32_encode_bits(ra->mode_ctrl, RTW89_H2C_RA_V1_W4_MODE_EHT) |
4787
+
le32_encode_bits(ra->bw_cap, RTW89_H2C_RA_V1_W4_BW_EHT);
4816
4788
4817
4789
done:
4818
4790
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
···
6943
6891
struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
6944
6892
c2h_work);
6945
6893
struct sk_buff *skb, *tmp;
6894
+
struct sk_buff_head c2hq;
6895
+
unsigned long flags;
6946
6896
6947
6897
lockdep_assert_wiphy(rtwdev->hw->wiphy);
6948
6898
6949
-
skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
6950
-
skb_unlink(skb, &rtwdev->c2h_queue);
6899
+
__skb_queue_head_init(&c2hq);
6900
+
6901
+
spin_lock_irqsave(&rtwdev->c2h_queue.lock, flags);
6902
+
skb_queue_splice_init(&rtwdev->c2h_queue, &c2hq);
6903
+
spin_unlock_irqrestore(&rtwdev->c2h_queue.lock, flags);
6904
+
6905
+
skb_queue_walk_safe(&c2hq, skb, tmp) {
6951
6906
rtw89_fw_c2h_cmd_handle(rtwdev, skb);
6952
6907
dev_kfree_skb_any(skb);
6953
6908
}
···
6964
6905
{
6965
6906
struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
6966
6907
struct sk_buff *skb, *tmp;
6967
-
int limit;
6908
+
struct sk_buff_head c2hq;
6909
+
unsigned long flags;
6968
6910
6969
6911
lockdep_assert_wiphy(rtwdev->hw->wiphy);
6970
6912
6971
-
limit = skb_queue_len(&rtwdev->c2h_queue);
6913
+
__skb_queue_head_init(&c2hq);
6972
6914
6973
-
skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
6915
+
spin_lock_irqsave(&rtwdev->c2h_queue.lock, flags);
6916
+
skb_queue_splice_init(&rtwdev->c2h_queue, &c2hq);
6917
+
spin_unlock_irqrestore(&rtwdev->c2h_queue.lock, flags);
6918
+
6919
+
skb_queue_walk_safe(&c2hq, skb, tmp) {
6974
6920
struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb);
6975
-
6976
-
if (--limit < 0)
6977
-
return;
6978
6921
6979
6922
if (!attr->is_scan_event || attr->scan_seq == scan_info->seq)
6980
6923
continue;
···
6985
6924
"purge obsoleted scan event with seq=%d (cur=%d)\n",
6986
6925
attr->scan_seq, scan_info->seq);
6987
6926
6988
-
skb_unlink(skb, &rtwdev->c2h_queue);
6927
+
__skb_unlink(skb, &c2hq);
6989
6928
dev_kfree_skb_any(skb);
6990
6929
}
6930
+
6931
+
spin_lock_irqsave(&rtwdev->c2h_queue.lock, flags);
6932
+
skb_queue_splice(&c2hq, &rtwdev->c2h_queue);
6933
+
spin_unlock_irqrestore(&rtwdev->c2h_queue.lock, flags);
6991
6934
}
6992
6935
6993
6936
static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev,
···
7839
7774
struct ieee80211_channel *channel;
7840
7775
struct list_head chan_list;
7841
7776
enum rtw89_chan_type type;
7777
+
bool chan_by_rnr;
7842
7778
bool random_seq;
7843
7779
int ret;
7844
7780
u32 idx;
7845
7781
7846
7782
random_seq = !!(req->flags & NL80211_SCAN_FLAG_RANDOM_SN);
7783
+
chan_by_rnr = rtwdev->chip->support_rnr &&
7784
+
(req->flags & NL80211_SCAN_FLAG_COLOCATED_6GHZ);
7847
7785
INIT_LIST_HEAD(&chan_list);
7848
7786
7849
7787
for (idx = 0; idx < req->n_channels; idx++) {
7850
7788
channel = req->channels[idx];
7789
+
7790
+
if (channel->band == NL80211_BAND_6GHZ &&
7791
+
!cfg80211_channel_is_psc(channel) && chan_by_rnr)
7792
+
continue;
7793
+
7851
7794
ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
7852
7795
if (!ch_info) {
7853
7796
ret = -ENOMEM;
···
8103
8030
struct rtw89_vif_link *rtwvif_link,
8104
8031
struct ieee80211_scan_request *scan_req)
8105
8032
{
8106
-
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
8107
8033
enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
8108
8034
struct cfg80211_scan_request *req = &scan_req->req;
8109
8035
const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
···
8114
8042
};
8115
8043
u32 rx_fltr = rtwdev->hal.rx_fltr;
8116
8044
u8 mac_addr[ETH_ALEN];
8117
-
u32 reg;
8118
8045
int ret;
8119
8046
8120
8047
/* clone op and keep it during scan */
···
8153
8082
rx_fltr &= ~B_AX_A_BC;
8154
8083
rx_fltr &= ~B_AX_A_A1_MATCH;
8155
8084
8156
-
reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
8157
-
rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rx_fltr);
8085
+
rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rx_fltr);
8158
8086
8159
8087
rtw89_chanctx_pause(rtwdev, &pause_parm);
8160
8088
rtw89_phy_dig_suspend(rtwdev);
···
8171
8101
8172
8102
static int rtw89_hw_scan_complete_cb(struct rtw89_dev *rtwdev, void *data)
8173
8103
{
8174
-
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
8175
8104
enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
8176
8105
struct rtw89_hw_scan_complete_cb_data *cb_data = data;
8177
8106
struct rtw89_vif_link *rtwvif_link = cb_data->rtwvif_link;
8178
8107
struct cfg80211_scan_info info = {
8179
8108
.aborted = cb_data->aborted,
8180
8109
};
8181
-
u32 reg;
8182
8110
8183
8111
if (!rtwvif_link)
8184
8112
return -EINVAL;
8185
8113
8186
-
reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
8187
-
rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr);
8114
+
rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr);
8188
8115
8189
8116
rtw89_core_scan_complete(rtwdev, rtwvif_link, true);
8190
8117
ieee80211_scan_completed(rtwdev->hw, &info);
+66
-1
drivers/net/wireless/realtek/rtw89/fw.h
+66
-1
drivers/net/wireless/realtek/rtw89/fw.h
···
297
297
298
298
struct rtw89_fw_bin_info {
299
299
u8 section_num;
300
+
u32 part_size;
300
301
u32 hdr_len;
301
302
bool dynamic_hdr_en;
302
303
u32 dynamic_hdr_len;
···
447
446
#define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
448
447
#define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
449
448
#define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
449
+
#define RTW89_H2C_RA_V1_W3_PARTIAL_BW_SU_ER BIT(15)
450
+
#define RTW89_H2C_RA_V1_W3_FIXED_CSI_RATE_L GENMASK(23, 16)
451
+
#define RTW89_H2C_RA_V1_W3_IS_NOISY BIT(24)
452
+
#define RTW89_H2C_RA_V1_W3_PSRA_EN BIT(25)
453
+
#define RTW89_H2C_RA_V1_W3_MACID_MSB GENMASK(28, 27)
454
+
#define RTW89_H2C_RA_V1_W3_BAND GENMASK(30, 29)
455
+
#define RTW89_H2C_RA_V1_W3_NEW_DBGREG BIT(31)
450
456
451
457
struct rtw89_h2c_ra_v1 {
452
458
struct rtw89_h2c_ra v0;
···
3655
3647
#define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3656
3648
#define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3657
3649
3650
+
struct rtw89_c2h_bcn_upd_done {
3651
+
struct rtw89_c2h_hdr hdr;
3652
+
__le32 w2;
3653
+
} __packed;
3654
+
3655
+
#define RTW89_C2H_BCN_UPD_DONE_W2_PORT GENMASK(2, 0)
3656
+
#define RTW89_C2H_BCN_UPD_DONE_W2_MBSSID GENMASK(6, 3)
3657
+
#define RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX BIT(7)
3658
+
3658
3659
struct rtw89_c2h_mac_bcnfltr_rpt {
3659
3660
__le32 w0;
3660
3661
__le32 w1;
···
3763
3746
le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3764
3747
#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3765
3748
le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3749
+
3750
+
struct rtw89_c2h_mac_tx_rpt {
3751
+
struct rtw89_c2h_hdr hdr;
3752
+
__le32 w2;
3753
+
__le32 w3;
3754
+
__le32 w4;
3755
+
__le32 w5;
3756
+
__le32 w6;
3757
+
__le32 w7;
3758
+
} __packed;
3759
+
3760
+
#define RTW89_C2H_MAC_TX_RPT_W2_TX_STATE GENMASK(7, 6)
3761
+
#define RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE GENMASK(11, 8)
3762
+
#define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT GENMASK(13, 8)
3763
+
#define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1 GENMASK(15, 10)
3764
+
3765
+
struct rtw89_c2h_mac_tx_rpt_v2 {
3766
+
struct rtw89_c2h_hdr hdr;
3767
+
__le32 w2;
3768
+
__le32 w3;
3769
+
__le32 w4;
3770
+
__le32 w5;
3771
+
__le32 w6;
3772
+
__le32 w7;
3773
+
__le32 w8;
3774
+
__le32 w9;
3775
+
__le32 w10;
3776
+
__le32 w11;
3777
+
__le32 w12;
3778
+
__le32 w13;
3779
+
__le32 w14;
3780
+
__le32 w15;
3781
+
__le32 w16;
3782
+
__le32 w17;
3783
+
__le32 w18;
3784
+
__le32 w19;
3785
+
} __packed;
3786
+
3787
+
#define RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2 GENMASK(9, 8)
3788
+
#define RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2 GENMASK(15, 12)
3789
+
#define RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2 GENMASK(15, 10)
3766
3790
3767
3791
struct rtw89_mac_mcc_tsf_rpt {
3768
3792
u32 macid_x;
···
4043
3985
RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_5GHZ = 25,
4044
3986
RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26,
4045
3987
RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ = 27,
3988
+
RTW89_FW_ELEMENT_ID_DIAG_MAC = 28,
4046
3989
4047
3990
RTW89_FW_ELEMENT_ID_NUM,
4048
3991
};
···
4221
4162
__le32 val;
4222
4163
} __packed infos[];
4223
4164
} __packed afe;
4165
+
struct {
4166
+
__le32 rule_size;
4167
+
u8 rsvd[4];
4168
+
u8 rules_and_msgs[];
4169
+
} __packed diag_mac;
4224
4170
struct __rtw89_fw_txpwr_element txpwr;
4225
4171
struct __rtw89_fw_regd_element regd;
4226
4172
} __packed u;
···
4887
4823
struct rtw89_vif_link *rtwvif_link, u32 offset);
4888
4824
int rtw89_fw_h2c_pwr_lvl(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
4889
4825
int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
4890
-
struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr);
4826
+
struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr,
4827
+
enum rtw89_upd_mode upd_mode);
4891
4828
int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4892
4829
struct rtw89_vif_link *rtwvif_link,
4893
4830
struct rtw89_sta_link *rtwsta_link);
+184
-16
drivers/net/wireless/realtek/rtw89/mac.c
+184
-16
drivers/net/wireless/realtek/rtw89/mac.c
···
12
12
#include "phy.h"
13
13
#include "ps.h"
14
14
#include "reg.h"
15
+
#include "ser.h"
15
16
#include "util.h"
16
17
17
18
static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = {
···
1295
1294
static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,
1296
1295
const struct rtw89_pwr_cfg * const *cfg_seq)
1297
1296
{
1297
+
u8 intf_msk;
1298
1298
int ret;
1299
+
1300
+
switch (rtwdev->hci.type) {
1301
+
case RTW89_HCI_TYPE_PCIE:
1302
+
intf_msk = PWR_INTF_MSK_PCIE;
1303
+
break;
1304
+
case RTW89_HCI_TYPE_USB:
1305
+
intf_msk = PWR_INTF_MSK_USB;
1306
+
break;
1307
+
case RTW89_HCI_TYPE_SDIO:
1308
+
intf_msk = PWR_INTF_MSK_SDIO;
1309
+
break;
1310
+
default:
1311
+
return -EOPNOTSUPP;
1312
+
}
1299
1313
1300
1314
for (; *cfg_seq; cfg_seq++) {
1301
1315
ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
1302
-
PWR_INTF_MSK_PCIE, *cfg_seq);
1316
+
intf_msk, *cfg_seq);
1303
1317
if (ret)
1304
1318
return -EBUSY;
1305
1319
}
···
1439
1423
if (!ret)
1440
1424
break;
1441
1425
1442
-
if (i == RPWM_TRY_CNT - 1)
1426
+
if (i == RPWM_TRY_CNT - 1) {
1443
1427
rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n",
1444
1428
enter ? "entering" : "leaving");
1445
-
else
1429
+
rtw89_ser_notify(rtwdev, MAC_AX_ERR_ASSERTION);
1430
+
} else {
1446
1431
rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
1447
1432
"%d time firmware failed to ack for %s ps mode\n",
1448
1433
i + 1, enter ? "entering" : "leaving");
1434
+
}
1449
1435
}
1450
1436
}
1451
1437
···
1669
1651
/* PCIE 64 */
1670
1652
.wde_size0 = {RTW89_WDE_PG_64, 4095, 1,},
1671
1653
.wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,},
1654
+
/* 8852A USB */
1655
+
.wde_size1 = {RTW89_WDE_PG_64, 768, 0,},
1672
1656
/* DLFW */
1673
1657
.wde_size4 = {RTW89_WDE_PG_64, 0, 4096,},
1674
1658
.wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,},
···
1680
1660
.wde_size7 = {RTW89_WDE_PG_64, 510, 2,},
1681
1661
/* DLFW */
1682
1662
.wde_size9 = {RTW89_WDE_PG_64, 0, 1024,},
1663
+
/* 8852C USB3.0 */
1664
+
.wde_size17 = {RTW89_WDE_PG_64, 354, 30,},
1683
1665
/* 8852C DLFW */
1684
1666
.wde_size18 = {RTW89_WDE_PG_64, 0, 2048,},
1685
1667
/* 8852C PCIE SCC */
···
1689
1667
.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
1690
1668
/* 8852B USB2.0/USB3.0 SCC */
1691
1669
.wde_size25 = {RTW89_WDE_PG_64, 162, 94,},
1670
+
/* 8852C USB2.0 */
1671
+
.wde_size31 = {RTW89_WDE_PG_64, 384, 0,},
1692
1672
/* PCIE */
1693
1673
.ple_size0 = {RTW89_PLE_PG_128, 1520, 16,},
1694
1674
.ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,},
1675
+
/* 8852A USB */
1676
+
.ple_size1 = {RTW89_PLE_PG_128, 3184, 16,},
1695
1677
.ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,},
1696
1678
/* DLFW */
1697
1679
.ple_size4 = {RTW89_PLE_PG_128, 64, 1472,},
···
1704
1678
/* DLFW */
1705
1679
.ple_size8 = {RTW89_PLE_PG_128, 64, 960,},
1706
1680
.ple_size9 = {RTW89_PLE_PG_128, 2288, 16,},
1681
+
/* 8852C USB */
1682
+
.ple_size17 = {RTW89_PLE_PG_128, 3368, 24,},
1707
1683
/* 8852C DLFW */
1708
1684
.ple_size18 = {RTW89_PLE_PG_128, 2544, 16,},
1709
1685
/* 8852C PCIE SCC */
···
1714
1686
.ple_size32 = {RTW89_PLE_PG_128, 620, 20,},
1715
1687
/* 8852B USB3.0 SCC */
1716
1688
.ple_size33 = {RTW89_PLE_PG_128, 632, 8,},
1689
+
/* 8852C USB2.0 */
1690
+
.ple_size34 = {RTW89_PLE_PG_128, 3374, 18,},
1717
1691
/* PCIE 64 */
1718
1692
.wde_qt0 = {3792, 196, 0, 107,},
1719
1693
.wde_qt0_v1 = {3302, 6, 0, 20,},
1694
+
/* 8852A USB */
1695
+
.wde_qt1 = {512, 196, 0, 60,},
1720
1696
/* DLFW */
1721
1697
.wde_qt4 = {0, 0, 0, 0,},
1722
1698
/* PCIE 64 */
1723
1699
.wde_qt6 = {448, 48, 0, 16,},
1724
1700
/* 8852B PCIE SCC */
1725
1701
.wde_qt7 = {446, 48, 0, 16,},
1702
+
/* 8852C USB3.0 */
1703
+
.wde_qt16 = {344, 2, 0, 8,},
1726
1704
/* 8852C DLFW */
1727
1705
.wde_qt17 = {0, 0, 0, 0,},
1728
1706
/* 8852C PCIE SCC */
···
1736
1702
.wde_qt23 = {958, 48, 0, 16,},
1737
1703
/* 8852B USB2.0/USB3.0 SCC */
1738
1704
.wde_qt25 = {152, 2, 0, 8,},
1705
+
/* 8852C USB2.0 */
1706
+
.wde_qt31 = {338, 6, 0, 40,},
1739
1707
.ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,},
1740
1708
.ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,},
1741
1709
/* PCIE SCC */
···
1749
1713
.ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,},
1750
1714
/* PCIE 64 */
1751
1715
.ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,},
1716
+
/* 8852A USB SCC */
1717
+
.ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,},
1718
+
.ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,},
1719
+
/* USB 52C USB3.0 */
1720
+
.ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
1721
+
/* USB 52C USB3.0 */
1722
+
.ple_qt43 = {3068, 0, 32, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
1752
1723
/* DLFW 52C */
1753
1724
.ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
1754
1725
/* DLFW 52C */
···
1775
1732
/* USB3.0 52B 92K */
1776
1733
.ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,},
1777
1734
.ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,},
1735
+
/* USB2.0 52C */
1736
+
.ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,},
1737
+
/* USB2.0 52C */
1738
+
.ple_qt79 = {1560, 0, 32, 48, 1253, 13, 1630, 0, 1272, 38, 120, 1256, 0,},
1778
1739
/* 8852A PCIE WOW */
1779
1740
.ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,},
1780
1741
/* 8852B PCIE WOW */
···
2371
2324
if (chip->chip_id == RTL8852C)
2372
2325
val |= B_AX_UC_MGNT_DEC;
2373
2326
if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
2374
-
chip->chip_id == RTL8851B)
2327
+
chip->chip_id == RTL8851B ||
2328
+
(chip->chip_id == RTL8852C && rtwdev->hci.type == RTW89_HCI_TYPE_USB))
2375
2329
val &= ~B_AX_TX_PARTIAL_MODE;
2376
2330
rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
2377
2331
···
2541
2493
rtw89_write32(rtwdev, reg, val);
2542
2494
2543
2495
return 0;
2496
+
}
2497
+
2498
+
void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr)
2499
+
{
2500
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2501
+
u32 reg;
2502
+
u32 val;
2503
+
2504
+
reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, mac_idx);
2505
+
2506
+
val = rtw89_read32(rtwdev, reg);
2507
+
/* B_AX_RX_FLTR_CFG_MASK is not a consecutive bit mask */
2508
+
val = (val & ~B_AX_RX_FLTR_CFG_MASK) | (rx_fltr & B_AX_RX_FLTR_CFG_MASK);
2509
+
rtw89_write32(rtwdev, reg, val);
2544
2510
}
2545
2511
2546
2512
static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
···
4042
3980
4043
3981
val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
4044
3982
val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST);
4045
-
val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) |
4046
-
B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1;
3983
+
val |= B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1;
3984
+
3985
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
3986
+
val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B);
3987
+
else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
3988
+
val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_USB);
3989
+
else
3990
+
val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_SDIO);
3991
+
4047
3992
rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
4048
3993
4049
3994
rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1,
···
4118
4049
rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
4119
4050
4120
4051
if (include_bb) {
4121
-
rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0);
4122
-
if (rtwdev->dbcc_en)
4123
-
rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1);
4052
+
/* Only call BB preinit including configuration of BB MCU for
4053
+
* the chips which need to download BB MCU firmware. Otherwise,
4054
+
* calling preinit later to prevent touching registers affecting
4055
+
* download firmware.
4056
+
*/
4057
+
rtw89_chip_bb_preinit(rtwdev);
4124
4058
}
4125
4059
4126
4060
ret = rtw89_mac_dmac_pre_init(rtwdev);
···
4143
4071
return 0;
4144
4072
}
4145
4073
4074
+
int rtw89_mac_preinit(struct rtw89_dev *rtwdev)
4075
+
{
4076
+
int ret;
4077
+
4078
+
ret = rtw89_mac_pwr_on(rtwdev);
4079
+
if (ret)
4080
+
return ret;
4081
+
4082
+
return 0;
4083
+
}
4084
+
4146
4085
int rtw89_mac_init(struct rtw89_dev *rtwdev)
4147
4086
{
4148
4087
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4149
4088
const struct rtw89_chip_info *chip = rtwdev->chip;
4150
4089
bool include_bb = !!chip->bbmcu_nr;
4151
4090
int ret;
4152
-
4153
-
ret = rtw89_mac_pwr_on(rtwdev);
4154
-
if (ret)
4155
-
return ret;
4156
4091
4157
4092
ret = rtw89_mac_partial_init(rtwdev, include_bb);
4158
4093
if (ret)
···
4849
4770
if (ret)
4850
4771
return ret;
4851
4772
4852
-
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
4773
+
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_CREATE);
4853
4774
if (ret)
4854
4775
return ret;
4855
4776
···
4874
4795
4875
4796
rtw89_cam_deinit(rtwdev, rtwvif_link);
4876
4797
4877
-
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
4798
+
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_REMOVE);
4878
4799
if (ret)
4879
4800
return ret;
4880
4801
···
5323
5244
}
5324
5245
5325
5246
static void
5326
-
rtw89_mac_c2h_bcn_upd_done(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5247
+
rtw89_mac_c2h_bcn_upd_done(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)
5327
5248
{
5249
+
const struct rtw89_c2h_bcn_upd_done *c2h =
5250
+
(const struct rtw89_c2h_bcn_upd_done *)skb_c2h->data;
5251
+
u8 band, port, mbssid;
5252
+
5253
+
port = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_PORT);
5254
+
mbssid = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_MBSSID);
5255
+
band = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX);
5256
+
5257
+
rtw89_debug(rtwdev, RTW89_DBG_FW,
5258
+
"BCN update done on port:%d mbssid:%d band:%d\n",
5259
+
port, mbssid, band);
5328
5260
}
5329
5261
5330
5262
static void
···
5545
5455
data.err = err;
5546
5456
cond = RTW89_MCC_WAIT_COND(group, func);
5547
5457
rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5458
+
}
5459
+
5460
+
static void
5461
+
rtw89_mac_c2h_tx_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5462
+
{
5463
+
struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
5464
+
struct rtw89_tx_skb_data *skb_data;
5465
+
u8 sw_define, tx_status, txcnt;
5466
+
struct sk_buff *skb;
5467
+
5468
+
if (rtwdev->chip->chip_id == RTL8922A) {
5469
+
const struct rtw89_c2h_mac_tx_rpt_v2 *rpt_v2;
5470
+
5471
+
rpt_v2 = (const struct rtw89_c2h_mac_tx_rpt_v2 *)c2h->data;
5472
+
sw_define = le32_get_bits(rpt_v2->w12,
5473
+
RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2);
5474
+
tx_status = le32_get_bits(rpt_v2->w12,
5475
+
RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2);
5476
+
txcnt = le32_get_bits(rpt_v2->w14,
5477
+
RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2);
5478
+
} else {
5479
+
const struct rtw89_c2h_mac_tx_rpt *rpt;
5480
+
5481
+
rpt = (const struct rtw89_c2h_mac_tx_rpt *)c2h->data;
5482
+
sw_define = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE);
5483
+
tx_status = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_TX_STATE);
5484
+
if (rtwdev->chip->chip_id == RTL8852C)
5485
+
txcnt = le32_get_bits(rpt->w5,
5486
+
RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1);
5487
+
else
5488
+
txcnt = le32_get_bits(rpt->w5,
5489
+
RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT);
5490
+
}
5491
+
5492
+
rtw89_debug(rtwdev, RTW89_DBG_TXRX,
5493
+
"C2H TX RPT: sn %d, tx_status %d, txcnt %d\n",
5494
+
sw_define, tx_status, txcnt);
5495
+
5496
+
/* claim sw_define is not over size of tx_rpt->skbs[] */
5497
+
static_assert(hweight32(RTW89_MAX_TX_RPTS_MASK) ==
5498
+
hweight32(RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2) &&
5499
+
hweight32(RTW89_MAX_TX_RPTS_MASK) ==
5500
+
hweight32(RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE));
5501
+
5502
+
scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) {
5503
+
skb = tx_rpt->skbs[sw_define];
5504
+
5505
+
/* skip if no skb (normally shouldn't happen) */
5506
+
if (!skb) {
5507
+
rtw89_debug(rtwdev, RTW89_DBG_TXRX,
5508
+
"C2H TX RPT: no skb found in queue\n");
5509
+
return;
5510
+
}
5511
+
5512
+
skb_data = RTW89_TX_SKB_CB(skb);
5513
+
5514
+
/* skip if TX attempt has failed and retry limit has not been
5515
+
* reached yet
5516
+
*/
5517
+
if (tx_status != RTW89_TX_DONE &&
5518
+
txcnt != skb_data->tx_pkt_cnt_lmt)
5519
+
return;
5520
+
5521
+
tx_rpt->skbs[sw_define] = NULL;
5522
+
rtw89_tx_rpt_tx_status(rtwdev, skb, tx_status);
5523
+
}
5548
5524
}
5549
5525
5550
5526
static void
···
5848
5692
};
5849
5693
5850
5694
static
5695
+
void (* const rtw89_mac_c2h_misc_handler[])(struct rtw89_dev *rtwdev,
5696
+
struct sk_buff *c2h, u32 len) = {
5697
+
[RTW89_MAC_C2H_FUNC_TX_REPORT] = rtw89_mac_c2h_tx_rpt,
5698
+
};
5699
+
5700
+
static
5851
5701
void (* const rtw89_mac_c2h_mlo_handler[])(struct rtw89_dev *rtwdev,
5852
5702
struct sk_buff *c2h, u32 len) = {
5853
5703
[RTW89_MAC_C2H_FUNC_MLO_GET_TBL] = NULL,
···
5939
5777
}
5940
5778
case RTW89_MAC_C2H_CLASS_MCC:
5941
5779
return true;
5780
+
case RTW89_MAC_C2H_CLASS_MISC:
5781
+
return true;
5942
5782
case RTW89_MAC_C2H_CLASS_MLO:
5943
5783
return true;
5944
5784
case RTW89_MAC_C2H_CLASS_MRC:
···
5975
5811
case RTW89_MAC_C2H_CLASS_MCC:
5976
5812
if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC)
5977
5813
handler = rtw89_mac_c2h_mcc_handler[func];
5814
+
break;
5815
+
case RTW89_MAC_C2H_CLASS_MISC:
5816
+
if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MISC)
5817
+
handler = rtw89_mac_c2h_misc_handler[func];
5978
5818
break;
5979
5819
case RTW89_MAC_C2H_CLASS_MLO:
5980
5820
if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MLO)
+112
-2
drivers/net/wireless/realtek/rtw89/mac.h
+112
-2
drivers/net/wireless/realtek/rtw89/mac.h
···
432
432
NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
433
433
};
434
434
435
+
enum rtw89_mac_c2h_misc_func {
436
+
RTW89_MAC_C2H_FUNC_TX_REPORT = 1,
437
+
438
+
NUM_OF_RTW89_MAC_C2H_FUNC_MISC,
439
+
};
440
+
435
441
enum rtw89_mac_c2h_mlo_func {
436
442
RTW89_MAC_C2H_FUNC_MLO_GET_TBL = 0x0,
437
443
RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE = 0x1,
···
476
470
RTW89_MAC_C2H_CLASS_WOW = 0x3,
477
471
RTW89_MAC_C2H_CLASS_MCC = 0x4,
478
472
RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
473
+
RTW89_MAC_C2H_CLASS_MISC = 0x9,
479
474
RTW89_MAC_C2H_CLASS_MLO = 0xc,
480
475
RTW89_MAC_C2H_CLASS_MRC = 0xe,
481
476
RTW89_MAC_C2H_CLASS_AP = 0x18,
···
581
574
RTW89_MAC_BF_RRSC_MAX = 32
582
575
};
583
576
584
-
#define RTW89_R32_EA 0xEAEAEAEA
585
-
#define RTW89_R32_DEAD 0xDEADBEEF
586
577
#define MAC_REG_POOL_COUNT 10
587
578
#define ACCESS_CMAC(_addr) \
588
579
({typeof(_addr) __addr = (_addr); \
···
922
917
const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
923
918
const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
924
919
const struct rtw89_dle_size wde_size0;
920
+
const struct rtw89_dle_size wde_size1;
925
921
const struct rtw89_dle_size wde_size0_v1;
926
922
const struct rtw89_dle_size wde_size4;
927
923
const struct rtw89_dle_size wde_size4_v1;
928
924
const struct rtw89_dle_size wde_size6;
929
925
const struct rtw89_dle_size wde_size7;
930
926
const struct rtw89_dle_size wde_size9;
927
+
const struct rtw89_dle_size wde_size17;
931
928
const struct rtw89_dle_size wde_size18;
932
929
const struct rtw89_dle_size wde_size19;
933
930
const struct rtw89_dle_size wde_size23;
934
931
const struct rtw89_dle_size wde_size25;
932
+
const struct rtw89_dle_size wde_size31;
935
933
const struct rtw89_dle_size ple_size0;
934
+
const struct rtw89_dle_size ple_size1;
936
935
const struct rtw89_dle_size ple_size0_v1;
937
936
const struct rtw89_dle_size ple_size3_v1;
938
937
const struct rtw89_dle_size ple_size4;
939
938
const struct rtw89_dle_size ple_size6;
940
939
const struct rtw89_dle_size ple_size8;
941
940
const struct rtw89_dle_size ple_size9;
941
+
const struct rtw89_dle_size ple_size17;
942
942
const struct rtw89_dle_size ple_size18;
943
943
const struct rtw89_dle_size ple_size19;
944
944
const struct rtw89_dle_size ple_size32;
945
945
const struct rtw89_dle_size ple_size33;
946
+
const struct rtw89_dle_size ple_size34;
946
947
const struct rtw89_wde_quota wde_qt0;
948
+
const struct rtw89_wde_quota wde_qt1;
947
949
const struct rtw89_wde_quota wde_qt0_v1;
948
950
const struct rtw89_wde_quota wde_qt4;
949
951
const struct rtw89_wde_quota wde_qt6;
950
952
const struct rtw89_wde_quota wde_qt7;
953
+
const struct rtw89_wde_quota wde_qt16;
951
954
const struct rtw89_wde_quota wde_qt17;
952
955
const struct rtw89_wde_quota wde_qt18;
953
956
const struct rtw89_wde_quota wde_qt23;
954
957
const struct rtw89_wde_quota wde_qt25;
958
+
const struct rtw89_wde_quota wde_qt31;
955
959
const struct rtw89_ple_quota ple_qt0;
956
960
const struct rtw89_ple_quota ple_qt1;
957
961
const struct rtw89_ple_quota ple_qt4;
···
968
954
const struct rtw89_ple_quota ple_qt9;
969
955
const struct rtw89_ple_quota ple_qt13;
970
956
const struct rtw89_ple_quota ple_qt18;
957
+
const struct rtw89_ple_quota ple_qt25;
958
+
const struct rtw89_ple_quota ple_qt26;
959
+
const struct rtw89_ple_quota ple_qt42;
960
+
const struct rtw89_ple_quota ple_qt43;
971
961
const struct rtw89_ple_quota ple_qt44;
972
962
const struct rtw89_ple_quota ple_qt45;
973
963
const struct rtw89_ple_quota ple_qt46;
···
983
965
const struct rtw89_ple_quota ple_qt73;
984
966
const struct rtw89_ple_quota ple_qt74;
985
967
const struct rtw89_ple_quota ple_qt75;
968
+
const struct rtw89_ple_quota ple_qt78;
969
+
const struct rtw89_ple_quota ple_qt79;
986
970
const struct rtw89_ple_quota ple_qt_52a_wow;
987
971
const struct rtw89_ple_quota ple_qt_52b_wow;
988
972
const struct rtw89_ple_quota ple_qt_52bt_wow;
···
1201
1181
int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev);
1202
1182
void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
1203
1183
int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb);
1184
+
int rtw89_mac_preinit(struct rtw89_dev *rtwdev);
1204
1185
int rtw89_mac_init(struct rtw89_dev *rtwdev);
1205
1186
int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1206
1187
enum rtw89_qta_mode ext_mode);
···
1340
1319
return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable);
1341
1320
}
1342
1321
1322
+
void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr);
1343
1323
void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev);
1344
1324
void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1345
1325
int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
···
1630
1608
}
1631
1609
1632
1610
return ret;
1611
+
}
1612
+
1613
+
static inline
1614
+
void rtw89_tx_rpt_init(struct rtw89_dev *rtwdev,
1615
+
struct rtw89_core_tx_request *tx_req)
1616
+
{
1617
+
struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1618
+
1619
+
if (!rtwdev->hci.tx_rpt_enabled)
1620
+
return;
1621
+
1622
+
tx_req->desc_info.report = true;
1623
+
/* firmware maintains a 4-bit sequence number */
1624
+
tx_req->desc_info.sn = atomic_inc_return(&tx_rpt->sn) &
1625
+
RTW89_MAX_TX_RPTS_MASK;
1626
+
tx_req->desc_info.tx_cnt_lmt_en = true;
1627
+
tx_req->desc_info.tx_cnt_lmt = 8;
1628
+
}
1629
+
1630
+
static inline
1631
+
bool rtw89_is_tx_rpt_skb(struct rtw89_dev *rtwdev, struct sk_buff *skb)
1632
+
{
1633
+
struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1634
+
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1635
+
1636
+
return rtw89_core_is_tx_wait(rtwdev, skb_data) ||
1637
+
(info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS);
1638
+
}
1639
+
1640
+
static inline
1641
+
void rtw89_tx_rpt_tx_status(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1642
+
u8 tx_status)
1643
+
{
1644
+
struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1645
+
struct ieee80211_tx_info *info;
1646
+
1647
+
if (rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status))
1648
+
return;
1649
+
1650
+
info = IEEE80211_SKB_CB(skb);
1651
+
ieee80211_tx_info_clear_status(info);
1652
+
1653
+
if (tx_status == RTW89_TX_DONE)
1654
+
info->flags |= IEEE80211_TX_STAT_ACK;
1655
+
else
1656
+
info->flags &= ~IEEE80211_TX_STAT_ACK;
1657
+
1658
+
ieee80211_tx_status_irqsafe(rtwdev->hw, skb);
1659
+
}
1660
+
1661
+
static inline
1662
+
void rtw89_tx_rpt_skb_add(struct rtw89_dev *rtwdev, struct sk_buff *skb)
1663
+
{
1664
+
struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1665
+
struct rtw89_tx_skb_data *skb_data;
1666
+
u8 idx;
1667
+
1668
+
skb_data = RTW89_TX_SKB_CB(skb);
1669
+
idx = skb_data->tx_rpt_sn;
1670
+
1671
+
scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) {
1672
+
/* if skb having the similar seq number is still in the queue,
1673
+
* this means the queue is overflowed - it isn't normal and
1674
+
* should indicate firmware doesn't provide TX reports in time;
1675
+
* report the old skb as dropped, we can't do much more here
1676
+
*/
1677
+
if (tx_rpt->skbs[idx])
1678
+
rtw89_tx_rpt_tx_status(rtwdev, tx_rpt->skbs[idx],
1679
+
RTW89_TX_MACID_DROP);
1680
+
tx_rpt->skbs[idx] = skb;
1681
+
}
1682
+
}
1683
+
1684
+
static inline
1685
+
void rtw89_tx_rpt_skbs_purge(struct rtw89_dev *rtwdev)
1686
+
{
1687
+
struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1688
+
struct sk_buff *skbs[RTW89_MAX_TX_RPTS];
1689
+
1690
+
scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) {
1691
+
memcpy(skbs, tx_rpt->skbs, sizeof(tx_rpt->skbs));
1692
+
memset(tx_rpt->skbs, 0, sizeof(tx_rpt->skbs));
1693
+
}
1694
+
1695
+
for (int i = 0; i < ARRAY_SIZE(skbs); i++)
1696
+
if (skbs[i])
1697
+
rtw89_tx_rpt_tx_status(rtwdev, skbs[i],
1698
+
RTW89_TX_MACID_DROP);
1633
1699
}
1634
1700
#endif
+77
-12
drivers/net/wireless/realtek/rtw89/mac80211.c
+77
-12
drivers/net/wireless/realtek/rtw89/mac80211.c
···
220
220
if (ret)
221
221
goto unset_link;
222
222
223
+
rtwdev->pure_monitor_mode_vif = vif->type == NL80211_IFTYPE_MONITOR ?
224
+
rtwvif : NULL;
223
225
rtw89_recalc_lps(rtwdev);
224
226
return 0;
225
227
···
269
267
rtw89_core_release_bit_map(rtwdev->hw_port, port);
270
268
rtw89_release_mac_id(rtwdev, macid);
271
269
270
+
rtwdev->pure_monitor_mode_vif = NULL;
271
+
272
272
rtw89_recalc_lps(rtwdev);
273
273
rtw89_enter_ips_by_hwflags(rtwdev);
274
274
}
···
307
303
u64 multicast)
308
304
{
309
305
struct rtw89_dev *rtwdev = hw->priv;
310
-
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
311
306
u32 rx_fltr;
312
307
313
308
lockdep_assert_wiphy(hw->wiphy);
···
368
365
rx_fltr &= ~B_AX_A_A1_MATCH;
369
366
}
370
367
371
-
rtw89_write32_mask(rtwdev,
372
-
rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
373
-
B_AX_RX_FLTR_CFG_MASK,
374
-
rx_fltr);
368
+
rtw89_mac_set_rx_fltr(rtwdev, RTW89_MAC_0, rx_fltr);
375
369
if (!rtwdev->dbcc_en)
376
370
return;
377
-
rtw89_write32_mask(rtwdev,
378
-
rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_1),
379
-
B_AX_RX_FLTR_CFG_MASK,
380
-
rx_fltr);
371
+
rtw89_mac_set_rx_fltr(rtwdev, RTW89_MAC_1, rx_fltr);
381
372
}
382
373
383
374
static const u8 ac_to_fw_idx[IEEE80211_NUM_ACS] = {
···
715
718
716
719
if (changed & BSS_CHANGED_ARP_FILTER)
717
720
rtwvif->ip_addr = vif->cfg.arp_addr_list[0];
721
+
722
+
if (changed & BSS_CHANGED_MLD_VALID_LINKS) {
723
+
struct rtw89_vif_link *cur = rtw89_get_designated_link(rtwvif);
724
+
725
+
rtw89_chip_rfk_channel(rtwdev, cur);
726
+
727
+
if (hweight16(vif->active_links) == 1)
728
+
rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
729
+
else
730
+
rtwvif->mlo_mode = RTW89_MLO_MODE_EMLSR;
731
+
}
718
732
}
719
733
720
734
static void rtw89_ops_link_info_changed(struct ieee80211_hw *hw,
···
752
744
if (changed & BSS_CHANGED_BSSID) {
753
745
ether_addr_copy(rtwvif_link->bssid, conf->bssid);
754
746
rtw89_cam_bssid_changed(rtwdev, rtwvif_link);
755
-
rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
747
+
rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_INFO_CHANGE);
756
748
WRITE_ONCE(rtwvif_link->sync_bcn_tsf, 0);
757
749
}
758
750
···
811
803
rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, NULL);
812
804
rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_TYPE_CHANGE);
813
805
rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true);
814
-
rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
806
+
rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_TYPE_CHANGE);
815
807
rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
816
808
817
809
if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) {
···
962
954
}
963
955
break;
964
956
case DISABLE_KEY:
957
+
flush_work(&rtwdev->txq_work);
965
958
rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1,
966
959
false);
967
960
rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, false);
···
1141
1132
{
1142
1133
struct rtw89_dev *rtwdev = hw->priv;
1143
1134
struct rtw89_hal *hal = &rtwdev->hal;
1135
+
const struct rtw89_chip_info *chip;
1144
1136
1145
1137
lockdep_assert_wiphy(hw->wiphy);
1138
+
1139
+
chip = rtwdev->chip;
1146
1140
1147
1141
if (hal->ant_diversity) {
1148
1142
if (tx_ant != rx_ant || hweight32(tx_ant) != 1)
1149
1143
return -EINVAL;
1144
+
} else if (chip->ops->cfg_txrx_path) {
1145
+
/* With cfg_txrx_path ops, chips can configure rx_ant */
1150
1146
} else if (rx_ant != hw->wiphy->available_antennas_rx && rx_ant != hal->antenna_rx) {
1151
1147
return -EINVAL;
1152
1148
}
···
1545
1531
u16 active_links)
1546
1532
{
1547
1533
struct rtw89_dev *rtwdev = hw->priv;
1534
+
struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
1535
+
u16 current_links = vif->active_links;
1536
+
struct rtw89_vif_ml_trans trans = {
1537
+
.mediate_links = current_links | active_links,
1538
+
.links_to_del = current_links & ~active_links,
1539
+
.links_to_add = active_links & ~current_links,
1540
+
};
1548
1541
1549
1542
lockdep_assert_wiphy(hw->wiphy);
1550
1543
1551
-
return rtw89_can_work_on_links(rtwdev, vif, active_links);
1544
+
if (!rtw89_can_work_on_links(rtwdev, vif, active_links))
1545
+
return false;
1546
+
1547
+
/*
1548
+
* Leave LPS at the beginning of ieee80211_set_active_links().
1549
+
* Because the entire process takes the same lock as our track
1550
+
* work, LPS will not enter during ieee80211_set_active_links().
1551
+
*/
1552
+
rtw89_leave_lps(rtwdev);
1553
+
1554
+
rtwvif->ml_trans = trans;
1555
+
1556
+
return true;
1552
1557
}
1553
1558
1554
1559
static void __rtw89_ops_clr_vif_links(struct rtw89_dev *rtwdev,
···
1612
1579
return 0;
1613
1580
}
1614
1581
1582
+
static void rtw89_vif_cfg_fw_links(struct rtw89_dev *rtwdev,
1583
+
struct rtw89_vif *rtwvif,
1584
+
unsigned long links, bool en)
1585
+
{
1586
+
struct rtw89_vif_link *rtwvif_link;
1587
+
unsigned int link_id;
1588
+
1589
+
for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) {
1590
+
rtwvif_link = rtwvif->links[link_id];
1591
+
if (unlikely(!rtwvif_link))
1592
+
continue;
1593
+
1594
+
rtw89_fw_h2c_mlo_link_cfg(rtwdev, rtwvif_link, en);
1595
+
}
1596
+
}
1597
+
1598
+
static void rtw89_vif_update_fw_links(struct rtw89_dev *rtwdev,
1599
+
struct rtw89_vif *rtwvif,
1600
+
u16 current_links)
1601
+
{
1602
+
struct rtw89_vif_ml_trans *trans = &rtwvif->ml_trans;
1603
+
1604
+
/* Do follow-up when all updating links exist. */
1605
+
if (current_links != trans->mediate_links)
1606
+
return;
1607
+
1608
+
rtw89_vif_cfg_fw_links(rtwdev, rtwvif, trans->links_to_del, false);
1609
+
rtw89_vif_cfg_fw_links(rtwdev, rtwvif, trans->links_to_add, true);
1610
+
}
1611
+
1615
1612
static
1616
1613
int rtw89_ops_change_vif_links(struct ieee80211_hw *hw,
1617
1614
struct ieee80211_vif *vif,
···
1682
1619
1683
1620
if (rtwdev->scanning)
1684
1621
rtw89_hw_scan_abort(rtwdev, rtwdev->scan_info.scanning_vif);
1622
+
1623
+
rtw89_vif_update_fw_links(rtwdev, rtwvif, old_links);
1685
1624
1686
1625
if (!old_links)
1687
1626
__rtw89_ops_clr_vif_links(rtwdev, rtwvif,
+8
-1
drivers/net/wireless/realtek/rtw89/mac_be.c
+8
-1
drivers/net/wireless/realtek/rtw89/mac_be.c
···
458
458
459
459
static int wcpu_on(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
460
460
{
461
+
const struct rtw89_chip_info *chip = rtwdev->chip;
461
462
u32 val32;
462
463
int ret;
463
464
···
480
479
481
480
rtw89_write32(rtwdev, R_BE_UDM1, 0);
482
481
rtw89_write32(rtwdev, R_BE_UDM2, 0);
482
+
rtw89_write32(rtwdev, R_BE_BOOT_DBG, 0x0);
483
483
rtw89_write32(rtwdev, R_BE_HALT_H2C, 0);
484
484
rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
485
485
rtw89_write32(rtwdev, R_BE_HALT_H2C_CTRL, 0);
···
495
493
B_BE_WDT_WAKE_PCIE_EN | B_BE_WDT_WAKE_USB_EN);
496
494
rtw89_write32_clr(rtwdev, R_BE_WCPU_FW_CTRL,
497
495
B_BE_WDT_PLT_RST_EN | B_BE_WCPU_ROM_CUT_GET);
496
+
rtw89_write32(rtwdev, R_BE_SECURE_BOOT_MALLOC_INFO, 0);
497
+
rtw89_write32_clr(rtwdev, R_BE_GPIO_MUXCFG, B_BE_BOOT_MODE);
498
+
499
+
if (chip->chip_id != RTL8922A)
500
+
rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, B_BE_HOST_EXIST);
498
501
499
502
rtw89_write16_mask(rtwdev, R_BE_BOOT_REASON, B_BE_BOOT_REASON_MASK, boot_reason);
500
503
rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
···
2027
2020
}
2028
2021
2029
2022
rtw89_write32_mask(rtwdev, R_BE_HW_PPDU_STATUS, B_BE_FWD_PPDU_STAT_MASK, 3);
2030
-
rtw89_write32(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN | B_BE_PPDU_MAC_INFO |
2023
+
rtw89_write32(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN |
2031
2024
B_BE_APP_RX_CNT_RPT | B_BE_APP_PLCP_HDR_RPT |
2032
2025
B_BE_PPDU_STAT_RPT_CRC32 | B_BE_PPDU_STAT_RPT_DMA);
2033
2026
+17
-1
drivers/net/wireless/realtek/rtw89/pci.c
+17
-1
drivers/net/wireless/realtek/rtw89/pci.c
···
464
464
struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
465
465
struct ieee80211_tx_info *info;
466
466
467
-
if (rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status == RTW89_TX_DONE))
467
+
if (rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status))
468
468
return;
469
469
470
470
info = IEEE80211_SKB_CB(skb);
···
2062
2062
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
2063
2063
2064
2064
writel(data, rtwpci->mmap + addr);
2065
+
}
2066
+
2067
+
static u32 rtw89_pci_ops_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr)
2068
+
{
2069
+
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
2070
+
struct pci_dev *pdev = rtwpci->pdev;
2071
+
u32 value;
2072
+
int ret;
2073
+
2074
+
ret = pci_read_config_dword(pdev, addr, &value);
2075
+
if (ret)
2076
+
return RTW89_R32_EA;
2077
+
2078
+
return value;
2065
2079
}
2066
2080
2067
2081
static void rtw89_pci_ctrl_dma_trx(struct rtw89_dev *rtwdev, bool enable)
···
4696
4682
.write8 = rtw89_pci_ops_write8,
4697
4683
.write16 = rtw89_pci_ops_write16,
4698
4684
.write32 = rtw89_pci_ops_write32,
4685
+
4686
+
.read32_pci_cfg = rtw89_pci_ops_read32_pci_cfg,
4699
4687
4700
4688
.mac_pre_init = rtw89_pci_ops_mac_pre_init,
4701
4689
.mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit,
-4
drivers/net/wireless/realtek/rtw89/pci.h
-4
drivers/net/wireless/realtek/rtw89/pci.h
···
1487
1487
#define RTW89_PCI_RPP_POLLUTED BIT(31)
1488
1488
#define RTW89_PCI_RPP_SEQ GENMASK(30, 16)
1489
1489
#define RTW89_PCI_RPP_TX_STATUS GENMASK(15, 13)
1490
-
#define RTW89_TX_DONE 0x0
1491
-
#define RTW89_TX_RETRY_LIMIT 0x1
1492
-
#define RTW89_TX_LIFE_TIME 0x2
1493
-
#define RTW89_TX_MACID_DROP 0x3
1494
1490
#define RTW89_PCI_RPP_QSEL GENMASK(12, 8)
1495
1491
#define RTW89_PCI_RPP_MACID GENMASK(7, 0)
1496
1492
+63
-2
drivers/net/wireless/realtek/rtw89/phy.c
+63
-2
drivers/net/wireless/realtek/rtw89/phy.c
···
231
231
return -1;
232
232
}
233
233
234
-
if (link_sta->he_cap.has_he) {
234
+
if (link_sta->eht_cap.has_eht) {
235
+
cfg_mask |= u64_encode_bits(mask->control[band].eht_mcs[0],
236
+
RA_MASK_EHT_1SS_RATES);
237
+
cfg_mask |= u64_encode_bits(mask->control[band].eht_mcs[1],
238
+
RA_MASK_EHT_2SS_RATES);
239
+
} else if (link_sta->he_cap.has_he) {
235
240
cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
236
241
RA_MASK_HE_1SS_RATES);
237
242
cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
···
476
471
ra->ra_mask = ra_mask;
477
472
ra->fix_giltf_en = fix_giltf_en;
478
473
ra->fix_giltf = fix_giltf;
474
+
ra->partial_bw_er = link_sta->he_cap.has_he ?
475
+
!!(link_sta->he_cap.he_cap_elem.phy_cap_info[6] &
476
+
IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE) : 0;
477
+
ra->band = chan->band_type;
479
478
480
479
if (!csi)
481
480
return;
···
566
557
return true;
567
558
}
568
559
560
+
enum __rtw89_hw_rate_invalid_bases {
561
+
/* no EHT rate for ax chip */
562
+
RTW89_HW_RATE_EHT_NSS1_MCS0 = RTW89_HW_RATE_INVAL,
563
+
RTW89_HW_RATE_EHT_NSS2_MCS0 = RTW89_HW_RATE_INVAL,
564
+
RTW89_HW_RATE_EHT_NSS3_MCS0 = RTW89_HW_RATE_INVAL,
565
+
RTW89_HW_RATE_EHT_NSS4_MCS0 = RTW89_HW_RATE_INVAL,
566
+
};
567
+
569
568
#define RTW89_HW_RATE_BY_CHIP_GEN(rate) \
570
569
{ \
571
570
[RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \
···
589
572
struct rtw89_phy_rate_pattern next_pattern = {0};
590
573
const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
591
574
rtwvif_link->chanctx_idx);
575
+
static const u16 hw_rate_eht[][RTW89_CHIP_GEN_NUM] = {
576
+
RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS1_MCS0),
577
+
RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS2_MCS0),
578
+
RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS3_MCS0),
579
+
RTW89_HW_RATE_BY_CHIP_GEN(EHT_NSS4_MCS0),
580
+
};
592
581
static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = {
593
582
RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0),
594
583
RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0),
···
619
596
u8 tx_nss = rtwdev->hal.tx_nss;
620
597
u8 i;
621
598
599
+
if (chip_gen == RTW89_CHIP_AX)
600
+
goto rs_11ax;
601
+
602
+
for (i = 0; i < tx_nss; i++)
603
+
if (!__check_rate_pattern(&next_pattern, hw_rate_eht[i][chip_gen],
604
+
RA_MASK_EHT_RATES, RTW89_RA_MODE_EHT,
605
+
mask->control[nl_band].eht_mcs[i],
606
+
0, true))
607
+
goto out;
608
+
609
+
rs_11ax:
622
610
for (i = 0; i < tx_nss; i++)
623
611
if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen],
624
612
RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
···
673
639
674
640
if (!next_pattern.enable)
675
641
goto out;
642
+
643
+
if (unlikely(next_pattern.rate >= RTW89_HW_RATE_INVAL)) {
644
+
rtw89_debug(rtwdev, RTW89_DBG_RA,
645
+
"pattern invalid target: chip_gen %d, mode 0x%x\n",
646
+
chip_gen, next_pattern.ra_mode);
647
+
goto out;
648
+
}
676
649
677
650
rtwvif_link->rate_pattern = next_pattern;
678
651
rtw89_debug(rtwdev, RTW89_DBG_RA,
···
2380
2339
}
2381
2340
}
2382
2341
2342
+
static bool rtw89_phy_validate_txpwr_limit_bw(struct rtw89_dev *rtwdev,
2343
+
u8 band, u8 bw)
2344
+
{
2345
+
switch (band) {
2346
+
case RTW89_BAND_2G:
2347
+
return bw < RTW89_2G_BW_NUM;
2348
+
case RTW89_BAND_5G:
2349
+
return bw < RTW89_5G_BW_NUM;
2350
+
case RTW89_BAND_6G:
2351
+
return bw < RTW89_6G_BW_NUM;
2352
+
default:
2353
+
return false;
2354
+
}
2355
+
}
2356
+
2383
2357
s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
2384
2358
u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
2385
2359
{
···
2418
2362
.ntx = ntx,
2419
2363
};
2420
2364
s8 cstr;
2365
+
2366
+
if (!rtw89_phy_validate_txpwr_limit_bw(rtwdev, band, bw)) {
2367
+
rtw89_warn(rtwdev, "invalid band %u bandwidth %u\n", band, bw);
2368
+
return 0;
2369
+
}
2421
2370
2422
2371
switch (band) {
2423
2372
case RTW89_BAND_2G:
···
4612
4551
s32 dcfo_comp_val;
4613
4552
int sign;
4614
4553
4615
-
if (rtwdev->chip->chip_id == RTL8922A)
4554
+
if (!dcfo_comp)
4616
4555
return;
4617
4556
4618
4557
if (!is_linked) {
+4
drivers/net/wireless/realtek/rtw89/phy_be.c
+4
drivers/net/wireless/realtek/rtw89/phy_be.c
···
266
266
case 3:
267
267
rtw89_phy_cfg_bb_gain_op1db_be(rtwdev, arg, reg->data);
268
268
break;
269
+
case 15:
270
+
rtw89_phy_write32_idx(rtwdev, reg->addr & 0xFFFFF, MASKHWORD,
271
+
reg->data, RTW89_PHY_0);
272
+
break;
269
273
case 4:
270
274
/* This cfg_type is only used by rfe_type >= 50 with eFEM */
271
275
if (efuse->rfe_type < 50)
+21
-2
drivers/net/wireless/realtek/rtw89/ps.c
+21
-2
drivers/net/wireless/realtek/rtw89/ps.c
···
11
11
#include "phy.h"
12
12
#include "ps.h"
13
13
#include "reg.h"
14
+
#include "ser.h"
14
15
#include "util.h"
15
16
16
17
static int rtw89_fw_receive_lps_h2c_check(struct rtw89_dev *rtwdev, u8 macid)
···
27
26
c2h_info.id = RTW89_FWCMD_C2HREG_FUNC_PS_LEAVE_ACK;
28
27
ret = rtw89_fw_msg_reg(rtwdev, NULL, &c2h_info);
29
28
if (ret)
30
-
return ret;
29
+
goto fw_fail;
31
30
32
31
c2hreg_macid = u32_get_bits(c2h_info.u.c2hreg[0],
33
32
RTW89_C2HREG_PS_LEAVE_ACK_MACID);
34
33
c2hreg_ret = u32_get_bits(c2h_info.u.c2hreg[1], RTW89_C2HREG_PS_LEAVE_ACK_RET);
35
34
36
-
if (macid != c2hreg_macid || c2hreg_ret)
35
+
if (macid != c2hreg_macid || c2hreg_ret) {
37
36
rtw89_warn(rtwdev, "rtw89: check lps h2c received by firmware fail\n");
37
+
ret = -EINVAL;
38
+
goto fw_fail;
39
+
}
40
+
rtwdev->ps_hang_cnt = 0;
38
41
39
42
return 0;
43
+
44
+
fw_fail:
45
+
rtwdev->ps_hang_cnt++;
46
+
if (rtwdev->ps_hang_cnt >= RTW89_PS_HANG_MAX_CNT)
47
+
rtw89_ser_notify(rtwdev, MAC_AX_ERR_ASSERTION);
48
+
49
+
return ret;
40
50
}
41
51
42
52
static int rtw89_fw_leave_lps_check(struct rtw89_dev *rtwdev, u8 macid)
···
63
51
mac->ps_status, chk_msk);
64
52
if (ret) {
65
53
rtw89_info(rtwdev, "rtw89: failed to leave lps state\n");
54
+
55
+
rtwdev->ps_hang_cnt++;
56
+
if (rtwdev->ps_hang_cnt >= RTW89_PS_HANG_MAX_CNT)
57
+
rtw89_ser_notify(rtwdev, MAC_AX_ERR_ASSERTION);
58
+
66
59
return -EBUSY;
67
60
}
61
+
62
+
rtwdev->ps_hang_cnt = 0;
68
63
69
64
return 0;
70
65
}
+23
-1
drivers/net/wireless/realtek/rtw89/reg.h
+23
-1
drivers/net/wireless/realtek/rtw89/reg.h
···
3963
3963
#define R_BE_EFUSE_CTRL_1_V1 0x0034
3964
3964
#define B_BE_EF_DATA_MASK GENMASK(31, 0)
3965
3965
3966
+
#define R_BE_GPIO_MUXCFG 0x0040
3967
+
#define B_BE_WCPU_AUTO_EN BIT(26)
3968
+
#define B_BE_WCPU_JTAG_EN BIT(24)
3969
+
#define B_BE_WCPU_DBG_EN BIT(23)
3970
+
#define B_BE_JTAG_CHAIN_EN BIT(20)
3971
+
#define B_BE_BOOT_MODE BIT(19)
3972
+
#define B_BE_WL_EECS_EXT_32K_SEL BIT(18)
3973
+
#define B_BE_WL_SEC_BONDING_OPT_STS BIT(17)
3974
+
#define B_BE_SECSIC_SEL BIT(16)
3975
+
#define B_BE_ENHTP BIT(14)
3976
+
#define B_BE_ENSIC BIT(12)
3977
+
#define B_BE_SIC_SWRST BIT(11)
3978
+
#define B_BE_PINMUX_PTA_EN BIT(10)
3979
+
#define B_BE_WL_BT_PTA_SEC BIT(9)
3980
+
#define B_BE_ENUARTTX BIT(8)
3981
+
#define B_BE_DBG_GNT_BT_S1_POLARITY BIT(4)
3982
+
#define B_BE_ENUARTRX BIT(2)
3983
+
3966
3984
#define R_BE_GPIO_EXT_CTRL 0x0060
3967
3985
#define B_BE_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)
3968
3986
#define B_BE_GPIO_MOD_9 BIT(25)
···
4341
4323
#define B_BE_RUN_ENV_MASK GENMASK(31, 30)
4342
4324
#define B_BE_WCPU_FWDL_STATUS_MASK GENMASK(29, 26)
4343
4325
#define B_BE_WDT_PLT_RST_EN BIT(17)
4326
+
#define B_BE_HOST_EXIST BIT(16)
4344
4327
#define B_BE_FW_SEC_AUTH_DONE BIT(14)
4345
4328
#define B_BE_FW_CPU_UTIL_STS_EN BIT(13)
4346
4329
#define B_BE_BBMCU1_FWDL_EN BIT(12)
···
4617
4598
#define B_BE_HCI_TRXBUF_EN BIT(2)
4618
4599
#define B_BE_HCI_RXDMA_EN BIT(1)
4619
4600
#define B_BE_HCI_TXDMA_EN BIT(0)
4601
+
4602
+
#define R_BE_BOOT_DBG 0x78F0
4603
+
#define B_BE_BOOT_STATUS_MASK GENMASK(31, 16)
4604
+
#define B_BE_SECUREBOOT_STATUS_MASK GENMASK(15, 0)
4620
4605
4621
4606
#define R_BE_DBG_WOW_READY 0x815E
4622
4607
#define B_BE_DBG_WOW_READY GENMASK(7, 0)
···
7499
7476
#define B_BE_PPDU_STAT_RPT_ADDR BIT(4)
7500
7477
#define B_BE_APP_PLCP_HDR_RPT BIT(3)
7501
7478
#define B_BE_APP_RX_CNT_RPT BIT(2)
7502
-
#define B_BE_PPDU_MAC_INFO BIT(1)
7503
7479
#define B_BE_PPDU_STAT_RPT_EN BIT(0)
7504
7480
7505
7481
#define R_BE_RX_SR_CTRL 0x1144A
+11
-11
drivers/net/wireless/realtek/rtw89/regd.c
+11
-11
drivers/net/wireless/realtek/rtw89/regd.c
···
723
723
chip_regd = rtw89_regd_find_reg_by_name(rtwdev, rtwdev->efuse.country_code);
724
724
if (!rtw89_regd_is_ww(chip_regd)) {
725
725
rtwdev->regulatory.regd = chip_regd;
726
+
rtwdev->regulatory.programmed = true;
727
+
726
728
/* Ignore country ie if there is a country domain programmed in chip */
727
729
wiphy->regulatory_flags |= REGULATORY_COUNTRY_IE_IGNORE;
728
730
wiphy->regulatory_flags |= REGULATORY_STRICT_REG;
···
869
867
wiphy->regulatory_flags |= REGULATORY_COUNTRY_IE_IGNORE;
870
868
else
871
869
wiphy->regulatory_flags &= ~REGULATORY_COUNTRY_IE_IGNORE;
872
-
873
-
rtw89_regd_apply_policy_unii4(rtwdev, wiphy);
874
-
rtw89_regd_apply_policy_6ghz(rtwdev, wiphy);
875
-
rtw89_regd_apply_policy_tas(rtwdev);
876
-
rtw89_regd_apply_policy_ant_gain(rtwdev);
877
870
}
878
871
879
872
static
···
880
883
wiphy_lock(wiphy);
881
884
rtw89_leave_ps_mode(rtwdev);
882
885
883
-
if (wiphy->regd) {
884
-
rtw89_debug(rtwdev, RTW89_DBG_REGD,
885
-
"There is a country domain programmed in chip, ignore notifications\n");
886
-
goto exit;
887
-
}
886
+
if (rtwdev->regulatory.programmed)
887
+
goto policy;
888
+
888
889
rtw89_regd_notifier_apply(rtwdev, wiphy, request);
889
890
rtw89_debug_regd(rtwdev, rtwdev->regulatory.regd,
890
891
"get from initiator %d, alpha2",
891
892
request->initiator);
892
893
894
+
policy:
895
+
rtw89_regd_apply_policy_unii4(rtwdev, wiphy);
896
+
rtw89_regd_apply_policy_6ghz(rtwdev, wiphy);
897
+
rtw89_regd_apply_policy_tas(rtwdev);
898
+
rtw89_regd_apply_policy_ant_gain(rtwdev);
899
+
893
900
rtw89_core_set_chip_txpwr(rtwdev);
894
901
895
-
exit:
896
902
wiphy_unlock(wiphy);
897
903
}
898
904
+4
-1
drivers/net/wireless/realtek/rtw89/rtw8851b.c
+4
-1
drivers/net/wireless/realtek/rtw89/rtw8851b.c
···
2537
2537
.query_rxdesc = rtw89_core_query_rxdesc,
2538
2538
.fill_txdesc = rtw89_core_fill_txdesc,
2539
2539
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2540
-
.get_ch_dma = rtw89_core_get_ch_dma,
2540
+
.get_ch_dma = {rtw89_core_get_ch_dma,
2541
+
rtw89_core_get_ch_dma,
2542
+
NULL,},
2541
2543
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2542
2544
.mac_cfg_gnt = rtw89_mac_cfg_gnt,
2543
2545
.stop_sch_tx = rtw89_mac_stop_sch_tx,
···
2648
2646
.bacam_num = 2,
2649
2647
.bacam_dynamic_num = 4,
2650
2648
.bacam_ver = RTW89_BACAM_V0,
2649
+
.addrcam_ver = 0,
2651
2650
.ppdu_max_usr = 4,
2652
2651
.sec_ctrl_efuse_size = 4,
2653
2652
.physical_efuse_size = 1216,
+4
-4
drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c
+4
-4
drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c
···
1626
1626
iqk_info->iqk_table_idx[path] = idx;
1627
1627
1628
1628
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n",
1629
-
path, phy, rtwdev->dbcc_en ? "on" : "off",
1629
+
path, phy, str_on_off(rtwdev->dbcc_en),
1630
1630
iqk_info->iqk_band[path] == 0 ? "2G" :
1631
1631
iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1632
1632
iqk_info->iqk_ch[path],
···
1901
1901
rtw89_debug(rtwdev, RTW89_DBG_RFK,
1902
1902
"[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
1903
1903
path, dpk->cur_idx[path], phy,
1904
-
rtwdev->is_tssi_mode[path] ? "on" : "off",
1905
-
rtwdev->dbcc_en ? "on" : "off",
1904
+
str_on_off(rtwdev->is_tssi_mode[path]),
1905
+
str_on_off(rtwdev->dbcc_en),
1906
1906
dpk->bp[path][kidx].band == 0 ? "2G" :
1907
1907
dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1908
1908
dpk->bp[path][kidx].ch,
···
2016
2016
rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H + (path << 13), B_TXPWRB_RDY, force);
2017
2017
2018
2018
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d txpwr_bb_force %s\n",
2019
-
path, force ? "on" : "off");
2019
+
path, str_on_off(force));
2020
2020
}
2021
2021
2022
2022
static void _dpk_kip_pwr_clk_onoff(struct rtw89_dev *rtwdev, bool turn_on)
+24
drivers/net/wireless/realtek/rtw89/rtw8851bu.c
+24
drivers/net/wireless/realtek/rtw89/rtw8851bu.c
···
5
5
#include <linux/module.h>
6
6
#include <linux/usb.h>
7
7
#include "rtw8851b.h"
8
+
#include "reg.h"
8
9
#include "usb.h"
10
+
11
+
static const struct rtw89_usb_info rtw8851b_usb_info = {
12
+
.usb_host_request_2 = R_AX_USB_HOST_REQUEST_2,
13
+
.usb_wlan0_1 = R_AX_USB_WLAN0_1,
14
+
.hci_func_en = R_AX_HCI_FUNC_EN,
15
+
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0,
16
+
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0,
17
+
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2,
18
+
.bulkout_id = {
19
+
[RTW89_DMA_ACH0] = 3,
20
+
[RTW89_DMA_ACH1] = 4,
21
+
[RTW89_DMA_ACH2] = 5,
22
+
[RTW89_DMA_ACH3] = 6,
23
+
[RTW89_DMA_B0MG] = 0,
24
+
[RTW89_DMA_B0HI] = 1,
25
+
[RTW89_DMA_H2C] = 2,
26
+
},
27
+
};
9
28
10
29
static const struct rtw89_driver_info rtw89_8851bu_info = {
11
30
.chip = &rtw8851b_chip_info,
12
31
.variant = NULL,
13
32
.quirks = NULL,
33
+
.bus = {
34
+
.usb = &rtw8851b_usb_info,
35
+
}
14
36
};
15
37
16
38
static const struct usb_device_id rtw_8851bu_id_table[] = {
39
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xb831, 0xff, 0xff, 0xff),
40
+
.driver_info = (kernel_ulong_t)&rtw89_8851bu_info },
17
41
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xb851, 0xff, 0xff, 0xff),
18
42
.driver_info = (kernel_ulong_t)&rtw89_8851bu_info },
19
43
/* D-Link AX9U rev. A1 */
+73
-12
drivers/net/wireless/realtek/rtw89/rtw8852a.c
+73
-12
drivers/net/wireless/realtek/rtw89/rtw8852a.c
···
48
48
[RTW89_QTA_INVALID] = {NULL},
49
49
};
50
50
51
+
static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_usb[] = {
52
+
{22, 402, grp_0}, /* ACH 0 */
53
+
{0, 0, grp_0}, /* ACH 1 */
54
+
{22, 402, grp_0}, /* ACH 2 */
55
+
{0, 0, grp_0}, /* ACH 3 */
56
+
{22, 402, grp_0}, /* ACH 4 */
57
+
{0, 0, grp_0}, /* ACH 5 */
58
+
{22, 402, grp_0}, /* ACH 6 */
59
+
{0, 0, grp_0}, /* ACH 7 */
60
+
{22, 402, grp_0}, /* B0MGQ */
61
+
{0, 0, grp_0}, /* B0HIQ */
62
+
{22, 402, grp_0}, /* B1MGQ */
63
+
{0, 0, grp_0}, /* B1HIQ */
64
+
{0, 0, 0} /* FWCMDQ */
65
+
};
66
+
67
+
static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_usb = {
68
+
512, /* Group 0 */
69
+
0, /* Group 1 */
70
+
512, /* Public Max */
71
+
104 /* WP threshold */
72
+
};
73
+
74
+
static const struct rtw89_hfc_prec_cfg rtw8852a_hfc_preccfg_usb = {
75
+
11, /* CH 0-11 pre-cost */
76
+
32, /* H2C pre-cost */
77
+
76, /* WP CH 0-7 pre-cost */
78
+
25, /* WP CH 8-11 pre-cost */
79
+
1, /* CH 0-11 full condition */
80
+
1, /* H2C full condition */
81
+
1, /* WP CH 0-7 full condition */
82
+
1, /* WP CH 8-11 full condition */
83
+
};
84
+
85
+
static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_usb[] = {
86
+
[RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_usb, &rtw8852a_hfc_pubcfg_usb,
87
+
&rtw8852a_hfc_preccfg_usb, RTW89_HCIFC_STF},
88
+
[RTW89_QTA_DLFW] = {NULL, NULL,
89
+
&rtw8852a_hfc_preccfg_usb, RTW89_HCIFC_STF},
90
+
[RTW89_QTA_INVALID] = {NULL},
91
+
};
92
+
51
93
static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
52
94
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
53
95
&rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
···
99
57
&rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
100
58
&rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
101
59
&rtw89_mac_size.ple_qt_52a_wow},
60
+
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
61
+
&rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
62
+
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
63
+
&rtw89_mac_size.ple_qt13},
64
+
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
65
+
NULL},
66
+
};
67
+
68
+
static const struct rtw89_dle_mem rtw8852a_dle_mem_usb[] = {
69
+
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size1,
70
+
&rtw89_mac_size.ple_size1, &rtw89_mac_size.wde_qt1,
71
+
&rtw89_mac_size.wde_qt1, &rtw89_mac_size.ple_qt25,
72
+
&rtw89_mac_size.ple_qt26},
102
73
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
103
74
&rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
104
75
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
···
621
566
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
622
567
};
623
568
624
-
static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
625
-
struct rtw8852a_efuse *map)
626
-
{
627
-
ether_addr_copy(efuse->addr, map->e.mac_addr);
628
-
efuse->rfe_type = map->rfe_type;
629
-
efuse->xtal_cap = map->xtal_k;
630
-
}
631
-
632
569
static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
633
570
struct rtw8852a_efuse *map)
634
571
{
···
666
619
667
620
switch (rtwdev->hci.type) {
668
621
case RTW89_HCI_TYPE_PCIE:
669
-
rtw8852ae_efuse_parsing(efuse, map);
622
+
ether_addr_copy(efuse->addr, map->e.mac_addr);
623
+
break;
624
+
case RTW89_HCI_TYPE_USB:
625
+
ether_addr_copy(efuse->addr, map->u.mac_addr);
670
626
break;
671
627
default:
672
628
return -ENOTSUPP;
673
629
}
630
+
631
+
efuse->rfe_type = map->rfe_type;
632
+
efuse->xtal_cap = map->xtal_k;
674
633
675
634
rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
676
635
···
2231
2178
.query_rxdesc = rtw89_core_query_rxdesc,
2232
2179
.fill_txdesc = rtw89_core_fill_txdesc,
2233
2180
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2234
-
.get_ch_dma = rtw89_core_get_ch_dma,
2181
+
.get_ch_dma = {rtw89_core_get_ch_dma,
2182
+
rtw89_core_get_ch_dma_v2,
2183
+
NULL,},
2235
2184
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2236
2185
.mac_cfg_gnt = rtw89_mac_cfg_gnt,
2237
2186
.stop_sch_tx = rtw89_mac_stop_sch_tx,
···
2277
2222
.max_amsdu_limit = 3500,
2278
2223
.dis_2g_40m_ul_ofdma = true,
2279
2224
.rsvd_ple_ofst = 0x6f800,
2280
-
.hfc_param_ini = {rtw8852a_hfc_param_ini_pcie, NULL, NULL},
2281
-
.dle_mem = {rtw8852a_dle_mem_pcie, NULL, NULL, NULL},
2225
+
.hfc_param_ini = {rtw8852a_hfc_param_ini_pcie,
2226
+
rtw8852a_hfc_param_ini_usb,
2227
+
NULL},
2228
+
.dle_mem = {rtw8852a_dle_mem_pcie,
2229
+
rtw8852a_dle_mem_usb,
2230
+
rtw8852a_dle_mem_usb,
2231
+
NULL},
2282
2232
.wde_qempty_acq_grpnum = 16,
2283
2233
.wde_qempty_mgq_grpsel = 16,
2284
2234
.rf_base_addr = {0xc000, 0xd000},
···
2334
2274
.bacam_num = 2,
2335
2275
.bacam_dynamic_num = 4,
2336
2276
.bacam_ver = RTW89_BACAM_V0,
2277
+
.addrcam_ver = 0,
2337
2278
.ppdu_max_usr = 4,
2338
2279
.sec_ctrl_efuse_size = 4,
2339
2280
.physical_efuse_size = 1216,
+8
-8
drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c
+8
-8
drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c
···
756
756
rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
757
757
rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x0);
758
758
udelay(1);
759
-
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303);
760
-
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000);
759
+
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0303);
760
+
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0000);
761
761
762
762
switch (iqk_info->iqk_band[path]) {
763
763
case RTW89_BAND_2G:
···
1239
1239
udelay(1);
1240
1240
rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041);
1241
1241
udelay(1);
1242
-
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303);
1243
-
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000);
1242
+
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0303);
1243
+
rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0000);
1244
1244
switch (iqk_info->iqk_band[path]) {
1245
1245
case RTW89_BAND_2G:
1246
1246
rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00);
···
1403
1403
path, iqk_info->iqk_ch[path]);
1404
1404
rtw89_debug(rtwdev, RTW89_DBG_RFK,
1405
1405
"[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy,
1406
-
rtwdev->dbcc_en ? "on" : "off",
1406
+
str_on_off(rtwdev->dbcc_en),
1407
1407
iqk_info->iqk_band[path] == 0 ? "2G" :
1408
1408
iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1409
1409
iqk_info->iqk_ch[path],
···
1881
1881
rtw89_debug(rtwdev, RTW89_DBG_RFK,
1882
1882
"[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
1883
1883
path, dpk->cur_idx[path], phy,
1884
-
rtwdev->is_tssi_mode[path] ? "on" : "off",
1885
-
rtwdev->dbcc_en ? "on" : "off",
1884
+
str_on_off(rtwdev->is_tssi_mode[path]),
1885
+
str_on_off(rtwdev->dbcc_en),
1886
1886
dpk->bp[path][kidx].band == 0 ? "2G" :
1887
1887
dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1888
1888
dpk->bp[path][kidx].ch,
···
2736
2736
MASKBYTE3, 0x6 | val);
2737
2737
2738
2738
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
2739
-
kidx, dpk->is_dpk_enable && !off ? "enable" : "disable");
2739
+
kidx, str_enable_disable(dpk->is_dpk_enable && !off));
2740
2740
}
2741
2741
2742
2742
static void _dpk_track(struct rtw89_dev *rtwdev)
+79
drivers/net/wireless/realtek/rtw89/rtw8852au.c
+79
drivers/net/wireless/realtek/rtw89/rtw8852au.c
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/* Copyright(c) 2025 Realtek Corporation
3
+
*/
4
+
5
+
#include <linux/module.h>
6
+
#include <linux/usb.h>
7
+
#include "rtw8852a.h"
8
+
#include "reg.h"
9
+
#include "usb.h"
10
+
11
+
static const struct rtw89_usb_info rtw8852a_usb_info = {
12
+
.usb_host_request_2 = R_AX_USB_HOST_REQUEST_2,
13
+
.usb_wlan0_1 = R_AX_USB_WLAN0_1,
14
+
.hci_func_en = R_AX_HCI_FUNC_EN,
15
+
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0,
16
+
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0,
17
+
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2,
18
+
.bulkout_id = {
19
+
[RTW89_DMA_ACH0] = 3,
20
+
[RTW89_DMA_ACH2] = 5,
21
+
[RTW89_DMA_ACH4] = 4,
22
+
[RTW89_DMA_ACH6] = 6,
23
+
[RTW89_DMA_B0MG] = 0,
24
+
[RTW89_DMA_B0HI] = 0,
25
+
[RTW89_DMA_B1MG] = 1,
26
+
[RTW89_DMA_B1HI] = 1,
27
+
[RTW89_DMA_H2C] = 2,
28
+
},
29
+
};
30
+
31
+
static const struct rtw89_driver_info rtw89_8852au_info = {
32
+
.chip = &rtw8852a_chip_info,
33
+
.variant = NULL,
34
+
.quirks = NULL,
35
+
.bus = {
36
+
.usb = &rtw8852a_usb_info,
37
+
}
38
+
};
39
+
40
+
static const struct usb_device_id rtw_8852au_id_table[] = {
41
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0411, 0x0312, 0xff, 0xff, 0xff),
42
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
43
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4020, 0xff, 0xff, 0xff),
44
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
45
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x1997, 0xff, 0xff, 0xff),
46
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
47
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0x8832, 0xff, 0xff, 0xff),
48
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
49
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0x885a, 0xff, 0xff, 0xff),
50
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
51
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0x885c, 0xff, 0xff, 0xff),
52
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
53
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3321, 0xff, 0xff, 0xff),
54
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
55
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x332c, 0xff, 0xff, 0xff),
56
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
57
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x013f, 0xff, 0xff, 0xff),
58
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
59
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0140, 0xff, 0xff, 0xff),
60
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
61
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0141, 0xff, 0xff, 0xff),
62
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
63
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x3625, 0x010f, 0xff, 0xff, 0xff),
64
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
65
+
{},
66
+
};
67
+
MODULE_DEVICE_TABLE(usb, rtw_8852au_id_table);
68
+
69
+
static struct usb_driver rtw_8852au_driver = {
70
+
.name = KBUILD_MODNAME,
71
+
.id_table = rtw_8852au_id_table,
72
+
.probe = rtw89_usb_probe,
73
+
.disconnect = rtw89_usb_disconnect,
74
+
};
75
+
module_usb_driver(rtw_8852au_driver);
76
+
77
+
MODULE_AUTHOR("Bitterblue Smith <rtl8821cerfe2@gmail.com>");
78
+
MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852AU driver");
79
+
MODULE_LICENSE("Dual BSD/GPL");
+4
-1
drivers/net/wireless/realtek/rtw89/rtw8852b.c
+4
-1
drivers/net/wireless/realtek/rtw89/rtw8852b.c
···
842
842
.query_rxdesc = rtw89_core_query_rxdesc,
843
843
.fill_txdesc = rtw89_core_fill_txdesc,
844
844
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
845
-
.get_ch_dma = rtw89_core_get_ch_dma,
845
+
.get_ch_dma = {rtw89_core_get_ch_dma,
846
+
rtw89_core_get_ch_dma,
847
+
NULL,},
846
848
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
847
849
.mac_cfg_gnt = rtw89_mac_cfg_gnt,
848
850
.stop_sch_tx = rtw89_mac_stop_sch_tx,
···
959
957
.bacam_num = 2,
960
958
.bacam_dynamic_num = 4,
961
959
.bacam_ver = RTW89_BACAM_V0,
960
+
.addrcam_ver = 0,
962
961
.ppdu_max_usr = 4,
963
962
.sec_ctrl_efuse_size = 4,
964
963
.physical_efuse_size = 1216,
+5
-1
drivers/net/wireless/realtek/rtw89/rtw8852b_common.c
+5
-1
drivers/net/wireless/realtek/rtw89/rtw8852b_common.c
···
1747
1747
struct rtw89_hal *hal = &rtwdev->hal;
1748
1748
const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1749
1749
enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB;
1750
+
u8 rx_nss = rtwdev->hal.rx_nss;
1751
+
1752
+
if (rx_path != RF_AB)
1753
+
rx_nss = 1;
1750
1754
1751
1755
rtw8852bx_bb_ctrl_rx_path(rtwdev, rx_path, chan);
1752
1756
rtw8852bx_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path);
1753
1757
1754
-
if (rtwdev->hal.rx_nss == 1) {
1758
+
if (rx_nss == 1) {
1755
1759
rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1756
1760
rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1757
1761
rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
+3
-3
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
+3
-3
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
···
1696
1696
MASKBYTE3, _dpk_order_convert(rtwdev) << 1 | val);
1697
1697
1698
1698
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
1699
-
kidx, dpk->is_dpk_enable && !off ? "enable" : "disable");
1699
+
kidx, str_enable_disable(dpk->is_dpk_enable && !off));
1700
1700
}
1701
1701
1702
1702
static void _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
···
1763
1763
rtw89_debug(rtwdev, RTW89_DBG_RFK,
1764
1764
"[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
1765
1765
path, dpk->cur_idx[path], phy,
1766
-
rtwdev->is_tssi_mode[path] ? "on" : "off",
1767
-
rtwdev->dbcc_en ? "on" : "off",
1766
+
str_on_off(rtwdev->is_tssi_mode[path]),
1767
+
str_on_off(rtwdev->dbcc_en),
1768
1768
dpk->bp[path][kidx].band == 0 ? "2G" :
1769
1769
dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1770
1770
dpk->bp[path][kidx].ch,
+4
-1
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
+4
-1
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
···
708
708
.query_rxdesc = rtw89_core_query_rxdesc,
709
709
.fill_txdesc = rtw89_core_fill_txdesc,
710
710
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
711
-
.get_ch_dma = rtw89_core_get_ch_dma,
711
+
.get_ch_dma = {rtw89_core_get_ch_dma,
712
+
NULL,
713
+
NULL,},
712
714
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
713
715
.mac_cfg_gnt = rtw89_mac_cfg_gnt,
714
716
.stop_sch_tx = rtw89_mac_stop_sch_tx,
···
818
816
.bacam_num = 2,
819
817
.bacam_dynamic_num = 4,
820
818
.bacam_ver = RTW89_BACAM_V0,
819
+
.addrcam_ver = 0,
821
820
.ppdu_max_usr = 4,
822
821
.sec_ctrl_efuse_size = 4,
823
822
.physical_efuse_size = 1216,
+24
drivers/net/wireless/realtek/rtw89/rtw8852bu.c
+24
drivers/net/wireless/realtek/rtw89/rtw8852bu.c
···
5
5
#include <linux/module.h>
6
6
#include <linux/usb.h>
7
7
#include "rtw8852b.h"
8
+
#include "reg.h"
8
9
#include "usb.h"
10
+
11
+
static const struct rtw89_usb_info rtw8852b_usb_info = {
12
+
.usb_host_request_2 = R_AX_USB_HOST_REQUEST_2,
13
+
.usb_wlan0_1 = R_AX_USB_WLAN0_1,
14
+
.hci_func_en = R_AX_HCI_FUNC_EN,
15
+
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0,
16
+
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0,
17
+
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2,
18
+
.bulkout_id = {
19
+
[RTW89_DMA_ACH0] = 3,
20
+
[RTW89_DMA_ACH1] = 4,
21
+
[RTW89_DMA_ACH2] = 5,
22
+
[RTW89_DMA_ACH3] = 6,
23
+
[RTW89_DMA_B0MG] = 0,
24
+
[RTW89_DMA_B0HI] = 1,
25
+
[RTW89_DMA_H2C] = 2,
26
+
},
27
+
};
9
28
10
29
static const struct rtw89_driver_info rtw89_8852bu_info = {
11
30
.chip = &rtw8852b_chip_info,
12
31
.variant = NULL,
13
32
.quirks = NULL,
33
+
.bus = {
34
+
.usb = &rtw8852b_usb_info,
35
+
}
14
36
};
15
37
16
38
static const struct usb_device_id rtw_8852bu_id_table[] = {
···
49
27
{ USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x3428, 0xff, 0xff, 0xff),
50
28
.driver_info = (kernel_ulong_t)&rtw89_8852bu_info },
51
29
{ USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x1a62, 0xff, 0xff, 0xff),
30
+
.driver_info = (kernel_ulong_t)&rtw89_8852bu_info },
31
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x1cb6, 0xff, 0xff, 0xff),
52
32
.driver_info = (kernel_ulong_t)&rtw89_8852bu_info },
53
33
{ USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0x6931, 0xff, 0xff, 0xff),
54
34
.driver_info = (kernel_ulong_t)&rtw89_8852bu_info },
+144
-26
drivers/net/wireless/realtek/rtw89/rtw8852c.c
+144
-26
drivers/net/wireless/realtek/rtw89/rtw8852c.c
···
51
51
[RTW89_QTA_INVALID] = {NULL},
52
52
};
53
53
54
+
static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_usb[] = {
55
+
{18, 344, grp_0}, /* ACH 0 */
56
+
{0, 0, grp_0}, /* ACH 1 */
57
+
{18, 344, grp_0}, /* ACH 2 */
58
+
{0, 0, grp_0}, /* ACH 3 */
59
+
{18, 344, grp_0}, /* ACH 4 */
60
+
{0, 0, grp_0}, /* ACH 5 */
61
+
{18, 344, grp_0}, /* ACH 6 */
62
+
{0, 0, grp_0}, /* ACH 7 */
63
+
{18, 344, grp_0}, /* B0MGQ */
64
+
{0, 0, grp_0}, /* B0HIQ */
65
+
{18, 344, grp_0}, /* B1MGQ */
66
+
{0, 0, grp_0}, /* B1HIQ */
67
+
{0, 0, 0} /* FWCMDQ */
68
+
};
69
+
70
+
static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_usb = {
71
+
344, /* Group 0 */
72
+
0, /* Group 1 */
73
+
344, /* Public Max */
74
+
0 /* WP threshold */
75
+
};
76
+
77
+
static const struct rtw89_hfc_prec_cfg rtw8852c_hfc_preccfg_usb = {
78
+
9, /* CH 0-11 pre-cost */
79
+
32, /* H2C pre-cost */
80
+
146, /* WP CH 0-7 pre-cost */
81
+
146, /* WP CH 8-11 pre-cost */
82
+
1, /* CH 0-11 full condition */
83
+
1, /* H2C full condition */
84
+
1, /* WP CH 0-7 full condition */
85
+
1, /* WP CH 8-11 full condition */
86
+
};
87
+
88
+
static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_usb[] = {
89
+
[RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_usb, &rtw8852c_hfc_pubcfg_usb,
90
+
&rtw8852c_hfc_preccfg_usb, RTW89_HCIFC_STF},
91
+
[RTW89_QTA_DLFW] = {NULL, NULL,
92
+
&rtw8852c_hfc_preccfg_usb, RTW89_HCIFC_STF},
93
+
[RTW89_QTA_INVALID] = {NULL},
94
+
};
95
+
54
96
static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = {
55
97
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19,
56
98
&rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18,
57
99
&rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46,
58
100
&rtw89_mac_size.ple_qt47},
101
+
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
102
+
&rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
103
+
&rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
104
+
&rtw89_mac_size.ple_qt45},
105
+
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
106
+
NULL},
107
+
};
108
+
109
+
static const struct rtw89_dle_mem rtw8852c_dle_mem_usb2[] = {
110
+
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size31,
111
+
&rtw89_mac_size.ple_size34, &rtw89_mac_size.wde_qt31,
112
+
&rtw89_mac_size.wde_qt31, &rtw89_mac_size.ple_qt78,
113
+
&rtw89_mac_size.ple_qt79},
114
+
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
115
+
&rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
116
+
&rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
117
+
&rtw89_mac_size.ple_qt45},
118
+
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
119
+
NULL},
120
+
};
121
+
122
+
static const struct rtw89_dle_mem rtw8852c_dle_mem_usb3[] = {
123
+
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size17,
124
+
&rtw89_mac_size.ple_size17, &rtw89_mac_size.wde_qt16,
125
+
&rtw89_mac_size.wde_qt16, &rtw89_mac_size.ple_qt42,
126
+
&rtw89_mac_size.ple_qt43},
59
127
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
60
128
&rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
61
129
&rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
···
282
214
int ret;
283
215
284
216
val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);
285
-
if (val32 == MAC_AX_HCI_SEL_PCIE_USB)
217
+
if (val32 == MAC_AX_HCI_SEL_PCIE_USB ||
218
+
rtwdev->hci.type == RTW89_HCI_TYPE_USB)
286
219
rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
287
220
288
221
rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
···
315
246
rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
316
247
317
248
rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
318
-
rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
249
+
250
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
251
+
rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
319
252
320
253
rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN);
321
254
rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP);
···
376
305
377
306
rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
378
307
rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
379
-
rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
380
-
B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
381
-
B_AX_LED1_PULL_LOW_EN);
308
+
309
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
310
+
rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
311
+
B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
312
+
B_AX_LED1_PULL_LOW_EN);
382
313
383
314
rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
384
315
B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
···
458
385
if (ret)
459
386
return ret;
460
387
461
-
rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
388
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
389
+
rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
390
+
else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
391
+
rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_EDSWR);
392
+
462
393
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
463
394
rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
464
395
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
465
396
B_AX_REG_ZCDC_H_MASK, 0x3);
466
-
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
397
+
398
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
399
+
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
400
+
} else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) {
401
+
val32 = rtw89_read32(rtwdev, R_AX_SYS_PW_CTRL);
402
+
val32 &= ~B_AX_AFSM_PCIE_SUS_EN;
403
+
val32 |= B_AX_AFSM_WLSUS_EN;
404
+
rtw89_write32(rtwdev, R_AX_SYS_PW_CTRL, val32);
405
+
}
467
406
468
407
return 0;
469
-
}
470
-
471
-
static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse,
472
-
struct rtw8852c_efuse *map)
473
-
{
474
-
ether_addr_copy(efuse->addr, map->e.mac_addr);
475
-
efuse->rfe_type = map->rfe_type;
476
-
efuse->xtal_cap = map->xtal_k;
477
408
}
478
409
479
410
static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
···
588
511
589
512
switch (rtwdev->hci.type) {
590
513
case RTW89_HCI_TYPE_PCIE:
591
-
rtw8852c_e_efuse_parsing(efuse, map);
514
+
ether_addr_copy(efuse->addr, map->e.mac_addr);
515
+
break;
516
+
case RTW89_HCI_TYPE_USB:
517
+
ether_addr_copy(efuse->addr, map->u.mac_addr);
592
518
break;
593
519
default:
594
520
return -ENOTSUPP;
595
521
}
522
+
523
+
efuse->rfe_type = map->rfe_type;
524
+
efuse->xtal_cap = map->xtal_k;
596
525
597
526
rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
598
527
···
670
587
}
671
588
}
672
589
590
+
#define __THM_MASK_SIGN BIT(0)
591
+
#define __THM_MASK_3BITS GENMASK(3, 1)
592
+
#define __THM_MASK_VAL8 BIT(4)
593
+
673
594
static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev)
674
595
{
675
-
#define __thm_setting(raw) \
676
-
({ \
677
-
u8 __v = (raw); \
678
-
((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
596
+
#define __thm_setting(raw) \
597
+
({ \
598
+
u8 __v = (raw); \
599
+
((__v & __THM_MASK_SIGN) << 3) | ((__v & __THM_MASK_3BITS) >> 1); \
679
600
})
680
601
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
681
602
u8 i, val;
···
2502
2415
static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2503
2416
{
2504
2417
struct rtw89_hal *hal = &rtwdev->hal;
2418
+
u8 nrx_path = RF_PATH_AB;
2419
+
u8 rx_nss = hal->rx_nss;
2505
2420
2506
-
rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB);
2421
+
if (hal->antenna_rx == RF_A)
2422
+
nrx_path = RF_PATH_A;
2423
+
else if (hal->antenna_rx == RF_B)
2424
+
nrx_path = RF_PATH_B;
2507
2425
2508
-
if (hal->rx_nss == 1) {
2426
+
if (nrx_path != RF_PATH_AB)
2427
+
rx_nss = 1;
2428
+
2429
+
rtw8852c_bb_cfg_rx_path(rtwdev, nrx_path);
2430
+
2431
+
if (rx_nss == 1) {
2509
2432
rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
2510
2433
rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
2511
2434
rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
···
2530
2433
2531
2434
static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2532
2435
{
2436
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
2437
+
s8 comp = 0;
2438
+
u8 val;
2439
+
2533
2440
rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2534
2441
rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2535
2442
rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2536
2443
2537
2444
fsleep(200);
2538
2445
2539
-
return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
2446
+
val = rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
2447
+
2448
+
if (info->pg_thermal_trim) {
2449
+
u8 trim = info->thermal_trim[rf_path];
2450
+
2451
+
if (trim & __THM_MASK_VAL8)
2452
+
comp = 8 * (trim & __THM_MASK_SIGN ? -1 : 1);
2453
+
}
2454
+
2455
+
return val + comp;
2540
2456
}
2541
2457
2542
2458
static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev)
···
3072
2962
.query_rxdesc = rtw89_core_query_rxdesc,
3073
2963
.fill_txdesc = rtw89_core_fill_txdesc_v1,
3074
2964
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1,
3075
-
.get_ch_dma = rtw89_core_get_ch_dma,
2965
+
.get_ch_dma = {rtw89_core_get_ch_dma,
2966
+
rtw89_core_get_ch_dma_v2,
2967
+
NULL,},
3076
2968
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1,
3077
2969
.mac_cfg_gnt = rtw89_mac_cfg_gnt_v1,
3078
2970
.stop_sch_tx = rtw89_mac_stop_sch_tx_v1,
···
3118
3006
.max_amsdu_limit = 8000,
3119
3007
.dis_2g_40m_ul_ofdma = false,
3120
3008
.rsvd_ple_ofst = 0x6f800,
3121
-
.hfc_param_ini = {rtw8852c_hfc_param_ini_pcie, NULL, NULL},
3122
-
.dle_mem = {rtw8852c_dle_mem_pcie, NULL, NULL, NULL},
3009
+
.hfc_param_ini = {rtw8852c_hfc_param_ini_pcie,
3010
+
rtw8852c_hfc_param_ini_usb,
3011
+
NULL},
3012
+
.dle_mem = {rtw8852c_dle_mem_pcie,
3013
+
rtw8852c_dle_mem_usb2,
3014
+
rtw8852c_dle_mem_usb3,
3015
+
NULL},
3123
3016
.wde_qempty_acq_grpnum = 16,
3124
3017
.wde_qempty_mgq_grpsel = 16,
3125
3018
.rf_base_addr = {0xe000, 0xf000},
···
3178
3061
.bacam_num = 8,
3179
3062
.bacam_dynamic_num = 8,
3180
3063
.bacam_ver = RTW89_BACAM_V0_EXT,
3064
+
.addrcam_ver = 0,
3181
3065
.ppdu_max_usr = 8,
3182
3066
.sec_ctrl_efuse_size = 4,
3183
3067
.physical_efuse_size = 1216,
+1
-1
drivers/net/wireless/realtek/rtw89/rtw8852c.h
+1
-1
drivers/net/wireless/realtek/rtw89/rtw8852c.h
+44
-25
drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
+44
-25
drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
···
1344
1344
path, iqk_info->iqk_ch[path]);
1345
1345
rtw89_debug(rtwdev, RTW89_DBG_RFK,
1346
1346
"[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy,
1347
-
rtwdev->dbcc_en ? "on" : "off",
1347
+
str_on_off(rtwdev->dbcc_en),
1348
1348
iqk_info->iqk_band[path] == 0 ? "2G" :
1349
1349
iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1350
1350
iqk_info->iqk_ch[path],
···
1920
1920
rtw89_debug(rtwdev, RTW89_DBG_RFK,
1921
1921
"[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
1922
1922
path, dpk->cur_idx[path], phy,
1923
-
rtwdev->is_tssi_mode[path] ? "on" : "off",
1924
-
rtwdev->dbcc_en ? "on" : "off",
1923
+
str_on_off(rtwdev->is_tssi_mode[path]),
1924
+
str_on_off(rtwdev->dbcc_en),
1925
1925
dpk->bp[path][kidx].band == 0 ? "2G" :
1926
1926
dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1927
1927
dpk->bp[path][kidx].ch,
···
2000
2000
rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H + (path << 13), B_TXPWRB_RDY, force);
2001
2001
2002
2002
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d txpwr_bb_force %s\n",
2003
-
path, force ? "on" : "off");
2003
+
path, str_on_off(force));
2004
2004
}
2005
2005
2006
2006
static void _dpk_kip_restore(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
···
2828
2828
B_DPD_MEN, val);
2829
2829
2830
2830
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
2831
-
kidx, dpk->is_dpk_enable && !off ? "enable" : "disable");
2831
+
kidx, str_enable_disable(dpk->is_dpk_enable && !off));
2832
2832
}
2833
2833
2834
2834
static void _dpk_track(struct rtw89_dev *rtwdev)
···
3987
3987
}
3988
3988
}
3989
3989
3990
+
static void _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3991
+
enum rtw89_bandwidth bw)
3992
+
{
3993
+
u32 val;
3994
+
3995
+
rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
3996
+
rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0xa);
3997
+
3998
+
switch (bw) {
3999
+
case RTW89_CHANNEL_WIDTH_20:
4000
+
val = 0x1b;
4001
+
break;
4002
+
case RTW89_CHANNEL_WIDTH_40:
4003
+
val = 0x13;
4004
+
break;
4005
+
case RTW89_CHANNEL_WIDTH_80:
4006
+
val = 0xb;
4007
+
break;
4008
+
case RTW89_CHANNEL_WIDTH_160:
4009
+
default:
4010
+
val = 0x3;
4011
+
break;
4012
+
}
4013
+
4014
+
rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, val);
4015
+
rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
4016
+
}
4017
+
4018
+
static void _set_tia_bw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
4019
+
enum rtw89_bandwidth bw)
4020
+
{
4021
+
if (bw == RTW89_CHANNEL_WIDTH_160)
4022
+
rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_EBW, 0x0);
4023
+
else
4024
+
rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_EBW, 0x2);
4025
+
}
4026
+
3990
4027
static void _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3991
4028
enum rtw89_bandwidth bw)
3992
4029
{
3993
4030
u8 kpath;
3994
4031
u8 path;
3995
-
u32 val;
3996
4032
3997
4033
kpath = _kpath(rtwdev, phy);
3998
4034
for (path = 0; path < 2; path++) {
3999
4035
if (!(kpath & BIT(path)))
4000
4036
continue;
4001
4037
4002
-
rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
4003
-
rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0xa);
4004
-
switch (bw) {
4005
-
case RTW89_CHANNEL_WIDTH_20:
4006
-
val = 0x1b;
4007
-
break;
4008
-
case RTW89_CHANNEL_WIDTH_40:
4009
-
val = 0x13;
4010
-
break;
4011
-
case RTW89_CHANNEL_WIDTH_80:
4012
-
val = 0xb;
4013
-
break;
4014
-
case RTW89_CHANNEL_WIDTH_160:
4015
-
default:
4016
-
val = 0x3;
4017
-
break;
4018
-
}
4019
-
rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, val);
4020
-
rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
4038
+
_set_rxbb_bw(rtwdev, path, bw);
4039
+
_set_tia_bw(rtwdev, path, bw);
4021
4040
}
4022
4041
}
4023
4042
+69
drivers/net/wireless/realtek/rtw89/rtw8852cu.c
+69
drivers/net/wireless/realtek/rtw89/rtw8852cu.c
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/* Copyright(c) 2025 Realtek Corporation
3
+
*/
4
+
5
+
#include <linux/module.h>
6
+
#include <linux/usb.h>
7
+
#include "rtw8852c.h"
8
+
#include "reg.h"
9
+
#include "usb.h"
10
+
11
+
static const struct rtw89_usb_info rtw8852c_usb_info = {
12
+
.usb_host_request_2 = R_AX_USB_HOST_REQUEST_2_V1,
13
+
.usb_wlan0_1 = R_AX_USB_WLAN0_1_V1,
14
+
.hci_func_en = R_AX_HCI_FUNC_EN_V1,
15
+
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0_V1,
16
+
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0_V1,
17
+
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2_V1,
18
+
.bulkout_id = {
19
+
[RTW89_DMA_ACH0] = 3,
20
+
[RTW89_DMA_ACH2] = 5,
21
+
[RTW89_DMA_ACH4] = 4,
22
+
[RTW89_DMA_ACH6] = 6,
23
+
[RTW89_DMA_B0MG] = 0,
24
+
[RTW89_DMA_B0HI] = 0,
25
+
[RTW89_DMA_B1MG] = 1,
26
+
[RTW89_DMA_B1HI] = 1,
27
+
[RTW89_DMA_H2C] = 2,
28
+
},
29
+
};
30
+
31
+
static const struct rtw89_driver_info rtw89_8852cu_info = {
32
+
.chip = &rtw8852c_chip_info,
33
+
.variant = NULL,
34
+
.quirks = NULL,
35
+
.bus = {
36
+
.usb = &rtw8852c_usb_info,
37
+
},
38
+
};
39
+
40
+
static const struct usb_device_id rtw_8852cu_id_table[] = {
41
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xc832, 0xff, 0xff, 0xff),
42
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
43
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xc85a, 0xff, 0xff, 0xff),
44
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
45
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xc85d, 0xff, 0xff, 0xff),
46
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
47
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0x991d, 0xff, 0xff, 0xff),
48
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
49
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x35b2, 0x0502, 0xff, 0xff, 0xff),
50
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
51
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0101, 0xff, 0xff, 0xff),
52
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
53
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0102, 0xff, 0xff, 0xff),
54
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
55
+
{},
56
+
};
57
+
MODULE_DEVICE_TABLE(usb, rtw_8852cu_id_table);
58
+
59
+
static struct usb_driver rtw_8852cu_driver = {
60
+
.name = KBUILD_MODNAME,
61
+
.id_table = rtw_8852cu_id_table,
62
+
.probe = rtw89_usb_probe,
63
+
.disconnect = rtw89_usb_disconnect,
64
+
};
65
+
module_usb_driver(rtw_8852cu_driver);
66
+
67
+
MODULE_AUTHOR("Bitterblue Smith <rtl8821cerfe2@gmail.com>");
68
+
MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852CU driver");
69
+
MODULE_LICENSE("Dual BSD/GPL");
+15
-2
drivers/net/wireless/realtek/rtw89/rtw8922a.c
+15
-2
drivers/net/wireless/realtek/rtw89/rtw8922a.c
···
2347
2347
enum rtw89_band band = chan->band_type;
2348
2348
struct rtw89_hal *hal = &rtwdev->hal;
2349
2349
u8 ntx_path = RF_PATH_AB;
2350
+
u8 nrx_path = RF_PATH_AB;
2350
2351
u32 tx_en0, tx_en1;
2352
+
u8 rx_nss = 2;
2351
2353
2352
2354
if (hal->antenna_tx == RF_A)
2353
2355
ntx_path = RF_PATH_A;
2354
2356
else if (hal->antenna_tx == RF_B)
2355
2357
ntx_path = RF_PATH_B;
2356
2358
2359
+
if (hal->antenna_rx == RF_A)
2360
+
nrx_path = RF_PATH_A;
2361
+
else if (hal->antenna_rx == RF_B)
2362
+
nrx_path = RF_PATH_B;
2363
+
2364
+
if (nrx_path != RF_PATH_AB)
2365
+
rx_nss = 1;
2366
+
2357
2367
rtw8922a_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, true);
2358
2368
if (rtwdev->dbcc_en)
2359
2369
rtw8922a_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
2360
2370
&tx_en1, true);
2361
2371
2362
-
rtw8922a_ctrl_trx_path(rtwdev, ntx_path, 2, RF_PATH_AB, 2);
2372
+
rtw8922a_ctrl_trx_path(rtwdev, ntx_path, 2, nrx_path, rx_nss);
2363
2373
2364
2374
rtw8922a_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, false);
2365
2375
if (rtwdev->dbcc_en)
···
2831
2821
.query_rxdesc = rtw89_core_query_rxdesc_v2,
2832
2822
.fill_txdesc = rtw89_core_fill_txdesc_v2,
2833
2823
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v2,
2834
-
.get_ch_dma = rtw89_core_get_ch_dma,
2824
+
.get_ch_dma = {rtw89_core_get_ch_dma,
2825
+
rtw89_core_get_ch_dma_v2,
2826
+
NULL,},
2835
2827
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v2,
2836
2828
.mac_cfg_gnt = rtw89_mac_cfg_gnt_v2,
2837
2829
.stop_sch_tx = rtw89_mac_stop_sch_tx_v2,
···
2931
2919
.bacam_num = 24,
2932
2920
.bacam_dynamic_num = 8,
2933
2921
.bacam_ver = RTW89_BACAM_V1,
2922
+
.addrcam_ver = 0,
2934
2923
.ppdu_max_usr = 16,
2935
2924
.sec_ctrl_efuse_size = 4,
2936
2925
.physical_efuse_size = 0x1300,
+6
-1
drivers/net/wireless/realtek/rtw89/txrx.h
+6
-1
drivers/net/wireless/realtek/rtw89/txrx.h
···
127
127
#define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)
128
128
129
129
/* TX WD INFO DWORD 1 */
130
+
#define RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL BIT(31)
131
+
#define RTW89_TXWD_INFO1_DATA_TXCNT_LMT GENMASK(30, 25)
130
132
#define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
131
133
#define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
132
134
#define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
···
141
139
#define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
142
140
143
141
/* TX WD INFO DWORD 3 */
142
+
#define RTW89_TXWD_INFO3_SPE_RPT BIT(10)
144
143
145
144
/* TX WD INFO DWORD 4 */
146
-
#define RTW89_TXWD_INFO4_RTS_EN BIT(27)
147
145
#define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
146
+
#define RTW89_TXWD_INFO4_RTS_EN BIT(27)
147
+
#define RTW89_TXWD_INFO4_SW_DEFINE GENMASK(3, 0)
148
148
149
149
/* TX WD INFO DWORD 5 */
150
150
···
421
417
#define RTW89_RXINFO_USER_MGMT BIT(3)
422
418
#define RTW89_RXINFO_USER_BCN BIT(4)
423
419
#define RTW89_RXINFO_USER_MACID GENMASK(15, 8)
420
+
#define RTW89_RXINFO_USER_MACID_V1 GENMASK(31, 20)
424
421
425
422
struct rtw89_rxinfo {
426
423
__le32 w0;
+72
-43
drivers/net/wireless/realtek/rtw89/usb.c
+72
-43
drivers/net/wireless/realtek/rtw89/usb.c
···
55
55
else if (ret < 0)
56
56
rtw89_warn(rtwdev,
57
57
"usb %s%u 0x%x fail ret=%d value=0x%x attempt=%d\n",
58
-
reqtype == RTW89_USB_VENQT_READ ? "read" : "write",
58
+
str_read_write(reqtype == RTW89_USB_VENQT_READ),
59
59
len * 8, addr, ret,
60
60
le32_to_cpup(rtwusb->vendor_req_buf),
61
61
attempt);
···
167
167
return 42; /* TODO some kind of calculation? */
168
168
}
169
169
170
-
static u8 rtw89_usb_get_bulkout_id(u8 ch_dma)
171
-
{
172
-
switch (ch_dma) {
173
-
case RTW89_DMA_ACH0:
174
-
return 3;
175
-
case RTW89_DMA_ACH1:
176
-
return 4;
177
-
case RTW89_DMA_ACH2:
178
-
return 5;
179
-
case RTW89_DMA_ACH3:
180
-
return 6;
181
-
default:
182
-
case RTW89_DMA_B0MG:
183
-
return 0;
184
-
case RTW89_DMA_B0HI:
185
-
return 1;
186
-
case RTW89_DMA_H2C:
187
-
return 2;
188
-
}
189
-
}
190
-
191
170
static void rtw89_usb_write_port_complete(struct urb *urb)
192
171
{
193
172
struct rtw89_usb_tx_ctrl_block *txcb = urb->context;
···
193
214
txdesc_size += rtwdev->chip->txwd_info_size;
194
215
195
216
skb_pull(skb, txdesc_size);
217
+
218
+
if (rtw89_is_tx_rpt_skb(rtwdev, skb)) {
219
+
if (urb->status == 0)
220
+
rtw89_tx_rpt_skb_add(rtwdev, skb);
221
+
else
222
+
rtw89_tx_rpt_tx_status(rtwdev, skb,
223
+
RTW89_TX_MACID_DROP);
224
+
continue;
225
+
}
196
226
197
227
info = IEEE80211_SKB_CB(skb);
198
228
ieee80211_tx_info_clear_status(info);
···
230
242
}
231
243
232
244
kfree(txcb);
233
-
usb_free_urb(urb);
234
245
}
235
246
236
247
static int rtw89_usb_write_port(struct rtw89_dev *rtwdev, u8 ch_dma,
237
248
void *data, int len, void *context)
238
249
{
239
250
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
251
+
const struct rtw89_usb_info *info = rtwusb->info;
240
252
struct usb_device *usbd = rtwusb->udev;
241
253
struct urb *urb;
242
-
u8 bulkout_id = rtw89_usb_get_bulkout_id(ch_dma);
254
+
u8 bulkout_id = info->bulkout_id[ch_dma];
243
255
unsigned int pipe;
244
256
int ret;
245
257
246
258
if (test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags))
247
-
return 0;
259
+
return -ENODEV;
248
260
249
261
urb = usb_alloc_urb(0, GFP_ATOMIC);
250
262
if (!urb)
···
255
267
usb_fill_bulk_urb(urb, usbd, pipe, data, len,
256
268
rtw89_usb_write_port_complete, context);
257
269
urb->transfer_flags |= URB_ZERO_PACKET;
258
-
ret = usb_submit_urb(urb, GFP_ATOMIC);
270
+
usb_anchor_urb(urb, &rtwusb->tx_submitted);
259
271
272
+
ret = usb_submit_urb(urb, GFP_ATOMIC);
260
273
if (ret)
261
-
usb_free_urb(urb);
274
+
usb_unanchor_urb(urb);
275
+
276
+
/* release our reference to this URB, USB core will eventually free it
277
+
* on its own after the completion callback finishes (or URB is
278
+
* immediately freed here if its submission has failed)
279
+
*/
280
+
usb_free_urb(urb);
262
281
263
282
if (ret == -ENODEV)
264
283
set_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags);
265
284
266
285
return ret;
286
+
}
287
+
288
+
static void rtw89_usb_tx_free_skb(struct rtw89_dev *rtwdev, u8 txch,
289
+
struct sk_buff *skb)
290
+
{
291
+
if (txch == RTW89_TXCH_CH12)
292
+
dev_kfree_skb_any(skb);
293
+
else
294
+
ieee80211_free_txskb(rtwdev->hw, skb);
267
295
}
268
296
269
297
static void rtw89_usb_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
···
296
292
297
293
txcb = kmalloc(sizeof(*txcb), GFP_ATOMIC);
298
294
if (!txcb) {
299
-
dev_kfree_skb_any(skb);
295
+
rtw89_usb_tx_free_skb(rtwdev, txch, skb);
300
296
continue;
301
297
}
302
298
···
309
305
ret = rtw89_usb_write_port(rtwdev, txch, skb->data, skb->len,
310
306
txcb);
311
307
if (ret) {
312
-
rtw89_err(rtwdev, "write port txch %d failed: %d\n",
313
-
txch, ret);
308
+
if (ret != -ENODEV)
309
+
rtw89_err(rtwdev, "write port txch %d failed: %d\n",
310
+
txch, ret);
314
311
315
312
skb_dequeue(&txcb->tx_ack_queue);
316
313
kfree(txcb);
317
-
dev_kfree_skb_any(skb);
314
+
rtw89_usb_tx_free_skb(rtwdev, txch, skb);
318
315
}
319
316
}
320
317
}
···
367
362
{
368
363
struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
369
364
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
365
+
struct rtw89_tx_skb_data *skb_data;
370
366
struct sk_buff *skb = tx_req->skb;
371
367
struct rtw89_txwd_body *txdesc;
372
368
u32 txdesc_size;
···
394
388
395
389
le32p_replace_bits(&txdesc->dword0, 1, RTW89_TXWD_BODY0_STF_MODE);
396
390
391
+
skb_data = RTW89_TX_SKB_CB(skb);
392
+
if (tx_req->desc_info.sn)
393
+
skb_data->tx_rpt_sn = tx_req->desc_info.sn;
394
+
if (tx_req->desc_info.tx_cnt_lmt)
395
+
skb_data->tx_pkt_cnt_lmt = tx_req->desc_info.tx_cnt_lmt;
396
+
397
397
skb_queue_tail(&rtwusb->tx_queue[desc_info->ch_dma], skb);
398
398
399
399
return 0;
···
422
410
423
411
if (skb_queue_len(&rtwusb->rx_queue) >= RTW89_USB_MAX_RXQ_LEN) {
424
412
rtw89_warn(rtwdev, "rx_queue overflow\n");
425
-
dev_kfree_skb_any(rx_skb);
426
-
continue;
413
+
goto free_or_reuse;
427
414
}
428
415
429
416
memset(&desc_info, 0, sizeof(desc_info));
···
433
422
rtw89_debug(rtwdev, RTW89_DBG_HCI,
434
423
"failed to allocate RX skb of size %u\n",
435
424
desc_info.pkt_size);
436
-
continue;
425
+
goto free_or_reuse;
437
426
}
438
427
439
428
pkt_offset = desc_info.offset + desc_info.rxd_len;
···
443
432
444
433
rtw89_core_rx(rtwdev, &desc_info, skb);
445
434
435
+
free_or_reuse:
446
436
if (skb_queue_len(&rtwusb->rx_free_queue) >= RTW89_USB_RX_SKB_NUM)
447
437
dev_kfree_skb_any(rx_skb);
448
438
else
···
579
567
}
580
568
}
581
569
570
+
static void rtw89_usb_cancel_tx_bufs(struct rtw89_usb *rtwusb)
571
+
{
572
+
usb_kill_anchored_urbs(&rtwusb->tx_submitted);
573
+
}
574
+
582
575
static void rtw89_usb_free_rx_bufs(struct rtw89_usb *rtwusb)
583
576
{
584
577
struct rtw89_usb_rx_ctrl_block *rxcb;
···
685
668
686
669
static void rtw89_usb_ops_reset(struct rtw89_dev *rtwdev)
687
670
{
688
-
/* TODO: anything to do here? */
671
+
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
672
+
673
+
rtw89_usb_cancel_tx_bufs(rtwusb);
674
+
rtw89_tx_rpt_skbs_purge(rtwdev);
689
675
}
690
676
691
677
static int rtw89_usb_ops_start(struct rtw89_dev *rtwdev)
···
718
698
719
699
static int rtw89_usb_ops_mac_pre_init(struct rtw89_dev *rtwdev)
720
700
{
701
+
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
702
+
const struct rtw89_usb_info *info = rtwusb->info;
721
703
u32 val32;
722
704
723
-
rtw89_write32_set(rtwdev, R_AX_USB_HOST_REQUEST_2, B_AX_R_USBIO_MODE);
705
+
rtw89_write32_set(rtwdev, info->usb_host_request_2,
706
+
B_AX_R_USBIO_MODE);
724
707
725
708
/* fix USB IO hang suggest by chihhanli@realtek.com */
726
-
rtw89_write32_clr(rtwdev, R_AX_USB_WLAN0_1,
709
+
rtw89_write32_clr(rtwdev, info->usb_wlan0_1,
727
710
B_AX_USBRX_RST | B_AX_USBTX_RST);
728
711
729
-
val32 = rtw89_read32(rtwdev, R_AX_HCI_FUNC_EN);
712
+
val32 = rtw89_read32(rtwdev, info->hci_func_en);
730
713
val32 &= ~(B_AX_HCI_RXDMA_EN | B_AX_HCI_TXDMA_EN);
731
-
rtw89_write32(rtwdev, R_AX_HCI_FUNC_EN, val32);
714
+
rtw89_write32(rtwdev, info->hci_func_en, val32);
732
715
733
716
val32 |= B_AX_HCI_RXDMA_EN | B_AX_HCI_TXDMA_EN;
734
-
rtw89_write32(rtwdev, R_AX_HCI_FUNC_EN, val32);
717
+
rtw89_write32(rtwdev, info->hci_func_en, val32);
735
718
/* fix USB TRX hang suggest by chihhanli@realtek.com */
736
719
737
720
return 0;
···
748
725
static int rtw89_usb_ops_mac_post_init(struct rtw89_dev *rtwdev)
749
726
{
750
727
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
728
+
const struct rtw89_usb_info *info = rtwusb->info;
751
729
enum usb_device_speed speed;
752
730
u32 ep;
753
731
754
-
rtw89_write32_clr(rtwdev, R_AX_USB3_MAC_NPI_CONFIG_INTF_0,
732
+
rtw89_write32_clr(rtwdev, info->usb3_mac_npi_config_intf_0,
755
733
B_AX_SSPHY_LFPS_FILTER);
756
734
757
735
speed = rtwusb->udev->speed;
···
768
744
if (ep == 8)
769
745
continue;
770
746
771
-
rtw89_write8_mask(rtwdev, R_AX_USB_ENDPOINT_0,
747
+
rtw89_write8_mask(rtwdev, info->usb_endpoint_0,
772
748
B_AX_EP_IDX, ep);
773
-
rtw89_write8(rtwdev, R_AX_USB_ENDPOINT_2 + 1, NUMP);
749
+
rtw89_write8(rtwdev, info->usb_endpoint_2 + 1, NUMP);
774
750
}
775
751
776
752
return 0;
···
925
901
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
926
902
int ret;
927
903
904
+
init_usb_anchor(&rtwusb->tx_submitted);
905
+
928
906
ret = rtw89_usb_parse(rtwdev, intf);
929
907
if (ret)
930
908
return ret;
···
975
949
976
950
rtwusb = rtw89_usb_priv(rtwdev);
977
951
rtwusb->rtwdev = rtwdev;
952
+
rtwusb->info = info->bus.usb;
978
953
979
954
rtwdev->hci.ops = &rtw89_usb_ops;
980
955
rtwdev->hci.type = RTW89_HCI_TYPE_USB;
956
+
rtwdev->hci.tx_rpt_enabled = true;
981
957
982
958
ret = rtw89_usb_intf_init(rtwdev, intf);
983
959
if (ret) {
···
1054
1026
rtwusb = rtw89_usb_priv(rtwdev);
1055
1027
1056
1028
rtw89_usb_cancel_rx_bufs(rtwusb);
1029
+
rtw89_usb_cancel_tx_bufs(rtwusb);
1057
1030
1058
1031
rtw89_core_unregister(rtwdev);
1059
1032
rtw89_core_deinit(rtwdev);
+12
drivers/net/wireless/realtek/rtw89/usb.h
+12
drivers/net/wireless/realtek/rtw89/usb.h
···
20
20
#define RTW89_MAX_ENDPOINT_NUM 9
21
21
#define RTW89_MAX_BULKOUT_NUM 7
22
22
23
+
struct rtw89_usb_info {
24
+
u32 usb_host_request_2;
25
+
u32 usb_wlan0_1;
26
+
u32 hci_func_en;
27
+
u32 usb3_mac_npi_config_intf_0;
28
+
u32 usb_endpoint_0;
29
+
u32 usb_endpoint_2;
30
+
u8 bulkout_id[RTW89_DMA_CH_NUM];
31
+
};
32
+
23
33
struct rtw89_usb_rx_ctrl_block {
24
34
struct rtw89_dev *rtwdev;
25
35
struct urb *rx_urb;
···
45
35
struct rtw89_usb {
46
36
struct rtw89_dev *rtwdev;
47
37
struct usb_device *udev;
38
+
const struct rtw89_usb_info *info;
48
39
49
40
__le32 *vendor_req_buf;
50
41
···
60
49
struct sk_buff_head rx_free_queue;
61
50
struct work_struct rx_work;
62
51
struct work_struct rx_urb_work;
52
+
struct usb_anchor tx_submitted;
63
53
64
54
struct sk_buff_head tx_queue[RTW89_TXCH_NUM];
65
55
};
+5
-3
drivers/net/wireless/realtek/rtw89/wow.c
+5
-3
drivers/net/wireless/realtek/rtw89/wow.c
···
1221
1221
}
1222
1222
}
1223
1223
1224
-
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
1224
+
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
1225
+
RTW89_ROLE_INFO_CHANGE);
1225
1226
if (ret) {
1226
1227
rtw89_warn(rtwdev, "failed to send h2c cam\n");
1227
1228
return ret;
···
1249
1248
mac->wow_ctrl.addr, mac->wow_ctrl.mask);
1250
1249
if (ret)
1251
1250
rtw89_err(rtwdev, "failed to check wow status %s\n",
1252
-
wow_enable ? "enabled" : "disabled");
1251
+
str_enabled_disabled(wow_enable));
1253
1252
return ret;
1254
1253
}
1255
1254
···
1319
1318
return ret;
1320
1319
}
1321
1320
1322
-
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
1321
+
ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
1322
+
RTW89_ROLE_FW_RESTORE);
1323
1323
if (ret) {
1324
1324
rtw89_warn(rtwdev, "failed to send h2c cam\n");
1325
1325
return ret;