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net/mlx5: Add IFC bits for extended ETS rate limit bandwidth value

Add hardware interface definitions to support extended bandwidth rate
limiting in the QoS Enhanced Transmission Selection (ETS) configuration.

The new fields include:
- max_bw_value: extended from 8-bit to 16-bit in ets_tcn_config_reg,
simplifying the implementation by using a single field instead of
separate MSB/LSB fields.
- qetcr_qshr_max_bw_val_msb: capability bit in qcam_qos_feature_cap_mask
indicating device support for the extended 16-bit max_bw_value field.

These interface additions are prerequisites for increasing the per-TC
rate limit beyond 255 Gbps to support higher-bandwidth NICs.

Signed-off-by: Alexei Lazar <alazar@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1768200608-1543180-1-git-send-email-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>

authored by

Alexei Lazar and committed by
Leon Romanovsky 49e41f3e f0b2fde9

+4 -3
+4 -3
include/linux/mlx5/mlx5_ifc.h
··· 11009 11009 }; 11010 11010 11011 11011 struct mlx5_ifc_qcam_qos_feature_cap_mask { 11012 - u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 11012 + u8 qcam_qos_feature_cap_mask_127_to_5[0x7B]; 11013 + u8 qetcr_qshr_max_bw_val_msb[0x1]; 11014 + u8 qcam_qos_feature_cap_mask_3_to_1[0x3]; 11013 11015 u8 qpts_trust_both[0x1]; 11014 11016 }; 11015 11017 ··· 11967 11965 11968 11966 u8 reserved_at_20[0xc]; 11969 11967 u8 max_bw_units[0x4]; 11970 - u8 reserved_at_30[0x8]; 11971 - u8 max_bw_value[0x8]; 11968 + u8 max_bw_value[0x10]; 11972 11969 }; 11973 11970 11974 11971 struct mlx5_ifc_ets_global_config_reg_bits {