dt-bindings: stm32: add STM32MP21 clocks and reset bindings

+199

Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: STM32MP21 Reset Clock Controller 8 + 9 + maintainers: 10 + - Gabriel Fernandez <gabriel.fernandez@foss.st.com> 11 + 12 + description: | 13 + The RCC hardware block is both a reset and a clock controller. 14 + RCC makes also power management (resume/suspend). 15 + 16 + See also: 17 + include/dt-bindings/clock/st,stm32mp21-rcc.h 18 + include/dt-bindings/reset/st,stm32mp21-rcc.h 19 + 20 + properties: 21 + compatible: 22 + enum: 23 + - st,stm32mp21-rcc 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + '#clock-cells': 29 + const: 1 30 + 31 + '#reset-cells': 32 + const: 1 33 + 34 + clocks: 35 + items: 36 + - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz) 37 + - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz) 38 + - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz) 39 + - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz) 40 + - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz) 41 + - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated) 42 + - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock 43 + - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock 44 + - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock 45 + - description: CK_SCMI_ICN_DDR DDR interconnect bus clock 46 + - description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock 47 + - description: CK_SCMI_ICN_HSL HSL interconnect bus clock 48 + - description: CK_SCMI_ICN_NIC NIC interconnect bus clock 49 + - description: CK_SCMI_FLEXGEN_07 flexgen clock 7 50 + - description: CK_SCMI_FLEXGEN_08 flexgen clock 8 51 + - description: CK_SCMI_FLEXGEN_09 flexgen clock 9 52 + - description: CK_SCMI_FLEXGEN_10 flexgen clock 10 53 + - description: CK_SCMI_FLEXGEN_11 flexgen clock 11 54 + - description: CK_SCMI_FLEXGEN_12 flexgen clock 12 55 + - description: CK_SCMI_FLEXGEN_13 flexgen clock 13 56 + - description: CK_SCMI_FLEXGEN_14 flexgen clock 14 57 + - description: CK_SCMI_FLEXGEN_16 flexgen clock 16 58 + - description: CK_SCMI_FLEXGEN_17 flexgen clock 17 59 + - description: CK_SCMI_FLEXGEN_18 flexgen clock 18 60 + - description: CK_SCMI_FLEXGEN_19 flexgen clock 19 61 + - description: CK_SCMI_FLEXGEN_20 flexgen clock 20 62 + - description: CK_SCMI_FLEXGEN_21 flexgen clock 21 63 + - description: CK_SCMI_FLEXGEN_22 flexgen clock 22 64 + - description: CK_SCMI_FLEXGEN_23 flexgen clock 23 65 + - description: CK_SCMI_FLEXGEN_24 flexgen clock 24 66 + - description: CK_SCMI_FLEXGEN_25 flexgen clock 25 67 + - description: CK_SCMI_FLEXGEN_26 flexgen clock 26 68 + - description: CK_SCMI_FLEXGEN_27 flexgen clock 27 69 + - description: CK_SCMI_FLEXGEN_29 flexgen clock 29 70 + - description: CK_SCMI_FLEXGEN_30 flexgen clock 30 71 + - description: CK_SCMI_FLEXGEN_31 flexgen clock 31 72 + - description: CK_SCMI_FLEXGEN_33 flexgen clock 33 73 + - description: CK_SCMI_FLEXGEN_36 flexgen clock 36 74 + - description: CK_SCMI_FLEXGEN_37 flexgen clock 37 75 + - description: CK_SCMI_FLEXGEN_38 flexgen clock 38 76 + - description: CK_SCMI_FLEXGEN_39 flexgen clock 39 77 + - description: CK_SCMI_FLEXGEN_40 flexgen clock 40 78 + - description: CK_SCMI_FLEXGEN_41 flexgen clock 41 79 + - description: CK_SCMI_FLEXGEN_42 flexgen clock 42 80 + - description: CK_SCMI_FLEXGEN_43 flexgen clock 43 81 + - description: CK_SCMI_FLEXGEN_44 flexgen clock 44 82 + - description: CK_SCMI_FLEXGEN_45 flexgen clock 45 83 + - description: CK_SCMI_FLEXGEN_46 flexgen clock 46 84 + - description: CK_SCMI_FLEXGEN_47 flexgen clock 47 85 + - description: CK_SCMI_FLEXGEN_48 flexgen clock 48 86 + - description: CK_SCMI_FLEXGEN_50 flexgen clock 50 87 + - description: CK_SCMI_FLEXGEN_51 flexgen clock 51 88 + - description: CK_SCMI_FLEXGEN_52 flexgen clock 52 89 + - description: CK_SCMI_FLEXGEN_53 flexgen clock 53 90 + - description: CK_SCMI_FLEXGEN_54 flexgen clock 54 91 + - description: CK_SCMI_FLEXGEN_55 flexgen clock 55 92 + - description: CK_SCMI_FLEXGEN_56 flexgen clock 56 93 + - description: CK_SCMI_FLEXGEN_57 flexgen clock 57 94 + - description: CK_SCMI_FLEXGEN_58 flexgen clock 58 95 + - description: CK_SCMI_FLEXGEN_61 flexgen clock 61 96 + - description: CK_SCMI_FLEXGEN_62 flexgen clock 62 97 + - description: CK_SCMI_FLEXGEN_63 flexgen clock 63 98 + - description: CK_SCMI_ICN_APB1 Peripheral bridge 1 99 + - description: CK_SCMI_ICN_APB2 Peripheral bridge 2 100 + - description: CK_SCMI_ICN_APB3 Peripheral bridge 3 101 + - description: CK_SCMI_ICN_APB4 Peripheral bridge 4 102 + - description: CK_SCMI_ICN_APB5 Peripheral bridge 5 103 + - description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug 104 + - description: CK_SCMI_TIMG1 Peripheral bridge for timer1 105 + - description: CK_SCMI_TIMG2 Peripheral bridge for timer2 106 + 107 + access-controllers: 108 + maxItems: 1 109 + 110 + required: 111 + - compatible 112 + - reg 113 + - '#clock-cells' 114 + - '#reset-cells' 115 + - clocks 116 + 117 + additionalProperties: false 118 + 119 + examples: 120 + - | 121 + #include <dt-bindings/clock/st,stm32mp21-rcc.h> 122 + 123 + clock-controller@44200000 { 124 + compatible = "st,stm32mp21-rcc"; 125 + reg = <0x44200000 0x10000>; 126 + #clock-cells = <1>; 127 + #reset-cells = <1>; 128 + clocks = <&scmi_clk CK_SCMI_HSE>, 129 + <&scmi_clk CK_SCMI_HSI>, 130 + <&scmi_clk CK_SCMI_MSI>, 131 + <&scmi_clk CK_SCMI_LSE>, 132 + <&scmi_clk CK_SCMI_LSI>, 133 + <&scmi_clk CK_SCMI_HSE_DIV2>, 134 + <&scmi_clk CK_SCMI_ICN_HS_MCU>, 135 + <&scmi_clk CK_SCMI_ICN_LS_MCU>, 136 + <&scmi_clk CK_SCMI_ICN_SDMMC>, 137 + <&scmi_clk CK_SCMI_ICN_DDR>, 138 + <&scmi_clk CK_SCMI_ICN_DISPLAY>, 139 + <&scmi_clk CK_SCMI_ICN_HSL>, 140 + <&scmi_clk CK_SCMI_ICN_NIC>, 141 + <&scmi_clk CK_SCMI_FLEXGEN_07>, 142 + <&scmi_clk CK_SCMI_FLEXGEN_08>, 143 + <&scmi_clk CK_SCMI_FLEXGEN_09>, 144 + <&scmi_clk CK_SCMI_FLEXGEN_10>, 145 + <&scmi_clk CK_SCMI_FLEXGEN_11>, 146 + <&scmi_clk CK_SCMI_FLEXGEN_12>, 147 + <&scmi_clk CK_SCMI_FLEXGEN_13>, 148 + <&scmi_clk CK_SCMI_FLEXGEN_14>, 149 + <&scmi_clk CK_SCMI_FLEXGEN_16>, 150 + <&scmi_clk CK_SCMI_FLEXGEN_17>, 151 + <&scmi_clk CK_SCMI_FLEXGEN_18>, 152 + <&scmi_clk CK_SCMI_FLEXGEN_19>, 153 + <&scmi_clk CK_SCMI_FLEXGEN_20>, 154 + <&scmi_clk CK_SCMI_FLEXGEN_21>, 155 + <&scmi_clk CK_SCMI_FLEXGEN_22>, 156 + <&scmi_clk CK_SCMI_FLEXGEN_23>, 157 + <&scmi_clk CK_SCMI_FLEXGEN_24>, 158 + <&scmi_clk CK_SCMI_FLEXGEN_25>, 159 + <&scmi_clk CK_SCMI_FLEXGEN_26>, 160 + <&scmi_clk CK_SCMI_FLEXGEN_27>, 161 + <&scmi_clk CK_SCMI_FLEXGEN_29>, 162 + <&scmi_clk CK_SCMI_FLEXGEN_30>, 163 + <&scmi_clk CK_SCMI_FLEXGEN_31>, 164 + <&scmi_clk CK_SCMI_FLEXGEN_33>, 165 + <&scmi_clk CK_SCMI_FLEXGEN_36>, 166 + <&scmi_clk CK_SCMI_FLEXGEN_37>, 167 + <&scmi_clk CK_SCMI_FLEXGEN_38>, 168 + <&scmi_clk CK_SCMI_FLEXGEN_39>, 169 + <&scmi_clk CK_SCMI_FLEXGEN_40>, 170 + <&scmi_clk CK_SCMI_FLEXGEN_41>, 171 + <&scmi_clk CK_SCMI_FLEXGEN_42>, 172 + <&scmi_clk CK_SCMI_FLEXGEN_43>, 173 + <&scmi_clk CK_SCMI_FLEXGEN_44>, 174 + <&scmi_clk CK_SCMI_FLEXGEN_45>, 175 + <&scmi_clk CK_SCMI_FLEXGEN_46>, 176 + <&scmi_clk CK_SCMI_FLEXGEN_47>, 177 + <&scmi_clk CK_SCMI_FLEXGEN_48>, 178 + <&scmi_clk CK_SCMI_FLEXGEN_50>, 179 + <&scmi_clk CK_SCMI_FLEXGEN_51>, 180 + <&scmi_clk CK_SCMI_FLEXGEN_52>, 181 + <&scmi_clk CK_SCMI_FLEXGEN_53>, 182 + <&scmi_clk CK_SCMI_FLEXGEN_54>, 183 + <&scmi_clk CK_SCMI_FLEXGEN_55>, 184 + <&scmi_clk CK_SCMI_FLEXGEN_56>, 185 + <&scmi_clk CK_SCMI_FLEXGEN_57>, 186 + <&scmi_clk CK_SCMI_FLEXGEN_58>, 187 + <&scmi_clk CK_SCMI_FLEXGEN_61>, 188 + <&scmi_clk CK_SCMI_FLEXGEN_62>, 189 + <&scmi_clk CK_SCMI_FLEXGEN_63>, 190 + <&scmi_clk CK_SCMI_ICN_APB1>, 191 + <&scmi_clk CK_SCMI_ICN_APB2>, 192 + <&scmi_clk CK_SCMI_ICN_APB3>, 193 + <&scmi_clk CK_SCMI_ICN_APB4>, 194 + <&scmi_clk CK_SCMI_ICN_APB5>, 195 + <&scmi_clk CK_SCMI_ICN_APBDBG>, 196 + <&scmi_clk CK_SCMI_TIMG1>, 197 + <&scmi_clk CK_SCMI_TIMG2>; 198 + }; 199 + ...

+426

include/dt-bindings/clock/st,stm32mp21-rcc.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 + /* 3 + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 + * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_STM32MP21_CLKS_H_ 8 + #define _DT_BINDINGS_STM32MP21_CLKS_H_ 9 + 10 + /* INTERNAL/EXTERNAL OSCILLATORS */ 11 + #define HSI_CK 0 12 + #define HSE_CK 1 13 + #define MSI_CK 2 14 + #define LSI_CK 3 15 + #define LSE_CK 4 16 + #define I2S_CK 5 17 + #define RTC_CK 6 18 + #define SPDIF_CK_SYMB 7 19 + 20 + /* PLL CLOCKS */ 21 + #define PLL1_CK 8 22 + #define PLL2_CK 9 23 + #define PLL4_CK 10 24 + #define PLL5_CK 11 25 + #define PLL6_CK 12 26 + #define PLL7_CK 13 27 + #define PLL8_CK 14 28 + 29 + #define CK_CPU1 15 30 + 31 + /* APB DIV CLOCKS */ 32 + #define CK_ICN_APB1 16 33 + #define CK_ICN_APB2 17 34 + #define CK_ICN_APB3 18 35 + #define CK_ICN_APB4 19 36 + #define CK_ICN_APB5 20 37 + #define CK_ICN_APBDBG 21 38 + 39 + /* GLOBAL TIMER */ 40 + #define TIMG1_CK 22 41 + #define TIMG2_CK 23 42 + 43 + /* FLEXGEN CLOCKS */ 44 + #define CK_ICN_HS_MCU 24 45 + #define CK_ICN_SDMMC 25 46 + #define CK_ICN_DDR 26 47 + #define CK_ICN_DISPLAY 27 48 + #define CK_ICN_HSL 28 49 + #define CK_ICN_NIC 29 50 + #define CK_ICN_VID 30 51 + #define CK_FLEXGEN_07 31 52 + #define CK_FLEXGEN_08 32 53 + #define CK_FLEXGEN_09 33 54 + #define CK_FLEXGEN_10 34 55 + #define CK_FLEXGEN_11 35 56 + #define CK_FLEXGEN_12 36 57 + #define CK_FLEXGEN_13 37 58 + #define CK_FLEXGEN_14 38 59 + #define CK_FLEXGEN_15 39 60 + #define CK_FLEXGEN_16 40 61 + #define CK_FLEXGEN_17 41 62 + #define CK_FLEXGEN_18 42 63 + #define CK_FLEXGEN_19 43 64 + #define CK_FLEXGEN_20 44 65 + #define CK_FLEXGEN_21 45 66 + #define CK_FLEXGEN_22 46 67 + #define CK_FLEXGEN_23 47 68 + #define CK_FLEXGEN_24 48 69 + #define CK_FLEXGEN_25 49 70 + #define CK_FLEXGEN_26 50 71 + #define CK_FLEXGEN_27 51 72 + #define CK_FLEXGEN_28 52 73 + #define CK_FLEXGEN_29 53 74 + #define CK_FLEXGEN_30 54 75 + #define CK_FLEXGEN_31 55 76 + #define CK_FLEXGEN_32 56 77 + #define CK_FLEXGEN_33 57 78 + #define CK_FLEXGEN_34 58 79 + #define CK_FLEXGEN_35 59 80 + #define CK_FLEXGEN_36 60 81 + #define CK_FLEXGEN_37 61 82 + #define CK_FLEXGEN_38 62 83 + #define CK_FLEXGEN_39 63 84 + #define CK_FLEXGEN_40 64 85 + #define CK_FLEXGEN_41 65 86 + #define CK_FLEXGEN_42 66 87 + #define CK_FLEXGEN_43 67 88 + #define CK_FLEXGEN_44 68 89 + #define CK_FLEXGEN_45 69 90 + #define CK_FLEXGEN_46 70 91 + #define CK_FLEXGEN_47 71 92 + #define CK_FLEXGEN_48 72 93 + #define CK_FLEXGEN_49 73 94 + #define CK_FLEXGEN_50 74 95 + #define CK_FLEXGEN_51 75 96 + #define CK_FLEXGEN_52 76 97 + #define CK_FLEXGEN_53 77 98 + #define CK_FLEXGEN_54 78 99 + #define CK_FLEXGEN_55 79 100 + #define CK_FLEXGEN_56 80 101 + #define CK_FLEXGEN_57 81 102 + #define CK_FLEXGEN_58 82 103 + #define CK_FLEXGEN_59 83 104 + #define CK_FLEXGEN_60 84 105 + #define CK_FLEXGEN_61 85 106 + #define CK_FLEXGEN_62 86 107 + #define CK_FLEXGEN_63 87 108 + 109 + /* LOW SPEED MCU CLOCK */ 110 + #define CK_ICN_LS_MCU 88 111 + 112 + #define CK_BUS_STM 89 113 + #define CK_BUS_FMC 90 114 + #define CK_BUS_ETH1 91 115 + #define CK_BUS_ETH2 92 116 + #define CK_BUS_DDRPHYC 93 117 + #define CK_BUS_SYSCPU1 94 118 + #define CK_BUS_HPDMA1 95 119 + #define CK_BUS_HPDMA2 96 120 + #define CK_BUS_HPDMA3 97 121 + #define CK_BUS_ADC1 98 122 + #define CK_BUS_ADC2 99 123 + #define CK_BUS_IPCC1 100 124 + #define CK_BUS_DCMIPSSI 101 125 + #define CK_BUS_CRC 102 126 + #define CK_BUS_MDF1 103 127 + #define CK_BUS_BKPSRAM 104 128 + #define CK_BUS_HASH1 105 129 + #define CK_BUS_HASH2 106 130 + #define CK_BUS_RNG1 107 131 + #define CK_BUS_RNG2 108 132 + #define CK_BUS_CRYP1 109 133 + #define CK_BUS_CRYP2 110 134 + #define CK_BUS_SAES 111 135 + #define CK_BUS_PKA 112 136 + #define CK_BUS_GPIOA 113 137 + #define CK_BUS_GPIOB 114 138 + #define CK_BUS_GPIOC 115 139 + #define CK_BUS_GPIOD 116 140 + #define CK_BUS_GPIOE 117 141 + #define CK_BUS_GPIOF 118 142 + #define CK_BUS_GPIOG 119 143 + #define CK_BUS_GPIOH 120 144 + #define CK_BUS_GPIOI 121 145 + #define CK_BUS_GPIOZ 122 146 + #define CK_BUS_RTC 124 147 + #define CK_BUS_LPUART1 125 148 + #define CK_BUS_LPTIM3 126 149 + #define CK_BUS_LPTIM4 127 150 + #define CK_BUS_LPTIM5 128 151 + #define CK_BUS_TIM2 129 152 + #define CK_BUS_TIM3 130 153 + #define CK_BUS_TIM4 131 154 + #define CK_BUS_TIM5 132 155 + #define CK_BUS_TIM6 133 156 + #define CK_BUS_TIM7 134 157 + #define CK_BUS_TIM10 135 158 + #define CK_BUS_TIM11 136 159 + #define CK_BUS_TIM12 137 160 + #define CK_BUS_TIM13 138 161 + #define CK_BUS_TIM14 139 162 + #define CK_BUS_LPTIM1 140 163 + #define CK_BUS_LPTIM2 141 164 + #define CK_BUS_SPI2 142 165 + #define CK_BUS_SPI3 143 166 + #define CK_BUS_SPDIFRX 144 167 + #define CK_BUS_USART2 145 168 + #define CK_BUS_USART3 146 169 + #define CK_BUS_UART4 147 170 + #define CK_BUS_UART5 148 171 + #define CK_BUS_I2C1 149 172 + #define CK_BUS_I2C2 150 173 + #define CK_BUS_I2C3 151 174 + #define CK_BUS_I3C1 152 175 + #define CK_BUS_I3C2 153 176 + #define CK_BUS_I3C3 154 177 + #define CK_BUS_TIM1 155 178 + #define CK_BUS_TIM8 156 179 + #define CK_BUS_TIM15 157 180 + #define CK_BUS_TIM16 158 181 + #define CK_BUS_TIM17 159 182 + #define CK_BUS_SAI1 160 183 + #define CK_BUS_SAI2 161 184 + #define CK_BUS_SAI3 162 185 + #define CK_BUS_SAI4 163 186 + #define CK_BUS_USART1 164 187 + #define CK_BUS_USART6 165 188 + #define CK_BUS_UART7 166 189 + #define CK_BUS_FDCAN 167 190 + #define CK_BUS_SPI1 168 191 + #define CK_BUS_SPI4 169 192 + #define CK_BUS_SPI5 170 193 + #define CK_BUS_SPI6 171 194 + #define CK_BUS_BSEC 172 195 + #define CK_BUS_IWDG1 173 196 + #define CK_BUS_IWDG2 174 197 + #define CK_BUS_IWDG3 175 198 + #define CK_BUS_IWDG4 176 199 + #define CK_BUS_WWDG1 177 200 + #define CK_BUS_VREF 178 201 + #define CK_BUS_DTS 179 202 + #define CK_BUS_SERC 180 203 + #define CK_BUS_HDP 181 204 + #define CK_BUS_DDRPERFM 182 205 + #define CK_BUS_OTG 183 206 + #define CK_BUS_LTDC 184 207 + #define CK_BUS_CSI 185 208 + #define CK_BUS_DCMIPP 186 209 + #define CK_BUS_DDRC 187 210 + #define CK_BUS_DDRCFG 188 211 + #define CK_BUS_STGEN 189 212 + #define CK_SYSDBG 190 213 + #define CK_KER_TIM2 191 214 + #define CK_KER_TIM3 192 215 + #define CK_KER_TIM4 193 216 + #define CK_KER_TIM5 194 217 + #define CK_KER_TIM6 195 218 + #define CK_KER_TIM7 196 219 + #define CK_KER_TIM10 197 220 + #define CK_KER_TIM11 198 221 + #define CK_KER_TIM12 199 222 + #define CK_KER_TIM13 200 223 + #define CK_KER_TIM14 201 224 + #define CK_KER_TIM1 202 225 + #define CK_KER_TIM8 203 226 + #define CK_KER_TIM15 204 227 + #define CK_KER_TIM16 205 228 + #define CK_KER_TIM17 206 229 + #define CK_BUS_SYSRAM 207 230 + #define CK_BUS_RETRAM 208 231 + #define CK_BUS_OSPI1 209 232 + #define CK_BUS_OTFD1 210 233 + #define CK_BUS_SRAM1 211 234 + #define CK_BUS_SDMMC1 212 235 + #define CK_BUS_SDMMC2 213 236 + #define CK_BUS_SDMMC3 214 237 + #define CK_BUS_DDR 215 238 + #define CK_BUS_RISAF4 216 239 + #define CK_BUS_USBHOHCI 217 240 + #define CK_BUS_USBHEHCI 218 241 + #define CK_KER_LPTIM1 219 242 + #define CK_KER_LPTIM2 220 243 + #define CK_KER_USART2 221 244 + #define CK_KER_UART4 222 245 + #define CK_KER_USART3 223 246 + #define CK_KER_UART5 224 247 + #define CK_KER_SPI2 225 248 + #define CK_KER_SPI3 226 249 + #define CK_KER_SPDIFRX 227 250 + #define CK_KER_I2C1 228 251 + #define CK_KER_I2C2 229 252 + #define CK_KER_I3C1 230 253 + #define CK_KER_I3C2 231 254 + #define CK_KER_I2C3 232 255 + #define CK_KER_I3C3 233 256 + #define CK_KER_SPI1 234 257 + #define CK_KER_SPI4 235 258 + #define CK_KER_SPI5 236 259 + #define CK_KER_SPI6 237 260 + #define CK_KER_USART1 238 261 + #define CK_KER_USART6 239 262 + #define CK_KER_UART7 240 263 + #define CK_KER_MDF1 241 264 + #define CK_KER_SAI1 242 265 + #define CK_KER_SAI2 243 266 + #define CK_KER_SAI3 244 267 + #define CK_KER_SAI4 245 268 + #define CK_KER_FDCAN 246 269 + #define CK_KER_CSI 247 270 + #define CK_KER_CSITXESC 248 271 + #define CK_KER_CSIPHY 249 272 + #define CK_KER_STGEN 250 273 + #define CK_KER_USB2PHY2EN 251 274 + #define CK_KER_LPUART1 252 275 + #define CK_KER_LPTIM3 253 276 + #define CK_KER_LPTIM4 254 277 + #define CK_KER_LPTIM5 255 278 + #define CK_KER_TSDBG 256 279 + #define CK_KER_TPIU 257 280 + #define CK_BUS_ETR 258 281 + #define CK_BUS_SYSATB 259 282 + #define CK_KER_ADC1 260 283 + #define CK_KER_ADC2 261 284 + #define CK_KER_OSPI1 262 285 + #define CK_KER_FMC 263 286 + #define CK_KER_SDMMC1 264 287 + #define CK_KER_SDMMC2 265 288 + #define CK_KER_SDMMC3 266 289 + #define CK_KER_ETH1 267 290 + #define CK_KER_ETH2 268 291 + #define CK_KER_ETH1PTP 269 292 + #define CK_KER_ETH2PTP 270 293 + #define CK_KER_USB2PHY1 271 294 + #define CK_KER_USB2PHY2 272 295 + #define CK_MCO1 273 296 + #define CK_MCO2 274 297 + #define CK_KER_DTS 275 298 + #define CK_ETH1_RX 276 299 + #define CK_ETH1_TX 277 300 + #define CK_ETH1_MAC 278 301 + #define CK_ETH2_RX 279 302 + #define CK_ETH2_TX 280 303 + #define CK_ETH2_MAC 281 304 + #define CK_ETH1_STP 282 305 + #define CK_ETH2_STP 283 306 + #define CK_KER_LTDC 284 307 + #define HSE_DIV2_CK 285 308 + #define CK_DBGMCU 286 309 + #define CK_DAP 287 310 + #define CK_KER_ETR 288 311 + #define CK_KER_STM 289 312 + 313 + #define CK_SCMI_ICN_HS_MCU 0 314 + #define CK_SCMI_ICN_SDMMC 1 315 + #define CK_SCMI_ICN_DDR 2 316 + #define CK_SCMI_ICN_DISPLAY 3 317 + #define CK_SCMI_ICN_HSL 4 318 + #define CK_SCMI_ICN_NIC 5 319 + #define CK_SCMI_FLEXGEN_07 7 320 + #define CK_SCMI_FLEXGEN_08 8 321 + #define CK_SCMI_FLEXGEN_09 9 322 + #define CK_SCMI_FLEXGEN_10 10 323 + #define CK_SCMI_FLEXGEN_11 11 324 + #define CK_SCMI_FLEXGEN_12 12 325 + #define CK_SCMI_FLEXGEN_13 13 326 + #define CK_SCMI_FLEXGEN_14 14 327 + #define CK_SCMI_FLEXGEN_15 15 328 + #define CK_SCMI_FLEXGEN_16 16 329 + #define CK_SCMI_FLEXGEN_17 17 330 + #define CK_SCMI_FLEXGEN_18 18 331 + #define CK_SCMI_FLEXGEN_19 19 332 + #define CK_SCMI_FLEXGEN_20 20 333 + #define CK_SCMI_FLEXGEN_21 21 334 + #define CK_SCMI_FLEXGEN_22 22 335 + #define CK_SCMI_FLEXGEN_23 23 336 + #define CK_SCMI_FLEXGEN_24 24 337 + #define CK_SCMI_FLEXGEN_25 25 338 + #define CK_SCMI_FLEXGEN_26 26 339 + #define CK_SCMI_FLEXGEN_27 27 340 + #define CK_SCMI_FLEXGEN_28 28 341 + #define CK_SCMI_FLEXGEN_29 29 342 + #define CK_SCMI_FLEXGEN_30 30 343 + #define CK_SCMI_FLEXGEN_31 31 344 + #define CK_SCMI_FLEXGEN_32 32 345 + #define CK_SCMI_FLEXGEN_33 33 346 + #define CK_SCMI_FLEXGEN_34 34 347 + #define CK_SCMI_FLEXGEN_35 35 348 + #define CK_SCMI_FLEXGEN_36 36 349 + #define CK_SCMI_FLEXGEN_37 37 350 + #define CK_SCMI_FLEXGEN_38 38 351 + #define CK_SCMI_FLEXGEN_39 39 352 + #define CK_SCMI_FLEXGEN_40 40 353 + #define CK_SCMI_FLEXGEN_41 41 354 + #define CK_SCMI_FLEXGEN_42 42 355 + #define CK_SCMI_FLEXGEN_43 43 356 + #define CK_SCMI_FLEXGEN_44 44 357 + #define CK_SCMI_FLEXGEN_45 45 358 + #define CK_SCMI_FLEXGEN_46 46 359 + #define CK_SCMI_FLEXGEN_47 47 360 + #define CK_SCMI_FLEXGEN_48 48 361 + #define CK_SCMI_FLEXGEN_49 49 362 + #define CK_SCMI_FLEXGEN_50 50 363 + #define CK_SCMI_FLEXGEN_51 51 364 + #define CK_SCMI_FLEXGEN_52 52 365 + #define CK_SCMI_FLEXGEN_53 53 366 + #define CK_SCMI_FLEXGEN_54 54 367 + #define CK_SCMI_FLEXGEN_55 55 368 + #define CK_SCMI_FLEXGEN_56 56 369 + #define CK_SCMI_FLEXGEN_57 57 370 + #define CK_SCMI_FLEXGEN_58 58 371 + #define CK_SCMI_FLEXGEN_59 59 372 + #define CK_SCMI_FLEXGEN_60 60 373 + #define CK_SCMI_FLEXGEN_61 61 374 + #define CK_SCMI_FLEXGEN_62 62 375 + #define CK_SCMI_FLEXGEN_63 63 376 + #define CK_SCMI_ICN_LS_MCU 64 377 + #define CK_SCMI_HSE 65 378 + #define CK_SCMI_LSE 66 379 + #define CK_SCMI_HSI 67 380 + #define CK_SCMI_LSI 68 381 + #define CK_SCMI_MSI 69 382 + #define CK_SCMI_HSE_DIV2 70 383 + #define CK_SCMI_CPU1 71 384 + #define CK_SCMI_SYSCPU1 72 385 + #define CK_SCMI_PLL2 73 386 + #define CK_SCMI_RTC 74 387 + #define CK_SCMI_RTCCK 75 388 + #define CK_SCMI_ICN_APB1 76 389 + #define CK_SCMI_ICN_APB2 77 390 + #define CK_SCMI_ICN_APB3 78 391 + #define CK_SCMI_ICN_APB4 79 392 + #define CK_SCMI_ICN_APB5 80 393 + #define CK_SCMI_ICN_APBDBG 81 394 + #define CK_SCMI_TIMG1 82 395 + #define CK_SCMI_TIMG2 83 396 + #define CK_SCMI_BKPSRAM 84 397 + #define CK_SCMI_BSEC 85 398 + #define CK_SCMI_BUS_ETR 86 399 + #define CK_SCMI_FMC 87 400 + #define CK_SCMI_GPIOA 88 401 + #define CK_SCMI_GPIOB 89 402 + #define CK_SCMI_GPIOC 90 403 + #define CK_SCMI_GPIOD 91 404 + #define CK_SCMI_GPIOE 92 405 + #define CK_SCMI_GPIOF 93 406 + #define CK_SCMI_GPIOG 94 407 + #define CK_SCMI_GPIOH 95 408 + #define CK_SCMI_GPIOI 96 409 + #define CK_SCMI_GPIOZ 97 410 + #define CK_SCMI_HPDMA1 98 411 + #define CK_SCMI_HPDMA2 99 412 + #define CK_SCMI_HPDMA3 100 413 + #define CK_SCMI_IPCC1 101 414 + #define CK_SCMI_RETRAM 102 415 + #define CK_SCMI_SRAM1 103 416 + #define CK_SCMI_SYSRAM 104 417 + #define CK_SCMI_OSPI1 105 418 + #define CK_SCMI_TPIU 106 419 + #define CK_SCMI_SYSDBG 107 420 + #define CK_SCMI_SYSATB 108 421 + #define CK_SCMI_TSDBG 109 422 + #define CK_SCMI_BUS_STM 110 423 + #define CK_SCMI_KER_STM 111 424 + #define CK_SCMI_KER_ETR 112 425 + 426 + #endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */

+138

include/dt-bindings/reset/st,stm32mp21-rcc.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 + /* 3 + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 + * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_STM32MP21_RESET_H_ 8 + #define _DT_BINDINGS_STM32MP21_RESET_H_ 9 + 10 + #define TIM1_R 0 11 + #define TIM2_R 1 12 + #define TIM3_R 2 13 + #define TIM4_R 3 14 + #define TIM5_R 4 15 + #define TIM6_R 5 16 + #define TIM7_R 6 17 + #define TIM8_R 7 18 + #define TIM10_R 8 19 + #define TIM11_R 9 20 + #define TIM12_R 10 21 + #define TIM13_R 11 22 + #define TIM14_R 12 23 + #define TIM15_R 13 24 + #define TIM16_R 14 25 + #define TIM17_R 15 26 + #define LPTIM1_R 16 27 + #define LPTIM2_R 17 28 + #define LPTIM3_R 18 29 + #define LPTIM4_R 19 30 + #define LPTIM5_R 20 31 + #define SPI1_R 21 32 + #define SPI2_R 22 33 + #define SPI3_R 23 34 + #define SPI4_R 24 35 + #define SPI5_R 25 36 + #define SPI6_R 26 37 + #define SPDIFRX_R 27 38 + #define USART1_R 28 39 + #define USART2_R 29 40 + #define USART3_R 30 41 + #define UART4_R 31 42 + #define UART5_R 32 43 + #define USART6_R 33 44 + #define UART7_R 34 45 + #define LPUART1_R 35 46 + #define I2C1_R 36 47 + #define I2C2_R 37 48 + #define I2C3_R 38 49 + #define SAI1_R 39 50 + #define SAI2_R 40 51 + #define SAI3_R 41 52 + #define SAI4_R 42 53 + #define MDF1_R 43 54 + #define FDCAN_R 44 55 + #define HDP_R 45 56 + #define ADC1_R 46 57 + #define ADC2_R 47 58 + #define ETH1_R 48 59 + #define ETH2_R 49 60 + #define USBH_R 50 61 + #define USB2PHY1_R 51 62 + #define USB2PHY2_R 52 63 + #define SDMMC1_R 53 64 + #define SDMMC1DLL_R 54 65 + #define SDMMC2_R 55 66 + #define SDMMC2DLL_R 56 67 + #define SDMMC3_R 57 68 + #define SDMMC3DLL_R 58 69 + #define LTDC_R 59 70 + #define CSI_R 60 71 + #define DCMIPP_R 61 72 + #define DCMIPSSI_R 62 73 + #define WWDG1_R 63 74 + #define VREF_R 64 75 + #define DTS_R 65 76 + #define CRC_R 66 77 + #define SERC_R 67 78 + #define I3C1_R 68 79 + #define I3C2_R 69 80 + #define I3C3_R 70 81 + #define IWDG2_KER_R 71 82 + #define IWDG4_KER_R 72 83 + #define RNG1_R 73 84 + #define RNG2_R 74 85 + #define PKA_R 75 86 + #define SAES_R 76 87 + #define HASH1_R 77 88 + #define HASH2_R 78 89 + #define CRYP1_R 79 90 + #define CRYP2_R 80 91 + #define OSPI1_R 81 92 + #define OSPI1DLL_R 82 93 + #define OTG_R 83 94 + #define FMC_R 84 95 + #define DBG_R 85 96 + #define GPIOA_R 86 97 + #define GPIOB_R 87 98 + #define GPIOC_R 88 99 + #define GPIOD_R 89 100 + #define GPIOE_R 90 101 + #define GPIOF_R 91 102 + #define GPIOG_R 92 103 + #define GPIOH_R 93 104 + #define GPIOI_R 94 105 + #define GPIOZ_R 95 106 + #define HPDMA1_R 96 107 + #define HPDMA2_R 97 108 + #define HPDMA3_R 98 109 + #define IPCC1_R 99 110 + #define C2_HOLDBOOT_R 100 111 + #define C1_HOLDBOOT_R 101 112 + #define C1_R 102 113 + #define C1P1POR_R 103 114 + #define C1P1_R 104 115 + #define C2_R 105 116 + #define SYS_R 106 117 + #define VSW_R 107 118 + #define C1MS_R 108 119 + #define DDRCP_R 109 120 + #define DDRCAPB_R 110 121 + #define DDRPHYCAPB_R 111 122 + #define DDRCFG_R 112 123 + #define DDR_R 113 124 + #define DDRPERFM_R 114 125 + #define IWDG1_SYS_R 116 126 + #define IWDG2_SYS_R 117 127 + #define IWDG3_SYS_R 118 128 + #define IWDG4_SYS_R 119 129 + 130 + #define RST_SCMI_C1_R 0 131 + #define RST_SCMI_C2_R 1 132 + #define RST_SCMI_C1_HOLDBOOT_R 2 133 + #define RST_SCMI_C2_HOLDBOOT_R 3 134 + #define RST_SCMI_FMC 4 135 + #define RST_SCMI_OSPI1 5 136 + #define RST_SCMI_OSPI1DLL 6 137 + 138 + #endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */

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