Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'i2c-for-5.19-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang:
"Two driver bugfixes and a typo fix"
* tag 'i2c-for-5.19-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: cadence: Change large transfer count reset logic to be unconditional
i2c: imx: fix typo in comment
i2c: mlxcpld: Fix register setting for 400KHz frequency
+7
-27
+5
-25
drivers/i2c/busses/i2c-cadence.c
+5
-25
drivers/i2c/busses/i2c-cadence.c
···
388
388
*/
389
389
static irqreturn_t cdns_i2c_master_isr(void *ptr)
390
390
{
391
-
unsigned int isr_status, avail_bytes, updatetx;
391
+
unsigned int isr_status, avail_bytes;
392
392
unsigned int bytes_to_send;
393
-
bool hold_quirk;
393
+
bool updatetx;
394
394
struct cdns_i2c *id = ptr;
395
395
/* Signal completion only after everything is updated */
396
396
int done_flag = 0;
···
410
410
* Check if transfer size register needs to be updated again for a
411
411
* large data receive operation.
412
412
*/
413
-
updatetx = 0;
414
-
if (id->recv_count > id->curr_recv_count)
415
-
updatetx = 1;
416
-
417
-
hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
413
+
updatetx = id->recv_count > id->curr_recv_count;
418
414
419
415
/* When receiving, handle data interrupt and completion interrupt */
420
416
if (id->p_recv_buf &&
···
441
445
break;
442
446
}
443
447
444
-
if (cdns_is_holdquirk(id, hold_quirk))
448
+
if (cdns_is_holdquirk(id, updatetx))
445
449
break;
446
450
}
447
451
···
452
456
* maintain transfer size non-zero while performing a large
453
457
* receive operation.
454
458
*/
455
-
if (cdns_is_holdquirk(id, hold_quirk)) {
459
+
if (cdns_is_holdquirk(id, updatetx)) {
456
460
/* wait while fifo is full */
457
461
while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
458
462
(id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
···
472
476
cdns_i2c_writereg(id->recv_count -
473
477
CDNS_I2C_FIFO_DEPTH,
474
478
CDNS_I2C_XFER_SIZE_OFFSET);
475
-
id->curr_recv_count = id->recv_count;
476
-
}
477
-
} else if (id->recv_count && !hold_quirk &&
478
-
!id->curr_recv_count) {
479
-
480
-
/* Set the slave address in address register*/
481
-
cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
482
-
CDNS_I2C_ADDR_OFFSET);
483
-
484
-
if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
485
-
cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
486
-
CDNS_I2C_XFER_SIZE_OFFSET);
487
-
id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
488
-
} else {
489
-
cdns_i2c_writereg(id->recv_count,
490
-
CDNS_I2C_XFER_SIZE_OFFSET);
491
479
id->curr_recv_count = id->recv_count;
492
480
}
493
481
}
+1
-1
drivers/i2c/busses/i2c-imx.c
+1
-1
drivers/i2c/busses/i2c-imx.c
···
66
66
67
67
/* IMX I2C registers:
68
68
* the I2C register offset is different between SoCs,
69
-
* to provid support for all these chips, split the
69
+
* to provide support for all these chips, split the
70
70
* register offset into a fixed base address and a
71
71
* variable shift value, then the full register offset
72
72
* will be calculated by
+1
-1
drivers/i2c/busses/i2c-mlxcpld.c
+1
-1
drivers/i2c/busses/i2c-mlxcpld.c