Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: freescale: fsl-samsung-hdmi: Replace register defines with macro
There are 47 registers defined as PHY_REG_xx were xx goes from 00 to
47. Simplify this by replacing them all with a macro which is passed
the register number to return the proper register offset.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Link: https://lore.kernel.org/r/20240914112816.520224-2-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Adam Ford
and committed by
Vinod Koul
4a5a9e25
3d7de6e8
+40
-87
+40
-87
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+40
-87
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
···
14
14
#include <linux/platform_device.h>
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15
#include <linux/pm_runtime.h>
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16
17
-
#define PHY_REG_00 0x00
18
-
#define PHY_REG_01 0x04
19
-
#define PHY_REG_02 0x08
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-
#define PHY_REG_08 0x20
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-
#define PHY_REG_09 0x24
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-
#define PHY_REG_10 0x28
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-
#define PHY_REG_11 0x2c
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+
#define PHY_REG(reg) (reg * 4)
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18
25
-
#define PHY_REG_12 0x30
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-
#define REG12_CK_DIV_MASK GENMASK(5, 4)
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+
#define REG12_CK_DIV_MASK GENMASK(5, 4)
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20
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-
#define PHY_REG_13 0x34
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-
#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
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+
#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
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22
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-
#define PHY_REG_14 0x38
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-
#define REG14_TOL_MASK GENMASK(7, 4)
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-
#define REG14_RP_CODE_MASK GENMASK(3, 1)
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-
#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
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+
#define REG14_TOL_MASK GENMASK(7, 4)
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+
#define REG14_RP_CODE_MASK GENMASK(3, 1)
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+
#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
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26
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-
#define PHY_REG_15 0x3c
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-
#define PHY_REG_16 0x40
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#define PHY_REG_17 0x44
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#define PHY_REG_18 0x48
40
-
#define PHY_REG_19 0x4c
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-
#define PHY_REG_20 0x50
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-
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#define PHY_REG_21 0x54
44
-
#define REG21_SEL_TX_CK_INV BIT(7)
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-
#define REG21_PMS_S_MASK GENMASK(3, 0)
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-
47
-
#define PHY_REG_22 0x58
48
-
#define PHY_REG_23 0x5c
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-
#define PHY_REG_24 0x60
50
-
#define PHY_REG_25 0x64
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-
#define PHY_REG_26 0x68
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-
#define PHY_REG_27 0x6c
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-
#define PHY_REG_28 0x70
54
-
#define PHY_REG_29 0x74
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-
#define PHY_REG_30 0x78
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-
#define PHY_REG_31 0x7c
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-
#define PHY_REG_32 0x80
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-
27
+
#define REG21_SEL_TX_CK_INV BIT(7)
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+
#define REG21_PMS_S_MASK GENMASK(3, 0)
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29
/*
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* REG33 does not match the ref manual. According to Sandor Yu from NXP,
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* "There is a doc issue on the i.MX8MP latest RM"
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* REG33 is being used per guidance from Sandor
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*/
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+
#define REG33_MODE_SET_DONE BIT(7)
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+
#define REG33_FIX_DA BIT(1)
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36
65
-
#define PHY_REG_33 0x84
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-
#define REG33_MODE_SET_DONE BIT(7)
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-
#define REG33_FIX_DA BIT(1)
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-
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-
#define PHY_REG_34 0x88
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-
#define REG34_PHY_READY BIT(7)
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-
#define REG34_PLL_LOCK BIT(6)
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-
#define REG34_PHY_CLK_READY BIT(5)
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-
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-
#define PHY_REG_35 0x8c
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-
#define PHY_REG_36 0x90
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-
#define PHY_REG_37 0x94
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-
#define PHY_REG_38 0x98
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-
#define PHY_REG_39 0x9c
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-
#define PHY_REG_40 0xa0
80
-
#define PHY_REG_41 0xa4
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-
#define PHY_REG_42 0xa8
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-
#define PHY_REG_43 0xac
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-
#define PHY_REG_44 0xb0
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-
#define PHY_REG_45 0xb4
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-
#define PHY_REG_46 0xb8
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-
#define PHY_REG_47 0xbc
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+
#define REG34_PHY_READY BIT(7)
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+
#define REG34_PLL_LOCK BIT(6)
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+
#define REG34_PHY_CLK_READY BIT(5)
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40
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#define PHY_PLL_DIV_REGS_NUM 6
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42
···
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};
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static const struct reg_settings common_phy_cfg[] = {
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-
{ PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 },
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-
{ PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 },
327
-
{ PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 },
372
+
{ PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 },
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+
{ PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },
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+
{ PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },
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/* REG12 pixclk specific */
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/* REG13 pixclk specific */
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/* REG14 pixclk specific */
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-
{ PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c },
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-
{ PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 },
333
-
{ PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 },
378
+
{ PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c },
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+
{ PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 },
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+
{ PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 },
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381
/* REG21 pixclk specific */
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-
{ PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 },
336
-
{ PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f },
337
-
{ PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 },
338
-
{ PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 },
339
-
{ PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 },
340
-
{ PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 },
341
-
{ PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 },
342
-
{ PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 },
343
-
{ PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 },
344
-
{ PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 },
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-
{ PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f },
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-
{ PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 },
347
-
{ PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 }
382
+
{ PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },
383
+
{ PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f },
384
+
{ PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 },
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+
{ PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 },
386
+
{ PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 },
387
+
{ PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 },
388
+
{ PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 },
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+
{ PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 },
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+
{ PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 },
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+
{ PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 },
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+
{ PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f },
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+
{ PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 },
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+
{ PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 }
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};
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struct fsl_samsung_hdmi_phy {
···
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}
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writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div),
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-
phy->regs + PHY_REG_21);
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+
phy->regs + PHY_REG(21));
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446
}
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401
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static void
···
422
469
break;
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}
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-
writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12);
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+
writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12));
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473
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/*
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* Calculation for the frequency lock detector target code (fld_tg_code)
···
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/* FLD_TOL and FLD_RP_CODE taken from downstream driver */
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writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code),
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-
phy->regs + PHY_REG_13);
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+
phy->regs + PHY_REG(13));
446
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writeb(FIELD_PREP(REG14_TOL_MASK, 2) |
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FIELD_PREP(REG14_RP_CODE_MASK, 2) |
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FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8),
449
-
phy->regs + PHY_REG_14);
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+
phy->regs + PHY_REG(14));
450
497
}
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static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
···
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u8 val;
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/* HDMI PHY init */
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-
writeb(REG33_FIX_DA, phy->regs + PHY_REG_33);
506
+
writeb(REG33_FIX_DA, phy->regs + PHY_REG(33));
460
507
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/* common PHY registers */
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for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++)
···
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511
465
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/* set individual PLL registers PHY_REG2 ... PHY_REG7 */
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for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++)
467
-
writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4);
514
+
writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4);
468
515
469
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fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg);
470
517
fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);
471
518
472
-
writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33);
519
+
writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));
473
520
474
-
ret = readb_poll_timeout(phy->regs + PHY_REG_34, val,
521
+
ret = readb_poll_timeout(phy->regs + PHY_REG(34), val,
475
522
val & REG34_PLL_LOCK, 50, 20000);
476
523
if (ret)
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dev_err(phy->dev, "PLL failed to lock\n");