+2 -4

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 904 904 struct amdgpu_reg_access reg; 905 905 /* protects concurrent PCIE register access */ 906 906 spinlock_t pcie_idx_lock; 907 907 - amdgpu_rreg64_ext_t pcie_rreg64_ext; 908 908 - amdgpu_wreg64_ext_t pcie_wreg64_ext; 909 907 struct amdgpu_doorbell doorbell; 910 908 911 909 /* clock/pll info */ ··· 1306 1308 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1307 1309 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1308 1310 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1309 1309 - #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1310 1310 - #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1311 1311 + #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1312 1312 + #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1311 1313 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1312 1314 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1313 1315 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg))

-18

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 858 858 return adev->nbio.funcs->get_rev_id(adev); 859 859 } 860 860 861 861 - static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg) 862 862 - { 863 863 - dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg); 864 864 - BUG(); 865 865 - return 0; 866 866 - } 867 867 - 868 868 - static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v) 869 869 - { 870 870 - dev_err(adev->dev, 871 871 - "Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n", 872 872 - reg, v); 873 873 - BUG(); 874 874 - } 875 875 - 876 861 static uint32_t amdgpu_device_get_vbios_flags(struct amdgpu_device *adev) 877 862 { 878 863 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU)) ··· 3688 3703 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 3689 3704 3690 3705 amdgpu_reg_access_init(adev); 3691 3691 - 3692 3692 - adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; 3693 3693 - adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; 3694 3706 3695 3707 dev_info( 3696 3708 adev->dev,

+21

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

reviewed

··· 65 65 adev->reg.pcie.wreg_ext = NULL; 66 66 adev->reg.pcie.rreg64 = NULL; 67 67 adev->reg.pcie.wreg64 = NULL; 68 68 + adev->reg.pcie.rreg64_ext = NULL; 69 69 + adev->reg.pcie.wreg64_ext = NULL; 68 70 adev->reg.pcie.port_rreg = NULL; 69 71 adev->reg.pcie.port_wreg = NULL; 70 72 } ··· 243 241 return; 244 242 } 245 243 adev->reg.pcie.wreg64(adev, reg, v); 244 244 + } 245 245 + 246 246 + uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg) 247 247 + { 248 248 + if (!adev->reg.pcie.rreg64_ext) { 249 249 + dev_err_once(adev->dev, "PCIE EXT 64-bit register read not supported\n"); 250 250 + return 0; 251 251 + } 252 252 + return adev->reg.pcie.rreg64_ext(adev, reg); 253 253 + } 254 254 + 255 255 + void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, 256 256 + uint64_t v) 257 257 + { 258 258 + if (!adev->reg.pcie.wreg64_ext) { 259 259 + dev_err_once(adev->dev, "PCIE EXT 64-bit register write not supported\n"); 260 260 + return; 261 261 + } 262 262 + adev->reg.pcie.wreg64_ext(adev, reg, v); 246 263 } 247 264 248 265 uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg)

+7 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h

reviewed

··· 35 35 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); 36 36 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); 37 37 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); 38 38 + typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); 39 39 + typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); 38 40 39 41 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, 40 42 uint32_t); ··· 62 60 amdgpu_wreg_ext_t wreg_ext; 63 61 amdgpu_rreg64_t rreg64; 64 62 amdgpu_wreg64_t wreg64; 63 63 + amdgpu_rreg64_ext_t rreg64_ext; 64 64 + amdgpu_wreg64_ext_t wreg64_ext; 65 65 amdgpu_rreg_t port_rreg; 66 66 amdgpu_wreg_t port_wreg; 67 67 }; ··· 102 98 uint32_t v); 103 99 uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg); 104 100 void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v); 101 101 + uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg); 102 102 + void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, 103 103 + uint64_t v); 105 104 uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); 106 105 void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, 107 106 uint32_t v); 108 108 - 109 109 - typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); 110 110 - typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); 111 107 112 108 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, 113 109 uint32_t acc_flags);

+2 -2

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 967 967 adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; 968 968 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 969 969 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 970 970 - adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 971 971 - adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 970 970 + adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 971 971 + adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 972 972 adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; 973 973 adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; 974 974 adev->reg.didt.rreg = &soc15_didt_rreg;

+2 -2

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

reviewed

··· 258 258 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 259 259 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 260 260 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 261 261 - adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 262 262 - adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 261 261 + adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 262 262 + adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 263 263 264 264 adev->asic_funcs = &soc_v1_0_asic_funcs; 265 265