Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes froom Stephen Boyd:
"A handful of fixes for the stm32mp1 clk driver came in during the
merge window for the driver that got merged in the merge window.
Plus a warning fix for unused PM ops and a couple fixes for the meson
clk driver clk names that went unnoticed with the regmap rework.
There's also another fix in here for the mux rounding flag which
wasn't doing what it said it did, but now it does"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
clk: meson: meson8b: fix meson8b_fclk_div3_div clock name
clk: meson: drop meson_aoclk_gate_regmap_ops
clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmap
clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux
clk: cs2000: mark resume function as __maybe_unused
clk: stm32mp1: remove ck_apb_dbg clock
clk: stm32mp1: set stgen_k clock as critical
clk: stm32mp1: add missing tzc2 clock
clk: stm32mp1: fix SAI3 & SAI4 clocks
clk: stm32mp1: remove unused dfsdm_src[] const
clk: stm32mp1: add missing static
+55
-43
+1
-1
drivers/clk/clk-cs2000-cp.c
+1
-1
drivers/clk/clk-cs2000-cp.c
+9
-1
drivers/clk/clk-mux.c
+9
-1
drivers/clk/clk-mux.c
···
112
112
return 0;
113
113
}
114
114
115
+
static int clk_mux_determine_rate(struct clk_hw *hw,
116
+
struct clk_rate_request *req)
117
+
{
118
+
struct clk_mux *mux = to_clk_mux(hw);
119
+
120
+
return clk_mux_determine_rate_flags(hw, req, mux->flags);
121
+
}
122
+
115
123
const struct clk_ops clk_mux_ops = {
116
124
.get_parent = clk_mux_get_parent,
117
125
.set_parent = clk_mux_set_parent,
118
-
.determine_rate = __clk_mux_determine_rate,
126
+
.determine_rate = clk_mux_determine_rate,
119
127
};
120
128
EXPORT_SYMBOL_GPL(clk_mux_ops);
121
129
+23
-31
drivers/clk/clk-stm32mp1.c
+23
-31
drivers/clk/clk-stm32mp1.c
···
216
216
"pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
217
217
};
218
218
219
-
const char * const usart234578_src[] = {
219
+
static const char * const usart234578_src[] = {
220
220
"pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
221
221
};
222
222
223
223
static const char * const usart6_src[] = {
224
224
"pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
225
-
};
226
-
227
-
static const char * const dfsdm_src[] = {
228
-
"pclk2", "ck_mcu"
229
225
};
230
226
231
227
static const char * const fdcan_src[] = {
···
312
316
struct clock_config {
313
317
u32 id;
314
318
const char *name;
315
-
union {
316
-
const char *parent_name;
317
-
const char * const *parent_names;
318
-
};
319
+
const char *parent_name;
320
+
const char * const *parent_names;
319
321
int num_parents;
320
322
unsigned long flags;
321
323
void *cfg;
···
463
469
}
464
470
}
465
471
466
-
const struct clk_ops mp1_gate_clk_ops = {
472
+
static const struct clk_ops mp1_gate_clk_ops = {
467
473
.enable = mp1_gate_clk_enable,
468
474
.disable = mp1_gate_clk_disable,
469
475
.is_enabled = clk_gate_is_enabled,
···
692
698
mp1_gate_clk_disable(hw);
693
699
}
694
700
695
-
const struct clk_ops mp1_mgate_clk_ops = {
701
+
static const struct clk_ops mp1_mgate_clk_ops = {
696
702
.enable = mp1_mgate_clk_enable,
697
703
.disable = mp1_mgate_clk_disable,
698
704
.is_enabled = clk_gate_is_enabled,
···
726
732
return 0;
727
733
}
728
734
729
-
const struct clk_ops clk_mmux_ops = {
735
+
static const struct clk_ops clk_mmux_ops = {
730
736
.get_parent = clk_mmux_get_parent,
731
737
.set_parent = clk_mmux_set_parent,
732
738
.determine_rate = __clk_mux_determine_rate,
···
1042
1048
u32 offset;
1043
1049
};
1044
1050
1045
-
struct clk_hw *_clk_register_pll(struct device *dev,
1046
-
struct clk_hw_onecell_data *clk_data,
1047
-
void __iomem *base, spinlock_t *lock,
1048
-
const struct clock_config *cfg)
1051
+
static struct clk_hw *_clk_register_pll(struct device *dev,
1052
+
struct clk_hw_onecell_data *clk_data,
1053
+
void __iomem *base, spinlock_t *lock,
1054
+
const struct clock_config *cfg)
1049
1055
{
1050
1056
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1051
1057
···
1399
1405
G_USBH,
1400
1406
G_ETHSTP,
1401
1407
G_RTCAPB,
1402
-
G_TZC,
1408
+
G_TZC1,
1409
+
G_TZC2,
1403
1410
G_TZPC,
1404
1411
G_IWDG1,
1405
1412
G_BSEC,
···
1412
1417
G_LAST
1413
1418
};
1414
1419
1415
-
struct stm32_mgate mp1_mgate[G_LAST];
1420
+
static struct stm32_mgate mp1_mgate[G_LAST];
1416
1421
1417
1422
#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1418
1423
_mgate, _ops)\
···
1435
1440
&mp1_mgate[_id], &mp1_mgate_clk_ops)
1436
1441
1437
1442
/* Peripheral gates */
1438
-
struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1443
+
static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1439
1444
/* Multi gates */
1440
1445
K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
1441
1446
K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
···
1501
1506
K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
1502
1507
K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
1503
1508
K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
1504
-
K_GATE(G_TZC, RCC_APB5ENSETR, 12, 0),
1509
+
K_GATE(G_TZC2, RCC_APB5ENSETR, 12, 0),
1510
+
K_GATE(G_TZC1, RCC_APB5ENSETR, 11, 0),
1505
1511
K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
1506
1512
K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
1507
1513
K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
···
1596
1600
M_LAST
1597
1601
};
1598
1602
1599
-
struct stm32_mmux ker_mux[M_LAST];
1603
+
static struct stm32_mmux ker_mux[M_LAST];
1600
1604
1601
1605
#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
1602
1606
[_id] = {\
···
1619
1623
_K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1620
1624
&ker_mux[_id], &clk_mmux_ops)
1621
1625
1622
-
const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1626
+
static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1623
1627
/* Kernel multi mux */
1624
1628
K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1625
1629
K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
···
1856
1860
PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1857
1861
PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
1858
1862
CLK_IS_CRITICAL, G_RTCAPB),
1859
-
PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
1863
+
PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
1864
+
PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
1860
1865
PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
1861
1866
PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1862
1867
PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
···
1913
1916
KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
1914
1917
KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
1915
1918
KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
1916
-
KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IGNORE_UNUSED,
1917
-
G_STGEN, M_STGEN),
1919
+
KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
1918
1920
KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
1919
1921
KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
1920
1922
KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
···
1944
1948
KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
1945
1949
KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
1946
1950
KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
1947
-
KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
1948
-
KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
1951
+
KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
1952
+
KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
1949
1953
KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
1950
1954
KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
1951
1955
KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
···
1988
1992
_DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
1989
1993
1990
1994
/* Debug clocks */
1991
-
FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
1992
-
1993
-
GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
1994
-
1995
1995
GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
1996
1996
1997
1997
COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
+4
-3
drivers/clk/clk.c
+4
-3
drivers/clk/clk.c
···
426
426
return now <= rate && now > best;
427
427
}
428
428
429
-
static int
430
-
clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
431
-
unsigned long flags)
429
+
int clk_mux_determine_rate_flags(struct clk_hw *hw,
430
+
struct clk_rate_request *req,
431
+
unsigned long flags)
432
432
{
433
433
struct clk_core *core = hw->core, *parent, *best_parent = NULL;
434
434
int i, num_parents, ret;
···
488
488
489
489
return 0;
490
490
}
491
+
EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
491
492
492
493
struct clk *__clk_lookup(const char *name)
493
494
{
+10
-1
drivers/clk/meson/clk-regmap.c
+10
-1
drivers/clk/meson/clk-regmap.c
···
153
153
val << mux->shift);
154
154
}
155
155
156
+
static int clk_regmap_mux_determine_rate(struct clk_hw *hw,
157
+
struct clk_rate_request *req)
158
+
{
159
+
struct clk_regmap *clk = to_clk_regmap(hw);
160
+
struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
161
+
162
+
return clk_mux_determine_rate_flags(hw, req, mux->flags);
163
+
}
164
+
156
165
const struct clk_ops clk_regmap_mux_ops = {
157
166
.get_parent = clk_regmap_mux_get_parent,
158
167
.set_parent = clk_regmap_mux_set_parent,
159
-
.determine_rate = __clk_mux_determine_rate,
168
+
.determine_rate = clk_regmap_mux_determine_rate,
160
169
};
161
170
EXPORT_SYMBOL_GPL(clk_regmap_mux_ops);
162
171
-2
drivers/clk/meson/gxbb-aoclk.h
-2
drivers/clk/meson/gxbb-aoclk.h
+3
-2
drivers/clk/meson/meson8b.c
+3
-2
drivers/clk/meson/meson8b.c
···
253
253
.mult = 1,
254
254
.div = 3,
255
255
.hw.init = &(struct clk_init_data){
256
-
.name = "fclk_div_div3",
256
+
.name = "fclk_div3_div",
257
257
.ops = &clk_fixed_factor_ops,
258
258
.parent_names = (const char *[]){ "fixed_pll" },
259
259
.num_parents = 1,
···
632
632
.hw.init = &(struct clk_init_data){
633
633
.name = "cpu_clk",
634
634
.ops = &clk_regmap_mux_ro_ops,
635
-
.parent_names = (const char *[]){ "xtal", "cpu_out_sel" },
635
+
.parent_names = (const char *[]){ "xtal",
636
+
"cpu_scale_out_sel" },
636
637
.num_parents = 2,
637
638
.flags = (CLK_SET_RATE_PARENT |
638
639
CLK_SET_RATE_NO_REPARENT),
+2
-2
include/dt-bindings/clock/stm32mp1-clks.h
+2
-2
include/dt-bindings/clock/stm32mp1-clks.h
···
76
76
#define I2C6 63
77
77
#define USART1 64
78
78
#define RTCAPB 65
79
-
#define TZC 66
79
+
#define TZC1 66
80
80
#define TZPC 67
81
81
#define IWDG1 68
82
82
#define BSEC 69
···
123
123
#define CRC1 110
124
124
#define USBH 111
125
125
#define ETHSTP 112
126
+
#define TZC2 113
126
127
127
128
/* Kernel clocks */
128
129
#define SDMMC1_K 118
···
229
228
#define CK_MCO2 212
230
229
231
230
/* TRACE & DEBUG clocks */
232
-
#define DBG 213
233
231
#define CK_DBG 214
234
232
#define CK_TRACE 215
235
233
+3
include/linux/clk-provider.h
+3
include/linux/clk-provider.h
···
765
765
int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
766
766
int __clk_mux_determine_rate_closest(struct clk_hw *hw,
767
767
struct clk_rate_request *req);
768
+
int clk_mux_determine_rate_flags(struct clk_hw *hw,
769
+
struct clk_rate_request *req,
770
+
unsigned long flags);
768
771
void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
769
772
void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
770
773
unsigned long max_rate);