Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
powerpc/radix: Move some functions into #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
With skiboot_defconfig, Clang reports:
CC arch/powerpc/mm/book3s64/radix_tlb.o
arch/powerpc/mm/book3s64/radix_tlb.c:419:20: error: unused function '_tlbie_pid_lpid' [-Werror,-Wunused-function]
static inline void _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
^
arch/powerpc/mm/book3s64/radix_tlb.c:663:20: error: unused function '_tlbie_va_range_lpid' [-Werror,-Wunused-function]
static inline void _tlbie_va_range_lpid(unsigned long start, unsigned long end,
^
This is because those functions are only called from functions
enclosed in a #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
Move below functions inside that #ifdef
* __tlbie_pid_lpid(unsigned long pid,
* __tlbie_va_lpid(unsigned long va, unsigned long pid,
* fixup_tlbie_pid_lpid(unsigned long pid, unsigned long lpid)
* _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
* fixup_tlbie_va_range_lpid(unsigned long va,
* __tlbie_va_range_lpid(unsigned long start, unsigned long end,
* _tlbie_va_range_lpid(unsigned long start, unsigned long end,
Fixes: f0c6fbbb9050 ("KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202307260802.Mjr99P5O-lkp@intel.com/
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/3d72efd39f986ee939d068af69fdce28bd600766.1691568093.git.christophe.leroy@csgroup.eu
authored by
Christophe Leroy
and committed by
Michael Ellerman
4a9dd8f2
ef73dcaa
+121
-119
+121
-119
arch/powerpc/mm/book3s64/radix_tlb.c
+121
-119
arch/powerpc/mm/book3s64/radix_tlb.c
···
127
127
trace_tlbie(0, 0, rb, rs, ric, prs, r);
128
128
}
129
129
130
-
static __always_inline void __tlbie_pid_lpid(unsigned long pid,
131
-
unsigned long lpid,
132
-
unsigned long ric)
133
-
{
134
-
unsigned long rb, rs, prs, r;
135
-
136
-
rb = PPC_BIT(53); /* IS = 1 */
137
-
rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
138
-
prs = 1; /* process scoped */
139
-
r = 1; /* radix format */
140
-
141
-
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
142
-
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
143
-
trace_tlbie(0, 0, rb, rs, ric, prs, r);
144
-
}
145
130
static __always_inline void __tlbie_lpid(unsigned long lpid, unsigned long ric)
146
131
{
147
132
unsigned long rb,rs,prs,r;
···
187
202
trace_tlbie(0, 0, rb, rs, ric, prs, r);
188
203
}
189
204
190
-
static __always_inline void __tlbie_va_lpid(unsigned long va, unsigned long pid,
191
-
unsigned long lpid,
192
-
unsigned long ap, unsigned long ric)
193
-
{
194
-
unsigned long rb, rs, prs, r;
195
-
196
-
rb = va & ~(PPC_BITMASK(52, 63));
197
-
rb |= ap << PPC_BITLSHIFT(58);
198
-
rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
199
-
prs = 1; /* process scoped */
200
-
r = 1; /* radix format */
201
-
202
-
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
203
-
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
204
-
trace_tlbie(0, 0, rb, rs, ric, prs, r);
205
-
}
206
-
207
205
static __always_inline void __tlbie_lpid_va(unsigned long va, unsigned long lpid,
208
206
unsigned long ap, unsigned long ric)
209
207
{
···
232
264
}
233
265
}
234
266
235
-
static inline void fixup_tlbie_va_range_lpid(unsigned long va,
236
-
unsigned long pid,
237
-
unsigned long lpid,
238
-
unsigned long ap)
239
-
{
240
-
if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
241
-
asm volatile("ptesync" : : : "memory");
242
-
__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
243
-
}
244
-
245
-
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
246
-
asm volatile("ptesync" : : : "memory");
247
-
__tlbie_va_lpid(va, pid, lpid, ap, RIC_FLUSH_TLB);
248
-
}
249
-
}
250
-
251
267
static inline void fixup_tlbie_pid(unsigned long pid)
252
268
{
253
269
/*
···
248
296
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
249
297
asm volatile("ptesync": : :"memory");
250
298
__tlbie_va(va, pid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);
251
-
}
252
-
}
253
-
254
-
static inline void fixup_tlbie_pid_lpid(unsigned long pid, unsigned long lpid)
255
-
{
256
-
/*
257
-
* We can use any address for the invalidation, pick one which is
258
-
* probably unused as an optimisation.
259
-
*/
260
-
unsigned long va = ((1UL << 52) - 1);
261
-
262
-
if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
263
-
asm volatile("ptesync" : : : "memory");
264
-
__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
265
-
}
266
-
267
-
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
268
-
asm volatile("ptesync" : : : "memory");
269
-
__tlbie_va_lpid(va, pid, lpid, mmu_get_ap(MMU_PAGE_64K),
270
-
RIC_FLUSH_TLB);
271
299
}
272
300
}
273
301
···
348
416
asm volatile("eieio; tlbsync; ptesync": : :"memory");
349
417
}
350
418
351
-
static inline void _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
352
-
unsigned long ric)
353
-
{
354
-
asm volatile("ptesync" : : : "memory");
355
-
356
-
/*
357
-
* Workaround the fact that the "ric" argument to __tlbie_pid
358
-
* must be a compile-time contraint to match the "i" constraint
359
-
* in the asm statement.
360
-
*/
361
-
switch (ric) {
362
-
case RIC_FLUSH_TLB:
363
-
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_TLB);
364
-
fixup_tlbie_pid_lpid(pid, lpid);
365
-
break;
366
-
case RIC_FLUSH_PWC:
367
-
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
368
-
break;
369
-
case RIC_FLUSH_ALL:
370
-
default:
371
-
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_ALL);
372
-
fixup_tlbie_pid_lpid(pid, lpid);
373
-
}
374
-
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
375
-
}
376
419
struct tlbiel_pid {
377
420
unsigned long pid;
378
421
unsigned long ric;
···
473
566
fixup_tlbie_va_range(addr - page_size, pid, ap);
474
567
}
475
568
476
-
static inline void __tlbie_va_range_lpid(unsigned long start, unsigned long end,
477
-
unsigned long pid, unsigned long lpid,
478
-
unsigned long page_size,
479
-
unsigned long psize)
480
-
{
481
-
unsigned long addr;
482
-
unsigned long ap = mmu_get_ap(psize);
483
-
484
-
for (addr = start; addr < end; addr += page_size)
485
-
__tlbie_va_lpid(addr, pid, lpid, ap, RIC_FLUSH_TLB);
486
-
487
-
fixup_tlbie_va_range_lpid(addr - page_size, pid, lpid, ap);
488
-
}
489
-
490
569
static __always_inline void _tlbie_va(unsigned long va, unsigned long pid,
491
570
unsigned long psize, unsigned long ric)
492
571
{
···
551
658
__tlbie_pid(pid, RIC_FLUSH_PWC);
552
659
__tlbie_va_range(start, end, pid, page_size, psize);
553
660
asm volatile("eieio; tlbsync; ptesync": : :"memory");
554
-
}
555
-
556
-
static inline void _tlbie_va_range_lpid(unsigned long start, unsigned long end,
557
-
unsigned long pid, unsigned long lpid,
558
-
unsigned long page_size,
559
-
unsigned long psize, bool also_pwc)
560
-
{
561
-
asm volatile("ptesync" : : : "memory");
562
-
if (also_pwc)
563
-
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
564
-
__tlbie_va_range_lpid(start, end, pid, lpid, page_size, psize);
565
-
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
566
661
}
567
662
568
663
static inline void _tlbiel_va_range_multicast(struct mm_struct *mm,
···
1395
1514
}
1396
1515
1397
1516
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
1517
+
static __always_inline void __tlbie_pid_lpid(unsigned long pid,
1518
+
unsigned long lpid,
1519
+
unsigned long ric)
1520
+
{
1521
+
unsigned long rb, rs, prs, r;
1522
+
1523
+
rb = PPC_BIT(53); /* IS = 1 */
1524
+
rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
1525
+
prs = 1; /* process scoped */
1526
+
r = 1; /* radix format */
1527
+
1528
+
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
1529
+
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
1530
+
trace_tlbie(0, 0, rb, rs, ric, prs, r);
1531
+
}
1532
+
1533
+
static __always_inline void __tlbie_va_lpid(unsigned long va, unsigned long pid,
1534
+
unsigned long lpid,
1535
+
unsigned long ap, unsigned long ric)
1536
+
{
1537
+
unsigned long rb, rs, prs, r;
1538
+
1539
+
rb = va & ~(PPC_BITMASK(52, 63));
1540
+
rb |= ap << PPC_BITLSHIFT(58);
1541
+
rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
1542
+
prs = 1; /* process scoped */
1543
+
r = 1; /* radix format */
1544
+
1545
+
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
1546
+
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
1547
+
trace_tlbie(0, 0, rb, rs, ric, prs, r);
1548
+
}
1549
+
1550
+
static inline void fixup_tlbie_pid_lpid(unsigned long pid, unsigned long lpid)
1551
+
{
1552
+
/*
1553
+
* We can use any address for the invalidation, pick one which is
1554
+
* probably unused as an optimisation.
1555
+
*/
1556
+
unsigned long va = ((1UL << 52) - 1);
1557
+
1558
+
if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
1559
+
asm volatile("ptesync" : : : "memory");
1560
+
__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
1561
+
}
1562
+
1563
+
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
1564
+
asm volatile("ptesync" : : : "memory");
1565
+
__tlbie_va_lpid(va, pid, lpid, mmu_get_ap(MMU_PAGE_64K),
1566
+
RIC_FLUSH_TLB);
1567
+
}
1568
+
}
1569
+
1570
+
static inline void _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
1571
+
unsigned long ric)
1572
+
{
1573
+
asm volatile("ptesync" : : : "memory");
1574
+
1575
+
/*
1576
+
* Workaround the fact that the "ric" argument to __tlbie_pid
1577
+
* must be a compile-time contraint to match the "i" constraint
1578
+
* in the asm statement.
1579
+
*/
1580
+
switch (ric) {
1581
+
case RIC_FLUSH_TLB:
1582
+
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_TLB);
1583
+
fixup_tlbie_pid_lpid(pid, lpid);
1584
+
break;
1585
+
case RIC_FLUSH_PWC:
1586
+
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
1587
+
break;
1588
+
case RIC_FLUSH_ALL:
1589
+
default:
1590
+
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_ALL);
1591
+
fixup_tlbie_pid_lpid(pid, lpid);
1592
+
}
1593
+
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
1594
+
}
1595
+
1596
+
static inline void fixup_tlbie_va_range_lpid(unsigned long va,
1597
+
unsigned long pid,
1598
+
unsigned long lpid,
1599
+
unsigned long ap)
1600
+
{
1601
+
if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
1602
+
asm volatile("ptesync" : : : "memory");
1603
+
__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
1604
+
}
1605
+
1606
+
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
1607
+
asm volatile("ptesync" : : : "memory");
1608
+
__tlbie_va_lpid(va, pid, lpid, ap, RIC_FLUSH_TLB);
1609
+
}
1610
+
}
1611
+
1612
+
static inline void __tlbie_va_range_lpid(unsigned long start, unsigned long end,
1613
+
unsigned long pid, unsigned long lpid,
1614
+
unsigned long page_size,
1615
+
unsigned long psize)
1616
+
{
1617
+
unsigned long addr;
1618
+
unsigned long ap = mmu_get_ap(psize);
1619
+
1620
+
for (addr = start; addr < end; addr += page_size)
1621
+
__tlbie_va_lpid(addr, pid, lpid, ap, RIC_FLUSH_TLB);
1622
+
1623
+
fixup_tlbie_va_range_lpid(addr - page_size, pid, lpid, ap);
1624
+
}
1625
+
1626
+
static inline void _tlbie_va_range_lpid(unsigned long start, unsigned long end,
1627
+
unsigned long pid, unsigned long lpid,
1628
+
unsigned long page_size,
1629
+
unsigned long psize, bool also_pwc)
1630
+
{
1631
+
asm volatile("ptesync" : : : "memory");
1632
+
if (also_pwc)
1633
+
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
1634
+
__tlbie_va_range_lpid(start, end, pid, lpid, page_size, psize);
1635
+
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
1636
+
}
1637
+
1398
1638
/*
1399
1639
* Performs process-scoped invalidations for a given LPID
1400
1640
* as part of H_RPT_INVALIDATE hcall.