Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Add soft fuse detection support
Recent chipsets like Glymur supports a new mechanism for SKU detection.
A new CX_MISC register exposes the combined (or final) speedbin value
from both HW fuse register and the Soft Fuse register. Implement this new
SKU detection along with a new quirk to identify the GPUs that has soft
fuse support.
There is a side effect of this patch on A4x and older series. The
speedbin field in the MSM_PARAM_CHIPID will be 0 instead of 0xffff. This
should be okay as Mesa correctly handles it. Speedbin was not even a
thing when those GPUs' support were added.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714676/
Message-ID: <20260327-a8xx-gpu-batch2-v2-12-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Akhil P Oommen
and committed by
Rob Clark
4ac686bf
bb79a606
+45
-12
+6
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+6
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
···
1731
1731
struct adreno_gpu *adreno_gpu;
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struct msm_gpu *gpu;
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unsigned int nr_rings;
1734
+
u32 speedbin;
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int ret;
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a5xx_gpu = kzalloc(sizeof(*a5xx_gpu), GFP_KERNEL);
···
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a5xx_destroy(&(a5xx_gpu->base.base));
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return ERR_PTR(ret);
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}
1759
+
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+
/* Set the speedbin value that is passed to userspace */
1761
+
if (adreno_read_speedbin(&pdev->dev, &speedbin) || !speedbin)
1762
+
speedbin = 0xffff;
1763
+
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
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msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
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a5xx_fault_handler);
+34
-7
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+34
-7
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
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return UINT_MAX;
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}
2548
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2549
-
static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
2549
+
static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu,
2550
+
const struct adreno_info *info, u32 *speedbin)
2551
+
{
2552
+
int ret;
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+
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+
/* Use speedbin fuse if present. Otherwise, fallback to softfuse */
2555
+
ret = adreno_read_speedbin(dev, speedbin);
2556
+
if (ret != -ENOENT)
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+
return ret;
2558
+
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+
if (info->quirks & ADRENO_QUIRK_SOFTFUSE) {
2560
+
*speedbin = a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
2561
+
*speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin);
2562
+
return 0;
2563
+
}
2564
+
2565
+
return -ENOENT;
2566
+
}
2567
+
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+
static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
2569
+
const struct adreno_info *info)
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{
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u32 supp_hw;
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u32 speedbin;
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int ret;
2554
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2555
-
ret = adreno_read_speedbin(dev, &speedbin);
2575
+
ret = a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin);
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/*
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* -ENOENT means that the platform doesn't support speedbin which is
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* fine
···
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struct msm_drm_private *priv = dev->dev_private;
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struct platform_device *pdev = priv->gpu_pdev;
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struct adreno_platform_config *config = pdev->dev.platform_data;
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+
const struct adreno_info *info = config->info;
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struct device_node *node;
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struct a6xx_gpu *a6xx_gpu;
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struct adreno_gpu *adreno_gpu;
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struct msm_gpu *gpu;
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extern int enable_preemption;
2595
+
u32 speedbin;
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bool is_a7xx;
2615
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int ret, nr_rings = 1;
2616
2598
···
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adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
2637
2615
2638
2616
adreno_gpu->base.hw_apriv =
2639
-
!!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
2617
+
!!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
2640
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/* gpu->info only gets assigned in adreno_gpu_init(). A8x is included intentionally */
2642
-
is_a7xx = config->info->family >= ADRENO_7XX_GEN1;
2620
+
is_a7xx = info->family >= ADRENO_7XX_GEN1;
2643
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a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
2645
2623
2646
-
ret = a6xx_set_supported_hw(&pdev->dev, config->info);
2624
+
ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info);
2647
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if (ret) {
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a6xx_llc_slices_destroy(a6xx_gpu);
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kfree(a6xx_gpu);
···
2651
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}
2652
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if ((enable_preemption == 1) || (enable_preemption == -1 &&
2654
-
(config->info->quirks & ADRENO_QUIRK_PREEMPTION)))
2632
+
(info->quirks & ADRENO_QUIRK_PREEMPTION)))
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nr_rings = 4;
2656
2634
2657
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_rings);
2635
+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, info->funcs, nr_rings);
2658
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if (ret) {
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a6xx_destroy(&(a6xx_gpu->base.base));
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return ERR_PTR(ret);
2661
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}
2640
+
2641
+
/* Set the speedbin value that is passed to userspace */
2642
+
if (a6xx_read_speedbin(&pdev->dev, a6xx_gpu, info, &speedbin) || !speedbin)
2643
+
speedbin = 0xffff;
2644
+
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
2662
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2663
2646
/*
2664
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* For now only clamp to idle freq for devices where this is known not
-5
drivers/gpu/drm/msm/adreno/adreno_gpu.c
-5
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
1182
1182
struct msm_gpu_config adreno_gpu_config = { 0 };
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struct msm_gpu *gpu = &adreno_gpu->base;
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const char *gpu_name;
1185
-
u32 speedbin;
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int ret;
1187
1186
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adreno_gpu->funcs = funcs;
···
1209
1210
} else
1210
1211
devm_pm_opp_set_clkname(dev, "core");
1211
1212
}
1212
-
1213
-
if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
1214
-
speedbin = 0xffff;
1215
-
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
1216
1213
1217
1214
gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
1218
1215
ADRENO_CHIPID_ARGS(config->chip_id));
+1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+4
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+4
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
···
5016
5016
<bitfield pos="1" name="LPAC" type="boolean"/>
5017
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<bitfield pos="2" name="RAYTRACING" type="boolean"/>
5018
5018
</reg32>
5019
+
<reg32 offset="0x0405" name="CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS" variants="A8XX-">
5020
+
<bitfield high="8" low="0" name="FINALFREQLIMIT"/>
5021
+
<bitfield pos="24" name="SOFTSKUDISABLED" type="boolean"/>
5022
+
</reg32>
5019
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</domain>
5020
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</database>