tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'timers-core-2023-09-04-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull clocksource/clockevent driver updates from Thomas Gleixner:

- Remove the OXNAS driver instead of adding a new one!

- A set of boring fixes, cleanups and improvements

* tag 'timers-core-2023-09-04-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
clocksource: Explicitly include correct DT includes
clocksource/drivers/sun5i: Convert to platform device driver
clocksource/drivers/sun5i: Remove pointless struct
clocksource/drivers/sun5i: Remove duplication of code and data
clocksource/drivers/loongson1: Set variable ls1x_timer_lock storage-class-specifier to static
clocksource/drivers/arm_arch_timer: Disable timer before programming CVAL
dt-bindings: timer: oxsemi,rps-timer: remove obsolete bindings
clocksource/drivers/timer-oxnas-rps: Remove obsolete timer driver

Linus Torvalds 4accdb98 7a1415ee

+131 -479
-17
Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt
··· 1 - Oxford Semiconductor OXNAS SoCs Family RPS Timer 2 - ================================================ 3 - 4 - Required properties: 5 - - compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer" 6 - - reg : Specifies base physical address and size of the registers. 7 - - interrupts : The interrupts of the two timers 8 - - clocks : The phandle of the timer clock source 9 - 10 - example: 11 - 12 - timer0: timer@200 { 13 - compatible = "oxsemi,ox810se-rps-timer"; 14 - reg = <0x200 0x40>; 15 - clocks = <&rpsclk>; 16 - interrupts = <4 5>; 17 - };
-7
drivers/clocksource/Kconfig
··· 461 461 help 462 462 Support for Periodic Interrupt Timer on Freescale Vybrid Family SoCs. 463 463 464 - config OXNAS_RPS_TIMER 465 - bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST 466 - select TIMER_OF 467 - select CLKSRC_MMIO 468 - help 469 - This enables support for the Oxford Semiconductor OXNAS RPS timers. 470 - 471 464 config SYS_SUPPORTS_SH_CMT 472 465 bool 473 466
-1
drivers/clocksource/Makefile
··· 54 54 obj-$(CONFIG_MTK_CPUX_TIMER) += timer-mediatek-cpux.o 55 55 obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o 56 56 obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o 57 - obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o 58 57 obj-$(CONFIG_OWL_TIMER) += timer-owl.o 59 58 obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o 60 59 obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
+7
drivers/clocksource/arm_arch_timer.c
··· 792 792 u64 cnt; 793 793 794 794 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); 795 + 796 + /* Timer must be disabled before programming CVAL */ 797 + if (ctrl & ARCH_TIMER_CTRL_ENABLE) { 798 + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 799 + arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); 800 + } 801 + 795 802 ctrl |= ARCH_TIMER_CTRL_ENABLE; 796 803 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; 797 804
+1 -1
drivers/clocksource/timer-loongson1-pwm.c
··· 28 28 29 29 #define CNTR_WIDTH 24 30 30 31 - DEFINE_RAW_SPINLOCK(ls1x_timer_lock); 31 + static DEFINE_RAW_SPINLOCK(ls1x_timer_lock); 32 32 33 33 struct ls1x_clocksource { 34 34 void __iomem *reg_base;
-288
drivers/clocksource/timer-oxnas-rps.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * drivers/clocksource/timer-oxnas-rps.c 4 - * 5 - * Copyright (C) 2009 Oxford Semiconductor Ltd 6 - * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com> 7 - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> 8 - */ 9 - 10 - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 - 12 - #include <linux/init.h> 13 - #include <linux/irq.h> 14 - #include <linux/io.h> 15 - #include <linux/clk.h> 16 - #include <linux/slab.h> 17 - #include <linux/interrupt.h> 18 - #include <linux/of_irq.h> 19 - #include <linux/of_address.h> 20 - #include <linux/clockchips.h> 21 - #include <linux/sched_clock.h> 22 - 23 - /* TIMER1 used as tick 24 - * TIMER2 used as clocksource 25 - */ 26 - 27 - /* Registers definitions */ 28 - 29 - #define TIMER_LOAD_REG 0x0 30 - #define TIMER_CURR_REG 0x4 31 - #define TIMER_CTRL_REG 0x8 32 - #define TIMER_CLRINT_REG 0xC 33 - 34 - #define TIMER_BITS 24 35 - 36 - #define TIMER_MAX_VAL (BIT(TIMER_BITS) - 1) 37 - 38 - #define TIMER_PERIODIC BIT(6) 39 - #define TIMER_ENABLE BIT(7) 40 - 41 - #define TIMER_DIV1 (0) 42 - #define TIMER_DIV16 (1 << 2) 43 - #define TIMER_DIV256 (2 << 2) 44 - 45 - #define TIMER1_REG_OFFSET 0 46 - #define TIMER2_REG_OFFSET 0x20 47 - 48 - /* Clockevent & Clocksource data */ 49 - 50 - struct oxnas_rps_timer { 51 - struct clock_event_device clkevent; 52 - void __iomem *clksrc_base; 53 - void __iomem *clkevt_base; 54 - unsigned long timer_period; 55 - unsigned int timer_prescaler; 56 - struct clk *clk; 57 - int irq; 58 - }; 59 - 60 - static irqreturn_t oxnas_rps_timer_irq(int irq, void *dev_id) 61 - { 62 - struct oxnas_rps_timer *rps = dev_id; 63 - 64 - writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG); 65 - 66 - rps->clkevent.event_handler(&rps->clkevent); 67 - 68 - return IRQ_HANDLED; 69 - } 70 - 71 - static void oxnas_rps_timer_config(struct oxnas_rps_timer *rps, 72 - unsigned long period, 73 - unsigned int periodic) 74 - { 75 - uint32_t cfg = rps->timer_prescaler; 76 - 77 - if (period) 78 - cfg |= TIMER_ENABLE; 79 - 80 - if (periodic) 81 - cfg |= TIMER_PERIODIC; 82 - 83 - writel_relaxed(period, rps->clkevt_base + TIMER_LOAD_REG); 84 - writel_relaxed(cfg, rps->clkevt_base + TIMER_CTRL_REG); 85 - } 86 - 87 - static int oxnas_rps_timer_shutdown(struct clock_event_device *evt) 88 - { 89 - struct oxnas_rps_timer *rps = 90 - container_of(evt, struct oxnas_rps_timer, clkevent); 91 - 92 - oxnas_rps_timer_config(rps, 0, 0); 93 - 94 - return 0; 95 - } 96 - 97 - static int oxnas_rps_timer_set_periodic(struct clock_event_device *evt) 98 - { 99 - struct oxnas_rps_timer *rps = 100 - container_of(evt, struct oxnas_rps_timer, clkevent); 101 - 102 - oxnas_rps_timer_config(rps, rps->timer_period, 1); 103 - 104 - return 0; 105 - } 106 - 107 - static int oxnas_rps_timer_set_oneshot(struct clock_event_device *evt) 108 - { 109 - struct oxnas_rps_timer *rps = 110 - container_of(evt, struct oxnas_rps_timer, clkevent); 111 - 112 - oxnas_rps_timer_config(rps, rps->timer_period, 0); 113 - 114 - return 0; 115 - } 116 - 117 - static int oxnas_rps_timer_next_event(unsigned long delta, 118 - struct clock_event_device *evt) 119 - { 120 - struct oxnas_rps_timer *rps = 121 - container_of(evt, struct oxnas_rps_timer, clkevent); 122 - 123 - oxnas_rps_timer_config(rps, delta, 0); 124 - 125 - return 0; 126 - } 127 - 128 - static int __init oxnas_rps_clockevent_init(struct oxnas_rps_timer *rps) 129 - { 130 - ulong clk_rate = clk_get_rate(rps->clk); 131 - ulong timer_rate; 132 - 133 - /* Start with prescaler 1 */ 134 - rps->timer_prescaler = TIMER_DIV1; 135 - rps->timer_period = DIV_ROUND_UP(clk_rate, HZ); 136 - timer_rate = clk_rate; 137 - 138 - if (rps->timer_period > TIMER_MAX_VAL) { 139 - rps->timer_prescaler = TIMER_DIV16; 140 - timer_rate = clk_rate / 16; 141 - rps->timer_period = DIV_ROUND_UP(timer_rate, HZ); 142 - } 143 - if (rps->timer_period > TIMER_MAX_VAL) { 144 - rps->timer_prescaler = TIMER_DIV256; 145 - timer_rate = clk_rate / 256; 146 - rps->timer_period = DIV_ROUND_UP(timer_rate, HZ); 147 - } 148 - 149 - rps->clkevent.name = "oxnas-rps"; 150 - rps->clkevent.features = CLOCK_EVT_FEAT_PERIODIC | 151 - CLOCK_EVT_FEAT_ONESHOT | 152 - CLOCK_EVT_FEAT_DYNIRQ; 153 - rps->clkevent.tick_resume = oxnas_rps_timer_shutdown; 154 - rps->clkevent.set_state_shutdown = oxnas_rps_timer_shutdown; 155 - rps->clkevent.set_state_periodic = oxnas_rps_timer_set_periodic; 156 - rps->clkevent.set_state_oneshot = oxnas_rps_timer_set_oneshot; 157 - rps->clkevent.set_next_event = oxnas_rps_timer_next_event; 158 - rps->clkevent.rating = 200; 159 - rps->clkevent.cpumask = cpu_possible_mask; 160 - rps->clkevent.irq = rps->irq; 161 - clockevents_config_and_register(&rps->clkevent, 162 - timer_rate, 163 - 1, 164 - TIMER_MAX_VAL); 165 - 166 - pr_info("Registered clock event rate %luHz prescaler %x period %lu\n", 167 - clk_rate, 168 - rps->timer_prescaler, 169 - rps->timer_period); 170 - 171 - return 0; 172 - } 173 - 174 - /* Clocksource */ 175 - 176 - static void __iomem *timer_sched_base; 177 - 178 - static u64 notrace oxnas_rps_read_sched_clock(void) 179 - { 180 - return ~readl_relaxed(timer_sched_base); 181 - } 182 - 183 - static int __init oxnas_rps_clocksource_init(struct oxnas_rps_timer *rps) 184 - { 185 - ulong clk_rate = clk_get_rate(rps->clk); 186 - int ret; 187 - 188 - /* use prescale 16 */ 189 - clk_rate = clk_rate / 16; 190 - 191 - writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG); 192 - writel_relaxed(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16, 193 - rps->clksrc_base + TIMER_CTRL_REG); 194 - 195 - timer_sched_base = rps->clksrc_base + TIMER_CURR_REG; 196 - sched_clock_register(oxnas_rps_read_sched_clock, 197 - TIMER_BITS, clk_rate); 198 - ret = clocksource_mmio_init(timer_sched_base, 199 - "oxnas_rps_clocksource_timer", 200 - clk_rate, 250, TIMER_BITS, 201 - clocksource_mmio_readl_down); 202 - if (WARN_ON(ret)) { 203 - pr_err("can't register clocksource\n"); 204 - return ret; 205 - } 206 - 207 - pr_info("Registered clocksource rate %luHz\n", clk_rate); 208 - 209 - return 0; 210 - } 211 - 212 - static int __init oxnas_rps_timer_init(struct device_node *np) 213 - { 214 - struct oxnas_rps_timer *rps; 215 - void __iomem *base; 216 - int ret; 217 - 218 - rps = kzalloc(sizeof(*rps), GFP_KERNEL); 219 - if (!rps) 220 - return -ENOMEM; 221 - 222 - rps->clk = of_clk_get(np, 0); 223 - if (IS_ERR(rps->clk)) { 224 - ret = PTR_ERR(rps->clk); 225 - goto err_alloc; 226 - } 227 - 228 - ret = clk_prepare_enable(rps->clk); 229 - if (ret) 230 - goto err_clk; 231 - 232 - base = of_iomap(np, 0); 233 - if (!base) { 234 - ret = -ENXIO; 235 - goto err_clk_prepare; 236 - } 237 - 238 - rps->irq = irq_of_parse_and_map(np, 0); 239 - if (!rps->irq) { 240 - ret = -EINVAL; 241 - goto err_iomap; 242 - } 243 - 244 - rps->clkevt_base = base + TIMER1_REG_OFFSET; 245 - rps->clksrc_base = base + TIMER2_REG_OFFSET; 246 - 247 - /* Disable timers */ 248 - writel_relaxed(0, rps->clkevt_base + TIMER_CTRL_REG); 249 - writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG); 250 - writel_relaxed(0, rps->clkevt_base + TIMER_LOAD_REG); 251 - writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG); 252 - writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG); 253 - writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG); 254 - 255 - ret = request_irq(rps->irq, oxnas_rps_timer_irq, 256 - IRQF_TIMER | IRQF_IRQPOLL, 257 - "rps-timer", rps); 258 - if (ret) 259 - goto err_iomap; 260 - 261 - ret = oxnas_rps_clocksource_init(rps); 262 - if (ret) 263 - goto err_irqreq; 264 - 265 - ret = oxnas_rps_clockevent_init(rps); 266 - if (ret) 267 - goto err_irqreq; 268 - 269 - return 0; 270 - 271 - err_irqreq: 272 - free_irq(rps->irq, rps); 273 - err_iomap: 274 - iounmap(base); 275 - err_clk_prepare: 276 - clk_disable_unprepare(rps->clk); 277 - err_clk: 278 - clk_put(rps->clk); 279 - err_alloc: 280 - kfree(rps); 281 - 282 - return ret; 283 - } 284 - 285 - TIMER_OF_DECLARE(ox810se_rps, 286 - "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init); 287 - TIMER_OF_DECLARE(ox820_rps, 288 - "oxsemi,ox820-rps-timer", oxnas_rps_timer_init);
+123 -165
drivers/clocksource/timer-sun5i.c
··· 16 16 #include <linux/irqreturn.h> 17 17 #include <linux/reset.h> 18 18 #include <linux/slab.h> 19 - #include <linux/of.h> 20 - #include <linux/of_address.h> 21 - #include <linux/of_irq.h> 19 + #include <linux/platform_device.h> 22 20 23 21 #define TIMER_IRQ_EN_REG 0x00 24 22 #define TIMER_IRQ_EN(val) BIT(val) ··· 38 40 struct clk *clk; 39 41 struct notifier_block clk_rate_cb; 40 42 u32 ticks_per_jiffy; 41 - }; 42 - 43 - #define to_sun5i_timer(x) \ 44 - container_of(x, struct sun5i_timer, clk_rate_cb) 45 - 46 - struct sun5i_timer_clksrc { 47 - struct sun5i_timer timer; 48 43 struct clocksource clksrc; 49 - }; 50 - 51 - #define to_sun5i_timer_clksrc(x) \ 52 - container_of(x, struct sun5i_timer_clksrc, clksrc) 53 - 54 - struct sun5i_timer_clkevt { 55 - struct sun5i_timer timer; 56 44 struct clock_event_device clkevt; 57 45 }; 58 46 59 - #define to_sun5i_timer_clkevt(x) \ 60 - container_of(x, struct sun5i_timer_clkevt, clkevt) 47 + #define nb_to_sun5i_timer(x) \ 48 + container_of(x, struct sun5i_timer, clk_rate_cb) 49 + #define clksrc_to_sun5i_timer(x) \ 50 + container_of(x, struct sun5i_timer, clksrc) 51 + #define clkevt_to_sun5i_timer(x) \ 52 + container_of(x, struct sun5i_timer, clkevt) 61 53 62 54 /* 63 55 * When we disable a timer, we need to wait at least for 2 cycles of ··· 55 67 * that is already setup and runs at the same frequency than the other 56 68 * timers, and we never will be disabled. 57 69 */ 58 - static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce) 70 + static void sun5i_clkevt_sync(struct sun5i_timer *ce) 59 71 { 60 - u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); 72 + u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); 61 73 62 - while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) 74 + while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) 63 75 cpu_relax(); 64 76 } 65 77 66 - static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer) 78 + static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer) 67 79 { 68 - u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); 69 - writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); 80 + u32 val = readl(ce->base + TIMER_CTL_REG(timer)); 81 + writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); 70 82 71 83 sun5i_clkevt_sync(ce); 72 84 } 73 85 74 - static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay) 86 + static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 delay) 75 87 { 76 - writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer)); 88 + writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); 77 89 } 78 90 79 - static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic) 91 + static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool periodic) 80 92 { 81 - u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); 93 + u32 val = readl(ce->base + TIMER_CTL_REG(timer)); 82 94 83 95 if (periodic) 84 96 val &= ~TIMER_CTL_ONESHOT; ··· 86 98 val |= TIMER_CTL_ONESHOT; 87 99 88 100 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, 89 - ce->timer.base + TIMER_CTL_REG(timer)); 101 + ce->base + TIMER_CTL_REG(timer)); 90 102 } 91 103 92 104 static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt) 93 105 { 94 - struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt); 106 + struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt); 95 107 96 108 sun5i_clkevt_time_stop(ce, 0); 97 109 return 0; ··· 99 111 100 112 static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt) 101 113 { 102 - struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt); 114 + struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt); 103 115 104 116 sun5i_clkevt_time_stop(ce, 0); 105 117 sun5i_clkevt_time_start(ce, 0, false); ··· 108 120 109 121 static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt) 110 122 { 111 - struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt); 123 + struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt); 112 124 113 125 sun5i_clkevt_time_stop(ce, 0); 114 - sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy); 126 + sun5i_clkevt_time_setup(ce, 0, ce->ticks_per_jiffy); 115 127 sun5i_clkevt_time_start(ce, 0, true); 116 128 return 0; 117 129 } ··· 119 131 static int sun5i_clkevt_next_event(unsigned long evt, 120 132 struct clock_event_device *clkevt) 121 133 { 122 - struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt); 134 + struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt); 123 135 124 136 sun5i_clkevt_time_stop(ce, 0); 125 137 sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS); ··· 130 142 131 143 static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id) 132 144 { 133 - struct sun5i_timer_clkevt *ce = dev_id; 145 + struct sun5i_timer *ce = dev_id; 134 146 135 - writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG); 147 + writel(0x1, ce->base + TIMER_IRQ_ST_REG); 136 148 ce->clkevt.event_handler(&ce->clkevt); 137 149 138 150 return IRQ_HANDLED; ··· 140 152 141 153 static u64 sun5i_clksrc_read(struct clocksource *clksrc) 142 154 { 143 - struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc); 155 + struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc); 144 156 145 - return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1)); 157 + return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1)); 146 158 } 147 159 148 - static int sun5i_rate_cb_clksrc(struct notifier_block *nb, 149 - unsigned long event, void *data) 160 + static int sun5i_rate_cb(struct notifier_block *nb, 161 + unsigned long event, void *data) 150 162 { 151 163 struct clk_notifier_data *ndata = data; 152 - struct sun5i_timer *timer = to_sun5i_timer(nb); 153 - struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer); 164 + struct sun5i_timer *cs = nb_to_sun5i_timer(nb); 154 165 155 166 switch (event) { 156 167 case PRE_RATE_CHANGE: ··· 158 171 159 172 case POST_RATE_CHANGE: 160 173 clocksource_register_hz(&cs->clksrc, ndata->new_rate); 174 + clockevents_update_freq(&cs->clkevt, ndata->new_rate); 175 + cs->ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ); 161 176 break; 162 177 163 178 default: ··· 169 180 return NOTIFY_DONE; 170 181 } 171 182 172 - static int __init sun5i_setup_clocksource(struct device_node *node, 173 - void __iomem *base, 174 - struct clk *clk, int irq) 183 + static int sun5i_setup_clocksource(struct platform_device *pdev, 184 + unsigned long rate) 175 185 { 176 - struct sun5i_timer_clksrc *cs; 177 - unsigned long rate; 186 + struct sun5i_timer *cs = platform_get_drvdata(pdev); 187 + void __iomem *base = cs->base; 178 188 int ret; 179 - 180 - cs = kzalloc(sizeof(*cs), GFP_KERNEL); 181 - if (!cs) 182 - return -ENOMEM; 183 - 184 - ret = clk_prepare_enable(clk); 185 - if (ret) { 186 - pr_err("Couldn't enable parent clock\n"); 187 - goto err_free; 188 - } 189 - 190 - rate = clk_get_rate(clk); 191 - if (!rate) { 192 - pr_err("Couldn't get parent clock rate\n"); 193 - ret = -EINVAL; 194 - goto err_disable_clk; 195 - } 196 - 197 - cs->timer.base = base; 198 - cs->timer.clk = clk; 199 - cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc; 200 - cs->timer.clk_rate_cb.next = NULL; 201 - 202 - ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb); 203 - if (ret) { 204 - pr_err("Unable to register clock notifier.\n"); 205 - goto err_disable_clk; 206 - } 207 189 208 190 writel(~0, base + TIMER_INTVAL_LO_REG(1)); 209 191 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, 210 192 base + TIMER_CTL_REG(1)); 211 193 212 - cs->clksrc.name = node->name; 194 + cs->clksrc.name = pdev->dev.of_node->name; 213 195 cs->clksrc.rating = 340; 214 196 cs->clksrc.read = sun5i_clksrc_read; 215 197 cs->clksrc.mask = CLOCKSOURCE_MASK(32); ··· 188 228 189 229 ret = clocksource_register_hz(&cs->clksrc, rate); 190 230 if (ret) { 191 - pr_err("Couldn't register clock source.\n"); 192 - goto err_remove_notifier; 231 + dev_err(&pdev->dev, "Couldn't register clock source.\n"); 232 + return ret; 193 233 } 194 234 195 235 return 0; 196 - 197 - err_remove_notifier: 198 - clk_notifier_unregister(clk, &cs->timer.clk_rate_cb); 199 - err_disable_clk: 200 - clk_disable_unprepare(clk); 201 - err_free: 202 - kfree(cs); 203 - return ret; 204 236 } 205 237 206 - static int sun5i_rate_cb_clkevt(struct notifier_block *nb, 207 - unsigned long event, void *data) 238 + static int sun5i_setup_clockevent(struct platform_device *pdev, 239 + unsigned long rate, int irq) 208 240 { 209 - struct clk_notifier_data *ndata = data; 210 - struct sun5i_timer *timer = to_sun5i_timer(nb); 211 - struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer); 212 - 213 - if (event == POST_RATE_CHANGE) { 214 - clockevents_update_freq(&ce->clkevt, ndata->new_rate); 215 - ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ); 216 - } 217 - 218 - return NOTIFY_DONE; 219 - } 220 - 221 - static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base, 222 - struct clk *clk, int irq) 223 - { 224 - struct sun5i_timer_clkevt *ce; 225 - unsigned long rate; 241 + struct device *dev = &pdev->dev; 242 + struct sun5i_timer *ce = platform_get_drvdata(pdev); 243 + void __iomem *base = ce->base; 226 244 int ret; 227 245 u32 val; 228 246 229 - ce = kzalloc(sizeof(*ce), GFP_KERNEL); 230 - if (!ce) 231 - return -ENOMEM; 232 - 233 - ret = clk_prepare_enable(clk); 234 - if (ret) { 235 - pr_err("Couldn't enable parent clock\n"); 236 - goto err_free; 237 - } 238 - 239 - rate = clk_get_rate(clk); 240 - if (!rate) { 241 - pr_err("Couldn't get parent clock rate\n"); 242 - ret = -EINVAL; 243 - goto err_disable_clk; 244 - } 245 - 246 - ce->timer.base = base; 247 - ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); 248 - ce->timer.clk = clk; 249 - ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt; 250 - ce->timer.clk_rate_cb.next = NULL; 251 - 252 - ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb); 253 - if (ret) { 254 - pr_err("Unable to register clock notifier.\n"); 255 - goto err_disable_clk; 256 - } 257 - 258 - ce->clkevt.name = node->name; 247 + ce->clkevt.name = dev->of_node->name; 259 248 ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 260 249 ce->clkevt.set_next_event = sun5i_clkevt_next_event; 261 250 ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown; ··· 222 313 clockevents_config_and_register(&ce->clkevt, rate, 223 314 TIMER_SYNC_TICKS, 0xffffffff); 224 315 225 - ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, 226 - "sun5i_timer0", ce); 316 + ret = devm_request_irq(dev, irq, sun5i_timer_interrupt, 317 + IRQF_TIMER | IRQF_IRQPOLL, 318 + "sun5i_timer0", ce); 227 319 if (ret) { 228 - pr_err("Unable to register interrupt\n"); 229 - goto err_remove_notifier; 320 + dev_err(dev, "Unable to register interrupt\n"); 321 + return ret; 230 322 } 231 323 232 324 return 0; 233 - 234 - err_remove_notifier: 235 - clk_notifier_unregister(clk, &ce->timer.clk_rate_cb); 236 - err_disable_clk: 237 - clk_disable_unprepare(clk); 238 - err_free: 239 - kfree(ce); 240 - return ret; 241 325 } 242 326 243 - static int __init sun5i_timer_init(struct device_node *node) 327 + static int sun5i_timer_probe(struct platform_device *pdev) 244 328 { 329 + struct device *dev = &pdev->dev; 330 + struct sun5i_timer *st; 245 331 struct reset_control *rstc; 246 332 void __iomem *timer_base; 247 333 struct clk *clk; 334 + unsigned long rate; 248 335 int irq, ret; 249 336 250 - timer_base = of_io_request_and_map(node, 0, of_node_full_name(node)); 337 + st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 338 + if (!st) 339 + return -ENOMEM; 340 + 341 + platform_set_drvdata(pdev, st); 342 + 343 + timer_base = devm_platform_ioremap_resource(pdev, 0); 251 344 if (IS_ERR(timer_base)) { 252 - pr_err("Can't map registers\n"); 345 + dev_err(dev, "Can't map registers\n"); 253 346 return PTR_ERR(timer_base); 254 347 } 255 348 256 - irq = irq_of_parse_and_map(node, 0); 257 - if (irq <= 0) { 258 - pr_err("Can't parse IRQ\n"); 259 - return -EINVAL; 349 + irq = platform_get_irq(pdev, 0); 350 + if (irq < 0) { 351 + dev_err(dev, "Can't get IRQ\n"); 352 + return irq; 260 353 } 261 354 262 - clk = of_clk_get(node, 0); 355 + clk = devm_clk_get_enabled(dev, NULL); 263 356 if (IS_ERR(clk)) { 264 - pr_err("Can't get timer clock\n"); 357 + dev_err(dev, "Can't get timer clock\n"); 265 358 return PTR_ERR(clk); 266 359 } 267 360 268 - rstc = of_reset_control_get(node, NULL); 269 - if (!IS_ERR(rstc)) 361 + rate = clk_get_rate(clk); 362 + if (!rate) { 363 + dev_err(dev, "Couldn't get parent clock rate\n"); 364 + return -EINVAL; 365 + } 366 + 367 + st->base = timer_base; 368 + st->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); 369 + st->clk = clk; 370 + st->clk_rate_cb.notifier_call = sun5i_rate_cb; 371 + st->clk_rate_cb.next = NULL; 372 + 373 + ret = devm_clk_notifier_register(dev, clk, &st->clk_rate_cb); 374 + if (ret) { 375 + dev_err(dev, "Unable to register clock notifier.\n"); 376 + return ret; 377 + } 378 + 379 + rstc = devm_reset_control_get_optional_exclusive(dev, NULL); 380 + if (rstc) 270 381 reset_control_deassert(rstc); 271 382 272 - ret = sun5i_setup_clocksource(node, timer_base, clk, irq); 383 + ret = sun5i_setup_clocksource(pdev, rate); 273 384 if (ret) 274 385 return ret; 275 386 276 - return sun5i_setup_clockevent(node, timer_base, clk, irq); 387 + ret = sun5i_setup_clockevent(pdev, rate, irq); 388 + if (ret) 389 + goto err_unreg_clocksource; 390 + 391 + return 0; 392 + 393 + err_unreg_clocksource: 394 + clocksource_unregister(&st->clksrc); 395 + return ret; 277 396 } 278 - TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer", 279 - sun5i_timer_init); 280 - TIMER_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer", 281 - sun5i_timer_init); 397 + 398 + static void sun5i_timer_remove(struct platform_device *pdev) 399 + { 400 + struct sun5i_timer *st = platform_get_drvdata(pdev); 401 + 402 + clocksource_unregister(&st->clksrc); 403 + } 404 + 405 + static const struct of_device_id sun5i_timer_of_match[] = { 406 + { .compatible = "allwinner,sun5i-a13-hstimer" }, 407 + { .compatible = "allwinner,sun7i-a20-hstimer" }, 408 + {}, 409 + }; 410 + MODULE_DEVICE_TABLE(of, sun5i_timer_of_match); 411 + 412 + static struct platform_driver sun5i_timer_driver = { 413 + .probe = sun5i_timer_probe, 414 + .remove_new = sun5i_timer_remove, 415 + .driver = { 416 + .name = "sun5i-timer", 417 + .of_match_table = sun5i_timer_of_match, 418 + .suppress_bind_attrs = true, 419 + }, 420 + }; 421 + module_platform_driver(sun5i_timer_driver);