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clk: qcom: ipq5424: fix software and hardware flow control error of UART

The UART’s software and hardware flow control are currently not
functioning correctly.

For software flow control, the following error is encountered:
qcom_geni_serial 1a80000.serial: Couldn't find suitable
clock rate for 56000000, 3500000, 2500000, 1152000, 921600, 19200

During hardware flow control testing, a “Retry 0: Got ZCAN error” is
observed.

To address these issues, update the UART frequency table to include all
supported frequencies according to the frequency plan.

Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC")
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20250124060914.1564681-1-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Manikanta Mylavarapu and committed by
Bjorn Andersson
4b28beb8 5eac3481

+11 -5
+11 -5
drivers/clk/qcom/gcc-ipq5424.c
··· 592 592 }; 593 593 594 594 static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] = { 595 - F(960000, P_XO, 10, 2, 5), 596 - F(4800000, P_XO, 5, 0, 0), 597 - F(9600000, P_XO, 2, 4, 5), 598 - F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 595 + F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625), 596 + F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625), 597 + F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625), 599 598 F(24000000, P_XO, 1, 0, 0), 600 599 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 601 - F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 600 + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), 601 + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), 602 + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500), 603 + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), 604 + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), 605 + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), 606 + F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625), 607 + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), 602 608 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 603 609 { } 604 610 };