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Merge branch 'net-dsa-lantiq-add-support-for-intel-gsw150'

Daniel Golle says:

====================
net: dsa: lantiq: add support for Intel GSW150

The Intel GSW150 Ethernet Switch (aka. Lantiq PEB7084) is the predecessor of
MaxLinear's GSW1xx series of switches. It shares most features, but has a
slightly different port layout and different MII interfaces.
Adding support for this switch to the mxl-gsw1xx driver is quite trivial.
====================

Link: https://patch.msgid.link/cover.1769099517.git.daniel@makrotopia.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

Paolo Abeni 4c17c01c 099ca412

+168 -74
+4 -2
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
··· 19 19 properties: 20 20 compatible: 21 21 enum: 22 + - intel,gsw150 23 + - lantiq,peb7084 22 24 - lantiq,xrx200-gswip 23 25 - lantiq,xrx300-gswip 24 26 - lantiq,xrx330-gswip ··· 340 338 #address-cells = <1>; 341 339 #size-cells = <0>; 342 340 343 - switchphy0: switchphy@0 { 341 + switchphy0: ethernet-phy@0 { 344 342 reg = <0>; 345 343 346 344 leds { ··· 355 353 }; 356 354 }; 357 355 358 - switchphy1: switchphy@1 { 356 + switchphy1: ethernet-phy@1 { 359 357 reg = <1>; 360 358 361 359 leds {
+3 -1
drivers/net/dsa/lantiq/Kconfig
··· 16 16 select NET_DSA_TAG_MXL_GSW1XX 17 17 select NET_DSA_LANTIQ_COMMON 18 18 help 19 - This enables support for the MaxLinear GSW1xx family of 1GE switches 19 + This enables support for the Intel/MaxLinear GSW1xx family of 1GE 20 + switches. 20 21 GSW120 4 port, 2 PHYs, RGMII & SGMII/2500Base-X 21 22 GSW125 4 port, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperature 22 23 GSW140 6 port, 4 PHYs, RGMII & SGMII/2500Base-X 23 24 GSW141 6 port, 4 PHYs, RGMII & SGMII 24 25 GSW145 6 port, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperature 26 + GSW150 7 port, 5 PHYs, 1x GMII/RGMII, 1x RGMII
+31 -15
drivers/net/dsa/lantiq/lantiq_gswip.c
··· 33 33 struct phylink_config *config) 34 34 { 35 35 switch (port) { 36 - case 0: 37 - case 1: 36 + case 0 ... 1: 38 37 phy_interface_set_rgmii(config->supported_interfaces); 39 38 __set_bit(PHY_INTERFACE_MODE_MII, 40 39 config->supported_interfaces); ··· 43 44 config->supported_interfaces); 44 45 break; 45 46 46 - case 2: 47 - case 3: 48 - case 4: 47 + case 2 ... 4: 49 48 case 6: 50 49 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 51 50 config->supported_interfaces); ··· 72 75 config->supported_interfaces); 73 76 break; 74 77 75 - case 1: 76 - case 2: 77 - case 3: 78 - case 4: 78 + case 1 ... 4: 79 79 case 6: 80 80 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 81 81 config->supported_interfaces); ··· 457 463 } 458 464 459 465 static const struct gswip_hw_info gswip_xrx200 = { 460 - .max_ports = 7, 466 + .max_ports = GSWIP_MAX_PORTS, 461 467 .allowed_cpu_ports = BIT(6), 462 - .mii_ports = BIT(0) | BIT(1) | BIT(5), 463 - .mii_port_reg_offset = 0, 468 + .mii_cfg = { 469 + [0] = GSWIP_MII_CFGp(0), 470 + [1] = GSWIP_MII_CFGp(1), 471 + [2 ... 4] = -1, 472 + [5] = GSWIP_MII_CFGp(5), 473 + [6] = -1, 474 + }, 475 + .mii_pcdu = { 476 + [0] = GSWIP_MII_PCDU0, 477 + [1] = GSWIP_MII_PCDU1, 478 + [2 ... 4] = -1, 479 + [5] = GSWIP_MII_PCDU5, 480 + [6] = -1, 481 + }, 464 482 .phylink_get_caps = gswip_xrx200_phylink_get_caps, 465 483 .pce_microcode = &gswip_pce_microcode, 466 484 .pce_microcode_size = ARRAY_SIZE(gswip_pce_microcode), ··· 480 474 }; 481 475 482 476 static const struct gswip_hw_info gswip_xrx300 = { 483 - .max_ports = 7, 477 + .max_ports = GSWIP_MAX_PORTS, 484 478 .allowed_cpu_ports = BIT(6), 485 - .mii_ports = BIT(0) | BIT(5), 486 - .mii_port_reg_offset = 0, 479 + .mii_cfg = { 480 + [0] = GSWIP_MII_CFGp(0), 481 + [1 ... 4] = -1, 482 + [5] = GSWIP_MII_CFGp(5), 483 + [6] = -1, 484 + }, 485 + .mii_pcdu = { 486 + [0] = GSWIP_MII_PCDU0, 487 + [1 ... 4] = -1, 488 + [5] = GSWIP_MII_PCDU5, 489 + [6] = -1, 490 + }, 487 491 .phylink_get_caps = gswip_xrx300_phylink_get_caps, 488 492 .pce_microcode = &gswip_pce_microcode, 489 493 .pce_microcode_size = ARRAY_SIZE(gswip_pce_microcode),
+4 -2
drivers/net/dsa/lantiq/lantiq_gswip.h
··· 243 243 244 244 #define GSWIP_VLAN_UNAWARE_PVID 0 245 245 246 + #define GSWIP_MAX_PORTS 7 247 + 246 248 struct gswip_pce_microcode { 247 249 u16 val_3; 248 250 u16 val_2; ··· 255 253 struct gswip_hw_info { 256 254 int max_ports; 257 255 unsigned int allowed_cpu_ports; 258 - unsigned int mii_ports; 259 - int mii_port_reg_offset; 256 + s16 mii_cfg[GSWIP_MAX_PORTS]; 257 + s16 mii_pcdu[GSWIP_MAX_PORTS]; 260 258 bool supports_2500m; 261 259 const struct gswip_pce_microcode (*pce_microcode)[]; 262 260 size_t pce_microcode_size;
+4 -23
drivers/net/dsa/lantiq/lantiq_gswip_common.c
··· 118 118 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 mask, u32 set, 119 119 int port) 120 120 { 121 - int reg_port; 122 - 123 121 /* MII_CFG register only exists for MII ports */ 124 - if (!(priv->hw_info->mii_ports & BIT(port))) 122 + if (priv->hw_info->mii_cfg[port] == -1) 125 123 return; 126 124 127 - reg_port = port + priv->hw_info->mii_port_reg_offset; 128 - 129 - regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), mask, 125 + regmap_write_bits(priv->mii, priv->hw_info->mii_cfg[port], mask, 130 126 set); 131 127 } 132 128 ··· 606 610 u32 tx_delay = GSWIP_MII_PCDU_TXDLY_DEFAULT; 607 611 u32 rx_delay = GSWIP_MII_PCDU_RXDLY_DEFAULT; 608 612 struct device_node *port_dn = dp->dn; 609 - u16 mii_pcdu_reg; 610 613 611 614 /* As MII_PCDU registers only exist for MII ports, silently return 612 615 * unless the port is an MII port 613 616 */ 614 - if (!(priv->hw_info->mii_ports & BIT(dp->index))) 617 + if (priv->hw_info->mii_pcdu[dp->index] == -1) 615 618 return; 616 - 617 - switch (dp->index + priv->hw_info->mii_port_reg_offset) { 618 - case 0: 619 - mii_pcdu_reg = GSWIP_MII_PCDU0; 620 - break; 621 - case 1: 622 - mii_pcdu_reg = GSWIP_MII_PCDU1; 623 - break; 624 - case 5: 625 - mii_pcdu_reg = GSWIP_MII_PCDU5; 626 - break; 627 - default: 628 - return; 629 - } 630 619 631 620 /* legacy code to set default delays according to the interface mode */ 632 621 switch (interface) { ··· 633 652 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 634 653 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 635 654 636 - regmap_write_bits(priv->mii, mii_pcdu_reg, 655 + regmap_write_bits(priv->mii, priv->hw_info->mii_pcdu[dp->index], 637 656 GSWIP_MII_PCDU_TXDLY_MASK | 638 657 GSWIP_MII_PCDU_RXDLY_MASK, 639 658 GSWIP_MII_PCDU_TXDLY(tx_delay) |
+120 -31
drivers/net/dsa/lantiq/mxl-gsw1xx.c
··· 502 502 .pcs_link_up = gsw1xx_pcs_link_up, 503 503 }; 504 504 505 + static void gsw1xx_phylink_get_lpi_caps(struct phylink_config *config) 506 + { 507 + config->lpi_capabilities = MAC_100FD | MAC_1000FD; 508 + config->lpi_timer_default = 20; 509 + memcpy(config->lpi_interfaces, config->supported_interfaces, 510 + sizeof(config->lpi_interfaces)); 511 + } 512 + 505 513 static void gsw1xx_phylink_get_caps(struct dsa_switch *ds, int port, 506 514 struct phylink_config *config) 507 515 { ··· 519 511 MAC_10 | MAC_100 | MAC_1000; 520 512 521 513 switch (port) { 522 - case 0: 523 - case 1: 524 - case 2: 525 - case 3: 514 + case 0 ... 3: /* built-in PHYs */ 526 515 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 527 516 config->supported_interfaces); 528 517 break; 529 - case 4: /* port 4: SGMII */ 518 + 519 + case 4: /* SGMII */ 530 520 __set_bit(PHY_INTERFACE_MODE_SGMII, 531 521 config->supported_interfaces); 532 522 __set_bit(PHY_INTERFACE_MODE_1000BASEX, ··· 535 529 config->mac_capabilities |= MAC_2500FD; 536 530 } 537 531 return; /* no support for EEE on SGMII port */ 538 - case 5: /* port 5: RGMII or RMII */ 532 + 533 + case 5: /* RGMII or RMII */ 539 534 __set_bit(PHY_INTERFACE_MODE_RMII, 540 535 config->supported_interfaces); 541 536 phy_interface_set_rgmii(config->supported_interfaces); 542 537 break; 543 538 } 544 539 545 - config->lpi_capabilities = MAC_100FD | MAC_1000FD; 546 - config->lpi_timer_default = 20; 547 - memcpy(config->lpi_interfaces, config->supported_interfaces, 548 - sizeof(config->lpi_interfaces)); 540 + gsw1xx_phylink_get_lpi_caps(config); 541 + } 542 + 543 + static void gsw150_phylink_get_caps(struct dsa_switch *ds, int port, 544 + struct phylink_config *config) 545 + { 546 + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 547 + MAC_10 | MAC_100 | MAC_1000; 548 + 549 + switch (port) { 550 + case 0 ... 4: /* built-in PHYs */ 551 + __set_bit(PHY_INTERFACE_MODE_INTERNAL, 552 + config->supported_interfaces); 553 + break; 554 + 555 + case 5: /* GMII or RGMII */ 556 + __set_bit(PHY_INTERFACE_MODE_GMII, 557 + config->supported_interfaces); 558 + fallthrough; 559 + 560 + case 6: /* RGMII */ 561 + phy_interface_set_rgmii(config->supported_interfaces); 562 + break; 563 + } 564 + 565 + gsw1xx_phylink_get_lpi_caps(config); 549 566 } 550 567 551 568 static struct phylink_pcs *gsw1xx_phylink_mac_select_pcs(struct phylink_config *config, ··· 645 616 priv, &config); 646 617 } 647 618 619 + static int gsw1xx_serdes_pcs_init(struct gsw1xx_priv *priv) 620 + { 621 + /* do nothing if the chip doesn't have a SerDes PCS */ 622 + if (!priv->gswip.hw_info->mac_select_pcs) 623 + return 0; 624 + 625 + priv->pcs.ops = &gsw1xx_pcs_ops; 626 + priv->pcs.poll = true; 627 + __set_bit(PHY_INTERFACE_MODE_SGMII, 628 + priv->pcs.supported_interfaces); 629 + __set_bit(PHY_INTERFACE_MODE_1000BASEX, 630 + priv->pcs.supported_interfaces); 631 + if (priv->gswip.hw_info->supports_2500m) 632 + __set_bit(PHY_INTERFACE_MODE_2500BASEX, 633 + priv->pcs.supported_interfaces); 634 + priv->tbi_interface = PHY_INTERFACE_MODE_NA; 635 + 636 + /* assert SGMII reset to power down SGMII unit */ 637 + return regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ, 638 + GSW1XX_RST_REQ_SGMII_SHELL); 639 + } 640 + 648 641 static int gsw1xx_probe(struct mdio_device *mdiodev) 649 642 { 650 643 struct device *dev = &mdiodev->dev; ··· 719 668 if (IS_ERR(priv->shell)) 720 669 return PTR_ERR(priv->shell); 721 670 722 - priv->pcs.ops = &gsw1xx_pcs_ops; 723 - priv->pcs.poll = true; 724 - __set_bit(PHY_INTERFACE_MODE_SGMII, 725 - priv->pcs.supported_interfaces); 726 - __set_bit(PHY_INTERFACE_MODE_1000BASEX, 727 - priv->pcs.supported_interfaces); 728 - if (priv->gswip.hw_info->supports_2500m) 729 - __set_bit(PHY_INTERFACE_MODE_2500BASEX, 730 - priv->pcs.supported_interfaces); 731 - priv->tbi_interface = PHY_INTERFACE_MODE_NA; 732 - 733 - /* assert SGMII reset to power down SGMII unit */ 734 - ret = regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ, 735 - GSW1XX_RST_REQ_SGMII_SHELL); 671 + ret = gsw1xx_serdes_pcs_init(priv); 736 672 if (ret < 0) 737 673 return ret; 738 674 ··· 777 739 static const struct gswip_hw_info gsw12x_data = { 778 740 .max_ports = GSW1XX_PORTS, 779 741 .allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT), 780 - .mii_ports = BIT(GSW1XX_MII_PORT), 781 - .mii_port_reg_offset = -GSW1XX_MII_PORT, 742 + .mii_cfg = { 743 + [0 ... GSW1XX_MII_PORT - 1] = -1, 744 + [GSW1XX_MII_PORT] = GSWIP_MII_CFGp(0), 745 + [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1, 746 + }, 747 + .mii_pcdu = { 748 + [0 ... GSW1XX_MII_PORT - 1] = -1, 749 + [GSW1XX_MII_PORT] = GSWIP_MII_PCDU0, 750 + [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1, 751 + }, 782 752 .mac_select_pcs = gsw1xx_phylink_mac_select_pcs, 783 753 .phylink_get_caps = &gsw1xx_phylink_get_caps, 784 754 .supports_2500m = true, ··· 799 753 static const struct gswip_hw_info gsw140_data = { 800 754 .max_ports = GSW1XX_PORTS, 801 755 .allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT), 802 - .mii_ports = BIT(GSW1XX_MII_PORT), 803 - .mii_port_reg_offset = -GSW1XX_MII_PORT, 756 + .mii_cfg = { 757 + [0 ... GSW1XX_MII_PORT - 1] = -1, 758 + [GSW1XX_MII_PORT] = GSWIP_MII_CFGp(0), 759 + [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1, 760 + }, 761 + .mii_pcdu = { 762 + [0 ... GSW1XX_MII_PORT - 1] = -1, 763 + [GSW1XX_MII_PORT] = GSWIP_MII_PCDU0, 764 + [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1, 765 + }, 804 766 .mac_select_pcs = gsw1xx_phylink_mac_select_pcs, 805 767 .phylink_get_caps = &gsw1xx_phylink_get_caps, 806 768 .supports_2500m = true, ··· 821 767 static const struct gswip_hw_info gsw141_data = { 822 768 .max_ports = GSW1XX_PORTS, 823 769 .allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT), 824 - .mii_ports = BIT(GSW1XX_MII_PORT), 825 - .mii_port_reg_offset = -GSW1XX_MII_PORT, 770 + .mii_cfg = { 771 + [0 ... GSW1XX_MII_PORT - 1] = -1, 772 + [GSW1XX_MII_PORT] = GSWIP_MII_CFGp(0), 773 + [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1, 774 + }, 775 + .mii_pcdu = { 776 + [0 ... GSW1XX_MII_PORT - 1] = -1, 777 + [GSW1XX_MII_PORT] = GSWIP_MII_PCDU0, 778 + [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1, 779 + }, 826 780 .mac_select_pcs = gsw1xx_phylink_mac_select_pcs, 827 781 .phylink_get_caps = gsw1xx_phylink_get_caps, 782 + .port_setup = gsw1xx_port_setup, 783 + .pce_microcode = &gsw1xx_pce_microcode, 784 + .pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode), 785 + .tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX, 786 + }; 787 + 788 + static const struct gswip_hw_info gsw150_data = { 789 + .max_ports = GSW150_PORTS, 790 + .allowed_cpu_ports = BIT(5) | BIT(6), 791 + .mii_cfg = { 792 + [0 ... 4] = -1, 793 + [5] = 0, 794 + [6] = 10, 795 + }, 796 + .mii_pcdu = { 797 + [0 ... 4] = -1, 798 + [5] = 1, 799 + [6] = 11, 800 + }, 801 + .phylink_get_caps = gsw150_phylink_get_caps, 802 + /* There is only a single RGMII_SLEW_CFG register in GSW150 and it is 803 + * unknown if RGMII slew configuration affects both RGMII ports 804 + * or only port 5. Use .port_setup which assumes it affects port 5 805 + * for now. 806 + */ 828 807 .port_setup = gsw1xx_port_setup, 829 808 .pce_microcode = &gsw1xx_pce_microcode, 830 809 .pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode), ··· 869 782 * GSW145 is the industrial temperature version of GSW140. 870 783 */ 871 784 static const struct of_device_id gsw1xx_of_match[] = { 785 + { .compatible = "intel,gsw150", .data = &gsw150_data }, 786 + { .compatible = "lantiq,peb7084", .data = &gsw150_data }, 872 787 { .compatible = "maxlinear,gsw120", .data = &gsw12x_data }, 873 788 { .compatible = "maxlinear,gsw125", .data = &gsw12x_data }, 874 789 { .compatible = "maxlinear,gsw140", .data = &gsw140_data }, ··· 894 805 mdio_module_driver(gsw1xx_driver); 895 806 896 807 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 897 - MODULE_DESCRIPTION("Driver for MaxLinear GSW1xx ethernet switch"); 808 + MODULE_DESCRIPTION("Driver for Intel/MaxLinear GSW1xx Ethernet switch"); 898 809 MODULE_LICENSE("GPL");
+2
drivers/net/dsa/lantiq/mxl-gsw1xx.h
··· 10 10 #include <linux/bitfield.h> 11 11 12 12 #define GSW1XX_PORTS 6 13 + #define GSW150_PORTS 7 14 + 13 15 /* Port used for RGMII or optional RMII */ 14 16 #define GSW1XX_MII_PORT 5 15 17 /* Port used for SGMII */