tjh.dev / kernel
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Merge tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx into soc/dt

ARM: nxp: lpc: device tree updates for v6.18

This pull request contains device tree changes for ARM NXP LPC32xx and
ARM NXP LPC18xx/LPC43xx for v6.18, please pull the following:

- Frank fixes a multitude of device tree checker warnings reported for
NXP LPC18xx/LPC43xx powered boards,
- Vladimir fixes a number of compile time warnings issued by a dt checker
for NXP LPC32xx powered boards,
- Vladimir replaces Roland as a maintainer of NXP LPC32xx platform
device trees, Roland is inactive for more than 10 years.

* tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx:
ARM: dts: lpc32xx: Correct PL080 DMA controller device node name
ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller
ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP
ARM: dts: lpc32xx: Correct SD/MMC controller device node name
ARM: dts: lpc32xx: Correct motor PWM device tree node name
ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
ARM: dts: lpc18xx: add missed arm,num-irq-priority-bits
ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller
ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio
ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]'
ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92
ARM: dts: lpc: add cfg surfix in pinctrl child node
ARM: dts: lpc: add #address-cells and #size-cells for sram node
ARM: dts: lpc18xx: swap clock-names bic and cui
ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0
ARM: dts: lpc18xx: rename node name mmcsd to mmc
ARM: dts: lpc18xx: rename node name flash-controller to spi

Link: https://lore.kernel.org/r/20250911130642.41958-1-vz@mleia.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 4c445734 58760bd7

+66 -34
+1 -1
Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml
··· 7 7 title: NXP LPC32xx Platforms 8 8 9 9 maintainers: 10 - - Roland Stigge <stigge@antcom.de> 10 + - Vladimir Zapolskiy <vz@mleia.com> 11 11 12 12 properties: 13 13 compatible:
+10 -4
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
··· 100 100 memcpy-bus-width = <32>; 101 101 }; 102 102 103 - spifi: flash-controller@40003000 { 103 + spifi: spi@40003000 { 104 104 compatible = "nxp,lpc1773-spifi"; 105 105 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; 106 106 reg-names = "spifi", "flash"; 107 107 interrupts = <30>; 108 108 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; 109 109 clock-names = "spifi", "reg"; 110 + #address-cells = <1>; 111 + #size-cells = <0>; 110 112 resets = <&rgu 53>; 111 113 status = "disabled"; 112 114 }; 113 115 114 - mmcsd: mmcsd@40004000 { 116 + mmcsd: mmc@40004000 { 115 117 compatible = "snps,dw-mshc"; 116 118 reg = <0x40004000 0x1000>; 117 119 interrupts = <6>; 118 - clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; 119 - clock-names = "ciu", "biu"; 120 + clocks = <&ccu1 CLK_CPU_SDIO>, <&ccu2 CLK_SDIO>; 121 + clock-names = "biu", "ciu"; 120 122 resets = <&rgu 20>; 121 123 status = "disabled"; 122 124 }; ··· 536 534 <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; 537 535 }; 538 536 }; 537 + }; 538 + 539 + &nvic { 540 + arm,num-irq-priority-bits = <3>; 539 541 };
+6 -5
arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
··· 77 77 status = "disabled"; 78 78 }; 79 79 80 - dma: dma@31000000 { 80 + dma: dma-controller@31000000 { 81 81 compatible = "arm,pl080", "arm,primecell"; 82 82 reg = <0x31000000 0x1000>; 83 83 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 84 84 clocks = <&clk LPC32XX_CLK_DMA>; 85 85 clock-names = "apb_pclk"; 86 + #dma-cells = <2>; 86 87 }; 87 88 88 89 usb { ··· 225 224 status = "disabled"; 226 225 }; 227 226 228 - sd: sd@20098000 { 229 - compatible = "arm,pl18x", "arm,primecell"; 227 + sd: mmc@20098000 { 228 + compatible = "arm,pl180", "arm,primecell"; 230 229 reg = <0x20098000 0x1000>; 231 230 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, 232 231 <13 IRQ_TYPE_LEVEL_HIGH>; ··· 299 298 clocks = <&clk LPC32XX_CLK_I2C2>; 300 299 }; 301 300 302 - mpwm: mpwm@400e8000 { 301 + mpwm: pwm@400e8000 { 303 302 compatible = "nxp,lpc3220-motor-pwm"; 304 303 reg = <0x400e8000 0x78>; 304 + #pwm-cells = <3>; 305 305 status = "disabled"; 306 - #pwm-cells = <2>; 307 306 }; 308 307 }; 309 308
+3 -3
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
··· 108 108 }; 109 109 110 110 ssp_pins: ssp-pins { 111 - ssp1_cs { 111 + ssp1_cs_cfg { 112 112 pins = "p6_7"; 113 113 function = "gpio"; 114 114 bias-pull-up; 115 115 bias-disable; 116 116 }; 117 117 118 - ssp1_miso_mosi { 118 + ssp1_miso_mosi_cfg { 119 119 pins = "p1_3", "p1_4"; 120 120 function = "ssp1"; 121 121 slew-rate = <1>; ··· 124 124 input-schmitt-disable; 125 125 }; 126 126 127 - ssp1_sck { 127 + ssp1_sck_cfg { 128 128 pins = "pf_4"; 129 129 function = "ssp1"; 130 130 slew-rate = <1>;
+13 -9
arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
··· 43 43 poll-interval = <100>; 44 44 autorepeat; 45 45 46 - button0 { 46 + button-0 { 47 47 label = "joy:right"; 48 48 linux,code = <KEY_RIGHT>; 49 49 gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; 50 50 }; 51 51 52 - button1 { 52 + button-1 { 53 53 label = "joy:up"; 54 54 linux,code = <KEY_UP>; 55 55 gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; 56 56 }; 57 57 58 58 59 - button2 { 59 + button-2 { 60 60 label = "joy:enter"; 61 61 linux,code = <KEY_ENTER>; 62 62 gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; 63 63 }; 64 64 65 - button3 { 65 + button-3 { 66 66 label = "joy:left"; 67 67 linux,code = <KEY_LEFT>; 68 68 gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; 69 69 }; 70 70 71 - button4 { 71 + button-4 { 72 72 label = "joy:down"; 73 73 linux,code = <KEY_DOWN>; 74 74 gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; 75 75 }; 76 76 77 - button5 { 77 + button-5 { 78 78 label = "user:sw3"; 79 79 linux,code = <KEY_F1>; 80 80 gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; 81 81 }; 82 82 83 - button6 { 83 + button-6 { 84 84 label = "user:sw4"; 85 85 linux,code = <KEY_F2>; 86 86 gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; 87 87 }; 88 88 89 - button7 { 89 + button-7 { 90 90 label = "user:sw5"; 91 91 linux,code = <KEY_F3>; 92 92 gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; ··· 406 406 ext_sram: sram@2,0 { 407 407 compatible = "mmio-sram"; 408 408 reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ 409 + #address-cells = <1>; 410 + #size-cells = <1>; 411 + ranges = <0 2 0 0x80000>; 409 412 }; 410 413 }; 411 414 }; ··· 454 451 pinctrl-names = "default"; 455 452 pinctrl-0 = <&spifi_pins>; 456 453 457 - flash { 454 + flash@0 { 458 455 compatible = "jedec,spi-nor"; 456 + reg = <0>; 459 457 spi-rx-bus-width = <4>; 460 458 #address-cells = <1>; 461 459 #size-cells = <1>;
+9
arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
··· 24 24 sram0: sram@10000000 { 25 25 compatible = "mmio-sram"; 26 26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ 27 + #address-cells = <1>; 28 + #size-cells = <1>; 29 + ranges; 27 30 }; 28 31 29 32 sram1: sram@10080000 { 30 33 compatible = "mmio-sram"; 31 34 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ 35 + #address-cells = <1>; 36 + #size-cells = <1>; 37 + ranges; 32 38 }; 33 39 34 40 sram2: sram@20000000 { 35 41 compatible = "mmio-sram"; 36 42 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ 43 + #address-cells = <1>; 44 + #size-cells = <1>; 45 + ranges; 37 46 }; 38 47 }; 39 48 };
+11 -10
arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
··· 60 60 poll-interval = <100>; 61 61 autorepeat; 62 62 63 - button0 { 63 + button-0 { 64 64 label = "joy_enter"; 65 65 linux,code = <KEY_ENTER>; 66 66 gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; 67 67 }; 68 68 69 - button1 { 69 + button-1 { 70 70 label = "joy_left"; 71 71 linux,code = <KEY_LEFT>; 72 72 gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; 73 73 }; 74 74 75 - button2 { 75 + button-2 { 76 76 label = "joy_up"; 77 77 linux,code = <KEY_UP>; 78 78 gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; 79 79 }; 80 80 81 - button3 { 81 + button-3 { 82 82 label = "joy_right"; 83 83 linux,code = <KEY_RIGHT>; 84 84 gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; 85 85 }; 86 86 87 - button4 { 87 + button-4 { 88 88 label = "joy_down"; 89 89 linux,code = <KEY_DOWN>; 90 90 gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; ··· 403 403 }; 404 404 405 405 ssp0_pins: ssp0-pins { 406 - ssp0_sck_miso_mosi { 406 + ssp0_sck_miso_mosi_cfg { 407 407 pins = "pf_0", "pf_2", "pf_3"; 408 408 function = "ssp0"; 409 409 slew-rate = <1>; ··· 412 412 input-schmitt-disable; 413 413 }; 414 414 415 - ssp0_ssel { 415 + ssp0_ssel_cfg { 416 416 pins = "pf_1"; 417 417 function = "ssp0"; 418 418 bias-pull-up; ··· 452 452 }; 453 453 454 454 usb0_pins: usb0-pins { 455 - usb0_pwr_enable { 455 + usb0_pwr_enable_cfg { 456 456 pins = "p2_3"; 457 457 function = "usb0"; 458 458 }; 459 459 460 - usb0_pwr_fault { 460 + usb0_pwr_fault_cfg { 461 461 pins = "p8_0"; 462 462 function = "usb0"; 463 463 bias-disable; ··· 582 582 pinctrl-names = "default"; 583 583 pinctrl-0 = <&spifi_pins>; 584 584 585 - flash { 585 + flash@0 { 586 586 compatible = "jedec,spi-nor"; 587 + reg = <0>; 587 588 spi-cpol; 588 589 spi-cpha; 589 590 spi-rx-bus-width = <4>;
+4 -2
arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
··· 63 63 64 64 panel: panel { 65 65 compatible = "innolux,at070tn92"; 66 + power-supply = <&vcc>; 66 67 67 68 port { 68 69 panel_input: endpoint { ··· 544 543 pinctrl-0 = <&enet_rmii_pins>; 545 544 phy-handle = <&phy1>; 546 545 547 - mdio0 { 546 + mdio { 548 547 #address-cells = <1>; 549 548 #size-cells = <0>; 550 549 compatible = "snps,dwmac-mdio"; ··· 570 569 pinctrl-0 = <&spifi_pins>; 571 570 572 571 /* Atmel AT25DF321A */ 573 - flash { 572 + flash@0 { 574 573 compatible = "jedec,spi-nor"; 574 + reg = <0>; 575 575 spi-max-frequency = <51000000>; 576 576 spi-cpol; 577 577 spi-cpha;
+9
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
··· 24 24 sram0: sram@10000000 { 25 25 compatible = "mmio-sram"; 26 26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ 27 + #address-cells = <1>; 28 + #size-cells = <1>; 29 + ranges; 27 30 }; 28 31 29 32 sram1: sram@10080000 { 30 33 compatible = "mmio-sram"; 31 34 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ 35 + #address-cells = <1>; 36 + #size-cells = <1>; 37 + ranges; 32 38 }; 33 39 34 40 sram2: sram@20000000 { 35 41 compatible = "mmio-sram"; 36 42 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ 43 + #address-cells = <1>; 44 + #size-cells = <1>; 45 + ranges; 37 46 }; 38 47 }; 39 48 };