Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC late updates from Olof Johansson:
"This is some material that we picked up into our tree late. Most of it
are smaller fixes and additions, some defconfig updates due to recent
development, etc.
Code-wise the largest portion is a series of PM updates for the at91
platform, and those have been in linux-next a while through the at91
tree before we picked them up"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (29 commits)
arm64: dts: sprd: Add clock properties for serial devices
Opt out of scripts/get_maintainer.pl
ARM: ixp4xx: Remove duplicated include from common.c
soc: ixp4xx: qmgr: Fix an NULL vs IS_ERR() check in probe
arm64: tegra: Disable XUSB support on Jetson TX2
arm64: tegra: Enable SMMU translation for PCI on Tegra186
arm64: tegra: Fix insecure SMMU users for Tegra186
arm64: tegra: Select ARM_GIC_PM
amba: tegra-ahb: Mark PM functions as __maybe_unused
ARM: dts: logicpd-som-lv: Fix MMC1 card detect
ARM: mvebu: drop return from void function
ARM: mvebu: prefix coprocessor operand with p
ARM: mvebu: drop unnecessary label
ARM: mvebu: fix a leaked reference by adding missing of_node_put
ARM: socfpga_defconfig: enable LTC2497
ARM: mvebu: kirkwood: remove error message when retrieving mac address
ARM: at91: sama5: make ov2640 as a module
ARM: OMAP1: ams-delta: fix early boot crash when LED support is disabled
ARM: at91: remove HAVE_FB_ATMEL for sama5 SoC as they use DRM
soc/fsl/qe: Fix an error code in qe_pin_request()
...
+277
-124
+1
.get_maintainer.ignore
+1
.get_maintainer.ignore
+1
Documentation/devicetree/bindings/arm/atmel-at91.txt
+1
Documentation/devicetree/bindings/arm/atmel-at91.txt
+1
-1
arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi
+1
-1
arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi
···
153
153
pinctrl-names = "default";
154
154
pinctrl-0 = <&mmc1_pins>;
155
155
wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
156
-
cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */
156
+
cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
157
157
vmmc-supply = <&vmmc1>;
158
158
bus-width = <4>;
159
159
cap-power-off-card;
+1
-1
arch/arm/configs/sama5_defconfig
+1
-1
arch/arm/configs/sama5_defconfig
+2
-1
arch/arm/configs/socfpga_defconfig
+2
-1
arch/arm/configs/socfpga_defconfig
···
21
21
CONFIG_OPROFILE=y
22
22
CONFIG_MODULES=y
23
23
CONFIG_MODULE_UNLOAD=y
24
-
# CONFIG_LBDAF is not set
25
24
# CONFIG_BLK_DEV_BSG is not set
26
25
CONFIG_NET=y
27
26
CONFIG_PACKET=y
···
127
128
CONFIG_DMADEVICES=y
128
129
CONFIG_PL330_DMA=y
129
130
CONFIG_DMATEST=m
131
+
CONFIG_IIO=y
132
+
CONFIG_LTC2497=y
130
133
CONFIG_FPGA=y
131
134
CONFIG_FPGA_MGR_SOCFPGA=y
132
135
CONFIG_FPGA_MGR_SOCFPGA_A10=y
-3
arch/arm/mach-at91/Kconfig
-3
arch/arm/mach-at91/Kconfig
···
21
21
depends on ARCH_MULTI_V7
22
22
select SOC_SAMA5
23
23
select CACHE_L2X0
24
-
select HAVE_FB_ATMEL
25
24
select HAVE_AT91_UTMI
26
25
select HAVE_AT91_USB_CLK
27
26
select HAVE_AT91_H32MX
···
35
36
bool "SAMA5D3 family"
36
37
depends on ARCH_MULTI_V7
37
38
select SOC_SAMA5
38
-
select HAVE_FB_ATMEL
39
39
select HAVE_AT91_UTMI
40
40
select HAVE_AT91_SMD
41
41
select HAVE_AT91_USB_CLK
···
48
50
depends on ARCH_MULTI_V7
49
51
select SOC_SAMA5
50
52
select CACHE_L2X0
51
-
select HAVE_FB_ATMEL
52
53
select HAVE_AT91_UTMI
53
54
select HAVE_AT91_SMD
54
55
select HAVE_AT91_USB_CLK
+18
arch/arm/mach-at91/at91sam9.c
+18
arch/arm/mach-at91/at91sam9.c
···
32
32
.init_machine = at91sam9_init,
33
33
.dt_compat = at91_dt_board_compat,
34
34
MACHINE_END
35
+
36
+
static void __init sam9x60_init(void)
37
+
{
38
+
of_platform_default_populate(NULL, NULL, NULL);
39
+
40
+
sam9x60_pm_init();
41
+
}
42
+
43
+
static const char *const sam9x60_dt_board_compat[] __initconst = {
44
+
"microchip,sam9x60",
45
+
NULL
46
+
};
47
+
48
+
DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
49
+
/* Maintainer: Microchip */
50
+
.init_machine = sam9x60_init,
51
+
.dt_compat = sam9x60_dt_board_compat,
52
+
MACHINE_END
+2
arch/arm/mach-at91/generic.h
+2
arch/arm/mach-at91/generic.h
···
14
14
#ifdef CONFIG_PM
15
15
extern void __init at91rm9200_pm_init(void);
16
16
extern void __init at91sam9_pm_init(void);
17
+
extern void __init sam9x60_pm_init(void);
17
18
extern void __init sama5_pm_init(void);
18
19
extern void __init sama5d2_pm_init(void);
19
20
#else
20
21
static inline void __init at91rm9200_pm_init(void) { }
21
22
static inline void __init at91sam9_pm_init(void) { }
23
+
static inline void __init sam9x60_pm_init(void) { }
22
24
static inline void __init sama5_pm_init(void) { }
23
25
static inline void __init sama5d2_pm_init(void) { }
24
26
#endif
+133
-60
arch/arm/mach-at91/pm.c
+133
-60
arch/arm/mach-at91/pm.c
···
39
39
extern void at91_pinctrl_gpio_resume(void);
40
40
#endif
41
41
42
+
struct at91_soc_pm {
43
+
int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
44
+
int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
45
+
const struct of_device_id *ws_ids;
46
+
struct at91_pm_data data;
47
+
};
48
+
49
+
static struct at91_soc_pm soc_pm = {
50
+
.data = {
51
+
.standby_mode = AT91_PM_STANDBY,
52
+
.suspend_mode = AT91_PM_ULP0,
53
+
},
54
+
};
55
+
42
56
static const match_table_t pm_modes __initconst = {
43
57
{ AT91_PM_STANDBY, "standby" },
44
58
{ AT91_PM_ULP0, "ulp0" },
···
61
47
{ -1, NULL },
62
48
};
63
49
64
-
static struct at91_pm_data pm_data = {
65
-
.standby_mode = AT91_PM_STANDBY,
66
-
.suspend_mode = AT91_PM_ULP0,
67
-
};
68
-
69
50
#define at91_ramc_read(id, field) \
70
-
__raw_readl(pm_data.ramc[id] + field)
51
+
__raw_readl(soc_pm.data.ramc[id] + field)
71
52
72
53
#define at91_ramc_write(id, field, value) \
73
-
__raw_writel(value, pm_data.ramc[id] + field)
54
+
__raw_writel(value, soc_pm.data.ramc[id] + field)
74
55
75
56
static int at91_pm_valid_state(suspend_state_t state)
76
57
{
···
100
91
{ .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
101
92
{ .pmc_fsmr_bit = AT91_PMC_USBAL },
102
93
{ .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
94
+
{ .pmc_fsmr_bit = AT91_PMC_RTTAL },
95
+
{ .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
103
96
};
104
97
105
98
static const struct of_device_id sama5d2_ws_ids[] = {
···
116
105
{ /* sentinel */ }
117
106
};
118
107
108
+
static const struct of_device_id sam9x60_ws_ids[] = {
109
+
{ .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
110
+
{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
111
+
{ .compatible = "usb-ohci", .data = &ws_info[2] },
112
+
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
113
+
{ .compatible = "usb-ehci", .data = &ws_info[2] },
114
+
{ .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
115
+
{ .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
116
+
{ /* sentinel */ }
117
+
};
118
+
119
119
static int at91_pm_config_ws(unsigned int pm_mode, bool set)
120
120
{
121
121
const struct wakeup_source_info *wsi;
···
138
116
if (pm_mode != AT91_PM_ULP1)
139
117
return 0;
140
118
141
-
if (!pm_data.pmc || !pm_data.shdwc)
119
+
if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
142
120
return -EPERM;
143
121
144
122
if (!set) {
145
-
writel(mode, pm_data.pmc + AT91_PMC_FSMR);
123
+
writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
146
124
return 0;
147
125
}
148
126
149
-
/* SHDWC.WUIR */
150
-
val = readl(pm_data.shdwc + 0x0c);
151
-
mode |= (val & 0x3ff);
152
-
polarity |= ((val >> 16) & 0x3ff);
127
+
if (soc_pm.config_shdwc_ws)
128
+
soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
153
129
154
130
/* SHDWC.MR */
155
-
val = readl(pm_data.shdwc + 0x04);
131
+
val = readl(soc_pm.data.shdwc + 0x04);
156
132
157
133
/* Loop through defined wakeup sources. */
158
-
for_each_matching_node_and_match(np, sama5d2_ws_ids, &match) {
134
+
for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
159
135
pdev = of_find_device_by_node(np);
160
136
if (!pdev)
161
137
continue;
···
175
155
}
176
156
177
157
if (mode) {
178
-
writel(mode, pm_data.pmc + AT91_PMC_FSMR);
179
-
writel(polarity, pm_data.pmc + AT91_PMC_FSPR);
158
+
if (soc_pm.config_pmc_ws)
159
+
soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
180
160
} else {
181
161
pr_err("AT91: PM: no ULP1 wakeup sources found!");
182
162
}
183
163
184
164
return mode ? 0 : -EPERM;
165
+
}
166
+
167
+
static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
168
+
u32 *polarity)
169
+
{
170
+
u32 val;
171
+
172
+
/* SHDWC.WUIR */
173
+
val = readl(shdwc + 0x0c);
174
+
*mode |= (val & 0x3ff);
175
+
*polarity |= ((val >> 16) & 0x3ff);
176
+
177
+
return 0;
178
+
}
179
+
180
+
static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
181
+
{
182
+
writel(mode, pmc + AT91_PMC_FSMR);
183
+
writel(polarity, pmc + AT91_PMC_FSPR);
184
+
185
+
return 0;
186
+
}
187
+
188
+
static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
189
+
{
190
+
writel(mode, pmc + AT91_PMC_FSMR);
191
+
192
+
return 0;
185
193
}
186
194
187
195
/*
···
219
171
{
220
172
switch (state) {
221
173
case PM_SUSPEND_MEM:
222
-
pm_data.mode = pm_data.suspend_mode;
174
+
soc_pm.data.mode = soc_pm.data.suspend_mode;
223
175
break;
224
176
225
177
case PM_SUSPEND_STANDBY:
226
-
pm_data.mode = pm_data.standby_mode;
178
+
soc_pm.data.mode = soc_pm.data.standby_mode;
227
179
break;
228
180
229
181
default:
230
-
pm_data.mode = -1;
182
+
soc_pm.data.mode = -1;
231
183
}
232
184
233
-
return at91_pm_config_ws(pm_data.mode, true);
185
+
return at91_pm_config_ws(soc_pm.data.mode, true);
234
186
}
235
187
236
188
/*
···
242
194
unsigned long scsr;
243
195
int i;
244
196
245
-
scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
197
+
scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
246
198
247
199
/* USB must not be using PLLB */
248
-
if ((scsr & pm_data.uhp_udp_mask) != 0) {
200
+
if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
249
201
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
250
202
return 0;
251
203
}
···
256
208
257
209
if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
258
210
continue;
259
-
css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
211
+
css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
260
212
if (css != AT91_PMC_CSS_SLOW) {
261
213
pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
262
214
return 0;
···
278
230
*/
279
231
int at91_suspend_entering_slow_clock(void)
280
232
{
281
-
return (pm_data.mode >= AT91_PM_ULP0);
233
+
return (soc_pm.data.mode >= AT91_PM_ULP0);
282
234
}
283
235
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
284
236
···
291
243
flush_cache_all();
292
244
outer_disable();
293
245
294
-
at91_suspend_sram_fn(&pm_data);
246
+
at91_suspend_sram_fn(&soc_pm.data);
295
247
296
248
return 0;
297
249
}
298
250
299
251
static void at91_pm_suspend(suspend_state_t state)
300
252
{
301
-
if (pm_data.mode == AT91_PM_BACKUP) {
253
+
if (soc_pm.data.mode == AT91_PM_BACKUP) {
302
254
pm_bu->suspended = 1;
303
255
304
256
cpu_suspend(0, at91_suspend_finish);
···
337
289
/*
338
290
* Ensure that clocks are in a valid state.
339
291
*/
340
-
if (pm_data.mode >= AT91_PM_ULP0 &&
292
+
if (soc_pm.data.mode >= AT91_PM_ULP0 &&
341
293
!at91_pm_verify_clocks())
342
294
goto error;
343
295
···
366
318
*/
367
319
static void at91_pm_end(void)
368
320
{
369
-
at91_pm_config_ws(pm_data.mode, false);
321
+
at91_pm_config_ws(soc_pm.data.mode, false);
370
322
}
371
323
372
324
···
399
351
" str %2, [%1, %3]\n\t"
400
352
" mcr p15, 0, %0, c7, c0, 4\n\t"
401
353
:
402
-
: "r" (0), "r" (pm_data.ramc[0]),
354
+
: "r" (0), "r" (soc_pm.data.ramc[0]),
403
355
"r" (1), "r" (AT91_MC_SDRAMC_SRR));
404
356
}
405
357
···
422
374
at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
423
375
}
424
376
425
-
if (pm_data.ramc[1]) {
377
+
if (soc_pm.data.ramc[1]) {
426
378
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
427
379
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
428
380
lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
···
440
392
441
393
/* self-refresh mode now */
442
394
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
443
-
if (pm_data.ramc[1])
395
+
if (soc_pm.data.ramc[1])
444
396
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
445
397
446
398
cpu_do_idle();
447
399
448
400
at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
449
401
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
450
-
if (pm_data.ramc[1]) {
402
+
if (soc_pm.data.ramc[1]) {
451
403
at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
452
404
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
453
405
}
···
477
429
u32 lpr0, lpr1 = 0;
478
430
u32 saved_lpr0, saved_lpr1 = 0;
479
431
480
-
if (pm_data.ramc[1]) {
432
+
if (soc_pm.data.ramc[1]) {
481
433
saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
482
434
lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
483
435
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
···
489
441
490
442
/* self-refresh mode now */
491
443
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
492
-
if (pm_data.ramc[1])
444
+
if (soc_pm.data.ramc[1])
493
445
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
494
446
495
447
cpu_do_idle();
496
448
497
449
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
498
-
if (pm_data.ramc[1])
450
+
if (soc_pm.data.ramc[1])
499
451
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
500
452
}
501
453
···
528
480
const struct ramc_info *ramc;
529
481
530
482
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
531
-
pm_data.ramc[idx] = of_iomap(np, 0);
532
-
if (!pm_data.ramc[idx])
483
+
soc_pm.data.ramc[idx] = of_iomap(np, 0);
484
+
if (!soc_pm.data.ramc[idx])
533
485
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
534
486
535
487
ramc = of_id->data;
536
488
if (!standby)
537
489
standby = ramc->idle;
538
-
pm_data.memctrl = ramc->memctrl;
490
+
soc_pm.data.memctrl = ramc->memctrl;
539
491
540
492
idx++;
541
493
}
···
557
509
* Disable the processor clock. The processor will be automatically
558
510
* re-enabled by an interrupt or by a reset.
559
511
*/
560
-
writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
512
+
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
513
+
}
514
+
515
+
static void at91sam9x60_idle(void)
516
+
{
517
+
cpu_do_idle();
561
518
}
562
519
563
520
static void at91sam9_idle(void)
564
521
{
565
-
writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
522
+
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
566
523
cpu_do_idle();
567
524
}
568
525
···
619
566
620
567
static bool __init at91_is_pm_mode_active(int pm_mode)
621
568
{
622
-
return (pm_data.standby_mode == pm_mode ||
623
-
pm_data.suspend_mode == pm_mode);
569
+
return (soc_pm.data.standby_mode == pm_mode ||
570
+
soc_pm.data.suspend_mode == pm_mode);
624
571
}
625
572
626
573
static int __init at91_pm_backup_init(void)
···
629
576
struct device_node *np;
630
577
struct platform_device *pdev = NULL;
631
578
int ret = -ENODEV;
579
+
580
+
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
581
+
return -EPERM;
632
582
633
583
if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
634
584
return 0;
···
642
586
return ret;
643
587
}
644
588
645
-
pm_data.sfrbu = of_iomap(np, 0);
589
+
soc_pm.data.sfrbu = of_iomap(np, 0);
646
590
of_node_put(np);
647
591
648
592
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
···
678
622
securam_fail:
679
623
put_device(&pdev->dev);
680
624
securam_fail_no_ref_dev:
681
-
iounmap(pm_data.sfrbu);
682
-
pm_data.sfrbu = NULL;
625
+
iounmap(soc_pm.data.sfrbu);
626
+
soc_pm.data.sfrbu = NULL;
683
627
return ret;
684
628
}
685
629
···
688
632
if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
689
633
return;
690
634
691
-
if (pm_data.standby_mode == pm_mode)
692
-
pm_data.standby_mode = AT91_PM_ULP0;
693
-
if (pm_data.suspend_mode == pm_mode)
694
-
pm_data.suspend_mode = AT91_PM_ULP0;
635
+
if (soc_pm.data.standby_mode == pm_mode)
636
+
soc_pm.data.standby_mode = AT91_PM_ULP0;
637
+
if (soc_pm.data.suspend_mode == pm_mode)
638
+
soc_pm.data.suspend_mode = AT91_PM_ULP0;
695
639
}
696
640
697
641
static void __init at91_pm_modes_init(void)
···
709
653
goto ulp1_default;
710
654
}
711
655
712
-
pm_data.shdwc = of_iomap(np, 0);
656
+
soc_pm.data.shdwc = of_iomap(np, 0);
713
657
of_node_put(np);
714
658
715
659
ret = at91_pm_backup_init();
···
723
667
return;
724
668
725
669
unmap:
726
-
iounmap(pm_data.shdwc);
727
-
pm_data.shdwc = NULL;
670
+
iounmap(soc_pm.data.shdwc);
671
+
soc_pm.data.shdwc = NULL;
728
672
ulp1_default:
729
673
at91_pm_use_default_mode(AT91_PM_ULP1);
730
674
backup_default:
···
767
711
platform_device_register(&at91_cpuidle_device);
768
712
769
713
pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
770
-
pm_data.pmc = of_iomap(pmc_np, 0);
771
-
if (!pm_data.pmc) {
714
+
soc_pm.data.pmc = of_iomap(pmc_np, 0);
715
+
if (!soc_pm.data.pmc) {
772
716
pr_err("AT91: PM not supported, PMC not found\n");
773
717
return;
774
718
}
775
719
776
720
pmc = of_id->data;
777
-
pm_data.uhp_udp_mask = pmc->uhp_udp_mask;
721
+
soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
778
722
779
723
if (pm_idle)
780
724
arm_pm_idle = pm_idle;
···
784
728
if (at91_suspend_sram_fn) {
785
729
suspend_set_ops(&at91_pm_ops);
786
730
pr_info("AT91: PM: standby: %s, suspend: %s\n",
787
-
pm_modes[pm_data.standby_mode].pattern,
788
-
pm_modes[pm_data.suspend_mode].pattern);
731
+
pm_modes[soc_pm.data.standby_mode].pattern,
732
+
pm_modes[soc_pm.data.suspend_mode].pattern);
789
733
} else {
790
734
pr_info("AT91: PM not supported, due to no SRAM allocated\n");
791
735
}
···
804
748
at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
805
749
806
750
at91_pm_init(at91rm9200_idle);
751
+
}
752
+
753
+
void __init sam9x60_pm_init(void)
754
+
{
755
+
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
756
+
return;
757
+
758
+
at91_pm_modes_init();
759
+
at91_dt_ramc();
760
+
at91_pm_init(at91sam9x60_idle);
761
+
762
+
soc_pm.ws_ids = sam9x60_ws_ids;
763
+
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
807
764
}
808
765
809
766
void __init at91sam9_pm_init(void)
···
844
775
845
776
at91_pm_modes_init();
846
777
sama5_pm_init();
778
+
779
+
soc_pm.ws_ids = sama5d2_ws_ids;
780
+
soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
781
+
soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
847
782
}
848
783
849
784
static int __init at91_pm_modes_select(char *str)
···
868
795
if (suspend < 0)
869
796
return 0;
870
797
871
-
pm_data.standby_mode = standby;
872
-
pm_data.suspend_mode = suspend;
798
+
soc_pm.data.standby_mode = standby;
799
+
soc_pm.data.suspend_mode = suspend;
873
800
874
801
return 0;
875
802
}
+77
-34
arch/arm/mach-at91/pm_suspend.S
+77
-34
arch/arm/mach-at91/pm_suspend.S
···
51
51
.endm
52
52
53
53
/*
54
-
* Wait until PLLA has locked.
55
-
*/
56
-
.macro wait_pllalock
57
-
1: ldr tmp1, [pmc, #AT91_PMC_SR]
58
-
tst tmp1, #AT91_PMC_LOCKA
59
-
beq 1b
60
-
.endm
61
-
62
-
/*
63
54
* Put the processor to enter the idle state
64
55
*/
65
56
.macro at91_cpu_idle
···
169
178
orr tmp1, tmp1, #AT91_PMC_KEY
170
179
str tmp1, [pmc, #AT91_CKGR_MOR]
171
180
181
+
/* Save RC oscillator state */
182
+
ldr tmp1, [pmc, #AT91_PMC_SR]
183
+
str tmp1, .saved_osc_status
184
+
tst tmp1, #AT91_PMC_MOSCRCS
185
+
bne 1f
186
+
187
+
/* Turn off RC oscillator */
188
+
ldr tmp1, [pmc, #AT91_CKGR_MOR]
189
+
bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
190
+
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
191
+
orr tmp1, tmp1, #AT91_PMC_KEY
192
+
str tmp1, [pmc, #AT91_CKGR_MOR]
193
+
194
+
/* Wait main RC disabled done */
195
+
2: ldr tmp1, [pmc, #AT91_PMC_SR]
196
+
tst tmp1, #AT91_PMC_MOSCRCS
197
+
bne 2b
198
+
172
199
/* Wait for interrupt */
173
-
at91_cpu_idle
200
+
1: at91_cpu_idle
201
+
202
+
/* Restore RC oscillator state */
203
+
ldr tmp1, .saved_osc_status
204
+
tst tmp1, #AT91_PMC_MOSCRCS
205
+
beq 4f
206
+
207
+
/* Turn on RC oscillator */
208
+
ldr tmp1, [pmc, #AT91_CKGR_MOR]
209
+
orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
210
+
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
211
+
orr tmp1, tmp1, #AT91_PMC_KEY
212
+
str tmp1, [pmc, #AT91_CKGR_MOR]
213
+
214
+
/* Wait main RC stabilization */
215
+
3: ldr tmp1, [pmc, #AT91_PMC_SR]
216
+
tst tmp1, #AT91_PMC_MOSCRCS
217
+
beq 3b
174
218
175
219
/* Turn on the crystal oscillator */
176
-
ldr tmp1, [pmc, #AT91_CKGR_MOR]
220
+
4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
177
221
orr tmp1, tmp1, #AT91_PMC_MOSCEN
178
222
orr tmp1, tmp1, #AT91_PMC_KEY
179
223
str tmp1, [pmc, #AT91_CKGR_MOR]
···
223
197
.macro at91_pm_ulp1_mode
224
198
ldr pmc, .pmc_base
225
199
226
-
/* Switch the main clock source to 12-MHz RC oscillator */
200
+
/* Save RC oscillator state and check if it is enabled. */
201
+
ldr tmp1, [pmc, #AT91_PMC_SR]
202
+
str tmp1, .saved_osc_status
203
+
tst tmp1, #AT91_PMC_MOSCRCS
204
+
bne 2f
205
+
206
+
/* Enable RC oscillator */
227
207
ldr tmp1, [pmc, #AT91_CKGR_MOR]
208
+
orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
209
+
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
210
+
orr tmp1, tmp1, #AT91_PMC_KEY
211
+
str tmp1, [pmc, #AT91_CKGR_MOR]
212
+
213
+
/* Wait main RC stabilization */
214
+
1: ldr tmp1, [pmc, #AT91_PMC_SR]
215
+
tst tmp1, #AT91_PMC_MOSCRCS
216
+
beq 1b
217
+
218
+
/* Switch the main clock source to 12-MHz RC oscillator */
219
+
2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
228
220
bic tmp1, tmp1, #AT91_PMC_MOSCSEL
229
221
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
230
222
orr tmp1, tmp1, #AT91_PMC_KEY
···
306
262
str tmp1, [pmc, #AT91_PMC_MCKR]
307
263
308
264
wait_mckrdy
265
+
266
+
/* Restore RC oscillator state */
267
+
ldr tmp1, .saved_osc_status
268
+
tst tmp1, #AT91_PMC_MOSCRCS
269
+
bne 3f
270
+
271
+
/* Disable RC oscillator */
272
+
ldr tmp1, [pmc, #AT91_CKGR_MOR]
273
+
bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
274
+
bic tmp1, tmp1, #AT91_PMC_KEY_MASK
275
+
orr tmp1, tmp1, #AT91_PMC_KEY
276
+
str tmp1, [pmc, #AT91_CKGR_MOR]
277
+
278
+
/* Wait RC oscillator disable done */
279
+
4: ldr tmp1, [pmc, #AT91_PMC_SR]
280
+
tst tmp1, #AT91_PMC_MOSCRCS
281
+
bne 4b
282
+
283
+
3:
309
284
.endm
310
285
311
286
ENTRY(at91_ulp_mode)
···
342
279
343
280
wait_mckrdy
344
281
345
-
/* Save PLLA setting and disable it */
346
-
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
347
-
str tmp1, .saved_pllar
348
-
349
-
mov tmp1, #AT91_PMC_PLLCOUNT
350
-
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
351
-
str tmp1, [pmc, #AT91_CKGR_PLLAR]
352
-
353
282
ldr r0, .pm_mode
354
283
cmp r0, #AT91_PM_ULP1
355
284
beq ulp1_mode
···
355
300
356
301
ulp_exit:
357
302
ldr pmc, .pmc_base
358
-
359
-
/* Restore PLLA setting */
360
-
ldr tmp1, .saved_pllar
361
-
str tmp1, [pmc, #AT91_CKGR_PLLAR]
362
-
363
-
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
364
-
bne 3f
365
-
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
366
-
beq 4f
367
-
3:
368
-
wait_pllalock
369
-
4:
370
303
371
304
/*
372
305
* Restore master clock setting
···
508
465
.word 0
509
466
.saved_mckr:
510
467
.word 0
511
-
.saved_pllar:
512
-
.word 0
513
468
.saved_sam9_lpr:
514
469
.word 0
515
470
.saved_sam9_lpr1:
···
515
474
.saved_sam9_mdr:
516
475
.word 0
517
476
.saved_sam9_mdr1:
477
+
.word 0
478
+
.saved_osc_status:
518
479
.word 0
519
480
520
481
ENTRY(at91_pm_suspend_in_sram_sz)
-1
arch/arm/mach-ixp4xx/common.c
-1
arch/arm/mach-ixp4xx/common.c
-1
arch/arm/mach-mvebu/board-v7.c
-1
arch/arm/mach-mvebu/board-v7.c
+1
-1
arch/arm/mach-mvebu/coherency_ll.S
+1
-1
arch/arm/mach-mvebu/coherency_ll.S
-2
arch/arm/mach-mvebu/kirkwood.c
-2
arch/arm/mach-mvebu/kirkwood.c
+8
-3
arch/arm/mach-mvebu/pm-board.c
+8
-3
arch/arm/mach-mvebu/pm-board.c
···
79
79
static int __init mvebu_armada_pm_init(void)
80
80
{
81
81
struct device_node *np;
82
-
struct device_node *gpio_ctrl_np;
82
+
struct device_node *gpio_ctrl_np = NULL;
83
83
int ret = 0, i;
84
84
85
85
if (!of_machine_is_compatible("marvell,axp-gp"))
···
126
126
goto out;
127
127
}
128
128
129
+
if (gpio_ctrl_np)
130
+
of_node_put(gpio_ctrl_np);
129
131
gpio_ctrl_np = args.np;
130
132
pic_raw_gpios[i] = args.args[0];
131
133
}
132
134
133
135
gpio_ctrl = of_iomap(gpio_ctrl_np, 0);
134
-
if (!gpio_ctrl)
135
-
return -ENOMEM;
136
+
if (!gpio_ctrl) {
137
+
ret = -ENOMEM;
138
+
goto out;
139
+
}
136
140
137
141
mvebu_pm_suspend_init(mvebu_armada_pm_enter);
138
142
139
143
out:
140
144
of_node_put(np);
145
+
of_node_put(gpio_ctrl_np);
141
146
return ret;
142
147
}
143
148
+1
-2
arch/arm/mach-mvebu/pmsu_ll.S
+1
-2
arch/arm/mach-mvebu/pmsu_ll.S
···
16
16
ENTRY(armada_38x_scu_power_up)
17
17
mrc p15, 4, r1, c15, c0 @ get SCU base address
18
18
orr r1, r1, #0x8 @ SCU CPU Power Status Register
19
-
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
19
+
mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
20
20
and r0, r0, #15
21
21
add r1, r1, r0
22
22
mov r0, #0x0
···
56
56
57
57
/* The following code will be executed from SRAM */
58
58
ENTRY(mvebu_boot_wa_start)
59
-
mvebu_boot_wa_start:
60
59
ARM_BE8(setend be)
61
60
adr r0, 1f
62
61
ldr r0, [r0] @ load the address of the
+1
-1
arch/arm/mach-omap1/board-ams-delta.c
+1
-1
arch/arm/mach-omap1/board-ams-delta.c
···
749
749
ARRAY_SIZE(ams_delta_gpio_tables));
750
750
751
751
leds_pdev = gpio_led_register_device(PLATFORM_DEVID_NONE, &leds_pdata);
752
-
if (!IS_ERR(leds_pdev)) {
752
+
if (!IS_ERR_OR_NULL(leds_pdev)) {
753
753
leds_gpio_table.dev_id = dev_name(&leds_pdev->dev);
754
754
gpiod_add_lookup_table(&leds_gpio_table);
755
755
}
+1
arch/arm64/Kconfig.platforms
+1
arch/arm64/Kconfig.platforms
+2
-2
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+2
-2
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
···
59
59
};
60
60
61
61
padctl@3520000 {
62
-
status = "okay";
62
+
status = "disabled";
63
63
64
64
avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
65
65
avdd-usb-supply = <&vdd_3v3_sys>;
···
137
137
};
138
138
139
139
usb@3530000 {
140
-
status = "okay";
140
+
status = "disabled";
141
141
142
142
phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
143
143
<&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+7
arch/arm64/boot/dts/nvidia/tegra186.dtsi
+7
arch/arm64/boot/dts/nvidia/tegra186.dtsi
···
60
60
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61
61
resets = <&bpmp TEGRA186_RESET_EQOS>;
62
62
reset-names = "eqos";
63
+
iommus = <&smmu TEGRA186_SID_EQOS>;
63
64
status = "disabled";
64
65
65
66
snps,write-requests = <1>;
···
339
338
<&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
340
339
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
341
340
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
341
+
iommus = <&smmu TEGRA186_SID_HDA>;
342
342
status = "disabled";
343
343
};
344
344
···
672
670
<&bpmp TEGRA186_RESET_PCIE>,
673
671
<&bpmp TEGRA186_RESET_PCIEXCLK>;
674
672
reset-names = "afi", "pex", "pcie_x";
673
+
674
+
iommus = <&smmu TEGRA186_SID_AFI>;
675
+
iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
676
+
iommu-map-mask = <0x0>;
675
677
676
678
status = "disabled";
677
679
···
1164
1158
1165
1159
bpmp: bpmp {
1166
1160
compatible = "nvidia,tegra186-bpmp";
1161
+
iommus = <&smmu TEGRA186_SID_BPMP>;
1167
1162
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1168
1163
TEGRA_HSP_DB_MASTER_BPMP>;
1169
1164
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+12
-4
arch/arm64/boot/dts/sprd/whale2.dtsi
+12
-4
arch/arm64/boot/dts/sprd/whale2.dtsi
···
75
75
"sprd,sc9836-uart";
76
76
reg = <0x0 0x100>;
77
77
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
78
-
clocks = <&ext_26m>;
78
+
clock-names = "enable", "uart", "source";
79
+
clocks = <&apapb_gate CLK_UART0_EB>,
80
+
<&ap_clk CLK_UART0>, <&ext_26m>;
79
81
status = "disabled";
80
82
};
81
83
···
86
84
"sprd,sc9836-uart";
87
85
reg = <0x100000 0x100>;
88
86
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
89
-
clocks = <&ext_26m>;
87
+
clock-names = "enable", "uart", "source";
88
+
clocks = <&apapb_gate CLK_UART1_EB>,
89
+
<&ap_clk CLK_UART1>, <&ext_26m>;
90
90
status = "disabled";
91
91
};
92
92
···
97
93
"sprd,sc9836-uart";
98
94
reg = <0x200000 0x100>;
99
95
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
100
-
clocks = <&ext_26m>;
96
+
clock-names = "enable", "uart", "source";
97
+
clocks = <&apapb_gate CLK_UART2_EB>,
98
+
<&ap_clk CLK_UART2>, <&ext_26m>;
101
99
status = "disabled";
102
100
};
103
101
···
108
102
"sprd,sc9836-uart";
109
103
reg = <0x300000 0x100>;
110
104
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
111
-
clocks = <&ext_26m>;
105
+
clock-names = "enable", "uart", "source";
106
+
clocks = <&apapb_gate CLK_UART3_EB>,
107
+
<&ap_clk CLK_UART3>, <&ext_26m>;
112
108
status = "disabled";
113
109
};
114
110
};
+2
-4
drivers/amba/tegra-ahb.c
+2
-4
drivers/amba/tegra-ahb.c
···
170
170
EXPORT_SYMBOL(tegra_ahb_enable_smmu);
171
171
#endif
172
172
173
-
#ifdef CONFIG_PM
174
-
static int tegra_ahb_suspend(struct device *dev)
173
+
static int __maybe_unused tegra_ahb_suspend(struct device *dev)
175
174
{
176
175
int i;
177
176
struct tegra_ahb *ahb = dev_get_drvdata(dev);
···
180
181
return 0;
181
182
}
182
183
183
-
static int tegra_ahb_resume(struct device *dev)
184
+
static int __maybe_unused tegra_ahb_resume(struct device *dev)
184
185
{
185
186
int i;
186
187
struct tegra_ahb *ahb = dev_get_drvdata(dev);
···
189
190
gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
190
191
return 0;
191
192
}
192
-
#endif
193
193
194
194
static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
195
195
tegra_ahb_suspend,
+3
-1
drivers/soc/fsl/qe/gpio.c
+3
-1
drivers/soc/fsl/qe/gpio.c
···
179
179
if (err < 0)
180
180
goto err0;
181
181
gc = gpio_to_chip(err);
182
-
if (WARN_ON(!gc))
182
+
if (WARN_ON(!gc)) {
183
+
err = -ENODEV;
183
184
goto err0;
185
+
}
184
186
185
187
if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
186
188
pr_debug("%s: tried to get a non-qe pin\n", __func__);
+2
-2
drivers/soc/ixp4xx/ixp4xx-qmgr.c
+2
-2
drivers/soc/ixp4xx/ixp4xx-qmgr.c
+1
include/linux/clk/at91_pmc.h
+1
include/linux/clk/at91_pmc.h
···
161
161
162
162
#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */
163
163
#define AT91_PMC_FSTT(n) BIT(n)
164
+
#define AT91_PMC_RTTAL BIT(16)
164
165
#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */
165
166
#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */
166
167
#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */