Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Documentation/gpu/amdgpu: Add programming model for DCN
One of the challenges to contributing to the display code is the
complexity of the DC component. This commit adds a documentation page
that discusses the programming model used by DCN and an overview of how
the display code is organized.
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Christian Konig <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rodrigo Siqueira
and committed by
Alex Deucher
4c5d0fc5
dec36b22
+1630
+731
Documentation/gpu/amdgpu/display/dc-arch-overview.svg
+731
Documentation/gpu/amdgpu/display/dc-arch-overview.svg
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+2
Documentation/gpu/amdgpu/display/dcn-blocks.rst
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Documentation/gpu/amdgpu/display/dcn-blocks.rst
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Documentation/gpu/amdgpu/display/dcn-overview.rst
+2
Documentation/gpu/amdgpu/display/dcn-overview.rst
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Documentation/gpu/amdgpu/display/index.rst
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Documentation/gpu/amdgpu/display/index.rst
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Documentation/gpu/amdgpu/display/programming-model-dcn.rst
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Documentation/gpu/amdgpu/display/programming-model-dcn.rst
···
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====================
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DC Programming Model
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====================
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In the :ref:`Display Core Next (DCN) <dcn_overview>` and :ref:`DCN Block
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<dcn_blocks>` pages, you learned about the hardware components and how they
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interact with each other. On this page, the focus is shifted to the display
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code architecture. Hence, it is reasonable to remind the reader that the code
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in DC is shared with other OSes; for this reason, DC provides a set of
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abstractions and operations to connect different APIs with the hardware
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configuration. See DC as a service available for a Display Manager (amdgpu_dm)
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to access and configure DCN/DCE hardware (DCE is also part of DC, but for
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simplicity's sake, this documentation only examines DCN).
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.. note::
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For this page, we will use the term GPU to refers to dGPU and APU.
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Overview
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========
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From the display hardware perspective, it is plausible to expect that if a
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problem is well-defined, it will probably be implemented at the hardware level.
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On the other hand, when there are multiple ways of achieving something without
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a very well-defined scope, the solution is usually implemented as a policy at
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the DC level. In other words, some policies are defined in the DC core
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(resource management, power optimization, image quality, etc.), and the others
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implemented in hardware are enabled via DC configuration.
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In terms of hardware management, DCN has multiple instances of the same block
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(e.g., HUBP, DPP, MPC, etc), and during the driver execution, it might be
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necessary to use some of these instances. The core has policies in place for
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handling those instances. Regarding resource management, the DC objective is
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quite simple: minimize the hardware shuffle when the driver performs some
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actions. When the state changes from A to B, the transition is considered
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easier to maneuver if the hardware resource is still used for the same set of
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driver objects. Usually, adding and removing a resource to a `pipe_ctx` (more
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details below) is not a problem; however, moving a resource from one `pipe_ctx`
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to another should be avoided.
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Another area of influence for DC is power optimization, which has a myriad of
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arrangement possibilities. In some way, just displaying an image via DCN should
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be relatively straightforward; however, showing it with the best power
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footprint is more desirable, but it has many associated challenges.
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Unfortunately, there is no straight-forward analytic way to determine if a
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configuration is the best one for the context due to the enormous variety of
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variables related to this problem (e.g., many different DCN/DCE hardware
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versions, different displays configurations, etc.) for this reason DC
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implements a dedicated library for trying some configuration and verify if it
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is possible to support it or not. This type of policy is extremely complex to
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create and maintain, and amdgpu driver relies on Display Mode Library (DML) to
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generate the best decisions.
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In summary, DC must deal with the complexity of handling multiple scenarios and
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determine policies to manage them. All of the above information is conveyed to
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give the reader some idea about the complexity of driving a display from the
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driver's perspective. This page hopes to allow the reader to better navigate
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over the amdgpu display code.
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Display Driver Architecture Overview
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====================================
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The diagram below provides an overview of the display driver architecture;
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notice it illustrates the software layers adopted by DC:
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.. kernel-figure:: dc-components.svg
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The first layer of the diagram is the high-level DC API represented by the
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`dc.h` file; below it are two big blocks represented by Core and Link. Next is
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the hardware configuration block; the main file describing it is
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the`hw_sequencer.h`, where the implementation of the callbacks can be found in
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the hardware sequencer folder. Almost at the end, you can see the block level
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API (`dc/inc/hw`), which represents each DCN low-level block, such as HUBP,
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DPP, MPC, OPTC, etc. Notice on the left side of the diagram that we have a
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different set of layers representing the interaction with the DMUB
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microcontroller.
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+
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Basic Objects
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-------------
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The below diagram outlines the basic display objects. In particular, pay
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attention to the names in the boxes since they represent a data structure in
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the driver:
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.. kernel-figure:: dc-arch-overview.svg
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Let's start with the central block in the image, `dc`. The `dc` struct is
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initialized per GPU; for example, one GPU has one `dc` instance, two GPUs have
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two `dc` instances, and so forth. In other words we have one 'dc' per 'amdgpu'
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instance. In some ways, this object behaves like the `Singleton` pattern.
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After the `dc` block in the diagram, you can see the `dc_link` component, which
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is a low-level abstraction for the connector. One interesting aspect of the
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image is that connectors are not part of the DCN block; they are defined by the
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platform/board and not by the SoC. The `dc_link` struct is the high-level data
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container with information such as connected sinks, connection status, signal
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types, etc. After `dc_link`, there is the `dc_sink`, which is the object that
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represents the connected display.
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+
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.. note::
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For historical reasons, we used the name `dc_link`, which gives the
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+
wrong impression that this abstraction only deals with physical connections
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that the developer can easily manipulate. However, this also covers
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conections like eDP or cases where the output is connected to other devices.
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There are two structs that are not represented in the diagram since they were
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elaborated in the DCN overview page (check the DCN block diagram :ref:`Display
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Core Next (DCN) <dcn_overview>`); still, it is worth bringing back for this
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overview which is `dc_stream` and `dc_state`. The `dc_stream` stores many
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properties associated with the data transmission, but most importantly, it
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represents the data flow from the connector to the display. Next we have
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`dc_state`, which represents the logic state within the hardware at the moment;
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`dc_state` is composed of `dc_stream` and `dc_plane`. The `dc_stream` is the DC
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+
version of `drm_crtc` and represents the post-blending pipeline.
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+
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Speaking of the `dc_plane` data structure (first part of the diagram), you can
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+
think about it as an abstraction similar to `drm_plane` that represents the
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+
pre-blending portion of the pipeline. This image was probably processed by GFX
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and is ready to be composited under a `dc_stream`. Normally, the driver may
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+
have one or more `dc_plane` connected to the same `dc_stream`, which defines a
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composition at the DC level.
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+
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+
Basic Operations
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+
----------------
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+
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Now that we have covered the basic objects, it is time to examine some of the
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basic hardware/software operations. Let's start with the `dc_create()`
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function, which directly works with the `dc` data struct; this function behaves
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+
like a constructor responsible for the basic software initialization and
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+
preparing for enabling other parts of the API. It is important to highlight
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+
that this operation does not touch any hardware configuration; it is only a
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+
software initialization.
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+
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Next, we have the `dc_hardware_init()`, which also relies on the `dc` data
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+
struct. Its main function is to put the hardware in a valid state. It is worth
135
+
highlighting that the hardware might initialize in an unknown state, and it is
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+
a requirement to put it in a valid state; this function has multiple callbacks
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+
for the hardware-specific initialization, whereas `dc_hardware_init` does the
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+
hardware initialization and is the first point where we touch hardware.
139
+
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+
The `dc_get_link_at_index` is an operation that depends on the `dc_link` data
141
+
structure. This function retrieves and enumerates all the `dc_links` available
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+
on the device; this is required since this information is not part of the SoC
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+
definition but depends on the board configuration. As soon as the `dc_link` is
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+
initialized, it is useful to figure out if any of them are already connected to
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+
the display by using the `dc_link_detect()` function. After the driver figures
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+
out if any display is connected to the device, the challenging phase starts:
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+
configuring the monitor to show something. Nonetheless, dealing with the ideal
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+
configuration is not a DC task since this is the Display Manager (`amdgpu_dm`)
149
+
responsibility which in turn is responsible for dealing with the atomic
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+
commits. The only interface DC provides to the configuration phase is the
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+
function `dc_validate_with_context` that receives the configuration information
152
+
and, based on that, validates whether the hardware can support it or not. It is
153
+
important to add that even if the display supports some specific configuration,
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+
it does not mean the DCN hardware can support it.
155
+
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+
After the DM and DC agree upon the configuration, the stream configuration
157
+
phase starts. This task activates one or more `dc_stream` at this phase, and in
158
+
the best-case scenario, you might be able to turn the display on with a black
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+
screen (it does not show anything yet since it does not have any plane
160
+
associated with it). The final step would be to call the
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+
`dc_update_planes_and_stream,` which will add or remove planes.
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+