Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'for-3.16-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata fixes from Tejun Heo:
"Nothing too interesting. All fixes are ahci_platform related"
* 'for-3.16-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
ahci_xgene: fix the dma state machine lockup for the IDENTIFY DEVICE PIO mode command.
libahci: export ahci_qc_issue() and ahci_start_fix_rx()
ata: ahci_imx: warn when disabling ahci link
ahci: disable ncq feature for hisilicon sata
ahci: imx: manage only sata_ref_clk in imx_sata_enable[disable]
libahci_platform: Fail when PHY required but PHY support disabled
+94
-22
+2
drivers/ata/ahci.h
+2
drivers/ata/ahci.h
···
371
371
int pmp, unsigned long deadline,
372
372
int (*check_ready)(struct ata_link *link));
373
373
374
+
unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
374
375
int ahci_stop_engine(struct ata_port *ap);
376
+
void ahci_start_fis_rx(struct ata_port *ap);
375
377
void ahci_start_engine(struct ata_port *ap);
376
378
int ahci_check_ready(struct ata_link *link);
377
379
int ahci_kick_engine(struct ata_port *ap);
+34
-4
drivers/ata/ahci_imx.c
+34
-4
drivers/ata/ahci_imx.c
···
58
58
struct imx_ahci_priv {
59
59
struct platform_device *ahci_pdev;
60
60
enum ahci_imx_type type;
61
+
struct clk *sata_clk;
62
+
struct clk *sata_ref_clk;
61
63
struct clk *ahb_clk;
62
64
struct regmap *gpr;
63
65
bool no_device;
···
226
224
return ret;
227
225
}
228
226
229
-
ret = ahci_platform_enable_clks(hpriv);
227
+
ret = clk_prepare_enable(imxpriv->sata_ref_clk);
230
228
if (ret < 0)
231
229
goto disable_regulator;
232
230
···
293
291
!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
294
292
}
295
293
296
-
ahci_platform_disable_clks(hpriv);
294
+
clk_disable_unprepare(imxpriv->sata_ref_clk);
297
295
298
296
if (hpriv->target_pwr)
299
297
regulator_disable(hpriv->target_pwr);
···
326
324
writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
327
325
imx_sata_disable(hpriv);
328
326
imxpriv->no_device = true;
327
+
328
+
dev_info(ap->dev, "no device found, disabling link.\n");
329
+
dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
329
330
}
330
331
331
332
static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
···
390
385
imxpriv->no_device = false;
391
386
imxpriv->first_time = true;
392
387
imxpriv->type = (enum ahci_imx_type)of_id->data;
388
+
389
+
imxpriv->sata_clk = devm_clk_get(dev, "sata");
390
+
if (IS_ERR(imxpriv->sata_clk)) {
391
+
dev_err(dev, "can't get sata clock.\n");
392
+
return PTR_ERR(imxpriv->sata_clk);
393
+
}
394
+
395
+
imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
396
+
if (IS_ERR(imxpriv->sata_ref_clk)) {
397
+
dev_err(dev, "can't get sata_ref clock.\n");
398
+
return PTR_ERR(imxpriv->sata_ref_clk);
399
+
}
400
+
393
401
imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
394
402
if (IS_ERR(imxpriv->ahb_clk)) {
395
403
dev_err(dev, "can't get ahb clock.\n");
···
425
407
426
408
hpriv->plat_data = imxpriv;
427
409
428
-
ret = imx_sata_enable(hpriv);
410
+
ret = clk_prepare_enable(imxpriv->sata_clk);
429
411
if (ret)
430
412
return ret;
413
+
414
+
ret = imx_sata_enable(hpriv);
415
+
if (ret)
416
+
goto disable_clk;
431
417
432
418
/*
433
419
* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
···
457
435
ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
458
436
0, 0, 0);
459
437
if (ret)
460
-
imx_sata_disable(hpriv);
438
+
goto disable_sata;
461
439
440
+
return 0;
441
+
442
+
disable_sata:
443
+
imx_sata_disable(hpriv);
444
+
disable_clk:
445
+
clk_disable_unprepare(imxpriv->sata_clk);
462
446
return ret;
463
447
}
464
448
465
449
static void ahci_imx_host_stop(struct ata_host *host)
466
450
{
467
451
struct ahci_host_priv *hpriv = host->private_data;
452
+
struct imx_ahci_priv *imxpriv = hpriv->plat_data;
468
453
469
454
imx_sata_disable(hpriv);
455
+
clk_disable_unprepare(imxpriv->sata_clk);
470
456
}
471
457
472
458
#ifdef CONFIG_PM_SLEEP
+1
-1
drivers/ata/ahci_platform.c
+1
-1
drivers/ata/ahci_platform.c
+47
-13
drivers/ata/ahci_xgene.c
+47
-13
drivers/ata/ahci_xgene.c
···
78
78
struct xgene_ahci_context {
79
79
struct ahci_host_priv *hpriv;
80
80
struct device *dev;
81
+
u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
81
82
void __iomem *csr_core; /* Core CSR address of IP */
82
83
void __iomem *csr_diag; /* Diag CSR address of IP */
83
84
void __iomem *csr_axi; /* AXI CSR address of IP */
···
99
98
}
100
99
101
100
/**
101
+
* xgene_ahci_restart_engine - Restart the dma engine.
102
+
* @ap : ATA port of interest
103
+
*
104
+
* Restarts the dma engine inside the controller.
105
+
*/
106
+
static int xgene_ahci_restart_engine(struct ata_port *ap)
107
+
{
108
+
struct ahci_host_priv *hpriv = ap->host->private_data;
109
+
110
+
ahci_stop_engine(ap);
111
+
ahci_start_fis_rx(ap);
112
+
hpriv->start_engine(ap);
113
+
114
+
return 0;
115
+
}
116
+
117
+
/**
118
+
* xgene_ahci_qc_issue - Issue commands to the device
119
+
* @qc: Command to issue
120
+
*
121
+
* Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot
122
+
* clear the BSY bit after receiving the PIO setup FIS. This results in the dma
123
+
* state machine goes into the CMFatalErrorUpdate state and locks up. By
124
+
* restarting the dma engine, it removes the controller out of lock up state.
125
+
*/
126
+
static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
127
+
{
128
+
struct ata_port *ap = qc->ap;
129
+
struct ahci_host_priv *hpriv = ap->host->private_data;
130
+
struct xgene_ahci_context *ctx = hpriv->plat_data;
131
+
int rc = 0;
132
+
133
+
if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA))
134
+
xgene_ahci_restart_engine(ap);
135
+
136
+
rc = ahci_qc_issue(qc);
137
+
138
+
/* Save the last command issued */
139
+
ctx->last_cmd[ap->port_no] = qc->tf.command;
140
+
141
+
return rc;
142
+
}
143
+
144
+
/**
102
145
* xgene_ahci_read_id - Read ID data from the specified device
103
146
* @dev: device
104
147
* @tf: proposed taskfile
105
148
* @id: data buffer
106
149
*
107
150
* This custom read ID function is required due to the fact that the HW
108
-
* does not support DEVSLP and the controller state machine may get stuck
109
-
* after processing the ID query command.
151
+
* does not support DEVSLP.
110
152
*/
111
153
static unsigned int xgene_ahci_read_id(struct ata_device *dev,
112
154
struct ata_taskfile *tf, u16 *id)
113
155
{
114
156
u32 err_mask;
115
-
void __iomem *port_mmio = ahci_port_base(dev->link->ap);
116
157
117
158
err_mask = ata_do_dev_read_id(dev, tf, id);
118
159
if (err_mask)
···
176
133
*/
177
134
id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8);
178
135
179
-
/*
180
-
* Due to HW errata, restart the port if no other command active.
181
-
* Otherwise the controller may get stuck.
182
-
*/
183
-
if (!readl(port_mmio + PORT_CMD_ISSUE)) {
184
-
writel(PORT_CMD_FIS_RX, port_mmio + PORT_CMD);
185
-
readl(port_mmio + PORT_CMD); /* Force a barrier */
186
-
writel(PORT_CMD_FIS_RX | PORT_CMD_START, port_mmio + PORT_CMD);
187
-
readl(port_mmio + PORT_CMD); /* Force a barrier */
188
-
}
189
136
return 0;
190
137
}
191
138
···
333
300
.host_stop = xgene_ahci_host_stop,
334
301
.hardreset = xgene_ahci_hardreset,
335
302
.read_id = xgene_ahci_read_id,
303
+
.qc_issue = xgene_ahci_qc_issue,
336
304
};
337
305
338
306
static const struct ata_port_info xgene_ahci_port_info = {
+4
-3
drivers/ata/libahci.c
+4
-3
drivers/ata/libahci.c
···
68
68
69
69
static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70
70
static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71
-
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72
71
static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73
72
static int ahci_port_start(struct ata_port *ap);
74
73
static void ahci_port_stop(struct ata_port *ap);
···
619
620
}
620
621
EXPORT_SYMBOL_GPL(ahci_stop_engine);
621
622
622
-
static void ahci_start_fis_rx(struct ata_port *ap)
623
+
void ahci_start_fis_rx(struct ata_port *ap)
623
624
{
624
625
void __iomem *port_mmio = ahci_port_base(ap);
625
626
struct ahci_host_priv *hpriv = ap->host->private_data;
···
645
646
/* flush */
646
647
readl(port_mmio + PORT_CMD);
647
648
}
649
+
EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
648
650
649
651
static int ahci_stop_fis_rx(struct ata_port *ap)
650
652
{
···
1945
1945
}
1946
1946
EXPORT_SYMBOL_GPL(ahci_interrupt);
1947
1947
1948
-
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1948
+
unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1949
1949
{
1950
1950
struct ata_port *ap = qc->ap;
1951
1951
void __iomem *port_mmio = ahci_port_base(ap);
···
1974
1974
1975
1975
return 0;
1976
1976
}
1977
+
EXPORT_SYMBOL_GPL(ahci_qc_issue);
1977
1978
1978
1979
static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1979
1980
{
+6
-1
drivers/ata/libahci_platform.c
+6
-1
drivers/ata/libahci_platform.c
···
250
250
if (IS_ERR(hpriv->phy)) {
251
251
rc = PTR_ERR(hpriv->phy);
252
252
switch (rc) {
253
-
case -ENODEV:
254
253
case -ENOSYS:
254
+
/* No PHY support. Check if PHY is required. */
255
+
if (of_find_property(dev->of_node, "phys", NULL)) {
256
+
dev_err(dev, "couldn't get sata-phy: ENOSYS\n");
257
+
goto err_out;
258
+
}
259
+
case -ENODEV:
255
260
/* continue normally */
256
261
hpriv->phy = NULL;
257
262
break;