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drm/amd/pm/smu13: Remove unused smu_v3 functions

smu_v13_0_display_clock_voltage_request() and
smu_v13_0_set_min_deep_sleep_dcefclk() were added in 2020 by
commit c05d1c401572 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)")
but have remained unused.

Remove them.

smu_v13_0_display_clock_voltage_request() was the only user
of smu_v13_0_set_hard_freq_limited_range(). Remove it.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Dr. David Alan Gilbert and committed by
Alex Deucher 4c83d453 2c599d66

-113
-12
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
··· 184 184 185 185 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); 186 186 187 - int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); 188 - 189 - int 190 - smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 191 - struct pp_display_clock_request 192 - *clock_req); 193 - 194 187 uint32_t 195 188 smu_v13_0_get_fan_control_mode(struct smu_context *smu); 196 189 ··· 219 226 220 227 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 221 228 uint32_t min, uint32_t max, bool automatic); 222 - 223 - int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 224 - enum smu_clk_type clk_type, 225 - uint32_t min, 226 - uint32_t max); 227 229 228 230 int smu_v13_0_set_performance_level(struct smu_context *smu, 229 231 enum amd_dpm_forced_level level);
-101
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
··· 709 709 return ret; 710 710 } 711 711 712 - int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 713 - { 714 - int ret; 715 - 716 - ret = smu_cmn_send_smc_msg_with_param(smu, 717 - SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 718 - if (ret) 719 - dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!"); 720 - 721 - return ret; 722 - } 723 - 724 712 int smu_v13_0_set_driver_table_location(struct smu_context *smu) 725 713 { 726 714 struct smu_table *driver_table = &smu->smu_table.driver_table; ··· 1059 1071 1060 1072 return 0; 1061 1073 1062 - } 1063 - 1064 - int 1065 - smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 1066 - struct pp_display_clock_request 1067 - *clock_req) 1068 - { 1069 - enum amd_pp_clock_type clk_type = clock_req->clock_type; 1070 - int ret = 0; 1071 - enum smu_clk_type clk_select = 0; 1072 - uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1073 - 1074 - if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1075 - smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1076 - switch (clk_type) { 1077 - case amd_pp_dcef_clock: 1078 - clk_select = SMU_DCEFCLK; 1079 - break; 1080 - case amd_pp_disp_clock: 1081 - clk_select = SMU_DISPCLK; 1082 - break; 1083 - case amd_pp_pixel_clock: 1084 - clk_select = SMU_PIXCLK; 1085 - break; 1086 - case amd_pp_phy_clock: 1087 - clk_select = SMU_PHYCLK; 1088 - break; 1089 - case amd_pp_mem_clock: 1090 - clk_select = SMU_UCLK; 1091 - break; 1092 - default: 1093 - dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1094 - ret = -EINVAL; 1095 - break; 1096 - } 1097 - 1098 - if (ret) 1099 - goto failed; 1100 - 1101 - if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1102 - return 0; 1103 - 1104 - ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1105 - 1106 - if (clk_select == SMU_UCLK) 1107 - smu->hard_min_uclk_req_from_dal = clk_freq; 1108 - } 1109 - 1110 - failed: 1111 - return ret; 1112 1074 } 1113 1075 1114 1076 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu) ··· 1582 1644 } 1583 1645 1584 1646 out: 1585 - return ret; 1586 - } 1587 - 1588 - int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 1589 - enum smu_clk_type clk_type, 1590 - uint32_t min, 1591 - uint32_t max) 1592 - { 1593 - int ret = 0, clk_id = 0; 1594 - uint32_t param; 1595 - 1596 - if (min <= 0 && max <= 0) 1597 - return -EINVAL; 1598 - 1599 - if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1600 - return 0; 1601 - 1602 - clk_id = smu_cmn_to_asic_specific_index(smu, 1603 - CMN2ASIC_MAPPING_CLK, 1604 - clk_type); 1605 - if (clk_id < 0) 1606 - return clk_id; 1607 - 1608 - if (max > 0) { 1609 - param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1610 - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1611 - param, NULL); 1612 - if (ret) 1613 - return ret; 1614 - } 1615 - 1616 - if (min > 0) { 1617 - param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1618 - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1619 - param, NULL); 1620 - if (ret) 1621 - return ret; 1622 - } 1623 - 1624 1647 return ret; 1625 1648 } 1626 1649