Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/dp: Move intel_dp_training_pattern()
Move intel_dp_training_pattern() upwards to avoid the forward
declaration for the POST_LT_ADJ_REQ stuff.
Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250710201718.25310-6-ville.syrjala@linux.intel.com
+57
-57
+57
-57
drivers/gpu/drm/i915/display/intel_dp_link_training.c
+57
-57
drivers/gpu/drm/i915/display/intel_dp_link_training.c
···
766
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}
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}
768
768
769
+
/*
770
+
* Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
771
+
* for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
772
+
* 1.2 devices that support it, TPS2 otherwise.
773
+
*/
774
+
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
775
+
const struct intel_crtc_state *crtc_state,
776
+
enum drm_dp_phy dp_phy)
777
+
{
778
+
struct intel_display *display = to_intel_display(intel_dp);
779
+
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
780
+
781
+
/* UHBR+ use separate 128b/132b TPS2 */
782
+
if (intel_dp_is_uhbr(crtc_state))
783
+
return DP_TRAINING_PATTERN_2;
784
+
785
+
/*
786
+
* TPS4 support is mandatory for all downstream devices that
787
+
* support HBR3. There are no known eDP panels that support
788
+
* TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
789
+
* LTTPRs must support TPS4.
790
+
*/
791
+
source_tps4 = intel_dp_source_supports_tps4(display);
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+
sink_tps4 = dp_phy != DP_PHY_DPRX ||
793
+
drm_dp_tps4_supported(intel_dp->dpcd);
794
+
if (source_tps4 && sink_tps4) {
795
+
return DP_TRAINING_PATTERN_4;
796
+
} else if (crtc_state->port_clock == 810000) {
797
+
if (!source_tps4)
798
+
lt_dbg(intel_dp, dp_phy,
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+
"8.1 Gbps link rate without source TPS4 support\n");
800
+
if (!sink_tps4)
801
+
lt_dbg(intel_dp, dp_phy,
802
+
"8.1 Gbps link rate without sink TPS4 support\n");
803
+
}
804
+
805
+
/*
806
+
* TPS3 support is mandatory for downstream devices that
807
+
* support HBR2. However, not all sinks follow the spec.
808
+
*/
809
+
source_tps3 = intel_dp_source_supports_tps3(display);
810
+
sink_tps3 = dp_phy != DP_PHY_DPRX ||
811
+
drm_dp_tps3_supported(intel_dp->dpcd);
812
+
if (source_tps3 && sink_tps3) {
813
+
return DP_TRAINING_PATTERN_3;
814
+
} else if (crtc_state->port_clock >= 540000) {
815
+
if (!source_tps3)
816
+
lt_dbg(intel_dp, dp_phy,
817
+
">=5.4/6.48 Gbps link rate without source TPS3 support\n");
818
+
if (!sink_tps3)
819
+
lt_dbg(intel_dp, dp_phy,
820
+
">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
821
+
}
822
+
823
+
return DP_TRAINING_PATTERN_2;
824
+
}
825
+
769
826
static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
770
827
const struct intel_crtc_state *crtc_state,
771
828
u8 link_bw, u8 rate_select)
···
1012
955
max_cr_tries);
1013
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return false;
1015
-
}
1016
-
1017
-
/*
1018
-
* Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
1019
-
* for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
1020
-
* 1.2 devices that support it, TPS2 otherwise.
1021
-
*/
1022
-
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
1023
-
const struct intel_crtc_state *crtc_state,
1024
-
enum drm_dp_phy dp_phy)
1025
-
{
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-
struct intel_display *display = to_intel_display(intel_dp);
1027
-
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
1028
-
1029
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/* UHBR+ use separate 128b/132b TPS2 */
1030
-
if (intel_dp_is_uhbr(crtc_state))
1031
-
return DP_TRAINING_PATTERN_2;
1032
-
1033
-
/*
1034
-
* TPS4 support is mandatory for all downstream devices that
1035
-
* support HBR3. There are no known eDP panels that support
1036
-
* TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
1037
-
* LTTPRs must support TPS4.
1038
-
*/
1039
-
source_tps4 = intel_dp_source_supports_tps4(display);
1040
-
sink_tps4 = dp_phy != DP_PHY_DPRX ||
1041
-
drm_dp_tps4_supported(intel_dp->dpcd);
1042
-
if (source_tps4 && sink_tps4) {
1043
-
return DP_TRAINING_PATTERN_4;
1044
-
} else if (crtc_state->port_clock == 810000) {
1045
-
if (!source_tps4)
1046
-
lt_dbg(intel_dp, dp_phy,
1047
-
"8.1 Gbps link rate without source TPS4 support\n");
1048
-
if (!sink_tps4)
1049
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lt_dbg(intel_dp, dp_phy,
1050
-
"8.1 Gbps link rate without sink TPS4 support\n");
1051
-
}
1052
-
1053
-
/*
1054
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* TPS3 support is mandatory for downstream devices that
1055
-
* support HBR2. However, not all sinks follow the spec.
1056
-
*/
1057
-
source_tps3 = intel_dp_source_supports_tps3(display);
1058
-
sink_tps3 = dp_phy != DP_PHY_DPRX ||
1059
-
drm_dp_tps3_supported(intel_dp->dpcd);
1060
-
if (source_tps3 && sink_tps3) {
1061
-
return DP_TRAINING_PATTERN_3;
1062
-
} else if (crtc_state->port_clock >= 540000) {
1063
-
if (!source_tps3)
1064
-
lt_dbg(intel_dp, dp_phy,
1065
-
">=5.4/6.48 Gbps link rate without source TPS3 support\n");
1066
-
if (!sink_tps3)
1067
-
lt_dbg(intel_dp, dp_phy,
1068
-
">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
1069
-
}
1070
-
1071
-
return DP_TRAINING_PATTERN_2;
1072
958
}
1073
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1074
960
/*