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arm64: mpam: Add initial MPAM documentation

MPAM (Memory Partitioning and Monitoring) is now exposed to user-space via
resctrl. Add some documentation so the user knows what features to expect.

Reviewed-by: Zeng Heng <zengheng4@huawei.com>
Reviewed-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Tested-by: Gavin Shan <gshan@redhat.com>
Tested-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Tested-by: Jesse Chick <jessechick@os.amperecomputing.com>
Signed-off-by: James Morse <james.morse@arm.com>

authored by

Ben Horgan and committed by
James Morse 4ce0a2cc aeb8595a

+73
+1
Documentation/arch/arm64/index.rst
··· 23 23 memory 24 24 memory-tagging-extension 25 25 mops 26 + mpam 26 27 perf 27 28 pointer-authentication 28 29 ptdump
+72
Documentation/arch/arm64/mpam.rst
··· 1 + .. SPDX-License-Identifier: GPL-2.0 2 + 3 + ==== 4 + MPAM 5 + ==== 6 + 7 + What is MPAM 8 + ============ 9 + MPAM (Memory Partitioning and Monitoring) is a feature in the CPUs and memory 10 + system components such as the caches or memory controllers that allow memory 11 + traffic to be labelled, partitioned and monitored. 12 + 13 + Traffic is labelled by the CPU, based on the control or monitor group the 14 + current task is assigned to using resctrl. Partitioning policy can be set 15 + using the schemata file in resctrl, and monitor values read via resctrl. 16 + See Documentation/filesystems/resctrl.rst for more details. 17 + 18 + This allows tasks that share memory system resources, such as caches, to be 19 + isolated from each other according to the partitioning policy (so called noisy 20 + neighbours). 21 + 22 + Supported Platforms 23 + =================== 24 + Use of this feature requires CPU support, support in the memory system 25 + components, and a description from firmware of where the MPAM device controls 26 + are in the MMIO address space. (e.g. the 'MPAM' ACPI table). 27 + 28 + The MMIO device that provides MPAM controls/monitors for a memory system 29 + component is called a memory system component. (MSC). 30 + 31 + Because the user interface to MPAM is via resctrl, only MPAM features that are 32 + compatible with resctrl can be exposed to user-space. 33 + 34 + MSC are considered as a group based on the topology. MSC that correspond with 35 + the L3 cache are considered together, it is not possible to mix MSC between L2 36 + and L3 to 'cover' a resctrl schema. 37 + 38 + The supported features are: 39 + 40 + * Cache portion bitmap controls (CPOR) on the L2 or L3 caches. To expose 41 + CPOR at L2 or L3, every CPU must have a corresponding CPU cache at this 42 + level that also supports the feature. Mismatched big/little platforms are 43 + not supported as resctrl's controls would then also depend on task 44 + placement. 45 + 46 + * Memory bandwidth maximum controls (MBW_MAX) on or after the L3 cache. 47 + resctrl uses the L3 cache-id to identify where the memory bandwidth 48 + control is applied. For this reason the platform must have an L3 cache 49 + with cache-id's supplied by firmware. (It doesn't need to support MPAM.) 50 + 51 + To be exported as the 'MB' schema, the topology of the group of MSC chosen 52 + must match the topology of the L3 cache so that the cache-id's can be 53 + repainted. For example: Platforms with Memory bandwidth maximum controls 54 + on CPU-less NUMA nodes cannot expose the 'MB' schema to resctrl as these 55 + nodes do not have a corresponding L3 cache. If the memory bandwidth 56 + control is on the memory rather than the L3 then there must be a single 57 + global L3 as otherwise it is unknown which L3 the traffic came from. There 58 + must be no caches between the L3 and the memory so that the two ends of 59 + the path have equivalent traffic. 60 + 61 + When the MPAM driver finds multiple groups of MSC it can use for the 'MB' 62 + schema, it prefers the group closest to the L3 cache. 63 + 64 + * Cache Storage Usage (CSU) counters can expose the 'llc_occupancy' provided 65 + there is at least one CSU monitor on each MSC that makes up the L3 group. 66 + Exposing CSU counters from other caches or devices is not supported. 67 + 68 + Reporting Bugs 69 + ============== 70 + If you are not seeing the counters or controls you expect please share the 71 + debug messages produced when enabling dynamic debug and booting with: 72 + dyndbg="file mpam_resctrl.c +pl"