Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 5241/1: provide ioremap_wc()
[ARM] omap: fix virtual vs physical address space confusions
[ARM] remove unused #include <version.h>
[ARM] omap: fix build error in ohci-omap.c
[ARM] omap: fix gpio.c build error
+50
-13
+4
-1
arch/arm/include/asm/io.h
+4
-1
arch/arm/include/asm/io.h
···
61
61
#define MT_DEVICE_NONSHARED 1
62
62
#define MT_DEVICE_CACHED 2
63
63
#define MT_DEVICE_IXP2000 3
64
+
#define MT_DEVICE_WC 4
64
65
/*
65
-
* types 4 onwards can be found in asm/mach/map.h and are undefined
66
+
* types 5 onwards can be found in asm/mach/map.h and are undefined
66
67
* for ioremap
67
68
*/
68
69
···
216
215
#define ioremap(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE)
217
216
#define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE)
218
217
#define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED)
218
+
#define ioremap_wc(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_WC)
219
219
#define iounmap(cookie) __iounmap(cookie)
220
220
#else
221
221
#define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
222
222
#define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
223
223
#define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
224
+
#define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
224
225
#define iounmap(cookie) __arch_iounmap(cookie)
225
226
#endif
226
227
+7
-7
arch/arm/include/asm/mach/map.h
+7
-7
arch/arm/include/asm/mach/map.h
···
18
18
unsigned int type;
19
19
};
20
20
21
-
/* types 0-3 are defined in asm/io.h */
22
-
#define MT_CACHECLEAN 4
23
-
#define MT_MINICLEAN 5
24
-
#define MT_LOW_VECTORS 6
25
-
#define MT_HIGH_VECTORS 7
26
-
#define MT_MEMORY 8
27
-
#define MT_ROM 9
21
+
/* types 0-4 are defined in asm/io.h */
22
+
#define MT_CACHECLEAN 5
23
+
#define MT_MINICLEAN 6
24
+
#define MT_LOW_VECTORS 7
25
+
#define MT_HIGH_VECTORS 8
26
+
#define MT_MEMORY 9
27
+
#define MT_ROM 10
28
28
29
29
#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
30
30
#define MT_IXP2000_DEVICE MT_DEVICE_IXP2000
+8
arch/arm/mach-omap1/mcbsp.c
+8
arch/arm/mach-omap1/mcbsp.c
···
159
159
#ifdef CONFIG_ARCH_OMAP730
160
160
static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
161
161
{
162
+
.phys_base = OMAP730_MCBSP1_BASE,
162
163
.virt_base = io_p2v(OMAP730_MCBSP1_BASE),
163
164
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
164
165
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
···
168
167
.ops = &omap1_mcbsp_ops,
169
168
},
170
169
{
170
+
.phys_base = OMAP730_MCBSP2_BASE,
171
171
.virt_base = io_p2v(OMAP730_MCBSP2_BASE),
172
172
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
173
173
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
···
186
184
#ifdef CONFIG_ARCH_OMAP15XX
187
185
static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
188
186
{
187
+
.phys_base = OMAP1510_MCBSP1_BASE,
189
188
.virt_base = OMAP1510_MCBSP1_BASE,
190
189
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
191
190
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
···
196
193
.clk_name = "mcbsp_clk",
197
194
},
198
195
{
196
+
.phys_base = OMAP1510_MCBSP2_BASE,
199
197
.virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
200
198
.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
201
199
.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
···
205
201
.ops = &omap1_mcbsp_ops,
206
202
},
207
203
{
204
+
.phys_base = OMAP1510_MCBSP3_BASE,
208
205
.virt_base = OMAP1510_MCBSP3_BASE,
209
206
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
210
207
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
···
224
219
#ifdef CONFIG_ARCH_OMAP16XX
225
220
static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
226
221
{
222
+
.phys_base = OMAP1610_MCBSP1_BASE,
227
223
.virt_base = OMAP1610_MCBSP1_BASE,
228
224
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
229
225
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
···
234
228
.clk_name = "mcbsp_clk",
235
229
},
236
230
{
231
+
.phys_base = OMAP1610_MCBSP2_BASE,
237
232
.virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
238
233
.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
239
234
.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
···
243
236
.ops = &omap1_mcbsp_ops,
244
237
},
245
238
{
239
+
.phys_base = OMAP1610_MCBSP3_BASE,
246
240
.virt_base = OMAP1610_MCBSP3_BASE,
247
241
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
248
242
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+4
arch/arm/mach-omap2/mcbsp.c
+4
arch/arm/mach-omap2/mcbsp.c
···
134
134
#ifdef CONFIG_ARCH_OMAP24XX
135
135
static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
136
136
{
137
+
.phys_base = OMAP24XX_MCBSP1_BASE,
137
138
.virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
138
139
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
139
140
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
···
144
143
.clk_name = "mcbsp_clk",
145
144
},
146
145
{
146
+
.phys_base = OMAP24XX_MCBSP2_BASE,
147
147
.virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
148
148
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
149
149
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
···
163
161
#ifdef CONFIG_ARCH_OMAP34XX
164
162
static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
165
163
{
164
+
.phys_base = OMAP34XX_MCBSP1_BASE,
166
165
.virt_base = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
167
166
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
168
167
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
···
173
170
.clk_name = "mcbsp_clk",
174
171
},
175
172
{
173
+
.phys_base = OMAP34XX_MCBSP2_BASE,
176
174
.virt_base = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
177
175
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
178
176
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
+20
arch/arm/mm/mmu.c
+20
arch/arm/mm/mmu.c
···
211
211
PMD_SECT_TEX(1),
212
212
.domain = DOMAIN_IO,
213
213
},
214
+
[MT_DEVICE_WC] = { /* ioremap_wc */
215
+
.prot_pte = PROT_PTE_DEVICE,
216
+
.prot_l1 = PMD_TYPE_TABLE,
217
+
.prot_sect = PROT_SECT_DEVICE,
218
+
.domain = DOMAIN_IO,
219
+
},
214
220
[MT_CACHECLEAN] = {
215
221
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
216
222
.domain = DOMAIN_KERNEL,
···
276
270
if (cachepolicy >= CPOLICY_WRITEALLOC)
277
271
cachepolicy = CPOLICY_WRITEBACK;
278
272
ecc_mask = 0;
273
+
}
274
+
275
+
/*
276
+
* On non-Xscale3 ARMv5-and-older systems, use CB=01
277
+
* (Uncached/Buffered) for ioremap_wc() mappings. On XScale3
278
+
* and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable
279
+
* in xsc3 parlance, Uncached Normal in ARMv6 parlance).
280
+
*/
281
+
if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
282
+
mem_types[MT_DEVICE_WC].prot_pte_ext |= PTE_EXT_TEX(1);
283
+
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
284
+
} else {
285
+
mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_BUFFERABLE;
286
+
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
279
287
}
280
288
281
289
/*
-1
arch/arm/plat-mxc/clock.c
-1
arch/arm/plat-mxc/clock.c
+1
-1
arch/arm/plat-omap/gpio.c
+1
-1
arch/arm/plat-omap/gpio.c
+2
arch/arm/plat-omap/include/mach/mcbsp.h
+2
arch/arm/plat-omap/include/mach/mcbsp.h
···
315
315
};
316
316
317
317
struct omap_mcbsp_platform_data {
318
+
unsigned long phys_base;
318
319
u32 virt_base;
319
320
u8 dma_rx_sync, dma_tx_sync;
320
321
u16 rx_irq, tx_irq;
···
325
324
326
325
struct omap_mcbsp {
327
326
struct device *dev;
327
+
unsigned long phys_base;
328
328
u32 io_base;
329
329
u8 id;
330
330
u8 free;
+3
-2
arch/arm/plat-omap/mcbsp.c
+3
-2
arch/arm/plat-omap/mcbsp.c
···
651
651
omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
652
652
src_port,
653
653
OMAP_DMA_AMODE_CONSTANT,
654
-
mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
654
+
mcbsp[id].phys_base + OMAP_MCBSP_REG_DXR1,
655
655
0, 0);
656
656
657
657
omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
···
712
712
omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
713
713
src_port,
714
714
OMAP_DMA_AMODE_CONSTANT,
715
-
mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
715
+
mcbsp[id].phys_base + OMAP_MCBSP_REG_DRR1,
716
716
0, 0);
717
717
718
718
omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
···
830
830
mcbsp[id].dma_tx_lch = -1;
831
831
mcbsp[id].dma_rx_lch = -1;
832
832
833
+
mcbsp[id].phys_base = pdata->phys_base;
833
834
mcbsp[id].io_base = pdata->virt_base;
834
835
/* Default I/O is IRQ based */
835
836
mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;