tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:

- Enabling the FPU is now a static_key

- Improvements to the Svpbmt support

- CPU topology bindings for a handful of systems

- Support for systems with 64-bit hart IDs

- Many settings have been enabled in the defconfig, including both
support for the StarFive systems and many of the Docker requirements

There are also a handful of cleanups and improvements, as usual.

* tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits)
riscv: enable Docker requirements in defconfig
riscv: convert the t-head pbmt errata to use the __nops macro
riscv: introduce nops and __nops macros for NOP sequences
RISC-V: Add fast call path of crash_kexec()
riscv: mmap with PROT_WRITE but no PROT_READ is invalid
riscv/efi_stub: Add 64bit boot-hartid support on RV64
riscv: cpu: Add 64bit hartid support on RV64
riscv: smp: Add 64bit hartid support on RV64
riscv: spinwait: Fix hartid variable type
riscv: cpu_ops_sbi: Add 64bit hartid support on RV64
riscv: dts: sifive: "fix" pmic watchdog node name
riscv: dts: canaan: Add k210 topology information
riscv: dts: sifive: Add fu740 topology information
riscv: dts: sifive: Add fu540 topology information
riscv: dts: starfive: Add JH7100 CPU topology
RISC-V: Add CONFIG_{NON,}PORTABLE
riscv: config: enable SOC_STARFIVE in defconfig
riscv: dts: microchip: Add mpfs' topology information
riscv: Kconfig.socs: Add comments
riscv: Kconfig.erratas: Add comments
...

Linus Torvalds 4d1044fc ea0c3926

+359 -141
+35 -12
arch/riscv/Kconfig
··· 223 223 224 224 menu "Platform type" 225 225 226 + config NONPORTABLE 227 + bool "Allow configurations that result in non-portable kernels" 228 + help 229 + RISC-V kernel binaries are compatible between all known systems 230 + whenever possible, but there are some use cases that can only be 231 + satisfied by configurations that result in kernel binaries that are 232 + not portable between systems. 233 + 234 + Selecting N does not guarantee kernels will be portable to all known 235 + systems. Selecting any of the options guarded by NONPORTABLE will 236 + result in kernel binaries that are unlikely to be portable between 237 + systems. 238 + 239 + If unsure, say N. 240 + 226 241 choice 227 242 prompt "Base ISA" 228 243 default ARCH_RV64I ··· 247 232 248 233 config ARCH_RV32I 249 234 bool "RV32I" 235 + depends on NONPORTABLE 250 236 select 32BIT 251 237 select GENERIC_LIB_ASHLDI3 252 238 select GENERIC_LIB_ASHRDI3 ··· 368 352 bool "Emit compressed instructions when building Linux" 369 353 default y 370 354 help 371 - Adds "C" to the ISA subsets that the toolchain is allowed to emit 372 - when building Linux, which results in compressed instructions in the 373 - Linux binary. 355 + Adds "C" to the ISA subsets that the toolchain is allowed to emit 356 + when building Linux, which results in compressed instructions in the 357 + Linux binary. 374 358 375 - If you don't know what to do here, say Y. 359 + If you don't know what to do here, say Y. 376 360 377 361 config RISCV_ISA_SVPBMT 378 362 bool "SVPBMT extension support" ··· 401 385 402 386 If you don't know what to do here, say Y. 403 387 404 - endmenu 388 + endmenu # "Platform type" 405 389 406 390 menu "Kernel features" 407 391 ··· 490 474 491 475 If you want to execute 32-bit userspace applications, say Y. 492 476 493 - endmenu 477 + endmenu # "Kernel features" 494 478 495 479 menu "Boot options" 496 480 ··· 525 509 appended to the built-in command line. This is useful in 526 510 cases where the provided arguments are insufficient and 527 511 you don't want to or cannot modify them. 528 - 529 512 530 513 config CMDLINE_FORCE 531 514 bool "Always use the default kernel command string" ··· 568 553 569 554 config PHYS_RAM_BASE_FIXED 570 555 bool "Explicitly specified physical RAM address" 556 + depends on NONPORTABLE 571 557 default n 572 558 573 559 config PHYS_RAM_BASE ··· 582 566 583 567 config XIP_KERNEL 584 568 bool "Kernel Execute-In-Place from ROM" 585 - depends on MMU && SPARSEMEM 569 + depends on MMU && SPARSEMEM && NONPORTABLE 586 570 # This prevents XIP from being enabled by all{yes,mod}config, which 587 571 # fail to build since XIP doesn't support large kernels. 588 572 depends on !COMPILE_TEST ··· 618 602 be linked for and stored to. This address is dependent on your 619 603 own flash usage. 620 604 621 - endmenu 605 + endmenu # "Boot options" 622 606 623 607 config BUILTIN_DTB 624 608 bool 625 - depends on OF 609 + depends on OF && NONPORTABLE 626 610 default y if XIP_KERNEL 611 + 612 + config PORTABLE 613 + bool 614 + default !NONPORTABLE 615 + select EFI 616 + select OF 617 + select MMU 627 618 628 619 menu "Power management options" 629 620 630 621 source "kernel/power/Kconfig" 631 622 632 - endmenu 623 + endmenu # "Power management options" 633 624 634 625 menu "CPU Power Management" 635 626 636 627 source "drivers/cpuidle/Kconfig" 637 628 638 - endmenu 629 + endmenu # "CPU Power Management" 639 630 640 631 source "arch/riscv/kvm/Kconfig"
+1 -1
arch/riscv/Kconfig.erratas
··· 55 55 56 56 If you don't know what to do here, say "Y". 57 57 58 - endmenu 58 + endmenu # "CPU errata selection"
+2 -2
arch/riscv/Kconfig.socs
··· 78 78 for the DTS file that will be used to produce the DTB linked into the 79 79 kernel. 80 80 81 - endif 81 + endif # SOC_CANAAN 82 82 83 - endmenu 83 + endmenu # "SoC selection"
+12
arch/riscv/boot/dts/canaan/k210.dtsi
··· 65 65 compatible = "riscv,cpu-intc"; 66 66 }; 67 67 }; 68 + 69 + cpu-map { 70 + cluster0 { 71 + core0 { 72 + cpu = <&cpu0>; 73 + }; 74 + 75 + core1 { 76 + cpu = <&cpu1>; 77 + }; 78 + }; 79 + }; 68 80 }; 69 81 70 82 sram: memory@80000000 {
+24 -3
arch/riscv/boot/dts/microchip/mpfs.dtsi
··· 142 142 interrupt-controller; 143 143 }; 144 144 }; 145 + 146 + cpu-map { 147 + cluster0 { 148 + core0 { 149 + cpu = <&cpu0>; 150 + }; 151 + 152 + core1 { 153 + cpu = <&cpu1>; 154 + }; 155 + 156 + core2 { 157 + cpu = <&cpu2>; 158 + }; 159 + 160 + core3 { 161 + cpu = <&cpu3>; 162 + }; 163 + 164 + core4 { 165 + cpu = <&cpu4>; 166 + }; 167 + }; 168 + }; 145 169 }; 146 170 147 171 refclk: mssrefclk { ··· 315 291 interrupt-parent = <&plic>; 316 292 interrupts = <54>; 317 293 clocks = <&clkcfg CLK_SPI0>; 318 - spi-max-frequency = <25000000>; 319 294 status = "disabled"; 320 295 }; 321 296 ··· 326 303 interrupt-parent = <&plic>; 327 304 interrupts = <55>; 328 305 clocks = <&clkcfg CLK_SPI1>; 329 - spi-max-frequency = <25000000>; 330 306 status = "disabled"; 331 307 }; 332 308 ··· 337 315 interrupt-parent = <&plic>; 338 316 interrupts = <85>; 339 317 clocks = <&clkcfg CLK_QSPI>; 340 - spi-max-frequency = <25000000>; 341 318 status = "disabled"; 342 319 }; 343 320
+24
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
··· 133 133 interrupt-controller; 134 134 }; 135 135 }; 136 + 137 + cpu-map { 138 + cluster0 { 139 + core0 { 140 + cpu = <&cpu0>; 141 + }; 142 + 143 + core1 { 144 + cpu = <&cpu1>; 145 + }; 146 + 147 + core2 { 148 + cpu = <&cpu2>; 149 + }; 150 + 151 + core3 { 152 + cpu = <&cpu3>; 153 + }; 154 + 155 + core4 { 156 + cpu = <&cpu4>; 157 + }; 158 + }; 159 + }; 136 160 }; 137 161 soc { 138 162 #address-cells = <2>;
+24
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
··· 134 134 interrupt-controller; 135 135 }; 136 136 }; 137 + 138 + cpu-map { 139 + cluster0 { 140 + core0 { 141 + cpu = <&cpu0>; 142 + }; 143 + 144 + core1 { 145 + cpu = <&cpu1>; 146 + }; 147 + 148 + core2 { 149 + cpu = <&cpu2>; 150 + }; 151 + 152 + core3 { 153 + cpu = <&cpu3>; 154 + }; 155 + 156 + core4 { 157 + cpu = <&cpu4>; 158 + }; 159 + }; 160 + }; 137 161 }; 138 162 soc { 139 163 #address-cells = <2>;
+1 -1
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
··· 90 90 compatible = "dlg,da9063-rtc"; 91 91 }; 92 92 93 - wdt { 93 + watchdog { 94 94 compatible = "dlg,da9063-watchdog"; 95 95 }; 96 96
+14 -2
arch/riscv/boot/dts/starfive/jh7100.dtsi
··· 17 17 #address-cells = <1>; 18 18 #size-cells = <0>; 19 19 20 - cpu@0 { 20 + U74_0: cpu@0 { 21 21 compatible = "sifive,u74-mc", "riscv"; 22 22 reg = <0>; 23 23 d-cache-block-size = <64>; ··· 42 42 }; 43 43 }; 44 44 45 - cpu@1 { 45 + U74_1: cpu@1 { 46 46 compatible = "sifive,u74-mc", "riscv"; 47 47 reg = <1>; 48 48 d-cache-block-size = <64>; ··· 64 64 compatible = "riscv,cpu-intc"; 65 65 interrupt-controller; 66 66 #interrupt-cells = <1>; 67 + }; 68 + }; 69 + 70 + cpu-map { 71 + cluster0 { 72 + core0 { 73 + cpu = <&U74_0>; 74 + }; 75 + 76 + core1 { 77 + cpu = <&U74_1>; 78 + }; 67 79 }; 68 80 }; 69 81 };
+2
arch/riscv/configs/32-bit.config
··· 1 1 CONFIG_ARCH_RV32I=y 2 2 CONFIG_32BIT=y 3 + # CONFIG_PORTABLE is not set 4 + CONFIG_NONPORTABLE=y
+64 -1
arch/riscv/configs/defconfig
··· 6 6 CONFIG_IKCONFIG=y 7 7 CONFIG_IKCONFIG_PROC=y 8 8 CONFIG_CGROUPS=y 9 + CONFIG_MEMCG=y 9 10 CONFIG_CGROUP_SCHED=y 10 11 CONFIG_CFS_BANDWIDTH=y 12 + CONFIG_RT_GROUP_SCHED=y 13 + CONFIG_CGROUP_PIDS=y 14 + CONFIG_CGROUP_FREEZER=y 15 + CONFIG_CGROUP_HUGETLB=y 16 + CONFIG_CPUSETS=y 17 + CONFIG_CGROUP_DEVICE=y 18 + CONFIG_CGROUP_CPUACCT=y 19 + CONFIG_CGROUP_PERF=y 11 20 CONFIG_CGROUP_BPF=y 12 21 CONFIG_NAMESPACES=y 13 22 CONFIG_USER_NS=y ··· 27 18 CONFIG_PROFILING=y 28 19 CONFIG_SOC_MICROCHIP_POLARFIRE=y 29 20 CONFIG_SOC_SIFIVE=y 21 + CONFIG_SOC_STARFIVE=y 30 22 CONFIG_SOC_VIRT=y 31 23 CONFIG_SMP=y 32 24 CONFIG_HOTPLUG_CPU=y ··· 38 28 CONFIG_JUMP_LABEL=y 39 29 CONFIG_MODULES=y 40 30 CONFIG_MODULE_UNLOAD=y 31 + CONFIG_BLK_DEV_THROTTLING=y 41 32 CONFIG_NET=y 42 33 CONFIG_PACKET=y 43 34 CONFIG_UNIX=y 35 + CONFIG_XFRM_USER=m 44 36 CONFIG_INET=y 45 37 CONFIG_IP_MULTICAST=y 46 38 CONFIG_IP_ADVANCED_ROUTER=y ··· 50 38 CONFIG_IP_PNP_DHCP=y 51 39 CONFIG_IP_PNP_BOOTP=y 52 40 CONFIG_IP_PNP_RARP=y 41 + CONFIG_INET_ESP=m 42 + CONFIG_NETFILTER=y 43 + CONFIG_BRIDGE_NETFILTER=m 44 + CONFIG_NF_CONNTRACK=m 45 + CONFIG_NF_CONNTRACK_FTP=m 46 + CONFIG_NF_CONNTRACK_TFTP=m 47 + CONFIG_NETFILTER_XT_MARK=m 48 + CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m 49 + CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m 50 + CONFIG_NETFILTER_XT_MATCH_IPVS=m 51 + CONFIG_IP_VS=m 52 + CONFIG_IP_VS_PROTO_TCP=y 53 + CONFIG_IP_VS_PROTO_UDP=y 54 + CONFIG_IP_VS_RR=m 55 + CONFIG_IP_VS_NFCT=y 56 + CONFIG_NF_LOG_ARP=m 57 + CONFIG_NF_LOG_IPV4=m 58 + CONFIG_IP_NF_IPTABLES=m 59 + CONFIG_IP_NF_FILTER=m 60 + CONFIG_IP_NF_TARGET_REJECT=m 61 + CONFIG_IP_NF_NAT=m 62 + CONFIG_IP_NF_TARGET_MASQUERADE=m 63 + CONFIG_IP_NF_TARGET_REDIRECT=m 64 + CONFIG_IP_NF_MANGLE=m 65 + CONFIG_NF_LOG_IPV6=m 66 + CONFIG_IP6_NF_IPTABLES=m 67 + CONFIG_IP6_NF_MATCH_IPV6HEADER=m 68 + CONFIG_IP6_NF_FILTER=m 69 + CONFIG_IP6_NF_TARGET_REJECT=m 70 + CONFIG_IP6_NF_MANGLE=m 71 + CONFIG_BRIDGE=m 72 + CONFIG_BRIDGE_VLAN_FILTERING=y 73 + CONFIG_VLAN_8021Q=m 74 + CONFIG_NET_SCHED=y 75 + CONFIG_NET_CLS_CGROUP=m 53 76 CONFIG_NETLINK_DIAG=y 77 + CONFIG_CGROUP_NET_PRIO=y 54 78 CONFIG_NET_9P=y 55 79 CONFIG_NET_9P_VIRTIO=y 56 80 CONFIG_PCI=y ··· 105 57 CONFIG_ATA=y 106 58 CONFIG_SATA_AHCI=y 107 59 CONFIG_SATA_AHCI_PLATFORM=y 60 + CONFIG_MD=y 61 + CONFIG_BLK_DEV_DM=m 62 + CONFIG_DM_THIN_PROVISIONING=m 108 63 CONFIG_NETDEVICES=y 64 + CONFIG_DUMMY=m 65 + CONFIG_MACVLAN=m 66 + CONFIG_IPVLAN=m 67 + CONFIG_VXLAN=m 68 + CONFIG_VETH=m 109 69 CONFIG_VIRTIO_NET=y 110 70 CONFIG_MACB=y 111 71 CONFIG_E1000E=y ··· 161 105 CONFIG_RPMSG_VIRTIO=y 162 106 CONFIG_EXT4_FS=y 163 107 CONFIG_EXT4_FS_POSIX_ACL=y 108 + CONFIG_EXT4_FS_SECURITY=y 109 + CONFIG_BTRFS_FS=m 110 + CONFIG_BTRFS_FS_POSIX_ACL=y 164 111 CONFIG_AUTOFS4_FS=y 112 + CONFIG_OVERLAY_FS=m 165 113 CONFIG_MSDOS_FS=y 166 114 CONFIG_VFAT_FS=y 167 115 CONFIG_TMPFS=y ··· 179 119 CONFIG_9P_FS=y 180 120 CONFIG_NLS_CODEPAGE_437=y 181 121 CONFIG_NLS_ISO8859_1=m 122 + CONFIG_SECURITY=y 123 + CONFIG_SECURITY_SELINUX=y 124 + CONFIG_SECURITY_APPARMOR=y 125 + CONFIG_DEFAULT_SECURITY_DAC=y 182 126 CONFIG_CRYPTO_USER_API_HASH=y 183 127 CONFIG_CRYPTO_DEV_VIRTIO=y 184 128 CONFIG_PRINTK_TIME=y ··· 201 137 CONFIG_DEBUG_MUTEXES=y 202 138 CONFIG_DEBUG_RWSEMS=y 203 139 CONFIG_DEBUG_ATOMIC_SLEEP=y 204 - CONFIG_STACKTRACE=y 205 140 CONFIG_DEBUG_LIST=y 206 141 CONFIG_DEBUG_PLIST=y 207 142 CONFIG_DEBUG_SG=y
+1
arch/riscv/configs/nommu_k210_defconfig
··· 28 28 CONFIG_SLOB=y 29 29 # CONFIG_MMU is not set 30 30 CONFIG_SOC_CANAAN=y 31 + CONFIG_NONPORTABLE=y 31 32 CONFIG_SMP=y 32 33 CONFIG_NR_CPUS=2 33 34 CONFIG_CMDLINE="earlycon console=ttySIF0"
+1
arch/riscv/configs/nommu_k210_sdcard_defconfig
··· 20 20 CONFIG_SLOB=y 21 21 # CONFIG_MMU is not set 22 22 CONFIG_SOC_CANAAN=y 23 + CONFIG_NONPORTABLE=y 23 24 CONFIG_SMP=y 24 25 CONFIG_NR_CPUS=2 25 26 CONFIG_CMDLINE="earlycon console=ttySIF0 root=/dev/mmcblk0p1 rootwait ro"
+1
arch/riscv/configs/nommu_virt_defconfig
··· 25 25 CONFIG_SLOB=y 26 26 # CONFIG_MMU is not set 27 27 CONFIG_SOC_VIRT=y 28 + CONFIG_NONPORTABLE=y 28 29 CONFIG_SMP=y 29 30 CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0" 30 31 CONFIG_CMDLINE_FORCE=y
+1
arch/riscv/configs/rv32_defconfig
··· 18 18 CONFIG_PROFILING=y 19 19 CONFIG_SOC_SIFIVE=y 20 20 CONFIG_SOC_VIRT=y 21 + CONFIG_NONPORTABLE=y 21 22 CONFIG_ARCH_RV32I=y 22 23 CONFIG_SMP=y 23 24 CONFIG_HOTPLUG_CPU=y
+12 -26
arch/riscv/errata/thead/errata.c
··· 14 14 #include <asm/patch.h> 15 15 #include <asm/vendorid_list.h> 16 16 17 - struct errata_info { 18 - char name[ERRATA_STRING_LENGTH_MAX]; 19 - bool (*check_func)(unsigned long arch_id, unsigned long impid); 20 - unsigned int stage; 21 - }; 22 - 23 - static bool errata_mt_check_func(unsigned long arch_id, unsigned long impid) 17 + static bool errata_probe_pbmt(unsigned int stage, 18 + unsigned long arch_id, unsigned long impid) 24 19 { 25 20 if (arch_id != 0 || impid != 0) 26 21 return false; 27 - return true; 22 + 23 + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT || 24 + stage == RISCV_ALTERNATIVES_MODULE) 25 + return true; 26 + 27 + return false; 28 28 } 29 29 30 - static const struct errata_info errata_list[ERRATA_THEAD_NUMBER] = { 31 - { 32 - .name = "memory-types", 33 - .stage = RISCV_ALTERNATIVES_EARLY_BOOT, 34 - .check_func = errata_mt_check_func 35 - }, 36 - }; 37 - 38 - static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) 30 + static u32 thead_errata_probe(unsigned int stage, 31 + unsigned long archid, unsigned long impid) 39 32 { 40 - const struct errata_info *info; 41 33 u32 cpu_req_errata = 0; 42 - int idx; 43 34 44 - for (idx = 0; idx < ERRATA_THEAD_NUMBER; idx++) { 45 - info = &errata_list[idx]; 46 - 47 - if ((stage == RISCV_ALTERNATIVES_MODULE || 48 - info->stage == stage) && info->check_func(archid, impid)) 49 - cpu_req_errata |= (1U << idx); 50 - } 35 + if (errata_probe_pbmt(stage, archid, impid)) 36 + cpu_req_errata |= (1U << ERRATA_THEAD_PBMT); 51 37 52 38 return cpu_req_errata; 53 39 }
+15
arch/riscv/include/asm/asm.h
··· 67 67 #error "Unexpected __SIZEOF_SHORT__" 68 68 #endif 69 69 70 + #ifdef __ASSEMBLY__ 71 + 72 + /* Common assembly source macros */ 73 + 74 + /* 75 + * NOP sequence 76 + */ 77 + .macro nops, num 78 + .rept \num 79 + nop 80 + .endr 81 + .endm 82 + 83 + #endif /* __ASSEMBLY__ */ 84 + 70 85 #endif /* _ASM_RISCV_ASM_H */
+2
arch/riscv/include/asm/barrier.h
··· 13 13 #ifndef __ASSEMBLY__ 14 14 15 15 #define nop() __asm__ __volatile__ ("nop") 16 + #define __nops(n) ".rept " #n "\nnop\n.endr\n" 17 + #define nops(n) __asm__ __volatile__ (__nops(n)) 16 18 17 19 #define RISCV_FENCE(p, s) \ 18 20 __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
+1 -7
arch/riscv/include/asm/errata_list.h
··· 68 68 */ 69 69 #define ALT_THEAD_PMA(_val) \ 70 70 asm volatile(ALTERNATIVE( \ 71 - "nop\n\t" \ 72 - "nop\n\t" \ 73 - "nop\n\t" \ 74 - "nop\n\t" \ 75 - "nop\n\t" \ 76 - "nop\n\t" \ 77 - "nop", \ 71 + __nops(7), \ 78 72 "li t3, %1\n\t" \ 79 73 "slli t3, t3, %3\n\t" \ 80 74 "and t3, %0, t3\n\t" \
+25
arch/riscv/include/asm/hwcap.h
··· 12 12 #include <uapi/asm/hwcap.h> 13 13 14 14 #ifndef __ASSEMBLY__ 15 + #include <linux/jump_label.h> 15 16 /* 16 17 * This yields a mask that user programs can use to figure out what 17 18 * instruction set this cpu supports. ··· 57 56 RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, 58 57 }; 59 58 59 + /* 60 + * This enum represents the logical ID for each RISC-V ISA extension static 61 + * keys. We can use static key to optimize code path if some ISA extensions 62 + * are available. 63 + */ 64 + enum riscv_isa_ext_key { 65 + RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ 66 + RISCV_ISA_EXT_KEY_MAX, 67 + }; 68 + 60 69 struct riscv_isa_ext_data { 61 70 /* Name of the extension displayed to userspace via /proc/cpuinfo */ 62 71 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; 63 72 /* The logical ISA extension ID */ 64 73 unsigned int isa_ext_id; 65 74 }; 75 + 76 + extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX]; 77 + 78 + static __always_inline int riscv_isa_ext2key(int num) 79 + { 80 + switch (num) { 81 + case RISCV_ISA_EXT_f: 82 + return RISCV_ISA_EXT_KEY_FPU; 83 + case RISCV_ISA_EXT_d: 84 + return RISCV_ISA_EXT_KEY_FPU; 85 + default: 86 + return -EINVAL; 87 + } 88 + } 66 89 67 90 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); 68 91
+3
arch/riscv/include/asm/pci.h
··· 12 12 13 13 #include <asm/io.h> 14 14 15 + #define PCIBIOS_MIN_IO 4 16 + #define PCIBIOS_MIN_MEM 16 17 + 15 18 #if defined(CONFIG_PCI) && defined(CONFIG_NUMA) 16 19 static inline int pcibus_to_node(struct pci_bus *bus) 17 20 {
+2 -2
arch/riscv/include/asm/processor.h
··· 79 79 } 80 80 81 81 struct device_node; 82 - int riscv_of_processor_hartid(struct device_node *node); 83 - int riscv_of_parent_hartid(struct device_node *node); 82 + int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); 83 + int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); 84 84 85 85 extern void riscv_fill_hwcap(void); 86 86 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
+2 -2
arch/riscv/include/asm/smp.h
··· 42 42 /* Hook for the generic smp_call_function_single() routine. */ 43 43 void arch_send_call_function_single_ipi(int cpu); 44 44 45 - int riscv_hartid_to_cpuid(int hartid); 45 + int riscv_hartid_to_cpuid(unsigned long hartid); 46 46 47 47 /* Set custom IPI operations */ 48 48 void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); ··· 70 70 { 71 71 } 72 72 73 - static inline int riscv_hartid_to_cpuid(int hartid) 73 + static inline int riscv_hartid_to_cpuid(unsigned long hartid) 74 74 { 75 75 if (hartid == boot_cpu_hartid) 76 76 return 0;
+2 -2
arch/riscv/include/asm/switch_to.h
··· 8 8 9 9 #include <linux/jump_label.h> 10 10 #include <linux/sched/task_stack.h> 11 + #include <asm/hwcap.h> 11 12 #include <asm/processor.h> 12 13 #include <asm/ptrace.h> 13 14 #include <asm/csr.h> ··· 57 56 fstate_restore(next, task_pt_regs(next)); 58 57 } 59 58 60 - extern struct static_key_false cpu_hwcap_fpu; 61 59 static __always_inline bool has_fpu(void) 62 60 { 63 - return static_branch_likely(&cpu_hwcap_fpu); 61 + return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]); 64 62 } 65 63 #else 66 64 static __always_inline bool has_fpu(void) { return false; }
+9 -9
arch/riscv/kernel/alternative.c
··· 20 20 unsigned long vendor_id; 21 21 unsigned long arch_id; 22 22 unsigned long imp_id; 23 - void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end, 23 + void (*patch_func)(struct alt_entry *begin, struct alt_entry *end, 24 24 unsigned long archid, unsigned long impid, 25 25 unsigned int stage); 26 26 }; ··· 40 40 switch (cpu_mfr_info->vendor_id) { 41 41 #ifdef CONFIG_ERRATA_SIFIVE 42 42 case SIFIVE_VENDOR_ID: 43 - cpu_mfr_info->vendor_patch_func = sifive_errata_patch_func; 43 + cpu_mfr_info->patch_func = sifive_errata_patch_func; 44 44 break; 45 45 #endif 46 46 #ifdef CONFIG_ERRATA_THEAD 47 47 case THEAD_VENDOR_ID: 48 - cpu_mfr_info->vendor_patch_func = thead_errata_patch_func; 48 + cpu_mfr_info->patch_func = thead_errata_patch_func; 49 49 break; 50 50 #endif 51 51 default: 52 - cpu_mfr_info->vendor_patch_func = NULL; 52 + cpu_mfr_info->patch_func = NULL; 53 53 } 54 54 } 55 55 ··· 68 68 69 69 riscv_cpufeature_patch_func(begin, end, stage); 70 70 71 - if (!cpu_mfr_info.vendor_patch_func) 71 + if (!cpu_mfr_info.patch_func) 72 72 return; 73 73 74 - cpu_mfr_info.vendor_patch_func(begin, end, 75 - cpu_mfr_info.arch_id, 76 - cpu_mfr_info.imp_id, 77 - stage); 74 + cpu_mfr_info.patch_func(begin, end, 75 + cpu_mfr_info.arch_id, 76 + cpu_mfr_info.imp_id, 77 + stage); 78 78 } 79 79 80 80 void __init apply_boot_alternatives(void)
+15 -11
arch/riscv/kernel/cpu.c
··· 14 14 * Returns the hart ID of the given device tree node, or -ENODEV if the node 15 15 * isn't an enabled and valid RISC-V hart node. 16 16 */ 17 - int riscv_of_processor_hartid(struct device_node *node) 17 + int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) 18 18 { 19 19 const char *isa; 20 - u32 hart; 21 20 22 21 if (!of_device_is_compatible(node, "riscv")) { 23 22 pr_warn("Found incompatible CPU\n"); 24 23 return -ENODEV; 25 24 } 26 25 27 - hart = of_get_cpu_hwid(node, 0); 28 - if (hart == ~0U) { 26 + *hart = (unsigned long) of_get_cpu_hwid(node, 0); 27 + if (*hart == ~0UL) { 29 28 pr_warn("Found CPU without hart ID\n"); 30 29 return -ENODEV; 31 30 } 32 31 33 32 if (!of_device_is_available(node)) { 34 - pr_info("CPU with hartid=%d is not available\n", hart); 33 + pr_info("CPU with hartid=%lu is not available\n", *hart); 35 34 return -ENODEV; 36 35 } 37 36 38 37 if (of_property_read_string(node, "riscv,isa", &isa)) { 39 - pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); 38 + pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); 40 39 return -ENODEV; 41 40 } 42 41 if (isa[0] != 'r' || isa[1] != 'v') { 43 - pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); 42 + pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); 44 43 return -ENODEV; 45 44 } 46 45 47 - return hart; 46 + return 0; 48 47 } 49 48 50 49 /* ··· 52 53 * To achieve this, we walk up the DT tree until we find an active 53 54 * RISC-V core (HART) node and extract the cpuid from it. 54 55 */ 55 - int riscv_of_parent_hartid(struct device_node *node) 56 + int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) 56 57 { 58 + int rc; 59 + 57 60 for (; node; node = node->parent) { 58 - if (of_device_is_compatible(node, "riscv")) 59 - return riscv_of_processor_hartid(node); 61 + if (of_device_is_compatible(node, "riscv")) { 62 + rc = riscv_of_processor_hartid(node, hartid); 63 + if (!rc) 64 + return 0; 65 + } 60 66 } 61 67 62 68 return -1;
+2 -2
arch/riscv/kernel/cpu_ops_sbi.c
··· 65 65 static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) 66 66 { 67 67 unsigned long boot_addr = __pa_symbol(secondary_start_sbi); 68 - int hartid = cpuid_to_hartid_map(cpuid); 68 + unsigned long hartid = cpuid_to_hartid_map(cpuid); 69 69 unsigned long hsm_data; 70 70 struct sbi_hart_boot_data *bdata = &per_cpu(boot_data, cpuid); 71 71 ··· 107 107 static int sbi_cpu_is_stopped(unsigned int cpuid) 108 108 { 109 109 int rc; 110 - int hartid = cpuid_to_hartid_map(cpuid); 110 + unsigned long hartid = cpuid_to_hartid_map(cpuid); 111 111 112 112 rc = sbi_hsm_hart_get_status(hartid); 113 113
+2 -2
arch/riscv/kernel/cpu_ops_spinwait.c
··· 18 18 static void cpu_update_secondary_bootdata(unsigned int cpuid, 19 19 struct task_struct *tidle) 20 20 { 21 - int hartid = cpuid_to_hartid_map(cpuid); 21 + unsigned long hartid = cpuid_to_hartid_map(cpuid); 22 22 23 23 /* 24 24 * The hartid must be less than NR_CPUS to avoid out-of-bound access ··· 27 27 * spinwait booting is not the recommended approach for any platforms 28 28 * booting Linux in S-mode and can be disabled in the future. 29 29 */ 30 - if (hartid == INVALID_HARTID || hartid >= NR_CPUS) 30 + if (hartid == INVALID_HARTID || hartid >= (unsigned long) NR_CPUS) 31 31 return; 32 32 33 33 /* Make sure tidle is updated */
+21 -31
arch/riscv/kernel/cpufeature.c
··· 27 27 /* Host ISA bitmap */ 28 28 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; 29 29 30 - #ifdef CONFIG_FPU 31 - __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); 32 - #endif 30 + __ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); 31 + EXPORT_SYMBOL(riscv_isa_ext_keys); 33 32 34 33 /** 35 34 * riscv_isa_extension_base() - Get base extension word ··· 72 73 struct device_node *node; 73 74 const char *isa; 74 75 char print_str[NUM_ALPHA_EXTS + 1]; 75 - int i, j; 76 + int i, j, rc; 76 77 static unsigned long isa2hwcap[256] = {0}; 78 + unsigned long hartid; 77 79 78 80 isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; 79 81 isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M; ··· 92 92 DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); 93 93 const char *temp; 94 94 95 - if (riscv_of_processor_hartid(node) < 0) 95 + rc = riscv_of_processor_hartid(node, &hartid); 96 + if (rc < 0) 96 97 continue; 97 98 98 99 if (of_property_read_string(node, "riscv,isa", &isa)) { ··· 239 238 print_str[j++] = (char)('a' + i); 240 239 pr_info("riscv: ELF capabilities %s\n", print_str); 241 240 242 - #ifdef CONFIG_FPU 243 - if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) 244 - static_branch_enable(&cpu_hwcap_fpu); 245 - #endif 241 + for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) { 242 + j = riscv_isa_ext2key(i); 243 + if (j >= 0) 244 + static_branch_enable(&riscv_isa_ext_keys[j]); 245 + } 246 246 } 247 247 248 248 #ifdef CONFIG_RISCV_ALTERNATIVE 249 - struct cpufeature_info { 250 - char name[ERRATA_STRING_LENGTH_MAX]; 251 - bool (*check_func)(unsigned int stage); 252 - }; 253 - 254 - static bool __init_or_module cpufeature_svpbmt_check_func(unsigned int stage) 249 + static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) 255 250 { 256 251 #ifdef CONFIG_RISCV_ISA_SVPBMT 257 252 switch (stage) { ··· 261 264 return false; 262 265 } 263 266 264 - static const struct cpufeature_info __initdata_or_module 265 - cpufeature_list[CPUFEATURE_NUMBER] = { 266 - { 267 - .name = "svpbmt", 268 - .check_func = cpufeature_svpbmt_check_func 269 - }, 270 - }; 271 - 267 + /* 268 + * Probe presence of individual extensions. 269 + * 270 + * This code may also be executed before kernel relocation, so we cannot use 271 + * addresses generated by the address-of operator as they won't be valid in 272 + * this context. 273 + */ 272 274 static u32 __init_or_module cpufeature_probe(unsigned int stage) 273 275 { 274 - const struct cpufeature_info *info; 275 276 u32 cpu_req_feature = 0; 276 - int idx; 277 277 278 - for (idx = 0; idx < CPUFEATURE_NUMBER; idx++) { 279 - info = &cpufeature_list[idx]; 280 - 281 - if (info->check_func(stage)) 282 - cpu_req_feature |= (1U << idx); 283 - } 278 + if (cpufeature_probe_svpbmt(stage)) 279 + cpu_req_feature |= (1U << CPUFEATURE_SVPBMT); 284 280 285 281 return cpu_req_feature; 286 282 }
+2 -2
arch/riscv/kernel/smp.c
··· 47 47 unsigned long bits ____cacheline_aligned; 48 48 } ipi_data[NR_CPUS] __cacheline_aligned; 49 49 50 - int riscv_hartid_to_cpuid(int hartid) 50 + int riscv_hartid_to_cpuid(unsigned long hartid) 51 51 { 52 52 int i; 53 53 ··· 55 55 if (cpuid_to_hartid_map(i) == hartid) 56 56 return i; 57 57 58 - pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); 58 + pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid); 59 59 return -ENOENT; 60 60 } 61 61
+5 -4
arch/riscv/kernel/smpboot.c
··· 72 72 void __init setup_smp(void) 73 73 { 74 74 struct device_node *dn; 75 - int hart; 75 + unsigned long hart; 76 76 bool found_boot_cpu = false; 77 77 int cpuid = 1; 78 + int rc; 78 79 79 80 cpu_set_ops(0); 80 81 81 82 for_each_of_cpu_node(dn) { 82 - hart = riscv_of_processor_hartid(dn); 83 - if (hart < 0) 83 + rc = riscv_of_processor_hartid(dn, &hart); 84 + if (rc < 0) 84 85 continue; 85 86 86 87 if (hart == cpuid_to_hartid_map(0)) { ··· 91 90 continue; 92 91 } 93 92 if (cpuid >= NR_CPUS) { 94 - pr_warn("Invalid cpuid [%d] for hartid [%d]\n", 93 + pr_warn("Invalid cpuid [%d] for hartid [%lu]\n", 95 94 cpuid, hart); 96 95 continue; 97 96 }
+2 -3
arch/riscv/kernel/sys_riscv.c
··· 18 18 if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) 19 19 return -EINVAL; 20 20 21 - if ((prot & PROT_WRITE) && (prot & PROT_EXEC)) 22 - if (unlikely(!(prot & PROT_READ))) 23 - return -EINVAL; 21 + if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ))) 22 + return -EINVAL; 24 23 25 24 return ksys_mmap_pgoff(addr, len, prot, flags, fd, 26 25 offset >> (PAGE_SHIFT - page_shift_offset));
+4
arch/riscv/kernel/traps.c
··· 16 16 #include <linux/mm.h> 17 17 #include <linux/module.h> 18 18 #include <linux/irq.h> 19 + #include <linux/kexec.h> 19 20 20 21 #include <asm/asm-prototypes.h> 21 22 #include <asm/bug.h> ··· 44 43 show_regs(regs); 45 44 46 45 ret = notify_die(DIE_OOPS, str, regs, 0, regs->cause, SIGSEGV); 46 + 47 + if (regs && kexec_should_crash(current)) 48 + crash_kexec(regs); 47 49 48 50 bust_spinlocks(0); 49 51 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
+8 -7
drivers/clocksource/timer-riscv.c
··· 101 101 102 102 static int __init riscv_timer_init_dt(struct device_node *n) 103 103 { 104 - int cpuid, hartid, error; 104 + int cpuid, error; 105 + unsigned long hartid; 105 106 struct device_node *child; 106 107 struct irq_domain *domain; 107 108 108 - hartid = riscv_of_processor_hartid(n); 109 - if (hartid < 0) { 110 - pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", 109 + error = riscv_of_processor_hartid(n, &hartid); 110 + if (error < 0) { 111 + pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", 111 112 n, hartid); 112 - return hartid; 113 + return error; 113 114 } 114 115 115 116 cpuid = riscv_hartid_to_cpuid(hartid); 116 117 if (cpuid < 0) { 117 - pr_warn("Invalid cpuid for hartid [%d]\n", hartid); 118 + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); 118 119 return cpuid; 119 120 } 120 121 ··· 141 140 return -ENODEV; 142 141 } 143 142 144 - pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", 143 + pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", 145 144 __func__, cpuid, hartid); 146 145 error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); 147 146 if (error) {
+10 -3
drivers/firmware/efi/libstub/riscv-stub.c
··· 8 8 9 9 #include <asm/efi.h> 10 10 #include <asm/sections.h> 11 + #include <asm/unaligned.h> 11 12 12 13 #include "efistub.h" 13 14 ··· 30 29 { 31 30 const void *fdt; 32 31 int chosen_node, len; 33 - const fdt32_t *prop; 32 + const void *prop; 34 33 35 34 fdt = get_efi_config_table(DEVICE_TREE_GUID); 36 35 if (!fdt) ··· 41 40 return -EINVAL; 42 41 43 42 prop = fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); 44 - if (!prop || len != sizeof(u32)) 43 + if (!prop) 45 44 return -EINVAL; 46 45 47 - hartid = fdt32_to_cpu(*prop); 46 + if (len == sizeof(u32)) 47 + hartid = (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); 48 + else if (len == sizeof(u64)) 49 + hartid = (unsigned long) fdt64_to_cpu(__get_unaligned_t(fdt64_t, prop)); 50 + else 51 + return -EINVAL; 52 + 48 53 return 0; 49 54 } 50 55
+4 -3
drivers/irqchip/irq-riscv-intc.c
··· 95 95 static int __init riscv_intc_init(struct device_node *node, 96 96 struct device_node *parent) 97 97 { 98 - int rc, hartid; 98 + int rc; 99 + unsigned long hartid; 99 100 100 - hartid = riscv_of_parent_hartid(node); 101 - if (hartid < 0) { 101 + rc = riscv_of_parent_hartid(node, &hartid); 102 + if (rc < 0) { 102 103 pr_warn("unable to find hart id for %pOF\n", node); 103 104 return 0; 104 105 }
+4 -3
drivers/irqchip/irq-sifive-plic.c
··· 374 374 for (i = 0; i < nr_contexts; i++) { 375 375 struct of_phandle_args parent; 376 376 irq_hw_number_t hwirq; 377 - int cpu, hartid; 377 + int cpu; 378 + unsigned long hartid; 378 379 379 380 if (of_irq_parse_one(node, i, &parent)) { 380 381 pr_err("failed to parse parent for context %d.\n", i); ··· 399 398 continue; 400 399 } 401 400 402 - hartid = riscv_of_parent_hartid(parent.np); 403 - if (hartid < 0) { 401 + error = riscv_of_parent_hartid(parent.np, &hartid); 402 + if (error < 0) { 404 403 pr_warn("failed to parse hart ID for context %d.\n", i); 405 404 continue; 406 405 }