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cache: Make top level Kconfig menu a boolean dependent on RISCV

The next patch will add a new type of cache maintenance driver responsible
for flushing deeper than is necessary for non coherent DMA (current
use case of drivers/cache drivers), as needed when performing operations
such as memory hotplug and security unlocking of persistent memory. The two
types of operation are similar enough to share a drivers/cache directory
and MAINTAINERS but are otherwise currently unrelated.

To avoid confusion have two separate menus. Each has dependencies that are
implemented by making them boolean symbols, here CACHEMAINT_FOR_DMA
which is dependent on RISCV as all driver are currently for platforms of
that architecture. Set new symbol default to y to avoid breaking existing
configs. This has no affect on actual code built, just visibility of the
menu.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

authored by

Jonathan Cameron and committed by
Conor Dooley
4d1608d0 9b9de5a5

+11 -4
+11 -4
drivers/cache/Kconfig
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 - menu "Cache Drivers" 2 + 3 + menuconfig CACHEMAINT_FOR_DMA 4 + bool "Cache management for noncoherent DMA" 5 + depends on RISCV 6 + default y 7 + help 8 + These drivers implement support for noncoherent DMA master devices 9 + on platforms that lack the standard CPU interfaces for this. 10 + 11 + if CACHEMAINT_FOR_DMA 3 12 4 13 config AX45MP_L2_CACHE 5 14 bool "Andes Technology AX45MP L2 Cache controller" 6 - depends on RISCV 7 15 select RISCV_NONSTANDARD_CACHE_OPS 8 16 help 9 17 Support for the L2 cache controller on Andes Technology AX45MP platforms. ··· 24 16 25 17 config STARFIVE_STARLINK_CACHE 26 18 bool "StarFive StarLink Cache controller" 27 - depends on RISCV 28 19 depends on ARCH_STARFIVE 29 20 depends on 64BIT 30 21 select RISCV_DMA_NONCOHERENT ··· 31 24 help 32 25 Support for the StarLink cache controller IP from StarFive. 33 26 34 - endmenu 27 + endif #CACHEMAINT_FOR_DMA