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net: airoha: Use gdm port enum value whenever possible

Use AIROHA_GDMx_IDX enum value whenever possible.
This patch is just cosmetic changes and does not introduce any logic one.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20260105-airoha-use-port-idx-enum-v1-1-503ca5763858@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Lorenzo Bianconi and committed by
Jakub Kicinski 4d513329 e9cd04b2

+21 -19
+21 -19
drivers/net/ethernet/airoha/airoha_eth.c
··· 108 108 u32 vip_port; 109 109 110 110 switch (port->id) { 111 - case 3: 111 + case AIROHA_GDM3_IDX: 112 112 /* FIXME: handle XSI_PCIE1_PORT */ 113 113 vip_port = XSI_PCIE0_VIP_PORT_MASK; 114 114 break; 115 - case 4: 115 + case AIROHA_GDM4_IDX: 116 116 /* FIXME: handle XSI_USB_PORT */ 117 117 vip_port = XSI_ETH_VIP_PORT_MASK; 118 118 break; ··· 514 514 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 515 515 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 516 516 517 - airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN_MASK); 518 - airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN_MASK); 517 + airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK); 518 + airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK); 519 519 520 520 airoha_fe_crsn_qsel_init(eth); 521 521 ··· 1690 1690 /* Forward the traffic to the proper GDM port */ 1691 1691 pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1692 1692 : FE_PSE_PORT_GDM4; 1693 - airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port); 1694 - airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC_MASK); 1693 + airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1694 + pse_port); 1695 + airoha_fe_clear(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1696 + GDM_STRIP_CRC_MASK); 1695 1697 1696 1698 /* Enable GDM2 loopback */ 1697 - airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff); 1698 - airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff); 1699 + airoha_fe_wr(eth, REG_GDM_TXCHN_EN(AIROHA_GDM2_IDX), 0xffffffff); 1700 + airoha_fe_wr(eth, REG_GDM_RXCHN_EN(AIROHA_GDM2_IDX), 0xffff); 1699 1701 1700 1702 chan = port->id == AIROHA_GDM3_IDX ? airoha_is_7581(eth) ? 4 : 3 : 0; 1701 - airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2), 1703 + airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(AIROHA_GDM2_IDX), 1702 1704 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1703 1705 FIELD_PREP(LPBK_CHAN_MASK, chan) | 1704 1706 LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK | 1705 1707 LBK_CHAN_MODE_MASK | LPBK_EN_MASK); 1706 - airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2), 1708 + airoha_fe_rmw(eth, REG_GDM_LEN_CFG(AIROHA_GDM2_IDX), 1707 1709 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1708 1710 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1709 1711 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1710 1712 1711 1713 /* Disable VIP and IFC for GDM2 */ 1712 - airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2)); 1713 - airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2)); 1714 + airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX)); 1715 + airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX)); 1714 1716 1715 1717 /* XXX: handle XSI_USB_PORT and XSI_PCE1_PORT */ 1716 1718 nbq = port->id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0; ··· 1748 1746 airoha_set_macaddr(port, dev->dev_addr); 1749 1747 1750 1748 switch (port->id) { 1751 - case 3: 1752 - case 4: 1749 + case AIROHA_GDM3_IDX: 1750 + case AIROHA_GDM4_IDX: 1753 1751 /* If GDM2 is active we can't enable loopback */ 1754 1752 if (!eth->ports[1]) { 1755 1753 int err; ··· 1759 1757 return err; 1760 1758 } 1761 1759 fallthrough; 1762 - case 2: 1760 + case AIROHA_GDM2_IDX: 1763 1761 if (airoha_ppe_is_enabled(eth, 1)) { 1764 1762 /* For PPE2 always use secondary cpu port. */ 1765 1763 fe_cpu_port = FE_PSE_PORT_CDM2; ··· 3103 3101 static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3104 3102 { 3105 3103 switch (port->id) { 3106 - case 3: 3104 + case AIROHA_GDM3_IDX: 3107 3105 /* 7581 SoC supports PCIe serdes on GDM3 port */ 3108 3106 if (nbq == 4) 3109 3107 return HSGMII_LAN_7581_PCIE0_SRCPORT; 3110 3108 if (nbq == 5) 3111 3109 return HSGMII_LAN_7581_PCIE1_SRCPORT; 3112 3110 break; 3113 - case 4: 3111 + case AIROHA_GDM4_IDX: 3114 3112 /* 7581 SoC supports eth and usb serdes on GDM4 port */ 3115 3113 if (!nbq) 3116 3114 return HSGMII_LAN_7581_ETH_SRCPORT; ··· 3134 3132 static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3135 3133 { 3136 3134 switch (port->id) { 3137 - case 3: 3135 + case AIROHA_GDM3_IDX: 3138 3136 /* 7583 SoC supports eth serdes on GDM3 port */ 3139 3137 if (!nbq) 3140 3138 return HSGMII_LAN_7583_ETH_SRCPORT; 3141 3139 break; 3142 - case 4: 3140 + case AIROHA_GDM4_IDX: 3143 3141 /* 7583 SoC supports PCIe and USB serdes on GDM4 port */ 3144 3142 if (!nbq) 3145 3143 return HSGMII_LAN_7583_PCIE_SRCPORT;