Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add msm8994 MMCC driver
Add a driver for managing MultiMedia SubSystem clocks on msm8994
and its derivatives.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210618111435.595689-2-konrad.dybcio@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Konrad Dybcio
and committed by
Stephen Boyd
4d5b4572
79726096
+2659
+9
drivers/clk/qcom/Kconfig
+9
drivers/clk/qcom/Kconfig
···
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Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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+
config MSM_MMCC_8994
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tristate "MSM8994 Multimedia Clock Controller"
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select MSM_GCC_8994
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select QCOM_GDSC
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help
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Support for the multimedia clock controller on msm8994 devices.
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+
Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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+
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config MSM_GCC_8994
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tristate "MSM8994 Global Clock Controller"
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help
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_MSM_GPUCC_8998) += gpucc-msm8998.o
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obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
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obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
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obj-$(CONFIG_MSM_MMCC_8994) += mmcc-msm8994.o
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obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
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obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o
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obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
+2494
drivers/clk/qcom/mmcc-msm8994.c
+2494
drivers/clk/qcom/mmcc-msm8994.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4
+
*/
5
+
6
+
#include <linux/kernel.h>
7
+
#include <linux/bitops.h>
8
+
#include <linux/err.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/clk-provider.h>
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+
#include <linux/regmap.h>
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+
#include <linux/reset-controller.h>
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+
#include <linux/clk.h>
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+
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#include <dt-bindings/clock/qcom,mmcc-msm8994.h>
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+
20
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#include "common.h"
21
+
#include "clk-regmap.h"
22
+
#include "clk-regmap-divider.h"
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+
#include "clk-alpha-pll.h"
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+
#include "clk-rcg.h"
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+
#include "clk-branch.h"
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+
#include "reset.h"
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+
#include "gdsc.h"
28
+
29
+
30
+
enum {
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+
P_XO,
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P_GPLL0,
33
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P_MMPLL0,
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P_MMPLL1,
35
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P_MMPLL3,
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P_MMPLL4,
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P_MMPLL5, /* Is this one even used by anything? Downstream doesn't tell. */
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+
P_DSI0PLL,
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P_DSI1PLL,
40
+
P_DSI0PLL_BYTE,
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P_DSI1PLL_BYTE,
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P_HDMIPLL,
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};
44
+
static const struct parent_map mmcc_xo_gpll0_map[] = {
45
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{ P_XO, 0 },
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{ P_GPLL0, 5 }
47
+
};
48
+
49
+
static const struct clk_parent_data mmcc_xo_gpll0[] = {
50
+
{ .fw_name = "xo" },
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{ .fw_name = "gpll0" },
52
+
};
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+
54
+
static const struct parent_map mmss_xo_hdmi_map[] = {
55
+
{ P_XO, 0 },
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{ P_HDMIPLL, 3 }
57
+
};
58
+
59
+
static const struct clk_parent_data mmss_xo_hdmi[] = {
60
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{ .fw_name = "xo" },
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{ .fw_name = "hdmipll" },
62
+
};
63
+
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static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
65
+
{ P_XO, 0 },
66
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{ P_DSI0PLL, 1 },
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{ P_DSI1PLL, 2 }
68
+
};
69
+
70
+
static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
71
+
{ .fw_name = "xo" },
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+
{ .fw_name = "dsi0pll" },
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{ .fw_name = "dsi1pll" },
74
+
};
75
+
76
+
static const struct parent_map mmcc_xo_dsibyte_map[] = {
77
+
{ P_XO, 0 },
78
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{ P_DSI0PLL_BYTE, 1 },
79
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{ P_DSI1PLL_BYTE, 2 }
80
+
};
81
+
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static const struct clk_parent_data mmcc_xo_dsibyte[] = {
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{ .fw_name = "xo" },
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{ .fw_name = "dsi0pllbyte" },
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{ .fw_name = "dsi1pllbyte" },
86
+
};
87
+
88
+
static struct pll_vco mmpll_p_vco[] = {
89
+
{ 250000000, 500000000, 3 },
90
+
{ 500000000, 1000000000, 2 },
91
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{ 1000000000, 1500000000, 1 },
92
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{ 1500000000, 2000000000, 0 },
93
+
};
94
+
95
+
static struct pll_vco mmpll_t_vco[] = {
96
+
{ 500000000, 1500000000, 0 },
97
+
};
98
+
99
+
static const struct alpha_pll_config mmpll_p_config = {
100
+
.post_div_mask = 0xf00,
101
+
};
102
+
103
+
static struct clk_alpha_pll mmpll0_early = {
104
+
.offset = 0x0,
105
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
106
+
.vco_table = mmpll_p_vco,
107
+
.num_vco = ARRAY_SIZE(mmpll_p_vco),
108
+
.clkr = {
109
+
.enable_reg = 0x100,
110
+
.enable_mask = BIT(0),
111
+
.hw.init = &(struct clk_init_data){
112
+
.name = "mmpll0_early",
113
+
.parent_data = &(const struct clk_parent_data){
114
+
.fw_name = "xo",
115
+
},
116
+
.num_parents = 1,
117
+
.ops = &clk_alpha_pll_ops,
118
+
},
119
+
},
120
+
};
121
+
122
+
static struct clk_alpha_pll_postdiv mmpll0 = {
123
+
.offset = 0x0,
124
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
125
+
.width = 4,
126
+
.clkr.hw.init = &(struct clk_init_data){
127
+
.name = "mmpll0",
128
+
.parent_hws = (const struct clk_hw *[]){ &mmpll0_early.clkr.hw },
129
+
.num_parents = 1,
130
+
.ops = &clk_alpha_pll_postdiv_ops,
131
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.flags = CLK_SET_RATE_PARENT,
132
+
},
133
+
};
134
+
135
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static struct clk_alpha_pll mmpll1_early = {
136
+
.offset = 0x30,
137
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
138
+
.vco_table = mmpll_p_vco,
139
+
.num_vco = ARRAY_SIZE(mmpll_p_vco),
140
+
.clkr = {
141
+
.enable_reg = 0x100,
142
+
.enable_mask = BIT(1),
143
+
.hw.init = &(struct clk_init_data){
144
+
.name = "mmpll1_early",
145
+
.parent_data = &(const struct clk_parent_data){
146
+
.fw_name = "xo",
147
+
},
148
+
.num_parents = 1,
149
+
.ops = &clk_alpha_pll_ops,
150
+
}
151
+
},
152
+
};
153
+
154
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static struct clk_alpha_pll_postdiv mmpll1 = {
155
+
.offset = 0x30,
156
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
157
+
.width = 4,
158
+
.clkr.hw.init = &(struct clk_init_data){
159
+
.name = "mmpll1",
160
+
.parent_hws = (const struct clk_hw *[]){ &mmpll1_early.clkr.hw },
161
+
.num_parents = 1,
162
+
.ops = &clk_alpha_pll_postdiv_ops,
163
+
.flags = CLK_SET_RATE_PARENT,
164
+
},
165
+
};
166
+
167
+
static struct clk_alpha_pll mmpll3_early = {
168
+
.offset = 0x60,
169
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
170
+
.vco_table = mmpll_p_vco,
171
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.num_vco = ARRAY_SIZE(mmpll_p_vco),
172
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.clkr.hw.init = &(struct clk_init_data){
173
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.name = "mmpll3_early",
174
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.parent_data = &(const struct clk_parent_data){
175
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.fw_name = "xo",
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},
177
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
179
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},
180
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};
181
+
182
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static struct clk_alpha_pll_postdiv mmpll3 = {
183
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.offset = 0x60,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
185
+
.width = 4,
186
+
.clkr.hw.init = &(struct clk_init_data){
187
+
.name = "mmpll3",
188
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.parent_hws = (const struct clk_hw *[]){ &mmpll3_early.clkr.hw },
189
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.num_parents = 1,
190
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.ops = &clk_alpha_pll_postdiv_ops,
191
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.flags = CLK_SET_RATE_PARENT,
192
+
},
193
+
};
194
+
195
+
static struct clk_alpha_pll mmpll4_early = {
196
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.offset = 0x90,
197
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
198
+
.vco_table = mmpll_t_vco,
199
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.num_vco = ARRAY_SIZE(mmpll_t_vco),
200
+
.clkr.hw.init = &(struct clk_init_data){
201
+
.name = "mmpll4_early",
202
+
.parent_data = &(const struct clk_parent_data){
203
+
.fw_name = "xo",
204
+
},
205
+
.num_parents = 1,
206
+
.ops = &clk_alpha_pll_ops,
207
+
},
208
+
};
209
+
210
+
static struct clk_alpha_pll_postdiv mmpll4 = {
211
+
.offset = 0x90,
212
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
213
+
.width = 2,
214
+
.clkr.hw.init = &(struct clk_init_data){
215
+
.name = "mmpll4",
216
+
.parent_hws = (const struct clk_hw *[]){ &mmpll4_early.clkr.hw },
217
+
.num_parents = 1,
218
+
.ops = &clk_alpha_pll_postdiv_ops,
219
+
.flags = CLK_SET_RATE_PARENT,
220
+
},
221
+
};
222
+
223
+
static const struct parent_map mmcc_xo_gpll0_mmpll1_map[] = {
224
+
{ P_XO, 0 },
225
+
{ P_GPLL0, 5 },
226
+
{ P_MMPLL1, 2 }
227
+
};
228
+
229
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static const struct clk_parent_data mmcc_xo_gpll0_mmpll1[] = {
230
+
{ .fw_name = "xo" },
231
+
{ .fw_name = "gpll0" },
232
+
{ .hw = &mmpll1.clkr.hw },
233
+
};
234
+
235
+
static const struct parent_map mmcc_xo_gpll0_mmpll0_map[] = {
236
+
{ P_XO, 0 },
237
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{ P_GPLL0, 5 },
238
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{ P_MMPLL0, 1 }
239
+
};
240
+
241
+
static const struct clk_parent_data mmcc_xo_gpll0_mmpll0[] = {
242
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{ .fw_name = "xo" },
243
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{ .fw_name = "gpll0" },
244
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{ .hw = &mmpll0.clkr.hw },
245
+
};
246
+
247
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static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll3_map[] = {
248
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{ P_XO, 0 },
249
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{ P_GPLL0, 5 },
250
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{ P_MMPLL0, 1 },
251
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{ P_MMPLL3, 3 }
252
+
};
253
+
254
+
static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll3[] = {
255
+
{ .fw_name = "xo" },
256
+
{ .fw_name = "gpll0" },
257
+
{ .hw = &mmpll0.clkr.hw },
258
+
{ .hw = &mmpll3.clkr.hw },
259
+
};
260
+
261
+
static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll4_map[] = {
262
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{ P_XO, 0 },
263
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{ P_GPLL0, 5 },
264
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{ P_MMPLL0, 1 },
265
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{ P_MMPLL4, 3 }
266
+
};
267
+
268
+
static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll4[] = {
269
+
{ .fw_name = "xo" },
270
+
{ .fw_name = "gpll0" },
271
+
{ .hw = &mmpll0.clkr.hw },
272
+
{ .hw = &mmpll4.clkr.hw },
273
+
};
274
+
275
+
static struct clk_alpha_pll mmpll5_early = {
276
+
.offset = 0xc0,
277
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
278
+
.vco_table = mmpll_p_vco,
279
+
.num_vco = ARRAY_SIZE(mmpll_p_vco),
280
+
.clkr.hw.init = &(struct clk_init_data){
281
+
.name = "mmpll5_early",
282
+
.parent_data = &(const struct clk_parent_data){
283
+
.fw_name = "xo",
284
+
},
285
+
.num_parents = 1,
286
+
.ops = &clk_alpha_pll_ops,
287
+
},
288
+
};
289
+
290
+
static struct clk_alpha_pll_postdiv mmpll5 = {
291
+
.offset = 0xc0,
292
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
293
+
.width = 4,
294
+
.clkr.hw.init = &(struct clk_init_data){
295
+
.name = "mmpll5",
296
+
.parent_hws = (const struct clk_hw *[]){ &mmpll5_early.clkr.hw },
297
+
.num_parents = 1,
298
+
.ops = &clk_alpha_pll_postdiv_ops,
299
+
.flags = CLK_SET_RATE_PARENT,
300
+
},
301
+
};
302
+
303
+
static const struct freq_tbl ftbl_ahb_clk_src[] = {
304
+
/* Note: There might be more frequencies desired here. */
305
+
F(19200000, P_XO, 1, 0, 0),
306
+
F(40000000, P_GPLL0, 15, 0, 0),
307
+
F(80000000, P_MMPLL0, 10, 0, 0),
308
+
{ }
309
+
};
310
+
311
+
static struct clk_rcg2 ahb_clk_src = {
312
+
.cmd_rcgr = 0x5000,
313
+
.hid_width = 5,
314
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
315
+
.freq_tbl = ftbl_ahb_clk_src,
316
+
.clkr.hw.init = &(struct clk_init_data){
317
+
.name = "ahb_clk_src",
318
+
.parent_data = mmcc_xo_gpll0_mmpll0,
319
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
320
+
.ops = &clk_rcg2_ops,
321
+
},
322
+
};
323
+
324
+
static const struct freq_tbl ftbl_axi_clk_src[] = {
325
+
F(75000000, P_GPLL0, 8, 0, 0),
326
+
F(150000000, P_GPLL0, 4, 0, 0),
327
+
F(333430000, P_MMPLL1, 3.5, 0, 0),
328
+
F(466800000, P_MMPLL1, 2.5, 0, 0),
329
+
{ }
330
+
};
331
+
332
+
static struct clk_rcg2 axi_clk_src = {
333
+
.cmd_rcgr = 0x5040,
334
+
.hid_width = 5,
335
+
.parent_map = mmcc_xo_gpll0_mmpll1_map,
336
+
.freq_tbl = ftbl_axi_clk_src,
337
+
.clkr.hw.init = &(struct clk_init_data){
338
+
.name = "axi_clk_src",
339
+
.parent_data = mmcc_xo_gpll0_mmpll1,
340
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll1),
341
+
.ops = &clk_rcg2_ops,
342
+
},
343
+
};
344
+
345
+
static const struct freq_tbl ftbl_csi0_1_2_3_clk_src[] = {
346
+
F(100000000, P_GPLL0, 6, 0, 0),
347
+
F(240000000, P_GPLL0, 2.5, 0, 0),
348
+
F(266670000, P_MMPLL0, 3, 0, 0),
349
+
{ }
350
+
};
351
+
352
+
static struct clk_rcg2 csi0_clk_src = {
353
+
.cmd_rcgr = 0x3090,
354
+
.hid_width = 5,
355
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
356
+
.freq_tbl = ftbl_csi0_1_2_3_clk_src,
357
+
.clkr.hw.init = &(struct clk_init_data){
358
+
.name = "csi0_clk_src",
359
+
.parent_data = mmcc_xo_gpll0_mmpll0,
360
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
361
+
.ops = &clk_rcg2_ops,
362
+
},
363
+
};
364
+
365
+
static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
366
+
F(66670000, P_GPLL0, 9, 0, 0),
367
+
F(100000000, P_GPLL0, 6, 0, 0),
368
+
F(133330000, P_GPLL0, 4.5, 0, 0),
369
+
F(150000000, P_GPLL0, 4, 0, 0),
370
+
F(200000000, P_MMPLL0, 4, 0, 0),
371
+
F(240000000, P_GPLL0, 2.5, 0, 0),
372
+
F(266670000, P_MMPLL0, 3, 0, 0),
373
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
374
+
F(510000000, P_MMPLL3, 2, 0, 0),
375
+
{ }
376
+
};
377
+
378
+
static struct clk_rcg2 vcodec0_clk_src = {
379
+
.cmd_rcgr = 0x1000,
380
+
.mnd_width = 8,
381
+
.hid_width = 5,
382
+
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll3_map,
383
+
.freq_tbl = ftbl_vcodec0_clk_src,
384
+
.clkr.hw.init = &(struct clk_init_data){
385
+
.name = "vcodec0_clk_src",
386
+
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll3,
387
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll3),
388
+
.ops = &clk_rcg2_ops,
389
+
},
390
+
};
391
+
392
+
static struct clk_rcg2 csi1_clk_src = {
393
+
.cmd_rcgr = 0x3100,
394
+
.hid_width = 5,
395
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
396
+
.freq_tbl = ftbl_csi0_1_2_3_clk_src,
397
+
.clkr.hw.init = &(struct clk_init_data){
398
+
.name = "csi1_clk_src",
399
+
.parent_data = mmcc_xo_gpll0_mmpll0,
400
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
401
+
.ops = &clk_rcg2_ops,
402
+
},
403
+
};
404
+
405
+
static struct clk_rcg2 csi2_clk_src = {
406
+
.cmd_rcgr = 0x3160,
407
+
.hid_width = 5,
408
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
409
+
.freq_tbl = ftbl_csi0_1_2_3_clk_src,
410
+
.clkr.hw.init = &(struct clk_init_data){
411
+
.name = "csi2_clk_src",
412
+
.parent_data = mmcc_xo_gpll0_mmpll0,
413
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
414
+
.ops = &clk_rcg2_ops,
415
+
},
416
+
};
417
+
418
+
static struct clk_rcg2 csi3_clk_src = {
419
+
.cmd_rcgr = 0x31c0,
420
+
.hid_width = 5,
421
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
422
+
.freq_tbl = ftbl_csi0_1_2_3_clk_src,
423
+
.clkr.hw.init = &(struct clk_init_data){
424
+
.name = "csi3_clk_src",
425
+
.parent_data = mmcc_xo_gpll0_mmpll0,
426
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
427
+
.ops = &clk_rcg2_ops,
428
+
},
429
+
};
430
+
431
+
static const struct freq_tbl ftbl_vfe0_clk_src[] = {
432
+
F(80000000, P_GPLL0, 7.5, 0, 0),
433
+
F(100000000, P_GPLL0, 6, 0, 0),
434
+
F(200000000, P_GPLL0, 3, 0, 0),
435
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
436
+
F(400000000, P_MMPLL0, 2, 0, 0),
437
+
F(480000000, P_MMPLL4, 2, 0, 0),
438
+
F(533330000, P_MMPLL0, 1.5, 0, 0),
439
+
F(600000000, P_GPLL0, 1, 0, 0),
440
+
{ }
441
+
};
442
+
443
+
static struct clk_rcg2 vfe0_clk_src = {
444
+
.cmd_rcgr = 0x3600,
445
+
.hid_width = 5,
446
+
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
447
+
.freq_tbl = ftbl_vfe0_clk_src,
448
+
.clkr.hw.init = &(struct clk_init_data){
449
+
.name = "vfe0_clk_src",
450
+
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
451
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
452
+
.ops = &clk_rcg2_ops,
453
+
},
454
+
};
455
+
456
+
static const struct freq_tbl ftbl_vfe1_clk_src[] = {
457
+
F(80000000, P_GPLL0, 7.5, 0, 0),
458
+
F(100000000, P_GPLL0, 6, 0, 0),
459
+
F(200000000, P_GPLL0, 3, 0, 0),
460
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
461
+
F(400000000, P_MMPLL0, 2, 0, 0),
462
+
F(533330000, P_MMPLL0, 1.5, 0, 0),
463
+
{ }
464
+
};
465
+
466
+
static struct clk_rcg2 vfe1_clk_src = {
467
+
.cmd_rcgr = 0x3620,
468
+
.hid_width = 5,
469
+
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
470
+
.freq_tbl = ftbl_vfe1_clk_src,
471
+
.clkr.hw.init = &(struct clk_init_data){
472
+
.name = "vfe1_clk_src",
473
+
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
474
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
475
+
.ops = &clk_rcg2_ops,
476
+
},
477
+
};
478
+
479
+
static const struct freq_tbl ftbl_cpp_clk_src[] = {
480
+
F(100000000, P_GPLL0, 6, 0, 0),
481
+
F(200000000, P_GPLL0, 3, 0, 0),
482
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
483
+
F(480000000, P_MMPLL4, 2, 0, 0),
484
+
F(600000000, P_GPLL0, 1, 0, 0),
485
+
F(640000000, P_MMPLL4, 1.5, 0, 0),
486
+
{ }
487
+
};
488
+
489
+
static struct clk_rcg2 cpp_clk_src = {
490
+
.cmd_rcgr = 0x3640,
491
+
.hid_width = 5,
492
+
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
493
+
.freq_tbl = ftbl_cpp_clk_src,
494
+
.clkr.hw.init = &(struct clk_init_data){
495
+
.name = "cpp_clk_src",
496
+
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
497
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
498
+
.ops = &clk_rcg2_ops,
499
+
},
500
+
};
501
+
502
+
static const struct freq_tbl ftbl_jpeg0_1_clk_src[] = {
503
+
F(75000000, P_GPLL0, 8, 0, 0),
504
+
F(150000000, P_GPLL0, 4, 0, 0),
505
+
F(228570000, P_MMPLL0, 3.5, 0, 0),
506
+
F(266670000, P_MMPLL0, 3, 0, 0),
507
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
508
+
F(480000000, P_MMPLL4, 2, 0, 0),
509
+
{ }
510
+
};
511
+
512
+
static struct clk_rcg2 jpeg1_clk_src = {
513
+
.cmd_rcgr = 0x3520,
514
+
.hid_width = 5,
515
+
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
516
+
.freq_tbl = ftbl_jpeg0_1_clk_src,
517
+
.clkr.hw.init = &(struct clk_init_data){
518
+
.name = "jpeg1_clk_src",
519
+
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
520
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
521
+
.ops = &clk_rcg2_ops,
522
+
},
523
+
};
524
+
525
+
static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
526
+
F(75000000, P_GPLL0, 8, 0, 0),
527
+
F(133330000, P_GPLL0, 4.5, 0, 0),
528
+
F(150000000, P_GPLL0, 4, 0, 0),
529
+
F(228570000, P_MMPLL0, 3.5, 0, 0),
530
+
F(266670000, P_MMPLL0, 3, 0, 0),
531
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
532
+
{ }
533
+
};
534
+
535
+
static struct clk_rcg2 jpeg2_clk_src = {
536
+
.cmd_rcgr = 0x3540,
537
+
.hid_width = 5,
538
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
539
+
.freq_tbl = ftbl_jpeg2_clk_src,
540
+
.clkr.hw.init = &(struct clk_init_data){
541
+
.name = "jpeg2_clk_src",
542
+
.parent_data = mmcc_xo_gpll0_mmpll0,
543
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
544
+
.ops = &clk_rcg2_ops,
545
+
},
546
+
};
547
+
548
+
static const struct freq_tbl ftbl_csi2phytimer_clk_src[] = {
549
+
F(50000000, P_GPLL0, 12, 0, 0),
550
+
F(100000000, P_GPLL0, 6, 0, 0),
551
+
F(200000000, P_MMPLL0, 4, 0, 0),
552
+
{ }
553
+
};
554
+
555
+
static struct clk_rcg2 csi2phytimer_clk_src = {
556
+
.cmd_rcgr = 0x3060,
557
+
.hid_width = 5,
558
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
559
+
.freq_tbl = ftbl_csi2phytimer_clk_src,
560
+
.clkr.hw.init = &(struct clk_init_data){
561
+
.name = "csi2phytimer_clk_src",
562
+
.parent_data = mmcc_xo_gpll0_mmpll0,
563
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
564
+
.ops = &clk_rcg2_ops,
565
+
},
566
+
};
567
+
568
+
static const struct freq_tbl ftbl_fd_core_clk_src[] = {
569
+
F(60000000, P_GPLL0, 10, 0, 0),
570
+
F(200000000, P_GPLL0, 3, 0, 0),
571
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
572
+
F(400000000, P_MMPLL0, 2, 0, 0),
573
+
{ }
574
+
};
575
+
576
+
static struct clk_rcg2 fd_core_clk_src = {
577
+
.cmd_rcgr = 0x3b00,
578
+
.hid_width = 5,
579
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
580
+
.freq_tbl = ftbl_fd_core_clk_src,
581
+
.clkr.hw.init = &(struct clk_init_data){
582
+
.name = "fd_core_clk_src",
583
+
.parent_data = mmcc_xo_gpll0_mmpll0,
584
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
585
+
.ops = &clk_rcg2_ops,
586
+
},
587
+
};
588
+
589
+
static const struct freq_tbl ftbl_mdp_clk_src[] = {
590
+
F(85710000, P_GPLL0, 7, 0, 0),
591
+
F(100000000, P_GPLL0, 6, 0, 0),
592
+
F(120000000, P_GPLL0, 5, 0, 0),
593
+
F(150000000, P_GPLL0, 4, 0, 0),
594
+
F(171430000, P_GPLL0, 3.5, 0, 0),
595
+
F(200000000, P_GPLL0, 3, 0, 0),
596
+
F(240000000, P_GPLL0, 2.5, 0, 0),
597
+
F(266670000, P_MMPLL0, 3, 0, 0),
598
+
F(300000000, P_GPLL0, 2, 0, 0),
599
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
600
+
F(400000000, P_MMPLL0, 2, 0, 0),
601
+
{ }
602
+
};
603
+
604
+
static struct clk_rcg2 mdp_clk_src = {
605
+
.cmd_rcgr = 0x2040,
606
+
.hid_width = 5,
607
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
608
+
.freq_tbl = ftbl_mdp_clk_src,
609
+
.clkr.hw.init = &(struct clk_init_data){
610
+
.name = "mdp_clk_src",
611
+
.parent_data = mmcc_xo_gpll0_mmpll0,
612
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
613
+
.ops = &clk_rcg2_ops,
614
+
},
615
+
};
616
+
617
+
static struct clk_rcg2 pclk0_clk_src = {
618
+
.cmd_rcgr = 0x2000,
619
+
.mnd_width = 8,
620
+
.hid_width = 5,
621
+
.parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
622
+
.clkr.hw.init = &(struct clk_init_data){
623
+
.name = "pclk0_clk_src",
624
+
.parent_data = mmcc_xo_dsi0pll_dsi1pll,
625
+
.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
626
+
.ops = &clk_pixel_ops,
627
+
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
628
+
},
629
+
};
630
+
631
+
static struct clk_rcg2 pclk1_clk_src = {
632
+
.cmd_rcgr = 0x2020,
633
+
.mnd_width = 8,
634
+
.hid_width = 5,
635
+
.parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
636
+
.clkr.hw.init = &(struct clk_init_data){
637
+
.name = "pclk1_clk_src",
638
+
.parent_data = mmcc_xo_dsi0pll_dsi1pll,
639
+
.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
640
+
.ops = &clk_pixel_ops,
641
+
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
642
+
},
643
+
};
644
+
645
+
static const struct freq_tbl ftbl_ocmemnoc_clk_src[] = {
646
+
F(19200000, P_XO, 1, 0, 0),
647
+
F(75000000, P_GPLL0, 8, 0, 0),
648
+
F(100000000, P_GPLL0, 6, 0, 0),
649
+
F(150000000, P_GPLL0, 4, 0, 0),
650
+
F(228570000, P_MMPLL0, 3.5, 0, 0),
651
+
F(266670000, P_MMPLL0, 3, 0, 0),
652
+
F(320000000, P_MMPLL0, 2.5, 0, 0),
653
+
F(400000000, P_MMPLL0, 2, 0, 0),
654
+
{ }
655
+
};
656
+
657
+
static struct clk_rcg2 ocmemnoc_clk_src = {
658
+
.cmd_rcgr = 0x5090,
659
+
.hid_width = 5,
660
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
661
+
.freq_tbl = ftbl_ocmemnoc_clk_src,
662
+
.clkr.hw.init = &(struct clk_init_data){
663
+
.name = "ocmemnoc_clk_src",
664
+
.parent_data = mmcc_xo_gpll0_mmpll0,
665
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
666
+
.ops = &clk_rcg2_ops,
667
+
},
668
+
};
669
+
670
+
static const struct freq_tbl ftbl_cci_clk_src[] = {
671
+
F(19200000, P_XO, 1, 0, 0),
672
+
F(37500000, P_GPLL0, 16, 0, 0),
673
+
F(50000000, P_GPLL0, 12, 0, 0),
674
+
F(100000000, P_GPLL0, 6, 0, 0),
675
+
{ }
676
+
};
677
+
678
+
static struct clk_rcg2 cci_clk_src = {
679
+
.cmd_rcgr = 0x3300,
680
+
.mnd_width = 8,
681
+
.hid_width = 5,
682
+
.parent_map = mmcc_xo_gpll0_map,
683
+
.freq_tbl = ftbl_cci_clk_src,
684
+
.clkr.hw.init = &(struct clk_init_data){
685
+
.name = "cci_clk_src",
686
+
.parent_data = mmcc_xo_gpll0,
687
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
688
+
.ops = &clk_rcg2_ops,
689
+
},
690
+
};
691
+
692
+
static const struct freq_tbl ftbl_mmss_gp0_1_clk_src[] = {
693
+
F(10000, P_XO, 16, 10, 120),
694
+
F(24000, P_GPLL0, 16, 1, 50),
695
+
F(6000000, P_GPLL0, 10, 1, 10),
696
+
F(12000000, P_GPLL0, 10, 1, 5),
697
+
F(13000000, P_GPLL0, 4, 13, 150),
698
+
F(24000000, P_GPLL0, 5, 1, 5),
699
+
{ }
700
+
};
701
+
702
+
static struct clk_rcg2 mmss_gp0_clk_src = {
703
+
.cmd_rcgr = 0x3420,
704
+
.mnd_width = 8,
705
+
.hid_width = 5,
706
+
.parent_map = mmcc_xo_gpll0_map,
707
+
.freq_tbl = ftbl_mmss_gp0_1_clk_src,
708
+
.clkr.hw.init = &(struct clk_init_data){
709
+
.name = "mmss_gp0_clk_src",
710
+
.parent_data = mmcc_xo_gpll0,
711
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
712
+
.ops = &clk_rcg2_ops,
713
+
},
714
+
};
715
+
716
+
static struct clk_rcg2 mmss_gp1_clk_src = {
717
+
.cmd_rcgr = 0x3450,
718
+
.mnd_width = 8,
719
+
.hid_width = 5,
720
+
.parent_map = mmcc_xo_gpll0_map,
721
+
.freq_tbl = ftbl_mmss_gp0_1_clk_src,
722
+
.clkr.hw.init = &(struct clk_init_data){
723
+
.name = "mmss_gp1_clk_src",
724
+
.parent_data = mmcc_xo_gpll0,
725
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
726
+
.ops = &clk_rcg2_ops,
727
+
},
728
+
};
729
+
730
+
static struct clk_rcg2 jpeg0_clk_src = {
731
+
.cmd_rcgr = 0x3500,
732
+
.hid_width = 5,
733
+
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
734
+
.freq_tbl = ftbl_jpeg0_1_clk_src,
735
+
.clkr.hw.init = &(struct clk_init_data){
736
+
.name = "jpeg0_clk_src",
737
+
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
738
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
739
+
.ops = &clk_rcg2_ops,
740
+
},
741
+
};
742
+
743
+
static struct clk_rcg2 jpeg_dma_clk_src = {
744
+
.cmd_rcgr = 0x3560,
745
+
.hid_width = 5,
746
+
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
747
+
.freq_tbl = ftbl_jpeg0_1_clk_src,
748
+
.clkr.hw.init = &(struct clk_init_data){
749
+
.name = "jpeg_dma_clk_src",
750
+
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
751
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
752
+
.ops = &clk_rcg2_ops,
753
+
},
754
+
};
755
+
756
+
static const struct freq_tbl ftbl_mclk0_1_2_3_clk_src[] = {
757
+
F(4800000, P_XO, 4, 0, 0),
758
+
F(6000000, P_GPLL0, 10, 1, 10),
759
+
F(8000000, P_GPLL0, 15, 1, 5),
760
+
F(9600000, P_XO, 2, 0, 0),
761
+
F(16000000, P_MMPLL0, 10, 1, 5),
762
+
F(19200000, P_XO, 1, 0, 0),
763
+
F(24000000, P_GPLL0, 5, 1, 5),
764
+
F(32000000, P_MMPLL0, 5, 1, 5),
765
+
F(48000000, P_GPLL0, 12.5, 0, 0),
766
+
F(64000000, P_MMPLL0, 12.5, 0, 0),
767
+
{ }
768
+
};
769
+
770
+
static struct clk_rcg2 mclk0_clk_src = {
771
+
.cmd_rcgr = 0x3360,
772
+
.mnd_width = 8,
773
+
.hid_width = 5,
774
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
775
+
.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
776
+
.clkr.hw.init = &(struct clk_init_data){
777
+
.name = "mclk0_clk_src",
778
+
.parent_data = mmcc_xo_gpll0_mmpll0,
779
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
780
+
.ops = &clk_rcg2_ops,
781
+
},
782
+
};
783
+
784
+
static struct clk_rcg2 mclk1_clk_src = {
785
+
.cmd_rcgr = 0x3390,
786
+
.mnd_width = 8,
787
+
.hid_width = 5,
788
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
789
+
.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
790
+
.clkr.hw.init = &(struct clk_init_data){
791
+
.name = "mclk1_clk_src",
792
+
.parent_data = mmcc_xo_gpll0_mmpll0,
793
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
794
+
.ops = &clk_rcg2_ops,
795
+
},
796
+
};
797
+
798
+
static struct clk_rcg2 mclk2_clk_src = {
799
+
.cmd_rcgr = 0x33c0,
800
+
.mnd_width = 8,
801
+
.hid_width = 5,
802
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
803
+
.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
804
+
.clkr.hw.init = &(struct clk_init_data){
805
+
.name = "mclk2_clk_src",
806
+
.parent_data = mmcc_xo_gpll0_mmpll0,
807
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
808
+
.ops = &clk_rcg2_ops,
809
+
},
810
+
};
811
+
812
+
static struct clk_rcg2 mclk3_clk_src = {
813
+
.cmd_rcgr = 0x33f0,
814
+
.mnd_width = 8,
815
+
.hid_width = 5,
816
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
817
+
.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
818
+
.clkr.hw.init = &(struct clk_init_data){
819
+
.name = "mclk3_clk_src",
820
+
.parent_data = mmcc_xo_gpll0_mmpll0,
821
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
822
+
.ops = &clk_rcg2_ops,
823
+
},
824
+
};
825
+
826
+
static const struct freq_tbl ftbl_csi0_1phytimer_clk_src[] = {
827
+
F(50000000, P_GPLL0, 12, 0, 0),
828
+
F(100000000, P_GPLL0, 6, 0, 0),
829
+
F(200000000, P_MMPLL0, 4, 0, 0),
830
+
{ }
831
+
};
832
+
833
+
static struct clk_rcg2 csi0phytimer_clk_src = {
834
+
.cmd_rcgr = 0x3000,
835
+
.hid_width = 5,
836
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
837
+
.freq_tbl = ftbl_csi0_1phytimer_clk_src,
838
+
.clkr.hw.init = &(struct clk_init_data){
839
+
.name = "csi0phytimer_clk_src",
840
+
.parent_data = mmcc_xo_gpll0_mmpll0,
841
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
842
+
.ops = &clk_rcg2_ops,
843
+
},
844
+
};
845
+
846
+
static struct clk_rcg2 csi1phytimer_clk_src = {
847
+
.cmd_rcgr = 0x3030,
848
+
.hid_width = 5,
849
+
.parent_map = mmcc_xo_gpll0_mmpll0_map,
850
+
.freq_tbl = ftbl_csi0_1phytimer_clk_src,
851
+
.clkr.hw.init = &(struct clk_init_data){
852
+
.name = "csi1phytimer_clk_src",
853
+
.parent_data = mmcc_xo_gpll0_mmpll0,
854
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
855
+
.ops = &clk_rcg2_ops,
856
+
},
857
+
};
858
+
859
+
static struct clk_rcg2 byte0_clk_src = {
860
+
.cmd_rcgr = 0x2120,
861
+
.hid_width = 5,
862
+
.parent_map = mmcc_xo_dsibyte_map,
863
+
.clkr.hw.init = &(struct clk_init_data){
864
+
.name = "byte0_clk_src",
865
+
.parent_data = mmcc_xo_dsibyte,
866
+
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
867
+
.ops = &clk_byte2_ops,
868
+
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
869
+
},
870
+
};
871
+
872
+
static struct clk_rcg2 byte1_clk_src = {
873
+
.cmd_rcgr = 0x2140,
874
+
.hid_width = 5,
875
+
.parent_map = mmcc_xo_dsibyte_map,
876
+
.clkr.hw.init = &(struct clk_init_data){
877
+
.name = "byte1_clk_src",
878
+
.parent_data = mmcc_xo_dsibyte,
879
+
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
880
+
.ops = &clk_byte2_ops,
881
+
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
882
+
},
883
+
};
884
+
885
+
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
886
+
F(19200000, P_XO, 1, 0, 0),
887
+
{ }
888
+
};
889
+
890
+
static struct clk_rcg2 esc0_clk_src = {
891
+
.cmd_rcgr = 0x2160,
892
+
.hid_width = 5,
893
+
.parent_map = mmcc_xo_dsibyte_map,
894
+
.freq_tbl = ftbl_mdss_esc0_1_clk,
895
+
.clkr.hw.init = &(struct clk_init_data){
896
+
.name = "esc0_clk_src",
897
+
.parent_data = mmcc_xo_dsibyte,
898
+
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
899
+
.ops = &clk_rcg2_ops,
900
+
},
901
+
};
902
+
903
+
static struct clk_rcg2 esc1_clk_src = {
904
+
.cmd_rcgr = 0x2180,
905
+
.hid_width = 5,
906
+
.parent_map = mmcc_xo_dsibyte_map,
907
+
.freq_tbl = ftbl_mdss_esc0_1_clk,
908
+
.clkr.hw.init = &(struct clk_init_data){
909
+
.name = "esc1_clk_src",
910
+
.parent_data = mmcc_xo_dsibyte,
911
+
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
912
+
.ops = &clk_rcg2_ops,
913
+
},
914
+
};
915
+
916
+
static struct freq_tbl extpclk_freq_tbl[] = {
917
+
{ .src = P_HDMIPLL },
918
+
{ }
919
+
};
920
+
921
+
static struct clk_rcg2 extpclk_clk_src = {
922
+
.cmd_rcgr = 0x2060,
923
+
.hid_width = 5,
924
+
.parent_map = mmss_xo_hdmi_map,
925
+
.freq_tbl = extpclk_freq_tbl,
926
+
.clkr.hw.init = &(struct clk_init_data){
927
+
.name = "extpclk_clk_src",
928
+
.parent_data = mmss_xo_hdmi,
929
+
.num_parents = ARRAY_SIZE(mmss_xo_hdmi),
930
+
.ops = &clk_rcg2_ops,
931
+
.flags = CLK_SET_RATE_PARENT,
932
+
},
933
+
};
934
+
935
+
static struct freq_tbl ftbl_hdmi_clk_src[] = {
936
+
F(19200000, P_XO, 1, 0, 0),
937
+
{ }
938
+
};
939
+
940
+
static struct clk_rcg2 hdmi_clk_src = {
941
+
.cmd_rcgr = 0x2100,
942
+
.hid_width = 5,
943
+
.parent_map = mmcc_xo_gpll0_map,
944
+
.freq_tbl = ftbl_hdmi_clk_src,
945
+
.clkr.hw.init = &(struct clk_init_data){
946
+
.name = "hdmi_clk_src",
947
+
.parent_data = mmcc_xo_gpll0,
948
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
949
+
.ops = &clk_rcg2_ops,
950
+
},
951
+
};
952
+
953
+
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
954
+
F(19200000, P_XO, 1, 0, 0),
955
+
{ }
956
+
};
957
+
958
+
static struct clk_rcg2 vsync_clk_src = {
959
+
.cmd_rcgr = 0x2080,
960
+
.hid_width = 5,
961
+
.parent_map = mmcc_xo_gpll0_map,
962
+
.freq_tbl = ftbl_mdss_vsync_clk,
963
+
.clkr.hw.init = &(struct clk_init_data){
964
+
.name = "vsync_clk_src",
965
+
.parent_data = mmcc_xo_gpll0,
966
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
967
+
.ops = &clk_rcg2_ops,
968
+
},
969
+
};
970
+
971
+
static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
972
+
F(19200000, P_XO, 1, 0, 0),
973
+
{ }
974
+
};
975
+
976
+
static struct clk_rcg2 rbbmtimer_clk_src = {
977
+
.cmd_rcgr = 0x4090,
978
+
.hid_width = 5,
979
+
.parent_map = mmcc_xo_gpll0_map,
980
+
.freq_tbl = ftbl_rbbmtimer_clk_src,
981
+
.clkr.hw.init = &(struct clk_init_data){
982
+
.name = "rbbmtimer_clk_src",
983
+
.parent_data = mmcc_xo_gpll0,
984
+
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
985
+
.ops = &clk_rcg2_ops,
986
+
},
987
+
};
988
+
989
+
static struct clk_branch camss_ahb_clk = {
990
+
.halt_reg = 0x348c,
991
+
.clkr = {
992
+
.enable_reg = 0x348c,
993
+
.enable_mask = BIT(0),
994
+
.hw.init = &(struct clk_init_data){
995
+
.name = "camss_ahb_clk",
996
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
997
+
.num_parents = 1,
998
+
.flags = CLK_SET_RATE_PARENT,
999
+
.ops = &clk_branch2_ops,
1000
+
},
1001
+
},
1002
+
};
1003
+
1004
+
static struct clk_branch camss_cci_cci_ahb_clk = {
1005
+
.halt_reg = 0x3348,
1006
+
.clkr = {
1007
+
.enable_reg = 0x3348,
1008
+
.enable_mask = BIT(0),
1009
+
.hw.init = &(struct clk_init_data){
1010
+
.name = "camss_cci_cci_ahb_clk",
1011
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1012
+
.num_parents = 1,
1013
+
.flags = CLK_SET_RATE_PARENT,
1014
+
.ops = &clk_branch2_ops,
1015
+
},
1016
+
},
1017
+
};
1018
+
1019
+
static struct clk_branch camss_cci_cci_clk = {
1020
+
.halt_reg = 0x3344,
1021
+
.clkr = {
1022
+
.enable_reg = 0x3344,
1023
+
.enable_mask = BIT(0),
1024
+
.hw.init = &(struct clk_init_data){
1025
+
.name = "camss_cci_cci_clk",
1026
+
.parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1027
+
.num_parents = 1,
1028
+
.ops = &clk_branch2_ops,
1029
+
},
1030
+
},
1031
+
};
1032
+
1033
+
static struct clk_branch camss_vfe_cpp_ahb_clk = {
1034
+
.halt_reg = 0x36b4,
1035
+
.clkr = {
1036
+
.enable_reg = 0x36b4,
1037
+
.enable_mask = BIT(0),
1038
+
.hw.init = &(struct clk_init_data){
1039
+
.name = "camss_vfe_cpp_ahb_clk",
1040
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1041
+
.num_parents = 1,
1042
+
.flags = CLK_SET_RATE_PARENT,
1043
+
.ops = &clk_branch2_ops,
1044
+
},
1045
+
},
1046
+
};
1047
+
1048
+
static struct clk_branch camss_vfe_cpp_axi_clk = {
1049
+
.halt_reg = 0x36c4,
1050
+
.clkr = {
1051
+
.enable_reg = 0x36c4,
1052
+
.enable_mask = BIT(0),
1053
+
.hw.init = &(struct clk_init_data){
1054
+
.name = "camss_vfe_cpp_axi_clk",
1055
+
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1056
+
.num_parents = 1,
1057
+
.ops = &clk_branch2_ops,
1058
+
},
1059
+
},
1060
+
};
1061
+
1062
+
static struct clk_branch camss_vfe_cpp_clk = {
1063
+
.halt_reg = 0x36b0,
1064
+
.clkr = {
1065
+
.enable_reg = 0x36b0,
1066
+
.enable_mask = BIT(0),
1067
+
.hw.init = &(struct clk_init_data){
1068
+
.name = "camss_vfe_cpp_clk",
1069
+
.parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1070
+
.num_parents = 1,
1071
+
.ops = &clk_branch2_ops,
1072
+
},
1073
+
},
1074
+
};
1075
+
1076
+
static struct clk_branch camss_csi0_ahb_clk = {
1077
+
.halt_reg = 0x30bc,
1078
+
.clkr = {
1079
+
.enable_reg = 0x30bc,
1080
+
.enable_mask = BIT(0),
1081
+
.hw.init = &(struct clk_init_data){
1082
+
.name = "camss_csi0_ahb_clk",
1083
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1084
+
.num_parents = 1,
1085
+
.flags = CLK_SET_RATE_PARENT,
1086
+
.ops = &clk_branch2_ops,
1087
+
},
1088
+
},
1089
+
};
1090
+
1091
+
static struct clk_branch camss_csi0_clk = {
1092
+
.halt_reg = 0x30b4,
1093
+
.clkr = {
1094
+
.enable_reg = 0x30b4,
1095
+
.enable_mask = BIT(0),
1096
+
.hw.init = &(struct clk_init_data){
1097
+
.name = "camss_csi0_clk",
1098
+
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1099
+
.num_parents = 1,
1100
+
.ops = &clk_branch2_ops,
1101
+
},
1102
+
},
1103
+
};
1104
+
1105
+
static struct clk_branch camss_csi0phy_clk = {
1106
+
.halt_reg = 0x30c4,
1107
+
.clkr = {
1108
+
.enable_reg = 0x30c4,
1109
+
.enable_mask = BIT(0),
1110
+
.hw.init = &(struct clk_init_data){
1111
+
.name = "camss_csi0phy_clk",
1112
+
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1113
+
.num_parents = 1,
1114
+
.ops = &clk_branch2_ops,
1115
+
},
1116
+
},
1117
+
};
1118
+
1119
+
static struct clk_branch camss_csi0pix_clk = {
1120
+
.halt_reg = 0x30e4,
1121
+
.clkr = {
1122
+
.enable_reg = 0x30e4,
1123
+
.enable_mask = BIT(0),
1124
+
.hw.init = &(struct clk_init_data){
1125
+
.name = "camss_csi0pix_clk",
1126
+
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1127
+
.num_parents = 1,
1128
+
.ops = &clk_branch2_ops,
1129
+
},
1130
+
},
1131
+
};
1132
+
1133
+
static struct clk_branch camss_csi0rdi_clk = {
1134
+
.halt_reg = 0x30d4,
1135
+
.clkr = {
1136
+
.enable_reg = 0x30d4,
1137
+
.enable_mask = BIT(0),
1138
+
.hw.init = &(struct clk_init_data){
1139
+
.name = "camss_csi0rdi_clk",
1140
+
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1141
+
.num_parents = 1,
1142
+
.ops = &clk_branch2_ops,
1143
+
},
1144
+
},
1145
+
};
1146
+
1147
+
static struct clk_branch camss_csi1_ahb_clk = {
1148
+
.halt_reg = 0x3128,
1149
+
.clkr = {
1150
+
.enable_reg = 0x3128,
1151
+
.enable_mask = BIT(0),
1152
+
.hw.init = &(struct clk_init_data){
1153
+
.name = "camss_csi1_ahb_clk",
1154
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1155
+
.num_parents = 1,
1156
+
.flags = CLK_SET_RATE_PARENT,
1157
+
.ops = &clk_branch2_ops,
1158
+
},
1159
+
},
1160
+
};
1161
+
1162
+
static struct clk_branch camss_csi1_clk = {
1163
+
.halt_reg = 0x3124,
1164
+
.clkr = {
1165
+
.enable_reg = 0x3124,
1166
+
.enable_mask = BIT(0),
1167
+
.hw.init = &(struct clk_init_data){
1168
+
.name = "camss_csi1_clk",
1169
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1170
+
.num_parents = 1,
1171
+
.ops = &clk_branch2_ops,
1172
+
},
1173
+
},
1174
+
};
1175
+
1176
+
static struct clk_branch camss_csi1phy_clk = {
1177
+
.halt_reg = 0x3134,
1178
+
.clkr = {
1179
+
.enable_reg = 0x3134,
1180
+
.enable_mask = BIT(0),
1181
+
.hw.init = &(struct clk_init_data){
1182
+
.name = "camss_csi1phy_clk",
1183
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1184
+
.num_parents = 1,
1185
+
.ops = &clk_branch2_ops,
1186
+
},
1187
+
},
1188
+
};
1189
+
1190
+
static struct clk_branch camss_csi1pix_clk = {
1191
+
.halt_reg = 0x3154,
1192
+
.clkr = {
1193
+
.enable_reg = 0x3154,
1194
+
.enable_mask = BIT(0),
1195
+
.hw.init = &(struct clk_init_data){
1196
+
.name = "camss_csi1pix_clk",
1197
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1198
+
.num_parents = 1,
1199
+
.ops = &clk_branch2_ops,
1200
+
},
1201
+
},
1202
+
};
1203
+
1204
+
static struct clk_branch camss_csi1rdi_clk = {
1205
+
.halt_reg = 0x3144,
1206
+
.clkr = {
1207
+
.enable_reg = 0x3144,
1208
+
.enable_mask = BIT(0),
1209
+
.hw.init = &(struct clk_init_data){
1210
+
.name = "camss_csi1rdi_clk",
1211
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1212
+
.num_parents = 1,
1213
+
.ops = &clk_branch2_ops,
1214
+
},
1215
+
},
1216
+
};
1217
+
1218
+
static struct clk_branch camss_csi2_ahb_clk = {
1219
+
.halt_reg = 0x3188,
1220
+
.clkr = {
1221
+
.enable_reg = 0x3188,
1222
+
.enable_mask = BIT(0),
1223
+
.hw.init = &(struct clk_init_data){
1224
+
.name = "camss_csi2_ahb_clk",
1225
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1226
+
.num_parents = 1,
1227
+
.flags = CLK_SET_RATE_PARENT,
1228
+
.ops = &clk_branch2_ops,
1229
+
},
1230
+
},
1231
+
};
1232
+
1233
+
static struct clk_branch camss_csi2_clk = {
1234
+
.halt_reg = 0x3184,
1235
+
.clkr = {
1236
+
.enable_reg = 0x3184,
1237
+
.enable_mask = BIT(0),
1238
+
.hw.init = &(struct clk_init_data){
1239
+
.name = "camss_csi2_clk",
1240
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1241
+
.num_parents = 1,
1242
+
.ops = &clk_branch2_ops,
1243
+
},
1244
+
},
1245
+
};
1246
+
1247
+
static struct clk_branch camss_csi2phy_clk = {
1248
+
.halt_reg = 0x3194,
1249
+
.clkr = {
1250
+
.enable_reg = 0x3194,
1251
+
.enable_mask = BIT(0),
1252
+
.hw.init = &(struct clk_init_data){
1253
+
.name = "camss_csi2phy_clk",
1254
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1255
+
.num_parents = 1,
1256
+
.ops = &clk_branch2_ops,
1257
+
},
1258
+
},
1259
+
};
1260
+
1261
+
static struct clk_branch camss_csi2pix_clk = {
1262
+
.halt_reg = 0x31b4,
1263
+
.clkr = {
1264
+
.enable_reg = 0x31b4,
1265
+
.enable_mask = BIT(0),
1266
+
.hw.init = &(struct clk_init_data){
1267
+
.name = "camss_csi2pix_clk",
1268
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1269
+
.num_parents = 1,
1270
+
.ops = &clk_branch2_ops,
1271
+
},
1272
+
},
1273
+
};
1274
+
1275
+
static struct clk_branch camss_csi2rdi_clk = {
1276
+
.halt_reg = 0x31a4,
1277
+
.clkr = {
1278
+
.enable_reg = 0x31a4,
1279
+
.enable_mask = BIT(0),
1280
+
.hw.init = &(struct clk_init_data){
1281
+
.name = "camss_csi2rdi_clk",
1282
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1283
+
.num_parents = 1,
1284
+
.ops = &clk_branch2_ops,
1285
+
},
1286
+
},
1287
+
};
1288
+
1289
+
static struct clk_branch camss_csi3_ahb_clk = {
1290
+
.halt_reg = 0x31e8,
1291
+
.clkr = {
1292
+
.enable_reg = 0x31e8,
1293
+
.enable_mask = BIT(0),
1294
+
.hw.init = &(struct clk_init_data){
1295
+
.name = "camss_csi3_ahb_clk",
1296
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1297
+
.num_parents = 1,
1298
+
.flags = CLK_SET_RATE_PARENT,
1299
+
.ops = &clk_branch2_ops,
1300
+
},
1301
+
},
1302
+
};
1303
+
1304
+
static struct clk_branch camss_csi3_clk = {
1305
+
.halt_reg = 0x31e4,
1306
+
.clkr = {
1307
+
.enable_reg = 0x31e4,
1308
+
.enable_mask = BIT(0),
1309
+
.hw.init = &(struct clk_init_data){
1310
+
.name = "camss_csi3_clk",
1311
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1312
+
.num_parents = 1,
1313
+
.ops = &clk_branch2_ops,
1314
+
},
1315
+
},
1316
+
};
1317
+
1318
+
static struct clk_branch camss_csi3phy_clk = {
1319
+
.halt_reg = 0x31f4,
1320
+
.clkr = {
1321
+
.enable_reg = 0x31f4,
1322
+
.enable_mask = BIT(0),
1323
+
.hw.init = &(struct clk_init_data){
1324
+
.name = "camss_csi3phy_clk",
1325
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1326
+
.num_parents = 1,
1327
+
.ops = &clk_branch2_ops,
1328
+
},
1329
+
},
1330
+
};
1331
+
1332
+
static struct clk_branch camss_csi3pix_clk = {
1333
+
.halt_reg = 0x3214,
1334
+
.clkr = {
1335
+
.enable_reg = 0x3214,
1336
+
.enable_mask = BIT(0),
1337
+
.hw.init = &(struct clk_init_data){
1338
+
.name = "camss_csi3pix_clk",
1339
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1340
+
.num_parents = 1,
1341
+
.ops = &clk_branch2_ops,
1342
+
},
1343
+
},
1344
+
};
1345
+
1346
+
static struct clk_branch camss_csi3rdi_clk = {
1347
+
.halt_reg = 0x3204,
1348
+
.clkr = {
1349
+
.enable_reg = 0x3204,
1350
+
.enable_mask = BIT(0),
1351
+
.hw.init = &(struct clk_init_data){
1352
+
.name = "camss_csi3rdi_clk",
1353
+
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1354
+
.num_parents = 1,
1355
+
.ops = &clk_branch2_ops,
1356
+
},
1357
+
},
1358
+
};
1359
+
1360
+
static struct clk_branch camss_csi_vfe0_clk = {
1361
+
.halt_reg = 0x3704,
1362
+
.clkr = {
1363
+
.enable_reg = 0x3704,
1364
+
.enable_mask = BIT(0),
1365
+
.hw.init = &(struct clk_init_data){
1366
+
.name = "camss_csi_vfe0_clk",
1367
+
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1368
+
.num_parents = 1,
1369
+
.ops = &clk_branch2_ops,
1370
+
},
1371
+
},
1372
+
};
1373
+
1374
+
static struct clk_branch camss_csi_vfe1_clk = {
1375
+
.halt_reg = 0x3714,
1376
+
.clkr = {
1377
+
.enable_reg = 0x3714,
1378
+
.enable_mask = BIT(0),
1379
+
.hw.init = &(struct clk_init_data){
1380
+
.name = "camss_csi_vfe1_clk",
1381
+
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1382
+
.num_parents = 1,
1383
+
.ops = &clk_branch2_ops,
1384
+
},
1385
+
},
1386
+
};
1387
+
1388
+
static struct clk_branch camss_gp0_clk = {
1389
+
.halt_reg = 0x3444,
1390
+
.clkr = {
1391
+
.enable_reg = 0x3444,
1392
+
.enable_mask = BIT(0),
1393
+
.hw.init = &(struct clk_init_data){
1394
+
.name = "camss_gp0_clk",
1395
+
.parent_hws = (const struct clk_hw *[]){ &mmss_gp0_clk_src.clkr.hw },
1396
+
.num_parents = 1,
1397
+
.ops = &clk_branch2_ops,
1398
+
},
1399
+
},
1400
+
};
1401
+
1402
+
static struct clk_branch camss_gp1_clk = {
1403
+
.halt_reg = 0x3474,
1404
+
.clkr = {
1405
+
.enable_reg = 0x3474,
1406
+
.enable_mask = BIT(0),
1407
+
.hw.init = &(struct clk_init_data){
1408
+
.name = "camss_gp1_clk",
1409
+
.parent_hws = (const struct clk_hw *[]){ &mmss_gp1_clk_src.clkr.hw },
1410
+
.num_parents = 1,
1411
+
.ops = &clk_branch2_ops,
1412
+
},
1413
+
},
1414
+
};
1415
+
1416
+
static struct clk_branch camss_ispif_ahb_clk = {
1417
+
.halt_reg = 0x3224,
1418
+
.clkr = {
1419
+
.enable_reg = 0x3224,
1420
+
.enable_mask = BIT(0),
1421
+
.hw.init = &(struct clk_init_data){
1422
+
.name = "camss_ispif_ahb_clk",
1423
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1424
+
.num_parents = 1,
1425
+
.flags = CLK_SET_RATE_PARENT,
1426
+
.ops = &clk_branch2_ops,
1427
+
},
1428
+
},
1429
+
};
1430
+
1431
+
static struct clk_branch camss_jpeg_dma_clk = {
1432
+
.halt_reg = 0x35c0,
1433
+
.clkr = {
1434
+
.enable_reg = 0x35c0,
1435
+
.enable_mask = BIT(0),
1436
+
.hw.init = &(struct clk_init_data){
1437
+
.name = "camss_jpeg_dma_clk",
1438
+
.parent_hws = (const struct clk_hw *[]){ &jpeg_dma_clk_src.clkr.hw },
1439
+
.num_parents = 1,
1440
+
.ops = &clk_branch2_ops,
1441
+
},
1442
+
},
1443
+
};
1444
+
1445
+
static struct clk_branch camss_jpeg_jpeg0_clk = {
1446
+
.halt_reg = 0x35a8,
1447
+
.clkr = {
1448
+
.enable_reg = 0x35a8,
1449
+
.enable_mask = BIT(0),
1450
+
.hw.init = &(struct clk_init_data){
1451
+
.name = "camss_jpeg_jpeg0_clk",
1452
+
.parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1453
+
.num_parents = 1,
1454
+
.ops = &clk_branch2_ops,
1455
+
},
1456
+
},
1457
+
};
1458
+
1459
+
static struct clk_branch camss_jpeg_jpeg1_clk = {
1460
+
.halt_reg = 0x35ac,
1461
+
.clkr = {
1462
+
.enable_reg = 0x35ac,
1463
+
.enable_mask = BIT(0),
1464
+
.hw.init = &(struct clk_init_data){
1465
+
.name = "camss_jpeg_jpeg1_clk",
1466
+
.parent_hws = (const struct clk_hw *[]){ &jpeg1_clk_src.clkr.hw },
1467
+
.num_parents = 1,
1468
+
.ops = &clk_branch2_ops,
1469
+
},
1470
+
},
1471
+
};
1472
+
1473
+
static struct clk_branch camss_jpeg_jpeg2_clk = {
1474
+
.halt_reg = 0x35b0,
1475
+
.clkr = {
1476
+
.enable_reg = 0x35b0,
1477
+
.enable_mask = BIT(0),
1478
+
.hw.init = &(struct clk_init_data){
1479
+
.name = "camss_jpeg_jpeg2_clk",
1480
+
.parent_hws = (const struct clk_hw *[]){ &jpeg2_clk_src.clkr.hw },
1481
+
.num_parents = 1,
1482
+
.ops = &clk_branch2_ops,
1483
+
},
1484
+
},
1485
+
};
1486
+
1487
+
static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1488
+
.halt_reg = 0x35b4,
1489
+
.clkr = {
1490
+
.enable_reg = 0x35b4,
1491
+
.enable_mask = BIT(0),
1492
+
.hw.init = &(struct clk_init_data){
1493
+
.name = "camss_jpeg_jpeg_ahb_clk",
1494
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1495
+
.num_parents = 1,
1496
+
.flags = CLK_SET_RATE_PARENT,
1497
+
.ops = &clk_branch2_ops,
1498
+
},
1499
+
},
1500
+
};
1501
+
1502
+
static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1503
+
.halt_reg = 0x35b8,
1504
+
.clkr = {
1505
+
.enable_reg = 0x35b8,
1506
+
.enable_mask = BIT(0),
1507
+
.hw.init = &(struct clk_init_data){
1508
+
.name = "camss_jpeg_jpeg_axi_clk",
1509
+
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1510
+
.num_parents = 1,
1511
+
.ops = &clk_branch2_ops,
1512
+
},
1513
+
},
1514
+
};
1515
+
1516
+
static struct clk_branch camss_mclk0_clk = {
1517
+
.halt_reg = 0x3384,
1518
+
.clkr = {
1519
+
.enable_reg = 0x3384,
1520
+
.enable_mask = BIT(0),
1521
+
.hw.init = &(struct clk_init_data){
1522
+
.name = "camss_mclk0_clk",
1523
+
.parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1524
+
.num_parents = 1,
1525
+
.ops = &clk_branch2_ops,
1526
+
},
1527
+
},
1528
+
};
1529
+
1530
+
static struct clk_branch camss_mclk1_clk = {
1531
+
.halt_reg = 0x33b4,
1532
+
.clkr = {
1533
+
.enable_reg = 0x33b4,
1534
+
.enable_mask = BIT(0),
1535
+
.hw.init = &(struct clk_init_data){
1536
+
.name = "camss_mclk1_clk",
1537
+
.parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1538
+
.num_parents = 1,
1539
+
.ops = &clk_branch2_ops,
1540
+
},
1541
+
},
1542
+
};
1543
+
1544
+
static struct clk_branch camss_mclk2_clk = {
1545
+
.halt_reg = 0x33e4,
1546
+
.clkr = {
1547
+
.enable_reg = 0x33e4,
1548
+
.enable_mask = BIT(0),
1549
+
.hw.init = &(struct clk_init_data){
1550
+
.name = "camss_mclk2_clk",
1551
+
.parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1552
+
.num_parents = 1,
1553
+
.ops = &clk_branch2_ops,
1554
+
},
1555
+
},
1556
+
};
1557
+
1558
+
static struct clk_branch camss_mclk3_clk = {
1559
+
.halt_reg = 0x3414,
1560
+
.clkr = {
1561
+
.enable_reg = 0x3414,
1562
+
.enable_mask = BIT(0),
1563
+
.hw.init = &(struct clk_init_data){
1564
+
.name = "camss_mclk3_clk",
1565
+
.parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1566
+
.num_parents = 1,
1567
+
.ops = &clk_branch2_ops,
1568
+
},
1569
+
},
1570
+
};
1571
+
1572
+
static struct clk_branch camss_micro_ahb_clk = {
1573
+
.halt_reg = 0x3494,
1574
+
.clkr = {
1575
+
.enable_reg = 0x3494,
1576
+
.enable_mask = BIT(0),
1577
+
.hw.init = &(struct clk_init_data){
1578
+
.name = "camss_micro_ahb_clk",
1579
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1580
+
.num_parents = 1,
1581
+
.flags = CLK_SET_RATE_PARENT,
1582
+
.ops = &clk_branch2_ops,
1583
+
},
1584
+
},
1585
+
};
1586
+
1587
+
static struct clk_branch camss_phy0_csi0phytimer_clk = {
1588
+
.halt_reg = 0x3024,
1589
+
.clkr = {
1590
+
.enable_reg = 0x3024,
1591
+
.enable_mask = BIT(0),
1592
+
.hw.init = &(struct clk_init_data){
1593
+
.name = "camss_phy0_csi0phytimer_clk",
1594
+
.parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1595
+
.num_parents = 1,
1596
+
.ops = &clk_branch2_ops,
1597
+
},
1598
+
},
1599
+
};
1600
+
1601
+
static struct clk_branch camss_phy1_csi1phytimer_clk = {
1602
+
.halt_reg = 0x3054,
1603
+
.clkr = {
1604
+
.enable_reg = 0x3054,
1605
+
.enable_mask = BIT(0),
1606
+
.hw.init = &(struct clk_init_data){
1607
+
.name = "camss_phy1_csi1phytimer_clk",
1608
+
.parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1609
+
.num_parents = 1,
1610
+
.ops = &clk_branch2_ops,
1611
+
},
1612
+
},
1613
+
};
1614
+
1615
+
static struct clk_branch camss_phy2_csi2phytimer_clk = {
1616
+
.halt_reg = 0x3084,
1617
+
.clkr = {
1618
+
.enable_reg = 0x3084,
1619
+
.enable_mask = BIT(0),
1620
+
.hw.init = &(struct clk_init_data){
1621
+
.name = "camss_phy2_csi2phytimer_clk",
1622
+
.parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1623
+
.num_parents = 1,
1624
+
.ops = &clk_branch2_ops,
1625
+
},
1626
+
},
1627
+
};
1628
+
1629
+
static struct clk_branch camss_top_ahb_clk = {
1630
+
.halt_reg = 0x3484,
1631
+
.clkr = {
1632
+
.enable_reg = 0x3484,
1633
+
.enable_mask = BIT(0),
1634
+
.hw.init = &(struct clk_init_data){
1635
+
.name = "camss_top_ahb_clk",
1636
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1637
+
.num_parents = 1,
1638
+
.flags = CLK_SET_RATE_PARENT,
1639
+
.ops = &clk_branch2_ops,
1640
+
},
1641
+
},
1642
+
};
1643
+
1644
+
static struct clk_branch camss_vfe_vfe0_clk = {
1645
+
.halt_reg = 0x36a8,
1646
+
.clkr = {
1647
+
.enable_reg = 0x36a8,
1648
+
.enable_mask = BIT(0),
1649
+
.hw.init = &(struct clk_init_data){
1650
+
.name = "camss_vfe_vfe0_clk",
1651
+
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1652
+
.num_parents = 1,
1653
+
.ops = &clk_branch2_ops,
1654
+
},
1655
+
},
1656
+
};
1657
+
1658
+
static struct clk_branch camss_vfe_vfe1_clk = {
1659
+
.halt_reg = 0x36ac,
1660
+
.clkr = {
1661
+
.enable_reg = 0x36ac,
1662
+
.enable_mask = BIT(0),
1663
+
.hw.init = &(struct clk_init_data){
1664
+
.name = "camss_vfe_vfe1_clk",
1665
+
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1666
+
.num_parents = 1,
1667
+
.ops = &clk_branch2_ops,
1668
+
},
1669
+
},
1670
+
};
1671
+
1672
+
static struct clk_branch camss_vfe_vfe_ahb_clk = {
1673
+
.halt_reg = 0x36b8,
1674
+
.clkr = {
1675
+
.enable_reg = 0x36b8,
1676
+
.enable_mask = BIT(0),
1677
+
.hw.init = &(struct clk_init_data){
1678
+
.name = "camss_vfe_vfe_ahb_clk",
1679
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1680
+
.num_parents = 1,
1681
+
.flags = CLK_SET_RATE_PARENT,
1682
+
.ops = &clk_branch2_ops,
1683
+
},
1684
+
},
1685
+
};
1686
+
1687
+
static struct clk_branch camss_vfe_vfe_axi_clk = {
1688
+
.halt_reg = 0x36bc,
1689
+
.clkr = {
1690
+
.enable_reg = 0x36bc,
1691
+
.enable_mask = BIT(0),
1692
+
.hw.init = &(struct clk_init_data){
1693
+
.name = "camss_vfe_vfe_axi_clk",
1694
+
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1695
+
.num_parents = 1,
1696
+
.ops = &clk_branch2_ops,
1697
+
},
1698
+
},
1699
+
};
1700
+
1701
+
static struct clk_branch fd_ahb_clk = {
1702
+
.halt_reg = 0x3b74,
1703
+
.clkr = {
1704
+
.enable_reg = 0x3b74,
1705
+
.enable_mask = BIT(0),
1706
+
.hw.init = &(struct clk_init_data){
1707
+
.name = "fd_ahb_clk",
1708
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1709
+
.num_parents = 1,
1710
+
.ops = &clk_branch2_ops,
1711
+
},
1712
+
},
1713
+
};
1714
+
1715
+
static struct clk_branch fd_axi_clk = {
1716
+
.halt_reg = 0x3b70,
1717
+
.clkr = {
1718
+
.enable_reg = 0x3b70,
1719
+
.enable_mask = BIT(0),
1720
+
.hw.init = &(struct clk_init_data){
1721
+
.name = "fd_axi_clk",
1722
+
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1723
+
.num_parents = 1,
1724
+
.ops = &clk_branch2_ops,
1725
+
},
1726
+
},
1727
+
};
1728
+
1729
+
static struct clk_branch fd_core_clk = {
1730
+
.halt_reg = 0x3b68,
1731
+
.clkr = {
1732
+
.enable_reg = 0x3b68,
1733
+
.enable_mask = BIT(0),
1734
+
.hw.init = &(struct clk_init_data){
1735
+
.name = "fd_core_clk",
1736
+
.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1737
+
.num_parents = 1,
1738
+
.ops = &clk_branch2_ops,
1739
+
},
1740
+
},
1741
+
};
1742
+
1743
+
static struct clk_branch fd_core_uar_clk = {
1744
+
.halt_reg = 0x3b6c,
1745
+
.clkr = {
1746
+
.enable_reg = 0x3b6c,
1747
+
.enable_mask = BIT(0),
1748
+
.hw.init = &(struct clk_init_data){
1749
+
.name = "fd_core_uar_clk",
1750
+
.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1751
+
.num_parents = 1,
1752
+
.ops = &clk_branch2_ops,
1753
+
},
1754
+
},
1755
+
};
1756
+
1757
+
static struct clk_branch mdss_ahb_clk = {
1758
+
.halt_reg = 0x2308,
1759
+
.halt_check = BRANCH_HALT,
1760
+
.clkr = {
1761
+
.enable_reg = 0x2308,
1762
+
.enable_mask = BIT(0),
1763
+
.hw.init = &(struct clk_init_data){
1764
+
.name = "mdss_ahb_clk",
1765
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1766
+
.num_parents = 1,
1767
+
.flags = CLK_SET_RATE_PARENT,
1768
+
.ops = &clk_branch2_ops,
1769
+
},
1770
+
},
1771
+
};
1772
+
1773
+
static struct clk_branch mdss_axi_clk = {
1774
+
.halt_reg = 0x2310,
1775
+
.clkr = {
1776
+
.enable_reg = 0x2310,
1777
+
.enable_mask = BIT(0),
1778
+
.hw.init = &(struct clk_init_data){
1779
+
.name = "mdss_axi_clk",
1780
+
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1781
+
.num_parents = 1,
1782
+
.flags = CLK_SET_RATE_PARENT,
1783
+
.ops = &clk_branch2_ops,
1784
+
},
1785
+
},
1786
+
};
1787
+
1788
+
static struct clk_branch mdss_byte0_clk = {
1789
+
.halt_reg = 0x233c,
1790
+
.clkr = {
1791
+
.enable_reg = 0x233c,
1792
+
.enable_mask = BIT(0),
1793
+
.hw.init = &(struct clk_init_data){
1794
+
.name = "mdss_byte0_clk",
1795
+
.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1796
+
.num_parents = 1,
1797
+
.flags = CLK_SET_RATE_PARENT,
1798
+
.ops = &clk_branch2_ops,
1799
+
},
1800
+
},
1801
+
};
1802
+
1803
+
static struct clk_branch mdss_byte1_clk = {
1804
+
.halt_reg = 0x2340,
1805
+
.clkr = {
1806
+
.enable_reg = 0x2340,
1807
+
.enable_mask = BIT(0),
1808
+
.hw.init = &(struct clk_init_data){
1809
+
.name = "mdss_byte1_clk",
1810
+
.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1811
+
.num_parents = 1,
1812
+
.flags = CLK_SET_RATE_PARENT,
1813
+
.ops = &clk_branch2_ops,
1814
+
},
1815
+
},
1816
+
};
1817
+
1818
+
static struct clk_branch mdss_esc0_clk = {
1819
+
.halt_reg = 0x2344,
1820
+
.clkr = {
1821
+
.enable_reg = 0x2344,
1822
+
.enable_mask = BIT(0),
1823
+
.hw.init = &(struct clk_init_data){
1824
+
.name = "mdss_esc0_clk",
1825
+
.parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1826
+
.num_parents = 1,
1827
+
.flags = CLK_SET_RATE_PARENT,
1828
+
.ops = &clk_branch2_ops,
1829
+
},
1830
+
},
1831
+
};
1832
+
1833
+
static struct clk_branch mdss_esc1_clk = {
1834
+
.halt_reg = 0x2348,
1835
+
.clkr = {
1836
+
.enable_reg = 0x2348,
1837
+
.enable_mask = BIT(0),
1838
+
.hw.init = &(struct clk_init_data){
1839
+
.name = "mdss_esc1_clk",
1840
+
.parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1841
+
.num_parents = 1,
1842
+
.flags = CLK_SET_RATE_PARENT,
1843
+
.ops = &clk_branch2_ops,
1844
+
},
1845
+
},
1846
+
};
1847
+
1848
+
static struct clk_branch mdss_extpclk_clk = {
1849
+
.halt_reg = 0x2324,
1850
+
.clkr = {
1851
+
.enable_reg = 0x2324,
1852
+
.enable_mask = BIT(0),
1853
+
.hw.init = &(struct clk_init_data){
1854
+
.name = "mdss_extpclk_clk",
1855
+
.parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1856
+
.num_parents = 1,
1857
+
.flags = CLK_SET_RATE_PARENT,
1858
+
.ops = &clk_branch2_ops,
1859
+
},
1860
+
},
1861
+
};
1862
+
1863
+
static struct clk_branch mdss_hdmi_ahb_clk = {
1864
+
.halt_reg = 0x230c,
1865
+
.clkr = {
1866
+
.enable_reg = 0x230c,
1867
+
.enable_mask = BIT(0),
1868
+
.hw.init = &(struct clk_init_data){
1869
+
.name = "mdss_hdmi_ahb_clk",
1870
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1871
+
.num_parents = 1,
1872
+
.flags = CLK_SET_RATE_PARENT,
1873
+
.ops = &clk_branch2_ops,
1874
+
},
1875
+
},
1876
+
};
1877
+
1878
+
static struct clk_branch mdss_hdmi_clk = {
1879
+
.halt_reg = 0x2338,
1880
+
.clkr = {
1881
+
.enable_reg = 0x2338,
1882
+
.enable_mask = BIT(0),
1883
+
.hw.init = &(struct clk_init_data){
1884
+
.name = "mdss_hdmi_clk",
1885
+
.parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1886
+
.num_parents = 1,
1887
+
.flags = CLK_SET_RATE_PARENT,
1888
+
.ops = &clk_branch2_ops,
1889
+
},
1890
+
},
1891
+
};
1892
+
1893
+
static struct clk_branch mdss_mdp_clk = {
1894
+
.halt_reg = 0x231c,
1895
+
.clkr = {
1896
+
.enable_reg = 0x231c,
1897
+
.enable_mask = BIT(0),
1898
+
.hw.init = &(struct clk_init_data){
1899
+
.name = "mdss_mdp_clk",
1900
+
.parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1901
+
.num_parents = 1,
1902
+
.flags = CLK_SET_RATE_PARENT,
1903
+
.ops = &clk_branch2_ops,
1904
+
},
1905
+
},
1906
+
};
1907
+
1908
+
static struct clk_branch mdss_pclk0_clk = {
1909
+
.halt_reg = 0x2314,
1910
+
.clkr = {
1911
+
.enable_reg = 0x2314,
1912
+
.enable_mask = BIT(0),
1913
+
.hw.init = &(struct clk_init_data){
1914
+
.name = "mdss_pclk0_clk",
1915
+
.parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1916
+
.num_parents = 1,
1917
+
.flags = CLK_SET_RATE_PARENT,
1918
+
.ops = &clk_branch2_ops,
1919
+
},
1920
+
},
1921
+
};
1922
+
1923
+
static struct clk_branch mdss_pclk1_clk = {
1924
+
.halt_reg = 0x2318,
1925
+
.clkr = {
1926
+
.enable_reg = 0x2318,
1927
+
.enable_mask = BIT(0),
1928
+
.hw.init = &(struct clk_init_data){
1929
+
.name = "mdss_pclk1_clk",
1930
+
.parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1931
+
.num_parents = 1,
1932
+
.flags = CLK_SET_RATE_PARENT,
1933
+
.ops = &clk_branch2_ops,
1934
+
},
1935
+
},
1936
+
};
1937
+
1938
+
static struct clk_branch mdss_vsync_clk = {
1939
+
.halt_reg = 0x2328,
1940
+
.clkr = {
1941
+
.enable_reg = 0x2328,
1942
+
.enable_mask = BIT(0),
1943
+
.hw.init = &(struct clk_init_data){
1944
+
.name = "mdss_vsync_clk",
1945
+
.parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1946
+
.num_parents = 1,
1947
+
.flags = CLK_SET_RATE_PARENT,
1948
+
.ops = &clk_branch2_ops,
1949
+
},
1950
+
},
1951
+
};
1952
+
1953
+
static struct clk_branch mmss_misc_ahb_clk = {
1954
+
.halt_reg = 0x502c,
1955
+
.clkr = {
1956
+
.enable_reg = 0x502c,
1957
+
.enable_mask = BIT(0),
1958
+
.hw.init = &(struct clk_init_data){
1959
+
.name = "mmss_misc_ahb_clk",
1960
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1961
+
.num_parents = 1,
1962
+
.flags = CLK_SET_RATE_PARENT,
1963
+
.ops = &clk_branch2_ops,
1964
+
},
1965
+
},
1966
+
};
1967
+
1968
+
static struct clk_branch mmss_mmssnoc_axi_clk = {
1969
+
.halt_reg = 0x506c,
1970
+
.clkr = {
1971
+
.enable_reg = 0x506c,
1972
+
.enable_mask = BIT(0),
1973
+
.hw.init = &(struct clk_init_data){
1974
+
.name = "mmss_mmssnoc_axi_clk",
1975
+
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1976
+
.num_parents = 1,
1977
+
/* Gating this clock will wreck havoc among MMSS! */
1978
+
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1979
+
.ops = &clk_branch2_ops,
1980
+
},
1981
+
},
1982
+
};
1983
+
1984
+
static struct clk_branch mmss_s0_axi_clk = {
1985
+
.halt_reg = 0x5064,
1986
+
.clkr = {
1987
+
.enable_reg = 0x5064,
1988
+
.enable_mask = BIT(0),
1989
+
.hw.init = &(struct clk_init_data){
1990
+
.name = "mmss_s0_axi_clk",
1991
+
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw, },
1992
+
.num_parents = 1,
1993
+
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1994
+
.ops = &clk_branch2_ops,
1995
+
},
1996
+
},
1997
+
};
1998
+
1999
+
static struct clk_branch ocmemcx_ocmemnoc_clk = {
2000
+
.halt_reg = 0x4058,
2001
+
.clkr = {
2002
+
.enable_reg = 0x4058,
2003
+
.enable_mask = BIT(0),
2004
+
.hw.init = &(struct clk_init_data){
2005
+
.name = "ocmemcx_ocmemnoc_clk",
2006
+
.parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2007
+
.num_parents = 1,
2008
+
.flags = CLK_SET_RATE_PARENT,
2009
+
.ops = &clk_branch2_ops,
2010
+
},
2011
+
},
2012
+
};
2013
+
2014
+
static struct clk_branch oxili_gfx3d_clk = {
2015
+
.halt_reg = 0x4028,
2016
+
.clkr = {
2017
+
.enable_reg = 0x4028,
2018
+
.enable_mask = BIT(0),
2019
+
.hw.init = &(struct clk_init_data){
2020
+
.name = "oxili_gfx3d_clk",
2021
+
.parent_data = &(const struct clk_parent_data){
2022
+
.fw_name = "oxili_gfx3d_clk_src",
2023
+
.name = "oxili_gfx3d_clk_src"
2024
+
},
2025
+
.num_parents = 1,
2026
+
.flags = CLK_SET_RATE_PARENT,
2027
+
.ops = &clk_branch2_ops,
2028
+
},
2029
+
},
2030
+
};
2031
+
2032
+
static struct clk_branch oxili_rbbmtimer_clk = {
2033
+
.halt_reg = 0x40b0,
2034
+
.clkr = {
2035
+
.enable_reg = 0x40b0,
2036
+
.enable_mask = BIT(0),
2037
+
.hw.init = &(struct clk_init_data){
2038
+
.name = "oxili_rbbmtimer_clk",
2039
+
.parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
2040
+
.num_parents = 1,
2041
+
.flags = CLK_SET_RATE_PARENT,
2042
+
.ops = &clk_branch2_ops,
2043
+
},
2044
+
},
2045
+
};
2046
+
2047
+
static struct clk_branch oxilicx_ahb_clk = {
2048
+
.halt_reg = 0x403c,
2049
+
.clkr = {
2050
+
.enable_reg = 0x403c,
2051
+
.enable_mask = BIT(0),
2052
+
.hw.init = &(struct clk_init_data){
2053
+
.name = "oxilicx_ahb_clk",
2054
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2055
+
.num_parents = 1,
2056
+
.flags = CLK_SET_RATE_PARENT,
2057
+
.ops = &clk_branch2_ops,
2058
+
},
2059
+
},
2060
+
};
2061
+
2062
+
static struct clk_branch venus0_ahb_clk = {
2063
+
.halt_reg = 0x1030,
2064
+
.clkr = {
2065
+
.enable_reg = 0x1030,
2066
+
.enable_mask = BIT(0),
2067
+
.hw.init = &(struct clk_init_data){
2068
+
.name = "venus0_ahb_clk",
2069
+
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2070
+
.num_parents = 1,
2071
+
.flags = CLK_SET_RATE_PARENT,
2072
+
.ops = &clk_branch2_ops,
2073
+
},
2074
+
},
2075
+
};
2076
+
2077
+
static struct clk_branch venus0_axi_clk = {
2078
+
.halt_reg = 0x1034,
2079
+
.clkr = {
2080
+
.enable_reg = 0x1034,
2081
+
.enable_mask = BIT(0),
2082
+
.hw.init = &(struct clk_init_data){
2083
+
.name = "venus0_axi_clk",
2084
+
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2085
+
.num_parents = 1,
2086
+
.ops = &clk_branch2_ops,
2087
+
},
2088
+
},
2089
+
};
2090
+
2091
+
static struct clk_branch venus0_ocmemnoc_clk = {
2092
+
.halt_reg = 0x1038,
2093
+
.clkr = {
2094
+
.enable_reg = 0x1038,
2095
+
.enable_mask = BIT(0),
2096
+
.hw.init = &(struct clk_init_data){
2097
+
.name = "venus0_ocmemnoc_clk",
2098
+
.parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2099
+
.num_parents = 1,
2100
+
.flags = CLK_SET_RATE_PARENT,
2101
+
.ops = &clk_branch2_ops,
2102
+
},
2103
+
},
2104
+
};
2105
+
2106
+
static struct clk_branch venus0_vcodec0_clk = {
2107
+
.halt_reg = 0x1028,
2108
+
.clkr = {
2109
+
.enable_reg = 0x1028,
2110
+
.enable_mask = BIT(0),
2111
+
.hw.init = &(struct clk_init_data){
2112
+
.name = "venus0_vcodec0_clk",
2113
+
.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2114
+
.num_parents = 1,
2115
+
.flags = CLK_SET_RATE_PARENT,
2116
+
.ops = &clk_branch2_ops,
2117
+
},
2118
+
},
2119
+
};
2120
+
2121
+
static struct clk_branch venus0_core0_vcodec_clk = {
2122
+
.halt_reg = 0x1048,
2123
+
.clkr = {
2124
+
.enable_reg = 0x1048,
2125
+
.enable_mask = BIT(0),
2126
+
.hw.init = &(struct clk_init_data){
2127
+
.name = "venus0_core0_vcodec_clk",
2128
+
.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2129
+
.num_parents = 1,
2130
+
.flags = CLK_SET_RATE_PARENT,
2131
+
.ops = &clk_branch2_ops,
2132
+
},
2133
+
},
2134
+
};
2135
+
2136
+
static struct clk_branch venus0_core1_vcodec_clk = {
2137
+
.halt_reg = 0x104c,
2138
+
.clkr = {
2139
+
.enable_reg = 0x104c,
2140
+
.enable_mask = BIT(0),
2141
+
.hw.init = &(struct clk_init_data){
2142
+
.name = "venus0_core1_vcodec_clk",
2143
+
.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2144
+
.num_parents = 1,
2145
+
.flags = CLK_SET_RATE_PARENT,
2146
+
.ops = &clk_branch2_ops,
2147
+
},
2148
+
},
2149
+
};
2150
+
2151
+
static struct clk_branch venus0_core2_vcodec_clk = {
2152
+
.halt_reg = 0x1054,
2153
+
.clkr = {
2154
+
.enable_reg = 0x1054,
2155
+
.enable_mask = BIT(0),
2156
+
.hw.init = &(struct clk_init_data){
2157
+
.name = "venus0_core2_vcodec_clk",
2158
+
.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2159
+
.num_parents = 1,
2160
+
.flags = CLK_SET_RATE_PARENT,
2161
+
.ops = &clk_branch2_ops,
2162
+
},
2163
+
},
2164
+
};
2165
+
2166
+
static struct gdsc venus_gdsc = {
2167
+
.gdscr = 0x1024,
2168
+
.cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2169
+
.cxc_count = 3,
2170
+
.pd = {
2171
+
.name = "venus_gdsc",
2172
+
},
2173
+
.pwrsts = PWRSTS_OFF_ON,
2174
+
};
2175
+
2176
+
static struct gdsc venus_core0_gdsc = {
2177
+
.gdscr = 0x1040,
2178
+
.cxcs = (unsigned int []){ 0x1048 },
2179
+
.cxc_count = 1,
2180
+
.pd = {
2181
+
.name = "venus_core0_gdsc",
2182
+
},
2183
+
.pwrsts = PWRSTS_OFF_ON,
2184
+
.flags = HW_CTRL,
2185
+
};
2186
+
2187
+
static struct gdsc venus_core1_gdsc = {
2188
+
.gdscr = 0x1044,
2189
+
.cxcs = (unsigned int []){ 0x104c },
2190
+
.cxc_count = 1,
2191
+
.pd = {
2192
+
.name = "venus_core1_gdsc",
2193
+
},
2194
+
.pwrsts = PWRSTS_OFF_ON,
2195
+
.flags = HW_CTRL,
2196
+
};
2197
+
2198
+
static struct gdsc venus_core2_gdsc = {
2199
+
.gdscr = 0x1050,
2200
+
.cxcs = (unsigned int []){ 0x1054 },
2201
+
.cxc_count = 1,
2202
+
.pd = {
2203
+
.name = "venus_core2_gdsc",
2204
+
},
2205
+
.pwrsts = PWRSTS_OFF_ON,
2206
+
.flags = HW_CTRL,
2207
+
};
2208
+
2209
+
static struct gdsc mdss_gdsc = {
2210
+
.gdscr = 0x2304,
2211
+
.cxcs = (unsigned int []){ 0x2310, 0x231c },
2212
+
.cxc_count = 2,
2213
+
.pd = {
2214
+
.name = "mdss_gdsc",
2215
+
},
2216
+
.pwrsts = PWRSTS_OFF_ON,
2217
+
};
2218
+
2219
+
static struct gdsc camss_top_gdsc = {
2220
+
.gdscr = 0x34a0,
2221
+
.cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2222
+
.cxc_count = 3,
2223
+
.pd = {
2224
+
.name = "camss_top_gdsc",
2225
+
},
2226
+
.pwrsts = PWRSTS_OFF_ON,
2227
+
};
2228
+
2229
+
static struct gdsc jpeg_gdsc = {
2230
+
.gdscr = 0x35a4,
2231
+
.cxcs = (unsigned int []){ 0x35a8 },
2232
+
.cxc_count = 1,
2233
+
.pd = {
2234
+
.name = "jpeg_gdsc",
2235
+
},
2236
+
.parent = &camss_top_gdsc.pd,
2237
+
.pwrsts = PWRSTS_OFF_ON,
2238
+
};
2239
+
2240
+
static struct gdsc vfe_gdsc = {
2241
+
.gdscr = 0x36a4,
2242
+
.cxcs = (unsigned int []){ 0x36bc },
2243
+
.cxc_count = 1,
2244
+
.pd = {
2245
+
.name = "vfe_gdsc",
2246
+
},
2247
+
.parent = &camss_top_gdsc.pd,
2248
+
.pwrsts = PWRSTS_OFF_ON,
2249
+
};
2250
+
2251
+
static struct gdsc cpp_gdsc = {
2252
+
.gdscr = 0x36d4,
2253
+
.cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2254
+
.cxc_count = 2,
2255
+
.pd = {
2256
+
.name = "cpp_gdsc",
2257
+
},
2258
+
.parent = &camss_top_gdsc.pd,
2259
+
.pwrsts = PWRSTS_OFF_ON,
2260
+
};
2261
+
2262
+
static struct gdsc fd_gdsc = {
2263
+
.gdscr = 0x3b64,
2264
+
.cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2265
+
.pd = {
2266
+
.name = "fd_gdsc",
2267
+
},
2268
+
.pwrsts = PWRSTS_OFF_ON,
2269
+
};
2270
+
2271
+
static struct gdsc oxili_cx_gdsc = {
2272
+
.gdscr = 0x4034,
2273
+
.pd = {
2274
+
.name = "oxili_cx_gdsc",
2275
+
},
2276
+
.pwrsts = PWRSTS_OFF_ON,
2277
+
.flags = VOTABLE,
2278
+
};
2279
+
2280
+
static struct gdsc oxili_gx_gdsc = {
2281
+
.gdscr = 0x4024,
2282
+
.cxcs = (unsigned int []){ 0x4028 },
2283
+
.cxc_count = 1,
2284
+
.pd = {
2285
+
.name = "oxili_gx_gdsc",
2286
+
},
2287
+
.pwrsts = PWRSTS_OFF_ON,
2288
+
.parent = &oxili_cx_gdsc.pd,
2289
+
.flags = CLAMP_IO,
2290
+
.supply = "VDD_GFX",
2291
+
};
2292
+
2293
+
static struct clk_regmap *mmcc_msm8994_clocks[] = {
2294
+
[MMPLL0_EARLY] = &mmpll0_early.clkr,
2295
+
[MMPLL0_PLL] = &mmpll0.clkr,
2296
+
[MMPLL1_EARLY] = &mmpll1_early.clkr,
2297
+
[MMPLL1_PLL] = &mmpll1.clkr,
2298
+
[MMPLL3_EARLY] = &mmpll3_early.clkr,
2299
+
[MMPLL3_PLL] = &mmpll3.clkr,
2300
+
[MMPLL4_EARLY] = &mmpll4_early.clkr,
2301
+
[MMPLL4_PLL] = &mmpll4.clkr,
2302
+
[MMPLL5_EARLY] = &mmpll5_early.clkr,
2303
+
[MMPLL5_PLL] = &mmpll5.clkr,
2304
+
[AHB_CLK_SRC] = &ahb_clk_src.clkr,
2305
+
[AXI_CLK_SRC] = &axi_clk_src.clkr,
2306
+
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2307
+
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2308
+
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2309
+
[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2310
+
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2311
+
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2312
+
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
2313
+
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2314
+
[JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2315
+
[JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2316
+
[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2317
+
[FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2318
+
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
2319
+
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2320
+
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2321
+
[OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2322
+
[CCI_CLK_SRC] = &cci_clk_src.clkr,
2323
+
[MMSS_GP0_CLK_SRC] = &mmss_gp0_clk_src.clkr,
2324
+
[MMSS_GP1_CLK_SRC] = &mmss_gp1_clk_src.clkr,
2325
+
[JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
2326
+
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2327
+
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2328
+
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2329
+
[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2330
+
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2331
+
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2332
+
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2333
+
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2334
+
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2335
+
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2336
+
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2337
+
[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2338
+
[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2339
+
[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2340
+
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2341
+
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2342
+
[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2343
+
[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2344
+
[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2345
+
[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2346
+
[CAMSS_VFE_CPP_AXI_CLK] = &camss_vfe_cpp_axi_clk.clkr,
2347
+
[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2348
+
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2349
+
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2350
+
[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2351
+
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2352
+
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2353
+
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2354
+
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2355
+
[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2356
+
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2357
+
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2358
+
[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2359
+
[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2360
+
[CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2361
+
[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2362
+
[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2363
+
[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2364
+
[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2365
+
[CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2366
+
[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2367
+
[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2368
+
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2369
+
[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2370
+
[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2371
+
[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2372
+
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2373
+
[CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
2374
+
[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2375
+
[CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2376
+
[CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2377
+
[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2378
+
[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2379
+
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2380
+
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2381
+
[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2382
+
[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2383
+
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2384
+
[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2385
+
[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2386
+
[CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2387
+
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2388
+
[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2389
+
[CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2390
+
[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2391
+
[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2392
+
[FD_AHB_CLK] = &fd_ahb_clk.clkr,
2393
+
[FD_AXI_CLK] = &fd_axi_clk.clkr,
2394
+
[FD_CORE_CLK] = &fd_core_clk.clkr,
2395
+
[FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2396
+
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2397
+
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2398
+
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2399
+
[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2400
+
[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2401
+
[MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2402
+
[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2403
+
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2404
+
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2405
+
[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2406
+
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2407
+
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2408
+
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2409
+
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2410
+
[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2411
+
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2412
+
[OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
2413
+
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2414
+
[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2415
+
[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2416
+
[VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2417
+
[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2418
+
[VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
2419
+
[VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
2420
+
[VENUS0_CORE2_VCODEC_CLK] = &venus0_core2_vcodec_clk.clkr,
2421
+
};
2422
+
2423
+
static struct gdsc *mmcc_msm8994_gdscs[] = {
2424
+
[VENUS_GDSC] = &venus_gdsc,
2425
+
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2426
+
[VENUS_CORE1_GDSC] = &venus_core1_gdsc,
2427
+
[VENUS_CORE2_GDSC] = &venus_core2_gdsc,
2428
+
[CAMSS_TOP_GDSC] = &camss_top_gdsc,
2429
+
[MDSS_GDSC] = &mdss_gdsc,
2430
+
[JPEG_GDSC] = &jpeg_gdsc,
2431
+
[VFE_GDSC] = &vfe_gdsc,
2432
+
[CPP_GDSC] = &cpp_gdsc,
2433
+
[OXILI_GX_GDSC] = &oxili_gx_gdsc,
2434
+
[OXILI_CX_GDSC] = &oxili_cx_gdsc,
2435
+
[FD_GDSC] = &fd_gdsc,
2436
+
};
2437
+
2438
+
static const struct qcom_reset_map mmcc_msm8994_resets[] = {
2439
+
[CAMSS_MICRO_BCR] = { 0x3490 },
2440
+
};
2441
+
2442
+
static const struct regmap_config mmcc_msm8994_regmap_config = {
2443
+
.reg_bits = 32,
2444
+
.reg_stride = 4,
2445
+
.val_bits = 32,
2446
+
.max_register = 0x5200,
2447
+
.fast_io = true,
2448
+
};
2449
+
2450
+
static const struct qcom_cc_desc mmcc_msm8994_desc = {
2451
+
.config = &mmcc_msm8994_regmap_config,
2452
+
.clks = mmcc_msm8994_clocks,
2453
+
.num_clks = ARRAY_SIZE(mmcc_msm8994_clocks),
2454
+
.resets = mmcc_msm8994_resets,
2455
+
.num_resets = ARRAY_SIZE(mmcc_msm8994_resets),
2456
+
.gdscs = mmcc_msm8994_gdscs,
2457
+
.num_gdscs = ARRAY_SIZE(mmcc_msm8994_gdscs),
2458
+
};
2459
+
2460
+
static const struct of_device_id mmcc_msm8994_match_table[] = {
2461
+
{ .compatible = "qcom,mmcc-msm8992" },
2462
+
{ .compatible = "qcom,mmcc-msm8994" }, /* V2 and V2.1 */
2463
+
{ }
2464
+
};
2465
+
MODULE_DEVICE_TABLE(of, mmcc_msm8994_match_table);
2466
+
2467
+
static int mmcc_msm8994_probe(struct platform_device *pdev)
2468
+
{
2469
+
struct regmap *regmap;
2470
+
2471
+
regmap = qcom_cc_map(pdev, &mmcc_msm8994_desc);
2472
+
if (IS_ERR(regmap))
2473
+
return PTR_ERR(regmap);
2474
+
2475
+
clk_alpha_pll_configure(&mmpll0_early, regmap, &mmpll_p_config);
2476
+
clk_alpha_pll_configure(&mmpll1_early, regmap, &mmpll_p_config);
2477
+
clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
2478
+
clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
2479
+
2480
+
return qcom_cc_really_probe(pdev, &mmcc_msm8994_desc, regmap);
2481
+
}
2482
+
2483
+
static struct platform_driver mmcc_msm8994_driver = {
2484
+
.probe = mmcc_msm8994_probe,
2485
+
.driver = {
2486
+
.name = "mmcc-msm8994",
2487
+
.of_match_table = mmcc_msm8994_match_table,
2488
+
},
2489
+
};
2490
+
module_platform_driver(mmcc_msm8994_driver);
2491
+
2492
+
MODULE_DESCRIPTION("QCOM MMCC MSM8994 Driver");
2493
+
MODULE_LICENSE("GPL v2");
2494
+
MODULE_ALIAS("platform:mmcc-msm8994");
+155
include/dt-bindings/clock/qcom,mmcc-msm8994.h
+155
include/dt-bindings/clock/qcom,mmcc-msm8994.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2020, Konrad Dybcio
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8994_H
7
+
#define _DT_BINDINGS_CLK_MSM_MMCC_8994_H
8
+
9
+
/* Clocks */
10
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#define MMPLL0_EARLY 0
11
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#define MMPLL0_PLL 1
12
+
#define MMPLL1_EARLY 2
13
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#define MMPLL1_PLL 3
14
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#define MMPLL3_EARLY 4
15
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#define MMPLL3_PLL 5
16
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#define MMPLL4_EARLY 6
17
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#define MMPLL4_PLL 7
18
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#define MMPLL5_EARLY 8
19
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#define MMPLL5_PLL 9
20
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#define AXI_CLK_SRC 10
21
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#define RBBMTIMER_CLK_SRC 11
22
+
#define PCLK0_CLK_SRC 12
23
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#define PCLK1_CLK_SRC 13
24
+
#define MDP_CLK_SRC 14
25
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#define VSYNC_CLK_SRC 15
26
+
#define BYTE0_CLK_SRC 16
27
+
#define BYTE1_CLK_SRC 17
28
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#define ESC0_CLK_SRC 18
29
+
#define ESC1_CLK_SRC 19
30
+
#define MDSS_AHB_CLK 20
31
+
#define MDSS_PCLK0_CLK 21
32
+
#define MDSS_PCLK1_CLK 22
33
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#define MDSS_VSYNC_CLK 23
34
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#define MDSS_BYTE0_CLK 24
35
+
#define MDSS_BYTE1_CLK 25
36
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#define MDSS_ESC0_CLK 26
37
+
#define MDSS_ESC1_CLK 27
38
+
#define CSI0_CLK_SRC 28
39
+
#define CSI1_CLK_SRC 29
40
+
#define CSI2_CLK_SRC 30
41
+
#define CSI3_CLK_SRC 31
42
+
#define VFE0_CLK_SRC 32
43
+
#define VFE1_CLK_SRC 33
44
+
#define CPP_CLK_SRC 34
45
+
#define JPEG0_CLK_SRC 35
46
+
#define JPEG1_CLK_SRC 36
47
+
#define JPEG2_CLK_SRC 37
48
+
#define CSI2PHYTIMER_CLK_SRC 38
49
+
#define FD_CORE_CLK_SRC 39
50
+
#define OCMEMNOC_CLK_SRC 40
51
+
#define CCI_CLK_SRC 41
52
+
#define MMSS_GP0_CLK_SRC 42
53
+
#define MMSS_GP1_CLK_SRC 43
54
+
#define JPEG_DMA_CLK_SRC 44
55
+
#define MCLK0_CLK_SRC 45
56
+
#define MCLK1_CLK_SRC 46
57
+
#define MCLK2_CLK_SRC 47
58
+
#define MCLK3_CLK_SRC 48
59
+
#define CSI0PHYTIMER_CLK_SRC 49
60
+
#define CSI1PHYTIMER_CLK_SRC 50
61
+
#define EXTPCLK_CLK_SRC 51
62
+
#define HDMI_CLK_SRC 52
63
+
#define CAMSS_AHB_CLK 53
64
+
#define CAMSS_CCI_CCI_AHB_CLK 54
65
+
#define CAMSS_CCI_CCI_CLK 55
66
+
#define CAMSS_VFE_CPP_AHB_CLK 56
67
+
#define CAMSS_VFE_CPP_AXI_CLK 57
68
+
#define CAMSS_VFE_CPP_CLK 58
69
+
#define CAMSS_CSI0_AHB_CLK 59
70
+
#define CAMSS_CSI0_CLK 60
71
+
#define CAMSS_CSI0PHY_CLK 61
72
+
#define CAMSS_CSI0PIX_CLK 62
73
+
#define CAMSS_CSI0RDI_CLK 63
74
+
#define CAMSS_CSI1_AHB_CLK 64
75
+
#define CAMSS_CSI1_CLK 65
76
+
#define CAMSS_CSI1PHY_CLK 66
77
+
#define CAMSS_CSI1PIX_CLK 67
78
+
#define CAMSS_CSI1RDI_CLK 68
79
+
#define CAMSS_CSI2_AHB_CLK 69
80
+
#define CAMSS_CSI2_CLK 70
81
+
#define CAMSS_CSI2PHY_CLK 71
82
+
#define CAMSS_CSI2PIX_CLK 72
83
+
#define CAMSS_CSI2RDI_CLK 73
84
+
#define CAMSS_CSI3_AHB_CLK 74
85
+
#define CAMSS_CSI3_CLK 75
86
+
#define CAMSS_CSI3PHY_CLK 76
87
+
#define CAMSS_CSI3PIX_CLK 77
88
+
#define CAMSS_CSI3RDI_CLK 78
89
+
#define CAMSS_CSI_VFE0_CLK 79
90
+
#define CAMSS_CSI_VFE1_CLK 80
91
+
#define CAMSS_GP0_CLK 81
92
+
#define CAMSS_GP1_CLK 82
93
+
#define CAMSS_ISPIF_AHB_CLK 83
94
+
#define CAMSS_JPEG_DMA_CLK 84
95
+
#define CAMSS_JPEG_JPEG0_CLK 85
96
+
#define CAMSS_JPEG_JPEG1_CLK 86
97
+
#define CAMSS_JPEG_JPEG2_CLK 87
98
+
#define CAMSS_JPEG_JPEG_AHB_CLK 88
99
+
#define CAMSS_JPEG_JPEG_AXI_CLK 89
100
+
#define CAMSS_MCLK0_CLK 90
101
+
#define CAMSS_MCLK1_CLK 91
102
+
#define CAMSS_MCLK2_CLK 92
103
+
#define CAMSS_MCLK3_CLK 93
104
+
#define CAMSS_MICRO_AHB_CLK 94
105
+
#define CAMSS_PHY0_CSI0PHYTIMER_CLK 95
106
+
#define CAMSS_PHY1_CSI1PHYTIMER_CLK 96
107
+
#define CAMSS_PHY2_CSI2PHYTIMER_CLK 97
108
+
#define CAMSS_TOP_AHB_CLK 98
109
+
#define CAMSS_VFE_VFE0_CLK 99
110
+
#define CAMSS_VFE_VFE1_CLK 100
111
+
#define CAMSS_VFE_VFE_AHB_CLK 101
112
+
#define CAMSS_VFE_VFE_AXI_CLK 102
113
+
#define FD_AXI_CLK 103
114
+
#define FD_CORE_CLK 104
115
+
#define FD_CORE_UAR_CLK 105
116
+
#define MDSS_AXI_CLK 106
117
+
#define MDSS_EXTPCLK_CLK 107
118
+
#define MDSS_HDMI_AHB_CLK 108
119
+
#define MDSS_HDMI_CLK 109
120
+
#define MDSS_MDP_CLK 110
121
+
#define MMSS_MISC_AHB_CLK 111
122
+
#define MMSS_MMSSNOC_AXI_CLK 112
123
+
#define MMSS_S0_AXI_CLK 113
124
+
#define OCMEMCX_OCMEMNOC_CLK 114
125
+
#define OXILI_GFX3D_CLK 115
126
+
#define OXILI_RBBMTIMER_CLK 116
127
+
#define OXILICX_AHB_CLK 117
128
+
#define VENUS0_AHB_CLK 118
129
+
#define VENUS0_AXI_CLK 119
130
+
#define VENUS0_OCMEMNOC_CLK 120
131
+
#define VENUS0_VCODEC0_CLK 121
132
+
#define VENUS0_CORE0_VCODEC_CLK 122
133
+
#define VENUS0_CORE1_VCODEC_CLK 123
134
+
#define VENUS0_CORE2_VCODEC_CLK 124
135
+
#define AHB_CLK_SRC 125
136
+
#define FD_AHB_CLK 126
137
+
138
+
/* GDSCs */
139
+
#define VENUS_GDSC 0
140
+
#define VENUS_CORE0_GDSC 1
141
+
#define VENUS_CORE1_GDSC 2
142
+
#define VENUS_CORE2_GDSC 3
143
+
#define CAMSS_TOP_GDSC 4
144
+
#define MDSS_GDSC 5
145
+
#define JPEG_GDSC 6
146
+
#define VFE_GDSC 7
147
+
#define CPP_GDSC 8
148
+
#define OXILI_GX_GDSC 9
149
+
#define OXILI_CX_GDSC 10
150
+
#define FD_GDSC 11
151
+
152
+
/* Resets */
153
+
#define CAMSS_MICRO_BCR 0
154
+
155
+
#endif