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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
Document the A/D 12-Bit successive approximation converters found in the
Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
RZ/T2H has two ADCs with 4 channels and one with 6.
RZ/N2H has two ADCs with 4 channels and one with 15.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Cosmin Tanislav
and committed by
Jonathan Cameron
4d8d5898
70fde048
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Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
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Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/T2H / RZ/N2H ADC12
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maintainers:
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- Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
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description: |
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A/D Converter block is a successive approximation analog-to-digital converter
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with a 12-bit accuracy. Up to 16 analog input channels can be selected.
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Conversions can be performed in single or continuous mode. Result of the ADC
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is stored in a 16-bit data register corresponding to each channel.
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properties:
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compatible:
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oneOf:
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- items:
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- const: renesas,r9a09g087-adc # RZ/N2H
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- const: renesas,r9a09g077-adc # RZ/T2H
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- items:
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- const: renesas,r9a09g077-adc # RZ/T2H
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: A/D scan end interrupt
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- description: A/D scan end interrupt for Group B
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- description: A/D scan end interrupt for Group C
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- description: Window A compare match
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- description: Window B compare match
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- description: Compare match
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- description: Compare mismatch
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interrupt-names:
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items:
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- const: adi
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- const: gbadi
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- const: gcadi
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- const: cmpai
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- const: cmpbi
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- const: wcmpm
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- const: wcmpum
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clocks:
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items:
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- description: Converter clock
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- description: Peripheral clock
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clock-names:
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items:
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- const: adclk
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- const: pclk
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power-domains:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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"#io-channel-cells":
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const: 1
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patternProperties:
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"^channel@[0-9a-f]$":
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$ref: adc.yaml
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type: object
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description: The external channels which are connected to the ADC.
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properties:
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reg:
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description: The channel number.
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maximum: 15
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required:
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- reg
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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adc@80008000 {
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compatible = "renesas,r9a09g077-adc";
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reg = <0x80008000 0x400>;
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interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "adi", "gbadi", "gcadi",
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"cmpai", "cmpbi", "wcmpm", "wcmpum";
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clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
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<&cpg CPG_MOD 225>;
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clock-names = "adclk", "pclk";
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power-domains = <&cpg>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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channel@0 {
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reg = <0x0>;
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};
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channel@1 {
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reg = <0x1>;
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};
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channel@2 {
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reg = <0x2>;
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};
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channel@3 {
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reg = <0x3>;
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};
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};
+7
MAINTAINERS
+7
MAINTAINERS
···
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F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
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F: drivers/counter/rz-mtu3-cnt.c
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RENESAS RZ/T2H / RZ/N2H A/D DRIVER
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M: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
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L: linux-iio@vger.kernel.org
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L: linux-renesas-soc@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
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RENESAS RTCA-3 RTC DRIVER
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M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
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L: linux-rtc@vger.kernel.org