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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: microchip: mpfs: convert cfg_clk to clk_divider
The cfg_clk struct is now just a redefinition of the clk_divider struct
with custom implentations of the ops, that implement an extra level of
redirection. Remove the custom struct and replace it with clk_divider.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-13-conor.dooley@microchip.com
authored by
Conor Dooley
and committed by
Claudiu Beznea
4da2404b
e7df7ba0
+8
-68
+8
-68
drivers/clk/microchip/clk-mpfs.c
+8
-68
drivers/clk/microchip/clk-mpfs.c
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#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
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struct mpfs_cfg_clock {
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void __iomem *reg;
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const struct clk_div_table *table;
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u8 shift;
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u8 width;
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u8 flags;
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};
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struct mpfs_cfg_hw_clock {
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struct mpfs_cfg_clock cfg;
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struct clk_hw hw;
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struct clk_divider cfg;
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struct clk_init_data init;
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unsigned int id;
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u32 reg_offset;
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};
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#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
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struct mpfs_periph_clock {
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void __iomem *reg;
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* "CFG" clocks
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*/
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static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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u32 val;
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val = readl_relaxed(cfg->reg) >> cfg->shift;
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val &= clk_div_mask(cfg->width);
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return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
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}
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static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0);
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}
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static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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unsigned long flags;
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u32 val;
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int divider_setting;
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divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0);
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if (divider_setting < 0)
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return divider_setting;
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spin_lock_irqsave(&mpfs_clk_lock, flags);
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val = readl_relaxed(cfg->reg);
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val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
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val |= divider_setting << cfg->shift;
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writel_relaxed(val, cfg->reg);
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spin_unlock_irqrestore(&mpfs_clk_lock, flags);
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return 0;
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}
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static const struct clk_ops mpfs_clk_cfg_ops = {
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.recalc_rate = mpfs_cfg_clk_recalc_rate,
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.round_rate = mpfs_cfg_clk_round_rate,
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.set_rate = mpfs_cfg_clk_set_rate,
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};
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#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
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.id = _id, \
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.cfg.shift = _shift, \
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.cfg.table = _table, \
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.reg_offset = _offset, \
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.cfg.flags = _flags, \
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.hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \
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.cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
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.cfg.lock = &mpfs_clk_lock, \
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}
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#define CLK_CPU_OFFSET 0u
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.cfg.table = mpfs_div_rtcref_table,
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.reg_offset = REG_RTC_CLOCK_CR,
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.cfg.flags = CLK_DIVIDER_ONE_BASED,
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.hw.init =
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CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0),
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.cfg.hw.init =
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CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
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}
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};
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struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
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cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
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ret = devm_clk_hw_register(dev, &cfg_hw->hw);
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ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
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cfg_hw->id);
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id = cfg_hw->id;
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data->hw_data.hws[id] = &cfg_hw->hw;
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data->hw_data.hws[id] = &cfg_hw->cfg.hw;
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}
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return 0;
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_flags), \
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}
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#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw)
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#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
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/*
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* Critical clocks: