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dmaengine: stm32-dma: introduce 3 helpers to address channel flags

Channels 0 to 3 flags are described in DMA_LISR and DMA_LIFCR (L as Low).
Channels 4 to 7 flags are described in DMA_HISR and DMA_HIFCR (H as High).
Macro STM32_DMA_ISR(n) returns the interrupt status register offset for the
channel id (n).
Macro STM32_DMA_IFCR(n) returns the interrupt flag clear register offset
for the channel id (n).

If chan->id % 4 = 2 or 3, then its flags are left-shifted by 16 bits.
If chan->id % 4 = 1 or 3, then its flags are additionally left-shifted by 6
bits.
If chan->id % 4 = 0, then its flags are not shifted.
Macro STM32_DMA_FLAGS_SHIFT(n) returns the required shift to get or set the
channel flags mask.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20220829154646.29867-2-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Amelie Delaunay and committed by
Vinod Koul 4dc36a53 9e08d213

+12 -17
+12 -17
drivers/dma/stm32-dma.c
··· 32 32 33 33 #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */ 34 34 #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */ 35 + #define STM32_DMA_ISR(n) (((n) & 4) ? STM32_DMA_HISR : STM32_DMA_LISR) 35 36 #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */ 36 37 #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */ 38 + #define STM32_DMA_IFCR(n) (((n) & 4) ? STM32_DMA_HIFCR : STM32_DMA_LIFCR) 37 39 #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ 38 40 #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ 39 41 #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ ··· 45 43 | STM32_DMA_TEI \ 46 44 | STM32_DMA_DMEI \ 47 45 | STM32_DMA_FEI) 46 + /* 47 + * If (chan->id % 4) is 2 or 3, left shift the mask by 16 bits; 48 + * if (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 49 + */ 50 + #define STM32_DMA_FLAGS_SHIFT(n) ({ typeof(n) (_n) = (n); \ 51 + (((_n) & 2) << 3) | (((_n) & 1) * 6); }) 48 52 49 53 /* DMA Stream x Configuration Register */ 50 54 #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ ··· 409 401 /* 410 402 * Read "flags" from DMA_xISR register corresponding to the selected 411 403 * DMA channel at the correct bit offset inside that register. 412 - * 413 - * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 414 - * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 415 404 */ 416 405 417 - if (chan->id & 4) 418 - dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR); 419 - else 420 - dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR); 421 - 422 - flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 406 + dma_isr = stm32_dma_read(dmadev, STM32_DMA_ISR(chan->id)); 407 + flags = dma_isr >> STM32_DMA_FLAGS_SHIFT(chan->id); 423 408 424 409 return flags & STM32_DMA_MASKI; 425 410 } ··· 425 424 /* 426 425 * Write "flags" to the DMA_xIFCR register corresponding to the selected 427 426 * DMA channel at the correct bit offset inside that register. 428 - * 429 - * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 430 - * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 431 427 */ 432 428 flags &= STM32_DMA_MASKI; 433 - dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 429 + dma_ifcr = flags << STM32_DMA_FLAGS_SHIFT(chan->id); 434 430 435 - if (chan->id & 4) 436 - stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); 437 - else 438 - stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); 431 + stm32_dma_write(dmadev, STM32_DMA_IFCR(chan->id), dma_ifcr); 439 432 } 440 433 441 434 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)