Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86-cpu-2025-07-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu update from Ingo Molnar:
"Add user-space CPUID faulting support for AMD CPUs"
* tag 'x86-cpu-2025-07-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/CPU/AMD: Add CPUID faulting support
+21
-7
+3
arch/x86/include/asm/cpufeatures.h
+3
arch/x86/include/asm/cpufeatures.h
···
458
458
#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* LFENCE always serializing / synchronizes RDTSC */
459
459
#define X86_FEATURE_VERW_CLEAR (20*32+ 5) /* The memory form of VERW mitigates TSA */
460
460
#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* Null Selector Clears Base */
461
+
461
462
#define X86_FEATURE_AUTOIBRS (20*32+ 8) /* Automatic IBRS */
462
463
#define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* SMM_CTL MSR is not present */
464
+
465
+
#define X86_FEATURE_GP_ON_USER_CPUID (20*32+17) /* User CPUID faulting */
463
466
464
467
#define X86_FEATURE_PREFETCHI (20*32+20) /* Prefetch Data/Instruction to Cache Level */
465
468
#define X86_FEATURE_SBPB (20*32+27) /* Selective Branch Prediction Barrier */
+1
arch/x86/include/asm/msr-index.h
+1
arch/x86/include/asm/msr-index.h
···
831
831
#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
832
832
#define MSR_K7_HWCR_IRPERF_EN_BIT 30
833
833
#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
834
+
#define MSR_K7_HWCR_CPUID_USER_DIS_BIT 35
834
835
#define MSR_K7_FID_VID_CTL 0xc0010041
835
836
#define MSR_K7_FID_VID_STATUS 0xc0010042
836
837
#define MSR_K7_HWCR_CPB_DIS_BIT 25
+3
-1
arch/x86/kernel/cpu/amd.c
+3
-1
arch/x86/kernel/cpu/amd.c
+14
-6
arch/x86/kernel/process.c
+14
-6
arch/x86/kernel/process.c
···
334
334
335
335
static void set_cpuid_faulting(bool on)
336
336
{
337
-
u64 msrval;
338
337
339
-
msrval = this_cpu_read(msr_misc_features_shadow);
340
-
msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
341
-
msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
342
-
this_cpu_write(msr_misc_features_shadow, msrval);
343
-
wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval);
338
+
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
339
+
u64 msrval;
340
+
341
+
msrval = this_cpu_read(msr_misc_features_shadow);
342
+
msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
343
+
msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
344
+
this_cpu_write(msr_misc_features_shadow, msrval);
345
+
wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval);
346
+
} else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
347
+
if (on)
348
+
msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_CPUID_USER_DIS_BIT);
349
+
else
350
+
msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_CPUID_USER_DIS_BIT);
351
+
}
344
352
}
345
353
346
354
static void disable_cpuid(void)