Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann:
"These five newly supported chips come with both devicetree
descriptions and the changes to wire them up to the build system for
easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
in the product line that started with the Digital StrongARM SA1100
based PDAs and continued with the Intel PXA2xx that dominated early
smartphones. This one only made it only into a few products before
the entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies
and is in the 'Voyager' reference board in MicroATX form factor. It
uses four in-order AX45MP cores, which is the midrange product from
Andes.
- CIX P1 is one of the few Arm chips designed for small workstations,
and this one uses 12 Cortex-A720/A520 cores, making it also one of
the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53
CPU cores described as a "Trusted Control/Compute Unit" that can be
used as a BMC in servers. In addition to the usual I/O, this one
comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V and
Arm cores that can run Linux. This was already supported for RISC-V
but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the
merge window"
* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
arm64: Add SOPHGO SOC family Kconfig support
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
arm64: dts: sophgo: Add Duo Module 01
arm64: dts: sophgo: Add initial SG2000 SoC device tree
MAINTAINERS: Add entry for Axiado
arm64: defconfig: enable the Axiado family
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
arm64: add Axiado SoC family
dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
dt-bindings: serial: cdns: add Axiado AX3000 UART controller
dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
dt-bindings: gpio: cdns: convert to YAML
dt-bindings: arm: axiado: add AX3000 EVK compatible strings
dt-bindings: vendor-prefixes: Add Axiado Corporation
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
...
+3428
-63
+23
Documentation/devicetree/bindings/arm/axiado.yaml
+23
Documentation/devicetree/bindings/arm/axiado.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/axiado.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Axiado Platforms
8
+
9
+
maintainers:
10
+
- Harshit Shah <hshah@axiado.com>
11
+
12
+
properties:
13
+
$nodename:
14
+
const: '/'
15
+
compatible:
16
+
oneOf:
17
+
- description: AX3000 based boards
18
+
items:
19
+
- enum:
20
+
- axiado,ax3000-evk # Axiado AX3000 Evaluation Board
21
+
- const: axiado,ax3000 # Axiado AX3000 SoC
22
+
23
+
additionalProperties: true
+26
Documentation/devicetree/bindings/arm/cix.yaml
+26
Documentation/devicetree/bindings/arm/cix.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/cix.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: CIX platforms
8
+
9
+
maintainers:
10
+
- Peter Chen <peter.chen@cixtech.com>
11
+
- Fugang Duan <fugang.duan@cixtech.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
const: '/'
16
+
compatible:
17
+
oneOf:
18
+
19
+
- description: Radxa Orion O6
20
+
items:
21
+
- const: radxa,orion-o6
22
+
- const: cix,sky1
23
+
24
+
additionalProperties: true
25
+
26
+
...
+5
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
+5
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
-43
Documentation/devicetree/bindings/gpio/cdns,gpio.txt
-43
Documentation/devicetree/bindings/gpio/cdns,gpio.txt
···
1
-
Cadence GPIO controller bindings
2
-
3
-
Required properties:
4
-
- compatible: should be "cdns,gpio-r1p02".
5
-
- reg: the register base address and size.
6
-
- #gpio-cells: should be 2.
7
-
* first cell is the GPIO number.
8
-
* second cell specifies the GPIO flags, as defined in
9
-
<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
10
-
and GPIO_ACTIVE_LOW flags are supported.
11
-
- gpio-controller: marks the device as a GPIO controller.
12
-
- clocks: should contain one entry referencing the peripheral clock driving
13
-
the GPIO controller.
14
-
15
-
Optional properties:
16
-
- ngpios: integer number of gpio lines supported by this controller, up to 32.
17
-
- interrupts: interrupt specifier for the controllers interrupt.
18
-
- interrupt-controller: marks the device as an interrupt controller. When
19
-
defined, interrupts, interrupt-parent and #interrupt-cells
20
-
are required.
21
-
- interrupt-cells: should be 2.
22
-
* first cell is the GPIO number you want to use as an IRQ source.
23
-
* second cell specifies the IRQ type, as defined in
24
-
<dt-bindings/interrupt-controller/irq.h>.
25
-
Currently only level sensitive IRQs are supported.
26
-
27
-
28
-
Example:
29
-
gpio0: gpio-controller@fd060000 {
30
-
compatible = "cdns,gpio-r1p02";
31
-
reg =<0xfd060000 0x1000>;
32
-
33
-
clocks = <&gpio_clk>;
34
-
35
-
interrupt-parent = <&gic>;
36
-
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
37
-
38
-
gpio-controller;
39
-
#gpio-cells = <2>;
40
-
41
-
interrupt-controller;
42
-
#interrupt-cells = <2>;
43
-
};
+84
Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
+84
Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/cdns,gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cadence GPIO Controller
8
+
9
+
maintainers:
10
+
- Jan Kotas <jank@cadence.com>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- const: cdns,gpio-r1p02
16
+
- items:
17
+
- enum:
18
+
- axiado,ax3000-gpio
19
+
- const: cdns,gpio-r1p02
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
maxItems: 1
26
+
27
+
ngpios:
28
+
minimum: 1
29
+
maximum: 32
30
+
31
+
gpio-controller: true
32
+
33
+
"#gpio-cells":
34
+
const: 2
35
+
description: |
36
+
- First cell is the GPIO line number.
37
+
- Second cell is flags as defined in <dt-bindings/gpio/gpio.h>,
38
+
only GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW supported.
39
+
40
+
interrupt-controller: true
41
+
42
+
"#interrupt-cells":
43
+
const: 2
44
+
description: |
45
+
- First cell is the GPIO line number used as IRQ.
46
+
- Second cell is the trigger type, as defined in
47
+
<dt-bindings/interrupt-controller/irq.h>.
48
+
49
+
interrupts:
50
+
maxItems: 1
51
+
52
+
required:
53
+
- compatible
54
+
- reg
55
+
- clocks
56
+
- gpio-controller
57
+
- "#gpio-cells"
58
+
59
+
if:
60
+
required: [interrupt-controller]
61
+
then:
62
+
required:
63
+
- interrupts
64
+
65
+
additionalProperties: false
66
+
67
+
examples:
68
+
- |
69
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
70
+
#include <dt-bindings/interrupt-controller/irq.h>
71
+
gpio0: gpio-controller@fd060000 {
72
+
compatible = "cdns,gpio-r1p02";
73
+
reg = <0xfd060000 0x1000>;
74
+
clocks = <&gpio_clk>;
75
+
76
+
interrupt-parent = <&gic>;
77
+
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
78
+
79
+
gpio-controller;
80
+
#gpio-cells = <2>;
81
+
82
+
interrupt-controller;
83
+
#interrupt-cells = <2>;
84
+
};
+6
-1
Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
+6
-1
Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
+54
Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
+54
Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Andes machine-level software interrupt controller
8
+
9
+
description:
10
+
In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
11
+
second time with all interrupt sources tied to zero as the software interrupt
12
+
controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
13
+
inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
14
+
controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
15
+
generate machine-mode inter-processor interrupts through programming its
16
+
registers.
17
+
18
+
maintainers:
19
+
- Ben Zong-You Xie <ben717@andestech.com>
20
+
21
+
properties:
22
+
compatible:
23
+
items:
24
+
- enum:
25
+
- andestech,qilai-plicsw
26
+
- const: andestech,plicsw
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
interrupts-extended:
32
+
minItems: 1
33
+
maxItems: 15872
34
+
description:
35
+
Specifies which harts are connected to the PLIC_SW. Each item must points
36
+
to a riscv,cpu-intc node, which has a riscv cpu node as parent.
37
+
38
+
additionalProperties: false
39
+
40
+
required:
41
+
- compatible
42
+
- reg
43
+
- interrupts-extended
44
+
45
+
examples:
46
+
- |
47
+
interrupt-controller@400000 {
48
+
compatible = "andestech,qilai-plicsw", "andestech,plicsw";
49
+
reg = <0x400000 0x400000>;
50
+
interrupts-extended = <&cpu0intc 3>,
51
+
<&cpu1intc 3>,
52
+
<&cpu2intc 3>,
53
+
<&cpu3intc 3>;
54
+
};
+1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+77
Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml
+77
Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mailbox/cix,sky1-mbox.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cixtech mailbox controller
8
+
9
+
maintainers:
10
+
- Guomin Chen <Guomin.Chen@cixtech.com>
11
+
12
+
description:
13
+
The Cixtech mailbox controller, used in the Cixtech Sky1 SoC,
14
+
is used for message transmission between multiple processors
15
+
within the SoC, such as the AP, PM, audio DSP, SensorHub MCU,
16
+
and others
17
+
18
+
Each Cixtech mailbox controller is unidirectional, so they are
19
+
typically used in pairs-one for receiving and one for transmitting.
20
+
21
+
Each Cixtech mailbox supports 11 channels with different transmission modes
22
+
channel 0-7 - Fast channel with 32bit transmit register and IRQ support
23
+
channel 8 - Doorbell mode,using the mailbox as an interrupt-generating
24
+
mechanism.
25
+
channel 9 - Fifo based channel with 32*32bit depth fifo and IRQ support
26
+
channel 10 - Reg based channel with 32*32bit transmit register and
27
+
Doorbell+transmit acknowledgment IRQ support
28
+
29
+
In the CIX Sky1 SoC use case, there are 4 pairs of mailbox controllers
30
+
AP <--> PM - using Doorbell transfer mode
31
+
AP <--> SE - using REG transfer mode
32
+
AP <--> DSP - using FIFO transfer mode
33
+
AP <--> SensorHub - using FIFO transfer mode
34
+
35
+
properties:
36
+
compatible:
37
+
const: cix,sky1-mbox
38
+
39
+
reg:
40
+
maxItems: 1
41
+
42
+
interrupts:
43
+
maxItems: 1
44
+
45
+
"#mbox-cells":
46
+
const: 1
47
+
48
+
cix,mbox-dir:
49
+
$ref: /schemas/types.yaml#/definitions/string
50
+
description: Direction of the mailbox relative to the AP
51
+
enum: [tx, rx]
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
- interrupts
57
+
- "#mbox-cells"
58
+
- cix,mbox-dir
59
+
60
+
additionalProperties: false
61
+
62
+
examples:
63
+
- |
64
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
65
+
66
+
soc {
67
+
#address-cells = <2>;
68
+
#size-cells = <2>;
69
+
70
+
mbox_ap2pm: mailbox@30000000 {
71
+
compatible = "cix,sky1-mbox";
72
+
reg = <0 0x30000000 0 0x10000>;
73
+
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
74
+
#mbox-cells = <1>;
75
+
cix,mbox-dir = "tx";
76
+
};
77
+
};
+20
-16
Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
+20
-16
Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
···
30
30
maxItems: 1
31
31
reg-names:
32
32
maxItems: 1
33
+
- if:
34
+
properties:
35
+
compatible:
36
+
contains:
37
+
const: mrvl,pxav1-mmc
38
+
then:
39
+
properties:
40
+
pinctrl-names:
41
+
description:
42
+
Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between
43
+
SDIO CMD and GPIO mode.
44
+
items:
45
+
- const: default
46
+
- const: state_cmd_gpio
47
+
pinctrl-0:
48
+
description:
49
+
Should contain default pinctrl.
50
+
pinctrl-1:
51
+
description:
52
+
Should switch CMD pin to GPIO mode as a high output.
33
53
34
54
properties:
35
55
compatible:
···
81
61
items:
82
62
- const: io
83
63
- const: core
84
-
85
-
pinctrl-names:
86
-
description:
87
-
Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between
88
-
SDIO CMD and GPIO mode.
89
-
items:
90
-
- const: default
91
-
- const: state_cmd_gpio
92
-
93
-
pinctrl-0:
94
-
description:
95
-
Should contain default pinctrl.
96
-
97
-
pinctrl-1:
98
-
description:
99
-
Should switch CMD pin to GPIO mode as a high output.
100
64
101
65
mrvl,clk-delay-cycles:
102
66
description: Specify a number of cycles to delay for tuning.
+25
Documentation/devicetree/bindings/riscv/andes.yaml
+25
Documentation/devicetree/bindings/riscv/andes.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/riscv/andes.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Andes SoC-based boards
8
+
9
+
maintainers:
10
+
- Ben Zong-You Xie <ben717@andestech.com>
11
+
12
+
description:
13
+
Andes SoC-based boards
14
+
15
+
properties:
16
+
$nodename:
17
+
const: '/'
18
+
compatible:
19
+
oneOf:
20
+
- items:
21
+
- enum:
22
+
- andestech,voyager
23
+
- const: andestech,qilai
24
+
25
+
additionalProperties: true
+4
-3
Documentation/devicetree/bindings/serial/cdns,uart.yaml
+4
-3
Documentation/devicetree/bindings/serial/cdns,uart.yaml
···
16
16
items:
17
17
- const: xlnx,xuartps
18
18
- const: cdns,uart-r1p8
19
-
- description: UART controller for Zynq Ultrascale+ MPSoC
20
-
items:
21
-
- const: xlnx,zynqmp-uart
19
+
- items:
20
+
- enum:
21
+
- axiado,ax3000-uart
22
+
- xlnx,zynqmp-uart
22
23
- const: cdns,uart-r1p12
23
24
24
25
reg:
+53
Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
+53
Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Andes machine-level timer
8
+
9
+
description:
10
+
The Andes machine-level timer device (PLMT0) provides machine-level timer
11
+
functionality for a set of HARTs on a RISC-V platform. It has a single
12
+
fixed-frequency monotonic time counter (MTIME) register and a time compare
13
+
register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
14
+
generated if MTIME >= MTIMECMP.
15
+
16
+
maintainers:
17
+
- Ben Zong-You Xie <ben717@andestech.com>
18
+
19
+
properties:
20
+
compatible:
21
+
items:
22
+
- enum:
23
+
- andestech,qilai-plmt
24
+
- const: andestech,plmt0
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
interrupts-extended:
30
+
minItems: 1
31
+
maxItems: 32
32
+
description:
33
+
Specifies which harts are connected to the PLMT0. Each item must points
34
+
to a riscv,cpu-intc node, which has a riscv cpu node as parent. The
35
+
PLMT0 supports 1 hart up to 32 harts.
36
+
37
+
additionalProperties: false
38
+
39
+
required:
40
+
- compatible
41
+
- reg
42
+
- interrupts-extended
43
+
44
+
examples:
45
+
- |
46
+
interrupt-controller@100000 {
47
+
compatible = "andestech,qilai-plmt", "andestech,plmt0";
48
+
reg = <0x100000 0x100000>;
49
+
interrupts-extended = <&cpu0intc 7>,
50
+
<&cpu1intc 7>,
51
+
<&cpu2intc 7>,
52
+
<&cpu3intc 7>;
53
+
};
+4
Documentation/devicetree/bindings/vendor-prefixes.yaml
+4
Documentation/devicetree/bindings/vendor-prefixes.yaml
···
203
203
description: Shanghai Awinic Technology Co., Ltd.
204
204
"^axentia,.*":
205
205
description: Axentia Technologies AB
206
+
"^axiado,.*":
207
+
description: Axiado Corporation
206
208
"^axis,.*":
207
209
description: Axis Communications AB
208
210
"^azoteq,.*":
···
311
309
description: Cirrus Logic, Inc.
312
310
"^cisco,.*":
313
311
description: Cisco Systems, Inc.
312
+
"^cix,.*":
313
+
description: CIX Technology Group Co., Ltd.
314
314
"^clockwork,.*":
315
315
description: Clockwork Tech LLC
316
316
"^cloos,.*":
+38
MAINTAINERS
+38
MAINTAINERS
···
2449
2449
F: arch/arm/mach-aspeed/
2450
2450
N: aspeed
2451
2451
2452
+
ARM/AXIADO ARCHITECTURE
2453
+
M: Harshit Shah <hshah@axiado.com>
2454
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2455
+
S: Maintained
2456
+
F: Documentation/devicetree/bindings/arm/axiado.yaml
2457
+
F: arch/arm64/boot/dts/axiado/
2458
+
N: axiado
2459
+
2452
2460
ARM/AXM LSI SOC
2453
2461
M: Krzysztof Kozlowski <krzk@kernel.org>
2454
2462
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
···
2515
2507
F: arch/arm/boot/compressed/misc-ep93xx.h
2516
2508
F: arch/arm/mach-ep93xx/
2517
2509
F: drivers/iio/adc/ep93xx_adc.c
2510
+
2511
+
ARM/CIX SOC SUPPORT
2512
+
M: Peter Chen <peter.chen@cixtech.com>
2513
+
M: Fugang Duan <fugang.duan@cixtech.com>
2514
+
R: CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
2515
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2516
+
S: Maintained
2517
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix.git
2518
+
F: Documentation/devicetree/bindings/arm/cix.yaml
2519
+
F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml
2520
+
F: arch/arm64/boot/dts/cix/
2521
+
F: drivers/mailbox/cix-mailbox.c
2522
+
K: \bcix\b
2518
2523
2519
2524
ARM/CLKDEV SUPPORT
2520
2525
M: Russell King <linux@armlinux.org.uk>
···
2844
2823
F: drivers/irqchip/irq-mvebu-*
2845
2824
F: drivers/pinctrl/mvebu/
2846
2825
F: drivers/rtc/rtc-armada38x.c
2826
+
2827
+
ARM/Marvell PXA1908 SOC support
2828
+
M: Duje Mihanović <duje@dujemihanovic.xyz>
2829
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2830
+
S: Maintained
2831
+
F: arch/arm64/boot/dts/marvell/mmp/
2832
+
F: drivers/clk/mmp/clk-pxa1908*.c
2833
+
F: include/dt-bindings/clock/marvell,pxa1908.h
2847
2834
2848
2835
ARM/Mediatek RTC DRIVER
2849
2836
M: Eddie Huang <eddie.huang@mediatek.com>
···
21407
21378
F: drivers/irqchip/irq-riscv-intc.c
21408
21379
F: include/linux/irqchip/riscv-aplic.h
21409
21380
F: include/linux/irqchip/riscv-imsic.h
21381
+
21382
+
RISC-V ANDES SoC Support
21383
+
M: Ben Zong-You Xie <ben717@andestech.com>
21384
+
S: Maintained
21385
+
T: git: https://github.com/ben717-linux/linux
21386
+
F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
21387
+
F: Documentation/devicetree/bindings/riscv/andes.yaml
21388
+
F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
21389
+
F: arch/riscv/boot/dts/andes/
21410
21390
21411
21391
RISC-V ARCHITECTURE
21412
21392
M: Paul Walmsley <paul.walmsley@sifive.com>
+26
arch/arm64/Kconfig.platforms
+26
arch/arm64/Kconfig.platforms
···
40
40
This enables support for Apple's in-house ARM SoC family, such
41
41
as the Apple M1.
42
42
43
+
config ARCH_AXIADO
44
+
bool "Axiado SoC Family"
45
+
select GPIOLIB
46
+
help
47
+
This enables support for Axiado SoC family like AX3000
48
+
43
49
menuconfig ARCH_BCM
44
50
bool "Broadcom SoC Support"
45
51
···
111
105
bool "Blaize SoC Platforms"
112
106
help
113
107
This enables support for the Blaize SoC family
108
+
109
+
config ARCH_CIX
110
+
bool "Cixtech SoC family"
111
+
help
112
+
This enables support for the Cixtech SoC family,
113
+
like P1(sky1).
114
114
115
115
config ARCH_EXYNOS
116
116
bool "Samsung Exynos SoC family"
···
189
177
help
190
178
This enables support for the arm64 based Amlogic SoCs
191
179
such as the s905, S905X/D, S912, A113X/D or S905X/D2
180
+
181
+
config ARCH_MMP
182
+
bool "Marvell MMP SoC Family"
183
+
select PINCTRL
184
+
select PINCTRL_SINGLE
185
+
help
186
+
This enables support for Marvell MMP SoC family, currently
187
+
supporting PXA1908 aka IAP140.
192
188
193
189
config ARCH_MVEBU
194
190
bool "Marvell EBU SoC Family"
···
326
306
This enables support for Intel's SoCFPGA ARMv8 families:
327
307
Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
328
308
Agilex and eASIC N5X.
309
+
310
+
config ARCH_SOPHGO
311
+
bool "Sophgo SoCs"
312
+
select ARCH_HAS_RESET_CONTROLLER
313
+
help
314
+
This enables support for Sophgo SoC platform hardware.
329
315
330
316
config ARCH_STM32
331
317
bool "STMicroelectronics STM32 SoC Family"
+3
arch/arm64/boot/dts/Makefile
+3
arch/arm64/boot/dts/Makefile
···
9
9
subdir-y += apm
10
10
subdir-y += apple
11
11
subdir-y += arm
12
+
subdir-y += axiado
12
13
subdir-y += bitmain
13
14
subdir-y += blaize
14
15
subdir-y += broadcom
15
16
subdir-y += cavium
17
+
subdir-y += cix
16
18
subdir-y += exynos
17
19
subdir-y += freescale
18
20
subdir-y += hisilicon
···
30
28
subdir-y += renesas
31
29
subdir-y += rockchip
32
30
subdir-y += socionext
31
+
subdir-y += sophgo
33
32
subdir-y += sprd
34
33
subdir-y += st
35
34
subdir-y += synaptics
+2
arch/arm64/boot/dts/axiado/Makefile
+2
arch/arm64/boot/dts/axiado/Makefile
+79
arch/arm64/boot/dts/axiado/ax3000-evk.dts
+79
arch/arm64/boot/dts/axiado/ax3000-evk.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "ax3000.dtsi"
9
+
10
+
/ {
11
+
model = "Axiado AX3000 EVK";
12
+
compatible = "axiado,ax3000-evk", "axiado,ax3000";
13
+
#address-cells = <2>;
14
+
#size-cells = <2>;
15
+
16
+
aliases {
17
+
serial3 = &uart3;
18
+
};
19
+
20
+
chosen {
21
+
stdout-path = "serial3:115200";
22
+
};
23
+
24
+
memory@0 {
25
+
device_type = "memory";
26
+
/* Cortex-A53 will use following memory map */
27
+
reg = <0x00000000 0x3d000000 0x00000000 0x23000000>,
28
+
<0x00000004 0x00000000 0x00000000 0x80000000>;
29
+
};
30
+
};
31
+
32
+
/* GPIO bank 0 - 7 */
33
+
&gpio0 {
34
+
status = "okay";
35
+
};
36
+
37
+
&gpio1 {
38
+
status = "okay";
39
+
};
40
+
41
+
&gpio2 {
42
+
status = "okay";
43
+
};
44
+
45
+
&gpio3 {
46
+
status = "okay";
47
+
};
48
+
49
+
&gpio4 {
50
+
status = "okay";
51
+
};
52
+
53
+
&gpio5 {
54
+
status = "okay";
55
+
};
56
+
57
+
&gpio6 {
58
+
status = "okay";
59
+
};
60
+
61
+
&gpio7 {
62
+
status = "okay";
63
+
};
64
+
65
+
&uart0 {
66
+
status = "okay";
67
+
};
68
+
69
+
&uart1 {
70
+
status = "okay";
71
+
};
72
+
73
+
&uart2 {
74
+
status = "okay";
75
+
};
76
+
77
+
&uart3 {
78
+
status = "okay";
79
+
};
+520
arch/arm64/boot/dts/axiado/ax3000.dtsi
+520
arch/arm64/boot/dts/axiado/ax3000.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include <dt-bindings/interrupt-controller/irq.h>
9
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
10
+
11
+
/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
12
+
/ {
13
+
model = "Axiado AX3000";
14
+
interrupt-parent = <&gic500>;
15
+
#address-cells = <2>;
16
+
#size-cells = <2>;
17
+
18
+
cpus {
19
+
#address-cells = <2>;
20
+
#size-cells = <0>;
21
+
22
+
cpu0: cpu@0 {
23
+
device_type = "cpu";
24
+
compatible = "arm,cortex-a53";
25
+
reg = <0x0 0x0>;
26
+
enable-method = "spin-table";
27
+
cpu-release-addr = <0x0 0x3c0013a0>;
28
+
d-cache-size = <0x8000>;
29
+
d-cache-line-size = <64>;
30
+
d-cache-sets = <128>;
31
+
i-cache-size = <0x8000>;
32
+
i-cache-line-size = <64>;
33
+
i-cache-sets = <256>;
34
+
next-level-cache = <&l2>;
35
+
};
36
+
37
+
cpu1: cpu@1 {
38
+
device_type = "cpu";
39
+
compatible = "arm,cortex-a53";
40
+
reg = <0x0 0x1>;
41
+
enable-method = "spin-table";
42
+
cpu-release-addr = <0x0 0x3c0013a0>;
43
+
d-cache-size = <0x8000>;
44
+
d-cache-line-size = <64>;
45
+
d-cache-sets = <128>;
46
+
i-cache-size = <0x8000>;
47
+
i-cache-line-size = <64>;
48
+
i-cache-sets = <256>;
49
+
next-level-cache = <&l2>;
50
+
};
51
+
52
+
cpu2: cpu@2 {
53
+
device_type = "cpu";
54
+
compatible = "arm,cortex-a53";
55
+
reg = <0x0 0x2>;
56
+
enable-method = "spin-table";
57
+
cpu-release-addr = <0x0 0x3c0013a0>;
58
+
d-cache-size = <0x8000>;
59
+
d-cache-line-size = <64>;
60
+
d-cache-sets = <128>;
61
+
i-cache-size = <0x8000>;
62
+
i-cache-line-size = <64>;
63
+
i-cache-sets = <256>;
64
+
next-level-cache = <&l2>;
65
+
};
66
+
67
+
cpu3: cpu@3 {
68
+
device_type = "cpu";
69
+
compatible = "arm,cortex-a53";
70
+
reg = <0x0 0x3>;
71
+
enable-method = "spin-table";
72
+
cpu-release-addr = <0x0 0x3c0013a0>;
73
+
d-cache-size = <0x8000>;
74
+
d-cache-line-size = <64>;
75
+
d-cache-sets = <128>;
76
+
i-cache-size = <0x8000>;
77
+
i-cache-line-size = <64>;
78
+
i-cache-sets = <256>;
79
+
next-level-cache = <&l2>;
80
+
};
81
+
82
+
l2: l2-cache0 {
83
+
compatible = "cache";
84
+
cache-size = <0x100000>;
85
+
cache-unified;
86
+
cache-line-size = <64>;
87
+
cache-sets = <1024>;
88
+
cache-level = <2>;
89
+
};
90
+
};
91
+
92
+
clocks {
93
+
clk_xin: clock-200000000 {
94
+
compatible = "fixed-clock";
95
+
#clock-cells = <0>;
96
+
clock-frequency = <200000000>;
97
+
clock-output-names = "clk_xin";
98
+
};
99
+
100
+
refclk: clock-125000000 {
101
+
compatible = "fixed-clock";
102
+
#clock-cells = <0>;
103
+
clock-frequency = <125000000>;
104
+
};
105
+
};
106
+
107
+
soc {
108
+
compatible = "simple-bus";
109
+
ranges;
110
+
#address-cells = <2>;
111
+
#size-cells = <2>;
112
+
interrupt-parent = <&gic500>;
113
+
114
+
gic500: interrupt-controller@80300000 {
115
+
compatible = "arm,gic-v3";
116
+
reg = <0x00 0x80300000 0x00 0x10000>,
117
+
<0x00 0x80380000 0x00 0x80000>;
118
+
ranges;
119
+
#interrupt-cells = <3>;
120
+
#address-cells = <2>;
121
+
#size-cells = <2>;
122
+
interrupt-controller;
123
+
#redistributor-regions = <1>;
124
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
125
+
};
126
+
127
+
/* GPIO Controller banks 0 - 7 */
128
+
gpio0: gpio-controller@80500000 {
129
+
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
130
+
reg = <0x00 0x80500000 0x00 0x400>;
131
+
clocks = <&refclk>;
132
+
interrupt-parent = <&gic500>;
133
+
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
134
+
gpio-controller;
135
+
#gpio-cells = <2>;
136
+
interrupt-controller;
137
+
#interrupt-cells = <2>;
138
+
status = "disabled";
139
+
};
140
+
141
+
gpio1: gpio-controller@80580000 {
142
+
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
143
+
reg = <0x00 0x80580000 0x00 0x400>;
144
+
clocks = <&refclk>;
145
+
interrupt-parent = <&gic500>;
146
+
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
147
+
gpio-controller;
148
+
#gpio-cells = <2>;
149
+
interrupt-controller;
150
+
#interrupt-cells = <2>;
151
+
status = "disabled";
152
+
};
153
+
154
+
gpio2: gpio-controller@80600000 {
155
+
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
156
+
reg = <0x00 0x80600000 0x00 0x400>;
157
+
clocks = <&refclk>;
158
+
interrupt-parent = <&gic500>;
159
+
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
160
+
gpio-controller;
161
+
#gpio-cells = <2>;
162
+
interrupt-controller;
163
+
#interrupt-cells = <2>;
164
+
status = "disabled";
165
+
};
166
+
167
+
gpio3: gpio-controller@80680000 {
168
+
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
169
+
reg = <0x00 0x80680000 0x00 0x400>;
170
+
clocks = <&refclk>;
171
+
interrupt-parent = <&gic500>;
172
+
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
173
+
gpio-controller;
174
+
#gpio-cells = <2>;
175
+
interrupt-controller;
176
+
#interrupt-cells = <2>;
177
+
status = "disabled";
178
+
};
179
+
180
+
gpio4: gpio-controller@80700000 {
181
+
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
182
+
reg = <0x00 0x80700000 0x00 0x400>;
183
+
clocks = <&refclk>;
184
+
interrupt-parent = <&gic500>;
185
+
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
186
+
gpio-controller;
187
+
#gpio-cells = <2>;
188
+
interrupt-controller;
189
+
#interrupt-cells = <2>;
190
+
status = "disabled";
191
+
};
192
+
193
+
gpio5: gpio-controller@80780000 {
194
+
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
195
+
reg = <0x00 0x80780000 0x00 0x400>;
196
+
clocks = <&refclk>;
197
+
interrupt-parent = <&gic500>;
198
+
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
199
+
gpio-controller;
200
+
#gpio-cells = <2>;
201
+
interrupt-controller;
202
+
#interrupt-cells = <2>;
203
+
status = "disabled";
204
+
};
205
+
206
+
gpio6: gpio-controller@80800000 {
207
+
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
208
+
reg = <0x00 0x80800000 0x00 0x400>;
209
+
clocks = <&refclk>;
210
+
interrupt-parent = <&gic500>;
211
+
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
212
+
gpio-controller;
213
+
#gpio-cells = <2>;
214
+
interrupt-controller;
215
+
#interrupt-cells = <2>;
216
+
status = "disabled";
217
+
};
218
+
219
+
gpio7: gpio-controller@80880000 {
220
+
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
221
+
reg = <0x00 0x80880000 0x00 0x400>;
222
+
clocks = <&refclk>;
223
+
interrupt-parent = <&gic500>;
224
+
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
225
+
gpio-controller;
226
+
#gpio-cells = <2>;
227
+
interrupt-controller;
228
+
#interrupt-cells = <2>;
229
+
status = "disabled";
230
+
};
231
+
232
+
/* I3C Controller 0 - 16 */
233
+
i3c0: i3c@80500400 {
234
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
235
+
reg = <0x00 0x80500400 0x00 0x400>;
236
+
clocks = <&refclk &clk_xin>;
237
+
clock-names = "pclk", "sysclk";
238
+
interrupt-parent = <&gic500>;
239
+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
240
+
i2c-scl-hz = <100000>;
241
+
i3c-scl-hz = <400000>;
242
+
#address-cells = <3>;
243
+
#size-cells = <0>;
244
+
status = "disabled";
245
+
};
246
+
247
+
i3c1: i3c@80500800 {
248
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
249
+
reg = <0x00 0x80500800 0x00 0x400>;
250
+
clocks = <&refclk &clk_xin>;
251
+
clock-names = "pclk", "sysclk";
252
+
interrupt-parent = <&gic500>;
253
+
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
254
+
i2c-scl-hz = <100000>;
255
+
i3c-scl-hz = <400000>;
256
+
#address-cells = <3>;
257
+
#size-cells = <0>;
258
+
status = "disabled";
259
+
};
260
+
261
+
i3c2: i3c@80580400 {
262
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
263
+
reg = <0x00 0x80580400 0x00 0x400>;
264
+
clocks = <&refclk &clk_xin>;
265
+
clock-names = "pclk", "sysclk";
266
+
interrupt-parent = <&gic500>;
267
+
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
268
+
i2c-scl-hz = <100000>;
269
+
i3c-scl-hz = <400000>;
270
+
#address-cells = <3>;
271
+
#size-cells = <0>;
272
+
status = "disabled";
273
+
};
274
+
275
+
i3c3: i3c@80580800 {
276
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
277
+
reg = <0x00 0x80580800 0x00 0x400>;
278
+
clocks = <&refclk &clk_xin>;
279
+
clock-names = "pclk", "sysclk";
280
+
interrupt-parent = <&gic500>;
281
+
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
282
+
i2c-scl-hz = <100000>;
283
+
i3c-scl-hz = <400000>;
284
+
#address-cells = <3>;
285
+
#size-cells = <0>;
286
+
status = "disabled";
287
+
};
288
+
289
+
i3c4: i3c@80600400 {
290
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
291
+
reg = <0x00 0x80600400 0x00 0x400>;
292
+
clocks = <&refclk &clk_xin>;
293
+
clock-names = "pclk", "sysclk";
294
+
interrupt-parent = <&gic500>;
295
+
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
296
+
i2c-scl-hz = <100000>;
297
+
i3c-scl-hz = <400000>;
298
+
#address-cells = <3>;
299
+
#size-cells = <0>;
300
+
status = "disabled";
301
+
};
302
+
303
+
i3c5: i3c@80600800 {
304
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
305
+
reg = <0x00 0x80600800 0x00 0x400>;
306
+
clocks = <&refclk &clk_xin>;
307
+
clock-names = "pclk", "sysclk";
308
+
interrupt-parent = <&gic500>;
309
+
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
310
+
i2c-scl-hz = <100000>;
311
+
i3c-scl-hz = <400000>;
312
+
#address-cells = <3>;
313
+
#size-cells = <0>;
314
+
status = "disabled";
315
+
};
316
+
317
+
i3c6: i3c@80680400 {
318
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
319
+
reg = <0x00 0x80680400 0x00 0x400>;
320
+
clocks = <&refclk &clk_xin>;
321
+
clock-names = "pclk", "sysclk";
322
+
interrupt-parent = <&gic500>;
323
+
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
324
+
i2c-scl-hz = <100000>;
325
+
i3c-scl-hz = <400000>;
326
+
#address-cells = <3>;
327
+
#size-cells = <0>;
328
+
status = "disabled";
329
+
};
330
+
331
+
i3c7: i3c@80680800 {
332
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
333
+
reg = <0x00 0x80680800 0x00 0x400>;
334
+
clocks = <&refclk &clk_xin>;
335
+
clock-names = "pclk", "sysclk";
336
+
interrupt-parent = <&gic500>;
337
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
338
+
i2c-scl-hz = <100000>;
339
+
i3c-scl-hz = <400000>;
340
+
#address-cells = <3>;
341
+
#size-cells = <0>;
342
+
status = "disabled";
343
+
};
344
+
345
+
i3c8: i3c@80700400 {
346
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
347
+
reg = <0x00 0x80700400 0x00 0x400>;
348
+
clocks = <&refclk &clk_xin>;
349
+
clock-names = "pclk", "sysclk";
350
+
interrupt-parent = <&gic500>;
351
+
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
352
+
i2c-scl-hz = <100000>;
353
+
i3c-scl-hz = <400000>;
354
+
#address-cells = <3>;
355
+
#size-cells = <0>;
356
+
status = "disabled";
357
+
};
358
+
359
+
i3c9: i3c@80700800 {
360
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
361
+
reg = <0x00 0x80700800 0x00 0x400>;
362
+
clocks = <&refclk &clk_xin>;
363
+
clock-names = "pclk", "sysclk";
364
+
interrupt-parent = <&gic500>;
365
+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
366
+
i2c-scl-hz = <100000>;
367
+
i3c-scl-hz = <400000>;
368
+
#address-cells = <3>;
369
+
#size-cells = <0>;
370
+
status = "disabled";
371
+
};
372
+
373
+
i3c10: i3c@80780400 {
374
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
375
+
reg = <0x00 0x80780400 0x00 0x400>;
376
+
clocks = <&refclk &clk_xin>;
377
+
clock-names = "pclk", "sysclk";
378
+
interrupt-parent = <&gic500>;
379
+
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
380
+
i2c-scl-hz = <100000>;
381
+
i3c-scl-hz = <400000>;
382
+
#address-cells = <3>;
383
+
#size-cells = <0>;
384
+
status = "disabled";
385
+
};
386
+
387
+
i3c11: i3c@80780800 {
388
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
389
+
reg = <0x00 0x80780800 0x00 0x400>;
390
+
clocks = <&refclk &clk_xin>;
391
+
clock-names = "pclk", "sysclk";
392
+
interrupt-parent = <&gic500>;
393
+
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
394
+
i2c-scl-hz = <100000>;
395
+
i3c-scl-hz = <400000>;
396
+
#address-cells = <3>;
397
+
#size-cells = <0>;
398
+
status = "disabled";
399
+
};
400
+
401
+
i3c12: i3c@80800400 {
402
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
403
+
reg = <0x00 0x80800400 0x00 0x400>;
404
+
clocks = <&refclk &clk_xin>;
405
+
clock-names = "pclk", "sysclk";
406
+
interrupt-parent = <&gic500>;
407
+
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
408
+
i2c-scl-hz = <100000>;
409
+
i3c-scl-hz = <400000>;
410
+
#address-cells = <3>;
411
+
#size-cells = <0>;
412
+
status = "disabled";
413
+
};
414
+
415
+
i3c13: i3c@80800800 {
416
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
417
+
reg = <0x00 0x80800800 0x00 0x400>;
418
+
clocks = <&refclk &clk_xin>;
419
+
clock-names = "pclk", "sysclk";
420
+
interrupt-parent = <&gic500>;
421
+
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
422
+
i2c-scl-hz = <100000>;
423
+
i3c-scl-hz = <400000>;
424
+
#address-cells = <3>;
425
+
#size-cells = <0>;
426
+
status = "disabled";
427
+
};
428
+
429
+
i3c14: i3c@80880400 {
430
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
431
+
reg = <0x00 0x80880400 0x00 0x400>;
432
+
clocks = <&refclk &clk_xin>;
433
+
clock-names = "pclk", "sysclk";
434
+
interrupt-parent = <&gic500>;
435
+
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
436
+
i2c-scl-hz = <100000>;
437
+
i3c-scl-hz = <400000>;
438
+
#address-cells = <3>;
439
+
#size-cells = <0>;
440
+
status = "disabled";
441
+
};
442
+
443
+
i3c15: i3c@80880800 {
444
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
445
+
reg = <0x00 0x80880800 0x00 0x400>;
446
+
clocks = <&refclk &clk_xin>;
447
+
clock-names = "pclk", "sysclk";
448
+
interrupt-parent = <&gic500>;
449
+
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
450
+
i2c-scl-hz = <100000>;
451
+
i3c-scl-hz = <400000>;
452
+
#address-cells = <3>;
453
+
#size-cells = <0>;
454
+
status = "disabled";
455
+
};
456
+
457
+
i3c16: i3c@80620400 {
458
+
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
459
+
reg = <0x00 0x80620400 0x00 0x400>;
460
+
clocks = <&refclk &clk_xin>;
461
+
clock-names = "pclk", "sysclk";
462
+
interrupt-parent = <&gic500>;
463
+
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
464
+
i2c-scl-hz = <100000>;
465
+
i3c-scl-hz = <400000>;
466
+
#address-cells = <3>;
467
+
#size-cells = <0>;
468
+
status = "disabled";
469
+
};
470
+
471
+
uart0: serial@80520000 {
472
+
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
473
+
reg = <0x00 0x80520000 0x00 0x100>;
474
+
interrupt-parent = <&gic500>;
475
+
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
476
+
clock-names = "uart_clk", "pclk";
477
+
clocks = <&refclk &refclk>;
478
+
status = "disabled";
479
+
};
480
+
481
+
uart1: serial@805a0000 {
482
+
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
483
+
reg = <0x00 0x805A0000 0x00 0x100>;
484
+
interrupt-parent = <&gic500>;
485
+
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
486
+
clock-names = "uart_clk", "pclk";
487
+
clocks = <&refclk &refclk>;
488
+
status = "disabled";
489
+
};
490
+
491
+
uart2: serial@80620000 {
492
+
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
493
+
reg = <0x00 0x80620000 0x00 0x100>;
494
+
interrupt-parent = <&gic500>;
495
+
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
496
+
clock-names = "uart_clk", "pclk";
497
+
clocks = <&refclk &refclk>;
498
+
status = "disabled";
499
+
};
500
+
501
+
uart3: serial@80520800 {
502
+
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
503
+
reg = <0x00 0x80520800 0x00 0x100>;
504
+
interrupt-parent = <&gic500>;
505
+
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
506
+
clock-names = "uart_clk", "pclk";
507
+
clocks = <&refclk &refclk>;
508
+
status = "disabled";
509
+
};
510
+
};
511
+
512
+
timer {
513
+
compatible = "arm,armv8-timer";
514
+
interrupt-parent = <&gic500>;
515
+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
516
+
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
517
+
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
518
+
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
519
+
};
520
+
};
+2
arch/arm64/boot/dts/cix/Makefile
+2
arch/arm64/boot/dts/cix/Makefile
+39
arch/arm64/boot/dts/cix/sky1-orion-o6.dts
+39
arch/arm64/boot/dts/cix/sky1-orion-o6.dts
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright 2025 Cix Technology Group Co., Ltd.
4
+
*
5
+
*/
6
+
7
+
/dts-v1/;
8
+
9
+
#include "sky1.dtsi"
10
+
/ {
11
+
model = "Radxa Orion O6";
12
+
compatible = "radxa,orion-o6", "cix,sky1";
13
+
14
+
aliases {
15
+
serial2 = &uart2;
16
+
};
17
+
18
+
chosen {
19
+
stdout-path = &uart2;
20
+
};
21
+
22
+
reserved-memory {
23
+
#address-cells = <2>;
24
+
#size-cells = <2>;
25
+
ranges;
26
+
27
+
linux,cma {
28
+
compatible = "shared-dma-pool";
29
+
reusable;
30
+
size = <0x0 0x28000000>;
31
+
linux,cma-default;
32
+
};
33
+
};
34
+
35
+
};
36
+
37
+
&uart2 {
38
+
status = "okay";
39
+
};
+330
arch/arm64/boot/dts/cix/sky1.dtsi
+330
arch/arm64/boot/dts/cix/sky1.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright 2025 Cix Technology Group Co., Ltd.
4
+
*
5
+
*/
6
+
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
#include <dt-bindings/clock/cix,sky1.h>
9
+
10
+
/ {
11
+
interrupt-parent = <&gic>;
12
+
#address-cells = <2>;
13
+
#size-cells = <2>;
14
+
15
+
cpus {
16
+
#address-cells = <2>;
17
+
#size-cells = <0>;
18
+
19
+
cpu0: cpu@0 {
20
+
compatible = "arm,cortex-a520";
21
+
enable-method = "psci";
22
+
reg = <0x0 0x0>;
23
+
device_type = "cpu";
24
+
capacity-dmips-mhz = <403>;
25
+
};
26
+
27
+
cpu1: cpu@100 {
28
+
compatible = "arm,cortex-a520";
29
+
enable-method = "psci";
30
+
reg = <0x0 0x100>;
31
+
device_type = "cpu";
32
+
capacity-dmips-mhz = <403>;
33
+
};
34
+
35
+
cpu2: cpu@200 {
36
+
compatible = "arm,cortex-a520";
37
+
enable-method = "psci";
38
+
reg = <0x0 0x200>;
39
+
device_type = "cpu";
40
+
capacity-dmips-mhz = <403>;
41
+
};
42
+
43
+
cpu3: cpu@300 {
44
+
compatible = "arm,cortex-a520";
45
+
enable-method = "psci";
46
+
reg = <0x0 0x300>;
47
+
device_type = "cpu";
48
+
capacity-dmips-mhz = <403>;
49
+
};
50
+
51
+
cpu4: cpu@400 {
52
+
compatible = "arm,cortex-a720";
53
+
enable-method = "psci";
54
+
reg = <0x0 0x400>;
55
+
device_type = "cpu";
56
+
capacity-dmips-mhz = <1024>;
57
+
};
58
+
59
+
cpu5: cpu@500 {
60
+
compatible = "arm,cortex-a720";
61
+
enable-method = "psci";
62
+
reg = <0x0 0x500>;
63
+
device_type = "cpu";
64
+
capacity-dmips-mhz = <1024>;
65
+
};
66
+
67
+
cpu6: cpu@600 {
68
+
compatible = "arm,cortex-a720";
69
+
enable-method = "psci";
70
+
reg = <0x0 0x600>;
71
+
device_type = "cpu";
72
+
capacity-dmips-mhz = <1024>;
73
+
};
74
+
75
+
cpu7: cpu@700 {
76
+
compatible = "arm,cortex-a720";
77
+
enable-method = "psci";
78
+
reg = <0x0 0x700>;
79
+
device_type = "cpu";
80
+
capacity-dmips-mhz = <1024>;
81
+
};
82
+
83
+
cpu8: cpu@800 {
84
+
compatible = "arm,cortex-a720";
85
+
enable-method = "psci";
86
+
reg = <0x0 0x800>;
87
+
device_type = "cpu";
88
+
capacity-dmips-mhz = <1024>;
89
+
};
90
+
91
+
cpu9: cpu@900 {
92
+
compatible = "arm,cortex-a720";
93
+
enable-method = "psci";
94
+
reg = <0x0 0x900>;
95
+
device_type = "cpu";
96
+
capacity-dmips-mhz = <1024>;
97
+
};
98
+
99
+
cpu10: cpu@a00 {
100
+
compatible = "arm,cortex-a720";
101
+
enable-method = "psci";
102
+
reg = <0x0 0xa00>;
103
+
device_type = "cpu";
104
+
capacity-dmips-mhz = <1024>;
105
+
};
106
+
107
+
cpu11: cpu@b00 {
108
+
compatible = "arm,cortex-a720";
109
+
enable-method = "psci";
110
+
reg = <0x0 0xb00>;
111
+
device_type = "cpu";
112
+
capacity-dmips-mhz = <1024>;
113
+
};
114
+
115
+
cpu-map {
116
+
cluster0 {
117
+
core0 {
118
+
cpu = <&cpu0>;
119
+
};
120
+
core1 {
121
+
cpu = <&cpu1>;
122
+
};
123
+
core2 {
124
+
cpu = <&cpu2>;
125
+
};
126
+
core3 {
127
+
cpu = <&cpu3>;
128
+
};
129
+
core4 {
130
+
cpu = <&cpu4>;
131
+
};
132
+
core5 {
133
+
cpu = <&cpu5>;
134
+
};
135
+
core6 {
136
+
cpu = <&cpu6>;
137
+
};
138
+
core7 {
139
+
cpu = <&cpu7>;
140
+
};
141
+
core8 {
142
+
cpu = <&cpu8>;
143
+
};
144
+
core9 {
145
+
cpu = <&cpu9>;
146
+
};
147
+
core10 {
148
+
cpu = <&cpu10>;
149
+
};
150
+
core11 {
151
+
cpu = <&cpu11>;
152
+
};
153
+
};
154
+
};
155
+
};
156
+
157
+
firmware {
158
+
ap_to_pm_scmi: scmi {
159
+
compatible = "arm,scmi";
160
+
mbox-names = "tx", "rx";
161
+
mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>;
162
+
shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>;
163
+
#address-cells = <1>;
164
+
#size-cells = <0>;
165
+
166
+
scmi_clk: protocol@14 {
167
+
reg = <0x14>;
168
+
#clock-cells = <1>;
169
+
};
170
+
};
171
+
};
172
+
173
+
pmu-a520 {
174
+
compatible = "arm,cortex-a520-pmu";
175
+
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
176
+
};
177
+
178
+
pmu-a720 {
179
+
compatible = "arm,cortex-a720-pmu";
180
+
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
181
+
};
182
+
183
+
psci {
184
+
compatible = "arm,psci-1.0";
185
+
method = "smc";
186
+
};
187
+
188
+
soc@0 {
189
+
compatible = "simple-bus";
190
+
ranges = <0 0 0 0 0x20 0>;
191
+
dma-ranges;
192
+
#address-cells = <2>;
193
+
#size-cells = <2>;
194
+
195
+
uart0: serial@40b0000 {
196
+
compatible = "arm,pl011", "arm,primecell";
197
+
reg = <0x0 0x040b0000 0x0 0x1000>;
198
+
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>;
199
+
clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>;
200
+
clock-names = "uartclk", "apb_pclk";
201
+
status = "disabled";
202
+
};
203
+
204
+
uart1: serial@40c0000 {
205
+
compatible = "arm,pl011", "arm,primecell";
206
+
reg = <0x0 0x040c0000 0x0 0x1000>;
207
+
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
208
+
clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>;
209
+
clock-names = "uartclk", "apb_pclk";
210
+
status = "disabled";
211
+
};
212
+
213
+
uart2: serial@40d0000 {
214
+
compatible = "arm,pl011", "arm,primecell";
215
+
reg = <0x0 0x040d0000 0x0 0x1000>;
216
+
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
217
+
clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>;
218
+
clock-names = "uartclk", "apb_pclk";
219
+
status = "disabled";
220
+
};
221
+
222
+
uart3: serial@40e0000 {
223
+
compatible = "arm,pl011", "arm,primecell";
224
+
reg = <0x0 0x040e0000 0x0 0x1000>;
225
+
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
226
+
clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>;
227
+
clock-names = "uartclk", "apb_pclk";
228
+
status = "disabled";
229
+
};
230
+
231
+
mbox_ap2se: mailbox@5060000 {
232
+
compatible = "cix,sky1-mbox";
233
+
reg = <0x0 0x05060000 0x0 0x10000>;
234
+
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>;
235
+
#mbox-cells = <1>;
236
+
cix,mbox-dir = "tx";
237
+
};
238
+
239
+
mbox_se2ap: mailbox@5070000 {
240
+
compatible = "cix,sky1-mbox";
241
+
reg = <0x0 0x05070000 0x0 0x10000>;
242
+
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
243
+
#mbox-cells = <1>;
244
+
cix,mbox-dir = "rx";
245
+
};
246
+
247
+
ap2pm_scmi_mem: shmem@6590000 {
248
+
compatible = "arm,scmi-shmem";
249
+
reg = <0x0 0x06590000 0x0 0x80>;
250
+
reg-io-width = <4>;
251
+
};
252
+
253
+
mbox_ap2pm: mailbox@6590080 {
254
+
compatible = "cix,sky1-mbox";
255
+
reg = <0x0 0x06590080 0x0 0xff80>;
256
+
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
257
+
#mbox-cells = <1>;
258
+
cix,mbox-dir = "tx";
259
+
};
260
+
261
+
pm2ap_scmi_mem: shmem@65a0000 {
262
+
compatible = "arm,scmi-shmem";
263
+
reg = <0x0 0x065a0000 0x0 0x80>;
264
+
reg-io-width = <4>;
265
+
};
266
+
267
+
mbox_pm2ap: mailbox@65a0080 {
268
+
compatible = "cix,sky1-mbox";
269
+
reg = <0x0 0x065a0080 0x0 0xff80>;
270
+
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>;
271
+
#mbox-cells = <1>;
272
+
cix,mbox-dir = "rx";
273
+
};
274
+
275
+
mbox_sfh2ap: mailbox@8090000 {
276
+
compatible = "cix,sky1-mbox";
277
+
reg = <0x0 0x08090000 0x0 0x10000>;
278
+
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
279
+
#mbox-cells = <1>;
280
+
cix,mbox-dir = "rx";
281
+
};
282
+
283
+
mbox_ap2sfh: mailbox@80a0000 {
284
+
compatible = "cix,sky1-mbox";
285
+
reg = <0x0 0x080a0000 0x0 0x10000>;
286
+
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
287
+
#mbox-cells = <1>;
288
+
cix,mbox-dir = "tx";
289
+
};
290
+
291
+
gic: interrupt-controller@e010000 {
292
+
compatible = "arm,gic-v3";
293
+
reg = <0x0 0x0e010000 0 0x10000>, /* GICD */
294
+
<0x0 0x0e090000 0 0x300000>; /* GICR * 12 */
295
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
296
+
#interrupt-cells = <4>;
297
+
interrupt-controller;
298
+
#address-cells = <2>;
299
+
#size-cells = <2>;
300
+
ranges;
301
+
302
+
gic_its: msi-controller@e050000 {
303
+
compatible = "arm,gic-v3-its";
304
+
reg = <0x0 0x0e050000 0x0 0x30000>;
305
+
msi-controller;
306
+
#msi-cells = <1>;
307
+
};
308
+
309
+
ppi-partitions {
310
+
ppi_partition0: interrupt-partition-0 {
311
+
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
312
+
};
313
+
314
+
ppi_partition1: interrupt-partition-1 {
315
+
affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>;
316
+
};
317
+
};
318
+
};
319
+
};
320
+
321
+
timer {
322
+
compatible = "arm,armv8-timer";
323
+
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
324
+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
325
+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
326
+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
327
+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
328
+
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
329
+
};
330
+
};
+2
arch/arm64/boot/dts/marvell/Makefile
+2
arch/arm64/boot/dts/marvell/Makefile
+2
arch/arm64/boot/dts/marvell/mmp/Makefile
+2
arch/arm64/boot/dts/marvell/mmp/Makefile
+331
arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts
+331
arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
#include "pxa1908.dtsi"
3
+
#include <dt-bindings/gpio/gpio.h>
4
+
#include <dt-bindings/input/linux-event-codes.h>
5
+
6
+
/ {
7
+
model = "Samsung Galaxy Core Prime VE LTE";
8
+
compatible = "samsung,coreprimevelte", "marvell,pxa1908";
9
+
10
+
aliases {
11
+
mmc0 = &sdh2; /* eMMC */
12
+
mmc1 = &sdh0; /* SD card */
13
+
serial0 = &uart0;
14
+
};
15
+
16
+
chosen {
17
+
#address-cells = <2>;
18
+
#size-cells = <2>;
19
+
ranges;
20
+
21
+
stdout-path = "serial0:115200n8";
22
+
23
+
fb0: framebuffer@17177000 {
24
+
compatible = "simple-framebuffer";
25
+
reg = <0 0x17177000 0 (480 * 800 * 4)>;
26
+
width = <480>;
27
+
height = <800>;
28
+
stride = <(480 * 4)>;
29
+
format = "a8r8g8b8";
30
+
};
31
+
};
32
+
33
+
/* Bootloader fills this in */
34
+
memory@0 {
35
+
device_type = "memory";
36
+
reg = <0 0 0 0>;
37
+
};
38
+
39
+
reserved-memory {
40
+
#address-cells = <2>;
41
+
#size-cells = <2>;
42
+
ranges;
43
+
44
+
framebuffer@17000000 {
45
+
reg = <0 0x17000000 0 0x1800000>;
46
+
no-map;
47
+
};
48
+
49
+
gpu@9000000 {
50
+
reg = <0 0x9000000 0 0x1000000>;
51
+
};
52
+
53
+
/* Communications processor, aka modem */
54
+
cp@5000000 {
55
+
reg = <0 0x5000000 0 0x3000000>;
56
+
};
57
+
58
+
cm3@a000000 {
59
+
reg = <0 0xa000000 0 0x80000>;
60
+
};
61
+
62
+
seclog@8000000 {
63
+
reg = <0 0x8000000 0 0x100000>;
64
+
};
65
+
66
+
ramoops@8100000 {
67
+
compatible = "ramoops";
68
+
reg = <0 0x8100000 0 0x40000>;
69
+
record-size = <0x8000>;
70
+
console-size = <0x20000>;
71
+
max-reason = <5>;
72
+
};
73
+
};
74
+
75
+
i2c-muic {
76
+
compatible = "i2c-gpio";
77
+
sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
78
+
scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
79
+
i2c-gpio,delay-us = <3>;
80
+
i2c-gpio,timeout-ms = <100>;
81
+
#address-cells = <1>;
82
+
#size-cells = <0>;
83
+
pinctrl-names = "default";
84
+
pinctrl-0 = <&i2c_muic_pins>;
85
+
86
+
muic: extcon@14 {
87
+
compatible = "siliconmitus,sm5504-muic";
88
+
reg = <0x14>;
89
+
interrupt-parent = <&gpio>;
90
+
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
91
+
};
92
+
};
93
+
94
+
gpio-keys {
95
+
compatible = "gpio-keys";
96
+
pinctrl-names = "default";
97
+
pinctrl-0 = <&gpio_keys_pins>;
98
+
autorepeat;
99
+
100
+
key-home {
101
+
label = "Home";
102
+
linux,code = <KEY_HOME>;
103
+
gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
104
+
};
105
+
106
+
key-volup {
107
+
label = "Volume Up";
108
+
linux,code = <KEY_VOLUMEUP>;
109
+
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
110
+
};
111
+
112
+
key-voldown {
113
+
label = "Volume Down";
114
+
linux,code = <KEY_VOLUMEDOWN>;
115
+
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
116
+
};
117
+
};
118
+
};
119
+
120
+
&smmu {
121
+
status = "okay";
122
+
};
123
+
124
+
&pmx {
125
+
pinctrl-single,gpio-range = <&range 55 55 0>,
126
+
<&range 110 32 0>,
127
+
<&range 52 1 0>;
128
+
129
+
pinctrl-names = "default";
130
+
pinctrl-0 = <&board_pins_0 &board_pins_1 &board_pins_2>;
131
+
132
+
board_pins_0: board-pins-0 {
133
+
pinctrl-single,pins = <
134
+
0x160 0
135
+
0x164 0
136
+
0x168 0
137
+
0x16c 0
138
+
>;
139
+
pinctrl-single,drive-strength = <0x1000 0x1800>;
140
+
pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>;
141
+
pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>;
142
+
pinctrl-single,input-schmitt = <0 0x30>;
143
+
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
144
+
pinctrl-single,low-power-mode = <0x288 0x388>;
145
+
};
146
+
147
+
board_pins_1: board-pins-1 {
148
+
pinctrl-single,pins = <
149
+
0x44 1
150
+
0x48 1
151
+
0x20 1
152
+
0x18 1
153
+
0x14 1
154
+
0x10 1
155
+
0xc 1
156
+
0x8 1
157
+
0x68 1
158
+
0x58 0
159
+
0x54 0
160
+
0x7c 0
161
+
0x6c 0
162
+
0x70 0
163
+
0x4c 1
164
+
0x50 1
165
+
0xac 0
166
+
0x90 0
167
+
0x8c 0
168
+
0x88 0
169
+
0x84 0
170
+
0xc8 0
171
+
0x128 0
172
+
0x190 0
173
+
0x194 0
174
+
0x1a0 0
175
+
0x114 0
176
+
0x118 0
177
+
0x1d8 0
178
+
0x1e4 0
179
+
0xe8 0
180
+
0x100 0
181
+
0x204 0
182
+
0x210 0
183
+
0x218 0
184
+
>;
185
+
pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
186
+
pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xc000>;
187
+
pinctrl-single,low-power-mode = <0x288 0x388>;
188
+
};
189
+
190
+
board_pins_2: board-pins-2 {
191
+
pinctrl-single,pins = <
192
+
0x260 0
193
+
0x264 0
194
+
0x268 0
195
+
0x26c 0
196
+
0x270 0
197
+
0x274 0
198
+
0x78 0
199
+
0x74 0
200
+
0xb0 1
201
+
>;
202
+
pinctrl-single,drive-strength = <0x1000 0x1800>;
203
+
pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
204
+
pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
205
+
pinctrl-single,input-schmitt = <0 0x30>;
206
+
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
207
+
pinctrl-single,low-power-mode = <0 0x388>;
208
+
};
209
+
210
+
uart0_pins: uart0-pins {
211
+
pinctrl-single,pins = <
212
+
0x198 6
213
+
0x19c 6
214
+
>;
215
+
pinctrl-single,drive-strength = <0x1000 0x1800>;
216
+
pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
217
+
pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
218
+
pinctrl-single,input-schmitt = <0 0x30>;
219
+
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
220
+
pinctrl-single,low-power-mode = <0 0x388>;
221
+
};
222
+
223
+
gpio_keys_pins: gpio-keys-pins {
224
+
pinctrl-single,pins = <
225
+
0x11c 0
226
+
0x120 0
227
+
0x1a4 0
228
+
>;
229
+
pinctrl-single,drive-strength = <0x1000 0x1800>;
230
+
pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
231
+
pinctrl-single,bias-pulldown = <0x8000 0xa0000 0x8000 0xa000>;
232
+
pinctrl-single,input-schmitt = <0 0x30>;
233
+
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
234
+
pinctrl-single,low-power-mode = <0 0x388>;
235
+
};
236
+
237
+
i2c_muic_pins: i2c-muic-pins {
238
+
pinctrl-single,pins = <
239
+
0x154 0
240
+
0x150 0
241
+
>;
242
+
pinctrl-single,drive-strength = <0x1000 0x1800>;
243
+
pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
244
+
pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
245
+
pinctrl-single,input-schmitt = <0 0x30>;
246
+
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
247
+
pinctrl-single,low-power-mode = <0x288 0x388>;
248
+
};
249
+
250
+
sdh0_pins_0: sdh0-pins-0 {
251
+
pinctrl-single,pins = <
252
+
0x108 0
253
+
>;
254
+
pinctrl-single,drive-strength = <0x1000 0x1800>;
255
+
pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
256
+
pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
257
+
pinctrl-single,input-schmitt = <0 0x30>;
258
+
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
259
+
pinctrl-single,low-power-mode = <0 0x388>;
260
+
};
261
+
262
+
sdh0_pins_1: sdh0-pins-1 {
263
+
pinctrl-single,pins = <
264
+
0x94 0
265
+
0x98 0
266
+
0x9c 0
267
+
0xa0 0
268
+
0xa4 0
269
+
>;
270
+
pinctrl-single,drive-strength = <0x800 0x1800>;
271
+
pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
272
+
pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
273
+
pinctrl-single,input-schmitt = <0 0x30>;
274
+
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
275
+
pinctrl-single,low-power-mode = <0 0x388>;
276
+
};
277
+
278
+
sdh0_pins_2: sdh0-pins-2 {
279
+
pinctrl-single,pins = <
280
+
0xa8 0
281
+
>;
282
+
pinctrl-single,drive-strength = <0x1000 0x1800>;
283
+
pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
284
+
pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
285
+
pinctrl-single,input-schmitt = <0 0x30>;
286
+
pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
287
+
pinctrl-single,low-power-mode = <0x208 0x388>;
288
+
};
289
+
};
290
+
291
+
&uart0 {
292
+
pinctrl-names = "default";
293
+
pinctrl-0 = <&uart0_pins>;
294
+
};
295
+
296
+
&twsi0 {
297
+
status = "okay";
298
+
};
299
+
300
+
&twsi1 {
301
+
status = "okay";
302
+
};
303
+
304
+
&twsi2 {
305
+
status = "okay";
306
+
};
307
+
308
+
&twsi3 {
309
+
status = "okay";
310
+
};
311
+
312
+
&usb {
313
+
extcon = <&muic>, <&muic>;
314
+
};
315
+
316
+
&sdh2 {
317
+
/* Disabled for now because initialization fails with -ETIMEDOUT. */
318
+
status = "disabled";
319
+
bus-width = <8>;
320
+
non-removable;
321
+
mmc-ddr-1_8v;
322
+
};
323
+
324
+
&sdh0 {
325
+
pinctrl-names = "default";
326
+
pinctrl-0 = <&sdh0_pins_0 &sdh0_pins_1 &sdh0_pins_2>;
327
+
cd-gpios = <&gpio 11 0>;
328
+
cd-inverted;
329
+
bus-width = <4>;
330
+
wp-inverted;
331
+
};
+300
arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi
+300
arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/dts-v1/;
3
+
4
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
5
+
#include <dt-bindings/clock/marvell,pxa1908.h>
6
+
7
+
/ {
8
+
model = "Marvell Armada PXA1908";
9
+
compatible = "marvell,pxa1908";
10
+
#address-cells = <2>;
11
+
#size-cells = <2>;
12
+
interrupt-parent = <&gic>;
13
+
14
+
cpus {
15
+
#address-cells = <2>;
16
+
#size-cells = <0>;
17
+
18
+
cpu0: cpu@0 {
19
+
device_type = "cpu";
20
+
compatible = "arm,cortex-a53";
21
+
reg = <0 0>;
22
+
enable-method = "psci";
23
+
};
24
+
25
+
cpu1: cpu@1 {
26
+
device_type = "cpu";
27
+
compatible = "arm,cortex-a53";
28
+
reg = <0 1>;
29
+
enable-method = "psci";
30
+
};
31
+
32
+
cpu2: cpu@2 {
33
+
device_type = "cpu";
34
+
compatible = "arm,cortex-a53";
35
+
reg = <0 2>;
36
+
enable-method = "psci";
37
+
};
38
+
39
+
cpu3: cpu@3 {
40
+
device_type = "cpu";
41
+
compatible = "arm,cortex-a53";
42
+
reg = <0 3>;
43
+
enable-method = "psci";
44
+
};
45
+
};
46
+
47
+
pmu {
48
+
compatible = "arm,cortex-a53-pmu";
49
+
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
50
+
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
51
+
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
52
+
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
53
+
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
54
+
};
55
+
56
+
psci {
57
+
compatible = "arm,psci-0.2";
58
+
method = "smc";
59
+
};
60
+
61
+
timer {
62
+
compatible = "arm,armv8-timer";
63
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
65
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
66
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
67
+
};
68
+
69
+
soc {
70
+
compatible = "simple-bus";
71
+
#address-cells = <2>;
72
+
#size-cells = <2>;
73
+
ranges;
74
+
75
+
smmu: iommu@c0010000 {
76
+
compatible = "arm,mmu-400";
77
+
reg = <0 0xc0010000 0 0x10000>;
78
+
#global-interrupts = <1>;
79
+
#iommu-cells = <1>;
80
+
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
81
+
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
82
+
status = "disabled";
83
+
};
84
+
85
+
gic: interrupt-controller@d1df9000 {
86
+
compatible = "arm,gic-400";
87
+
reg = <0 0xd1df9000 0 0x1000>,
88
+
<0 0xd1dfa000 0 0x2000>,
89
+
/* The subsequent registers are guesses. */
90
+
<0 0xd1dfc000 0 0x2000>,
91
+
<0 0xd1dfe000 0 0x2000>;
92
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93
+
interrupt-controller;
94
+
#interrupt-cells = <3>;
95
+
};
96
+
97
+
apb@d4000000 {
98
+
compatible = "simple-bus";
99
+
reg = <0 0xd4000000 0 0x200000>;
100
+
#address-cells = <1>;
101
+
#size-cells = <1>;
102
+
ranges = <0 0 0xd4000000 0x200000>;
103
+
104
+
pdma: dma-controller@0 {
105
+
compatible = "marvell,pdma-1.0";
106
+
reg = <0 0x10000>;
107
+
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
108
+
dma-channels = <30>;
109
+
#dma-cells = <2>;
110
+
};
111
+
112
+
twsi1: i2c@10800 {
113
+
compatible = "mrvl,mmp-twsi";
114
+
#address-cells = <1>;
115
+
#size-cells = <0>;
116
+
reg = <0x10800 0x64>;
117
+
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
118
+
clocks = <&apbc PXA1908_CLK_TWSI1>;
119
+
mrvl,i2c-fast-mode;
120
+
status = "disabled";
121
+
};
122
+
123
+
twsi0: i2c@11000 {
124
+
compatible = "mrvl,mmp-twsi";
125
+
#address-cells = <1>;
126
+
#size-cells = <0>;
127
+
reg = <0x11000 0x64>;
128
+
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
129
+
clocks = <&apbc PXA1908_CLK_TWSI0>;
130
+
mrvl,i2c-fast-mode;
131
+
status = "disabled";
132
+
};
133
+
134
+
twsi3: i2c@13800 {
135
+
compatible = "mrvl,mmp-twsi";
136
+
#address-cells = <1>;
137
+
#size-cells = <0>;
138
+
reg = <0x13800 0x64>;
139
+
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
140
+
clocks = <&apbc PXA1908_CLK_TWSI3>;
141
+
mrvl,i2c-fast-mode;
142
+
status = "disabled";
143
+
};
144
+
145
+
apbc: clock-controller@15000 {
146
+
compatible = "marvell,pxa1908-apbc";
147
+
reg = <0x15000 0x1000>;
148
+
#clock-cells = <1>;
149
+
};
150
+
151
+
uart0: serial@17000 {
152
+
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
153
+
reg = <0x17000 0x1000>;
154
+
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
155
+
clocks = <&apbc PXA1908_CLK_UART0>;
156
+
reg-shift = <2>;
157
+
};
158
+
159
+
uart1: serial@18000 {
160
+
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
161
+
reg = <0x18000 0x1000>;
162
+
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
163
+
clocks = <&apbc PXA1908_CLK_UART1>;
164
+
reg-shift = <2>;
165
+
};
166
+
167
+
gpio: gpio@19000 {
168
+
compatible = "marvell,mmp-gpio";
169
+
reg = <0x19000 0x800>;
170
+
#address-cells = <1>;
171
+
#size-cells = <1>;
172
+
gpio-controller;
173
+
#gpio-cells = <2>;
174
+
clocks = <&apbc PXA1908_CLK_GPIO>;
175
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
176
+
interrupt-names = "gpio_mux";
177
+
interrupt-controller;
178
+
#interrupt-cells = <2>;
179
+
ranges = <0 0x19000 0x800>;
180
+
181
+
gpio@0 {
182
+
reg = <0x0 0x4>;
183
+
};
184
+
185
+
gpio@4 {
186
+
reg = <0x4 0x4>;
187
+
};
188
+
189
+
gpio@8 {
190
+
reg = <0x8 0x4>;
191
+
};
192
+
193
+
gpio@100 {
194
+
reg = <0x100 0x4>;
195
+
};
196
+
};
197
+
198
+
pmx: pinmux@1e000 {
199
+
compatible = "marvell,pxa1908-padconf", "pinconf-single";
200
+
reg = <0x1e000 0x330>;
201
+
202
+
#pinctrl-cells = <1>;
203
+
pinctrl-single,register-width = <32>;
204
+
pinctrl-single,function-mask = <7>;
205
+
206
+
range: gpio-range {
207
+
#pinctrl-single,gpio-range-cells = <3>;
208
+
};
209
+
};
210
+
211
+
uart2: serial@36000 {
212
+
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
213
+
reg = <0x36000 0x1000>;
214
+
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
215
+
clocks = <&apbcp PXA1908_CLK_UART2>;
216
+
reg-shift = <2>;
217
+
};
218
+
219
+
twsi2: i2c@37000 {
220
+
compatible = "mrvl,mmp-twsi";
221
+
#address-cells = <1>;
222
+
#size-cells = <0>;
223
+
reg = <0x37000 0x64>;
224
+
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
225
+
clocks = <&apbcp PXA1908_CLK_TWSI2>;
226
+
mrvl,i2c-fast-mode;
227
+
status = "disabled";
228
+
};
229
+
230
+
apbcp: clock-controller@3b000 {
231
+
compatible = "marvell,pxa1908-apbcp";
232
+
reg = <0x3b000 0x1000>;
233
+
#clock-cells = <1>;
234
+
};
235
+
236
+
mpmu: clock-controller@50000 {
237
+
compatible = "marvell,pxa1908-mpmu";
238
+
reg = <0x50000 0x1000>;
239
+
#clock-cells = <1>;
240
+
};
241
+
};
242
+
243
+
axi@d4200000 {
244
+
compatible = "simple-bus";
245
+
reg = <0 0xd4200000 0 0x200000>;
246
+
#address-cells = <1>;
247
+
#size-cells = <1>;
248
+
ranges = <0 0 0xd4200000 0x200000>;
249
+
250
+
usbphy: phy@7000 {
251
+
compatible = "marvell,pxa1928-usb-phy";
252
+
reg = <0x7000 0x200>;
253
+
clocks = <&apmu PXA1908_CLK_USB>;
254
+
#phy-cells = <0>;
255
+
};
256
+
257
+
usb: usb@8000 {
258
+
compatible = "chipidea,usb2";
259
+
reg = <0x8000 0x200>;
260
+
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
261
+
clocks = <&apmu PXA1908_CLK_USB>;
262
+
phys = <&usbphy>;
263
+
phy-names = "usb-phy";
264
+
};
265
+
266
+
sdh0: mmc@80000 {
267
+
compatible = "mrvl,pxav3-mmc";
268
+
reg = <0x80000 0x120>;
269
+
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
270
+
clocks = <&apmu PXA1908_CLK_SDH0>;
271
+
clock-names = "io";
272
+
mrvl,clk-delay-cycles = <31>;
273
+
};
274
+
275
+
sdh1: mmc@80800 {
276
+
compatible = "mrvl,pxav3-mmc";
277
+
reg = <0x80800 0x120>;
278
+
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
279
+
clocks = <&apmu PXA1908_CLK_SDH1>;
280
+
clock-names = "io";
281
+
mrvl,clk-delay-cycles = <31>;
282
+
};
283
+
284
+
sdh2: mmc@81000 {
285
+
compatible = "mrvl,pxav3-mmc";
286
+
reg = <0x81000 0x120>;
287
+
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
288
+
clocks = <&apmu PXA1908_CLK_SDH2>;
289
+
clock-names = "io";
290
+
mrvl,clk-delay-cycles = <31>;
291
+
};
292
+
293
+
apmu: clock-controller@82800 {
294
+
compatible = "marvell,pxa1908-apmu";
295
+
reg = <0x82800 0x400>;
296
+
#clock-cells = <1>;
297
+
};
298
+
};
299
+
};
300
+
};
+2
arch/arm64/boot/dts/sophgo/Makefile
+2
arch/arm64/boot/dts/sophgo/Makefile
+76
arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
+76
arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
3
+
/dts-v1/;
4
+
5
+
#include "sg2000-milkv-duo-module-01.dtsi"
6
+
7
+
/ {
8
+
model = "Milk-V Duo Module 01 Evaluation Board";
9
+
compatible = "milkv,duo-module-01-evb", "milkv,duo-module-01", "sophgo,sg2000";
10
+
11
+
chosen {
12
+
stdout-path = "serial0:115200n8";
13
+
};
14
+
};
15
+
16
+
&pinctrl {
17
+
sdhci0_cfg: sdhci0-cfg {
18
+
sdhci0-cd-pins {
19
+
pinmux = <PINMUX(PIN_SD0_CD, 0)>;
20
+
bias-pull-up;
21
+
drive-strength-microamp = <10800>;
22
+
power-source = <3300>;
23
+
};
24
+
25
+
sdhci0-clk-pins {
26
+
pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
27
+
bias-pull-up;
28
+
drive-strength-microamp = <16100>;
29
+
power-source = <3300>;
30
+
};
31
+
32
+
sdhci0-cmd-pins {
33
+
pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
34
+
bias-pull-up;
35
+
drive-strength-microamp = <10800>;
36
+
power-source = <3300>;
37
+
};
38
+
39
+
sdhci0-data-pins {
40
+
pinmux = <PINMUX(PIN_SD0_D0, 0)>,
41
+
<PINMUX(PIN_SD0_D1, 0)>,
42
+
<PINMUX(PIN_SD0_D2, 0)>,
43
+
<PINMUX(PIN_SD0_D3, 0)>;
44
+
bias-pull-up;
45
+
drive-strength-microamp = <10800>;
46
+
power-source = <3300>;
47
+
};
48
+
};
49
+
50
+
uart0_cfg: uart0-cfg {
51
+
uart0-pins {
52
+
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
53
+
<PINMUX(PIN_UART0_RX, 0)>;
54
+
bias-pull-up;
55
+
drive-strength-microamp = <10800>;
56
+
power-source = <3300>;
57
+
};
58
+
};
59
+
};
60
+
61
+
&uart0 {
62
+
pinctrl-0 = <&uart0_cfg>;
63
+
pinctrl-names = "default";
64
+
status = "okay";
65
+
};
66
+
67
+
&sdhci0 {
68
+
bus-width = <4>;
69
+
no-1-8-v;
70
+
no-mmc;
71
+
no-sdio;
72
+
disable-wp;
73
+
pinctrl-0 = <&sdhci0_cfg>;
74
+
pinctrl-names = "default";
75
+
status = "okay";
76
+
};
+40
arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
+40
arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
3
+
#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
4
+
#include "sg2000.dtsi"
5
+
6
+
/ {
7
+
model = "Milk-V Duo Module 01";
8
+
compatible = "milkv,duo-module-01", "sophgo,sg2000";
9
+
10
+
aliases {
11
+
serial0 = &uart0;
12
+
serial1 = &uart1;
13
+
serial2 = &uart2;
14
+
serial3 = &uart3;
15
+
serial4 = &uart4;
16
+
};
17
+
};
18
+
19
+
&osc {
20
+
clock-frequency = <25000000>;
21
+
};
22
+
23
+
&emmc {
24
+
bus-width = <4>;
25
+
no-1-8-v;
26
+
cap-mmc-hw-reset;
27
+
no-sd;
28
+
no-sdio;
29
+
non-removable;
30
+
status = "okay";
31
+
};
32
+
33
+
/* Wi-Fi */
34
+
&sdhci1 {
35
+
bus-width = <4>;
36
+
cap-sdio-irq;
37
+
no-mmc;
38
+
no-sd;
39
+
non-removable;
40
+
};
+86
arch/arm64/boot/dts/sophgo/sg2000.dtsi
+86
arch/arm64/boot/dts/sophgo/sg2000.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
3
+
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr)
4
+
5
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
6
+
#include <riscv/sophgo/cv180x.dtsi>
7
+
#include <riscv/sophgo/cv181x.dtsi>
8
+
9
+
/ {
10
+
compatible = "sophgo,sg2000";
11
+
interrupt-parent = <&gic>;
12
+
13
+
cpus {
14
+
#address-cells = <1>;
15
+
#size-cells = <0>;
16
+
17
+
cpu@0 {
18
+
compatible = "arm,cortex-a53";
19
+
device_type = "cpu";
20
+
reg = <0>;
21
+
enable-method = "psci";
22
+
i-cache-size = <32768>;
23
+
d-cache-size = <32768>;
24
+
next-level-cache = <&l2>;
25
+
};
26
+
27
+
l2: l2-cache {
28
+
compatible = "cache";
29
+
cache-level = <2>;
30
+
cache-unified;
31
+
cache-size = <0x20000>;
32
+
};
33
+
};
34
+
35
+
memory@80000000 {
36
+
device_type = "memory";
37
+
reg = <0x80000000 0x20000000>; /* 512MiB */
38
+
};
39
+
40
+
pmu {
41
+
compatible = "arm,cortex-a53-pmu";
42
+
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
43
+
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
44
+
};
45
+
46
+
psci {
47
+
compatible = "arm,psci-0.2";
48
+
method = "smc";
49
+
cpu_on = <0xc4000003>;
50
+
cpu_off = <0x84000002>;
51
+
};
52
+
53
+
soc {
54
+
gic: interrupt-controller@1f01000 {
55
+
compatible = "arm,cortex-a15-gic";
56
+
interrupt-controller;
57
+
#interrupt-cells = <3>;
58
+
reg = <0x01f01000 0x1000>,
59
+
<0x01f02000 0x2000>;
60
+
};
61
+
62
+
pinctrl: pinctrl@3001000 {
63
+
compatible = "sophgo,sg2000-pinctrl";
64
+
reg = <0x03001000 0x1000>,
65
+
<0x05027000 0x1000>;
66
+
reg-names = "sys", "rtc";
67
+
};
68
+
69
+
clk: clock-controller@3002000 {
70
+
compatible = "sophgo,sg2000-clk";
71
+
reg = <0x03002000 0x1000>;
72
+
clocks = <&osc>;
73
+
#clock-cells = <1>;
74
+
};
75
+
};
76
+
77
+
timer {
78
+
compatible = "arm,armv8-timer";
79
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
80
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
81
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
82
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
83
+
always-on;
84
+
clock-frequency = <25000000>;
85
+
};
86
+
};
+7
arch/arm64/configs/defconfig
+7
arch/arm64/configs/defconfig
···
38
38
CONFIG_ARCH_SUNXI=y
39
39
CONFIG_ARCH_ALPINE=y
40
40
CONFIG_ARCH_APPLE=y
41
+
CONFIG_ARCH_AXIADO=y
41
42
CONFIG_ARCH_BCM=y
42
43
CONFIG_ARCH_BCM2835=y
43
44
CONFIG_ARCH_BCM_IPROC=y
···
46
45
CONFIG_ARCH_BRCMSTB=y
47
46
CONFIG_ARCH_BERLIN=y
48
47
CONFIG_ARCH_BLAIZE=y
48
+
CONFIG_ARCH_CIX=y
49
49
CONFIG_ARCH_EXYNOS=y
50
50
CONFIG_ARCH_SPARX5=y
51
51
CONFIG_ARCH_K3=y
···
68
66
CONFIG_ARCH_ROCKCHIP=y
69
67
CONFIG_ARCH_SEATTLE=y
70
68
CONFIG_ARCH_INTEL_SOCFPGA=y
69
+
CONFIG_ARCH_SOPHGO=y
71
70
CONFIG_ARCH_STM32=y
72
71
CONFIG_ARCH_SYNQUACER=y
73
72
CONFIG_ARCH_TEGRA=y
···
658
655
CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
659
656
CONFIG_PINCTRL_SM8550_LPASS_LPI=m
660
657
CONFIG_PINCTRL_SM8650_LPASS_LPI=m
658
+
CONFIG_PINCTRL_SOPHGO_SG2000=y
661
659
CONFIG_GPIO_ALTERA=m
662
660
CONFIG_GPIO_DAVINCI=y
663
661
CONFIG_GPIO_DWAPB=y
···
1436
1432
CONFIG_CLK_GFM_LPASS_SM8250=m
1437
1433
CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
1438
1434
CONFIG_CLK_RENESAS_VBATTB=m
1435
+
CONFIG_CLK_SOPHGO_CV1800=y
1439
1436
CONFIG_HWSPINLOCK=y
1440
1437
CONFIG_HWSPINLOCK_OMAP=m
1441
1438
CONFIG_HWSPINLOCK_QCOM=y
···
1453
1448
CONFIG_MTK_ADSP_MBOX=m
1454
1449
CONFIG_QCOM_CPUCP_MBOX=m
1455
1450
CONFIG_QCOM_IPCC=y
1451
+
CONFIG_CIX_MBOX=y
1456
1452
CONFIG_ROCKCHIP_IOMMU=y
1457
1453
CONFIG_TEGRA_IOMMU_SMMU=y
1458
1454
CONFIG_ARM_SMMU=y
···
1540
1534
CONFIG_QCOM_SPMI_ADC5=m
1541
1535
CONFIG_ROCKCHIP_SARADC=m
1542
1536
CONFIG_RZG2L_ADC=m
1537
+
CONFIG_SOPHGO_CV1800B_ADC=m
1543
1538
CONFIG_TI_ADS1015=m
1544
1539
CONFIG_TI_AM335X_ADC=m
1545
1540
CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+7
arch/riscv/Kconfig.socs
+7
arch/riscv/Kconfig.socs
+1
arch/riscv/boot/dts/Makefile
+1
arch/riscv/boot/dts/Makefile
+2
arch/riscv/boot/dts/andes/Makefile
+2
arch/riscv/boot/dts/andes/Makefile
+28
arch/riscv/boot/dts/andes/qilai-voyager.dts
+28
arch/riscv/boot/dts/andes/qilai-voyager.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR MIT
2
+
/*
3
+
* Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
4
+
*/
5
+
6
+
#include "qilai.dtsi"
7
+
8
+
/ {
9
+
model = "Voyager";
10
+
compatible = "andestech,voyager", "andestech,qilai";
11
+
12
+
aliases {
13
+
serial0 = &uart0;
14
+
};
15
+
16
+
chosen {
17
+
stdout-path = "serial0:115200n8";
18
+
};
19
+
20
+
memory@400000000 {
21
+
device_type = "memory";
22
+
reg = <0x4 0x00000000 0x4 0x00000000>;
23
+
};
24
+
};
25
+
26
+
&uart0 {
27
+
status = "okay";
28
+
};
+186
arch/riscv/boot/dts/andes/qilai.dtsi
+186
arch/riscv/boot/dts/andes/qilai.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/*
3
+
* Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include <dt-bindings/interrupt-controller/irq.h>
9
+
10
+
/ {
11
+
#address-cells = <2>;
12
+
#size-cells = <2>;
13
+
14
+
cpus {
15
+
#address-cells = <1>;
16
+
#size-cells = <0>;
17
+
timebase-frequency = <62500000>;
18
+
19
+
cpu0: cpu@0 {
20
+
compatible = "andestech,ax45mp", "riscv";
21
+
device_type = "cpu";
22
+
reg = <0>;
23
+
riscv,isa-base = "rv64i";
24
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
25
+
"zicntr", "zicsr", "zifencei",
26
+
"zihpm", "xandespmu";
27
+
mmu-type = "riscv,sv39";
28
+
clock-frequency = <100000000>;
29
+
i-cache-size = <0x8000>;
30
+
i-cache-sets = <256>;
31
+
i-cache-line-size = <64>;
32
+
d-cache-size = <0x8000>;
33
+
d-cache-sets = <128>;
34
+
d-cache-line-size = <64>;
35
+
next-level-cache = <&l2_cache>;
36
+
37
+
cpu0_intc: interrupt-controller {
38
+
compatible = "andestech,cpu-intc", "riscv,cpu-intc";
39
+
#interrupt-cells = <1>;
40
+
interrupt-controller;
41
+
};
42
+
};
43
+
44
+
cpu1: cpu@1 {
45
+
compatible = "andestech,ax45mp", "riscv";
46
+
device_type = "cpu";
47
+
reg = <1>;
48
+
riscv,isa-base = "rv64i";
49
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
50
+
"zicntr", "zicsr", "zifencei",
51
+
"zihpm", "xandespmu";
52
+
mmu-type = "riscv,sv39";
53
+
clock-frequency = <100000000>;
54
+
i-cache-size = <0x8000>;
55
+
i-cache-sets = <256>;
56
+
i-cache-line-size = <64>;
57
+
d-cache-size = <0x8000>;
58
+
d-cache-sets = <128>;
59
+
d-cache-line-size = <64>;
60
+
next-level-cache = <&l2_cache>;
61
+
62
+
cpu1_intc: interrupt-controller {
63
+
compatible = "andestech,cpu-intc",
64
+
"riscv,cpu-intc";
65
+
#interrupt-cells = <1>;
66
+
interrupt-controller;
67
+
};
68
+
};
69
+
70
+
cpu2: cpu@2 {
71
+
compatible = "andestech,ax45mp", "riscv";
72
+
device_type = "cpu";
73
+
reg = <2>;
74
+
riscv,isa-base = "rv64i";
75
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
76
+
"zicntr", "zicsr", "zifencei",
77
+
"zihpm", "xandespmu";
78
+
mmu-type = "riscv,sv39";
79
+
clock-frequency = <100000000>;
80
+
i-cache-size = <0x8000>;
81
+
i-cache-sets = <256>;
82
+
i-cache-line-size = <64>;
83
+
d-cache-size = <0x8000>;
84
+
d-cache-sets = <128>;
85
+
d-cache-line-size = <64>;
86
+
next-level-cache = <&l2_cache>;
87
+
88
+
cpu2_intc: interrupt-controller {
89
+
compatible = "andestech,cpu-intc",
90
+
"riscv,cpu-intc";
91
+
#interrupt-cells = <1>;
92
+
interrupt-controller;
93
+
};
94
+
};
95
+
96
+
cpu3: cpu@3 {
97
+
compatible = "andestech,ax45mp", "riscv";
98
+
device_type = "cpu";
99
+
reg = <3>;
100
+
riscv,isa-base = "rv64i";
101
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
102
+
"zicntr", "zicsr", "zifencei",
103
+
"zihpm", "xandespmu";
104
+
mmu-type = "riscv,sv39";
105
+
clock-frequency = <100000000>;
106
+
i-cache-size = <0x8000>;
107
+
i-cache-sets = <256>;
108
+
i-cache-line-size = <64>;
109
+
d-cache-size = <0x8000>;
110
+
d-cache-sets = <128>;
111
+
d-cache-line-size = <64>;
112
+
next-level-cache = <&l2_cache>;
113
+
114
+
cpu3_intc: interrupt-controller {
115
+
compatible = "andestech,cpu-intc",
116
+
"riscv,cpu-intc";
117
+
#interrupt-cells = <1>;
118
+
interrupt-controller;
119
+
};
120
+
};
121
+
};
122
+
123
+
soc {
124
+
compatible = "simple-bus";
125
+
ranges;
126
+
interrupt-parent = <&plic>;
127
+
#address-cells = <2>;
128
+
#size-cells = <2>;
129
+
130
+
plmt: timer@100000 {
131
+
compatible = "andestech,qilai-plmt", "andestech,plmt0";
132
+
reg = <0x0 0x00100000 0x0 0x100000>;
133
+
interrupts-extended = <&cpu0_intc 7>,
134
+
<&cpu1_intc 7>,
135
+
<&cpu2_intc 7>,
136
+
<&cpu3_intc 7>;
137
+
};
138
+
139
+
l2_cache: cache-controller@200000 {
140
+
compatible = "andestech,qilai-ax45mp-cache",
141
+
"andestech,ax45mp-cache", "cache";
142
+
reg = <0x0 0x00200000 0x0 0x100000>;
143
+
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
144
+
cache-line-size = <64>;
145
+
cache-level = <2>;
146
+
cache-sets = <2048>;
147
+
cache-size = <0x200000>;
148
+
cache-unified;
149
+
};
150
+
151
+
plic_sw: interrupt-controller@400000 {
152
+
compatible = "andestech,qilai-plicsw",
153
+
"andestech,plicsw";
154
+
reg = <0x0 0x00400000 0x0 0x400000>;
155
+
interrupts-extended = <&cpu0_intc 3>,
156
+
<&cpu1_intc 3>,
157
+
<&cpu2_intc 3>,
158
+
<&cpu3_intc 3>;
159
+
};
160
+
161
+
plic: interrupt-controller@2000000 {
162
+
compatible = "andestech,qilai-plic",
163
+
"andestech,nceplic100";
164
+
reg = <0x0 0x02000000 0x0 0x2000000>;
165
+
#address-cells = <0>;
166
+
#interrupt-cells = <2>;
167
+
interrupt-controller;
168
+
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
169
+
<&cpu1_intc 11>, <&cpu1_intc 9>,
170
+
<&cpu2_intc 11>, <&cpu2_intc 9>,
171
+
<&cpu3_intc 11>, <&cpu3_intc 9>;
172
+
riscv,ndev = <71>;
173
+
};
174
+
175
+
uart0: serial@30300000 {
176
+
compatible = "andestech,uart16550", "ns16550a";
177
+
reg = <0x0 0x30300000 0x0 0x100000>;
178
+
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
179
+
clock-frequency = <50000000>;
180
+
reg-offset = <32>;
181
+
reg-shift = <2>;
182
+
reg-io-width = <4>;
183
+
no-loopback-test;
184
+
};
185
+
};
186
+
};
+1
arch/riscv/configs/defconfig
+1
arch/riscv/configs/defconfig
+10
drivers/mailbox/Kconfig
+10
drivers/mailbox/Kconfig
···
340
340
kernel is running, and E902 core used for power management among other
341
341
things.
342
342
343
+
config CIX_MBOX
344
+
tristate "CIX Mailbox"
345
+
depends on ARCH_CIX || COMPILE_TEST
346
+
depends on OF
347
+
help
348
+
Mailbox implementation for CIX IPC system. The controller supports
349
+
11 mailbox channels with different operating mode and every channel
350
+
is unidirectional. Say Y here if you want to use the CIX Mailbox
351
+
support.
352
+
343
353
endif
+2
drivers/mailbox/Makefile
+2
drivers/mailbox/Makefile
+645
drivers/mailbox/cix-mailbox.c
+645
drivers/mailbox/cix-mailbox.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright 2025 Cix Technology Group Co., Ltd.
4
+
*/
5
+
6
+
#include <linux/device.h>
7
+
#include <linux/err.h>
8
+
#include <linux/io.h>
9
+
#include <linux/interrupt.h>
10
+
#include <linux/kernel.h>
11
+
#include <linux/mailbox_controller.h>
12
+
#include <linux/module.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "mailbox.h"
16
+
17
+
/*
18
+
* The maximum transmission size is 32 words or 128 bytes.
19
+
*/
20
+
#define CIX_MBOX_MSG_WORDS 32 /* Max length = 32 words */
21
+
#define CIX_MBOX_MSG_LEN_MASK 0x7fL /* Max length = 128 bytes */
22
+
23
+
/* [0~7] Fast channel
24
+
* [8] doorbell base channel
25
+
* [9]fifo base channel
26
+
* [10] register base channel
27
+
*/
28
+
#define CIX_MBOX_FAST_IDX 7
29
+
#define CIX_MBOX_DB_IDX 8
30
+
#define CIX_MBOX_FIFO_IDX 9
31
+
#define CIX_MBOX_REG_IDX 10
32
+
#define CIX_MBOX_CHANS 11
33
+
34
+
/* Register define */
35
+
#define CIX_REG_MSG(n) (0x0 + 0x4*(n)) /* 0x0~0x7c */
36
+
#define CIX_REG_DB_ACK CIX_REG_MSG(CIX_MBOX_MSG_WORDS) /* 0x80 */
37
+
#define CIX_ERR_COMP (CIX_REG_DB_ACK + 0x4) /* 0x84 */
38
+
#define CIX_ERR_COMP_CLR (CIX_REG_DB_ACK + 0x8) /* 0x88 */
39
+
#define CIX_REG_F_INT(IDX) (CIX_ERR_COMP_CLR + 0x4*(IDX+1)) /* 0x8c~0xa8 */
40
+
#define CIX_FIFO_WR (CIX_REG_F_INT(CIX_MBOX_FAST_IDX+1)) /* 0xac */
41
+
#define CIX_FIFO_RD (CIX_FIFO_WR + 0x4) /* 0xb0 */
42
+
#define CIX_FIFO_STAS (CIX_FIFO_WR + 0x8) /* 0xb4 */
43
+
#define CIX_FIFO_WM (CIX_FIFO_WR + 0xc) /* 0xb8 */
44
+
#define CIX_INT_ENABLE (CIX_FIFO_WR + 0x10) /* 0xbc */
45
+
#define CIX_INT_ENABLE_SIDE_B (CIX_FIFO_WR + 0x14) /* 0xc0 */
46
+
#define CIX_INT_CLEAR (CIX_FIFO_WR + 0x18) /* 0xc4 */
47
+
#define CIX_INT_STATUS (CIX_FIFO_WR + 0x1c) /* 0xc8 */
48
+
#define CIX_FIFO_RST (CIX_FIFO_WR + 0x20) /* 0xcc */
49
+
50
+
#define CIX_MBOX_TX 0
51
+
#define CIX_MBOX_RX 1
52
+
53
+
#define CIX_DB_INT_BIT BIT(0)
54
+
#define CIX_DB_ACK_INT_BIT BIT(1)
55
+
56
+
#define CIX_FIFO_WM_DEFAULT CIX_MBOX_MSG_WORDS
57
+
#define CIX_FIFO_STAS_WMK BIT(0)
58
+
#define CIX_FIFO_STAS_FULL BIT(1)
59
+
#define CIX_FIFO_STAS_EMPTY BIT(2)
60
+
#define CIX_FIFO_STAS_UFLOW BIT(3)
61
+
#define CIX_FIFO_STAS_OFLOW BIT(4)
62
+
63
+
#define CIX_FIFO_RST_BIT BIT(0)
64
+
65
+
#define CIX_DB_INT BIT(0)
66
+
#define CIX_ACK_INT BIT(1)
67
+
#define CIX_FIFO_FULL_INT BIT(2)
68
+
#define CIX_FIFO_EMPTY_INT BIT(3)
69
+
#define CIX_FIFO_WM01_INT BIT(4)
70
+
#define CIX_FIFO_WM10_INT BIT(5)
71
+
#define CIX_FIFO_OFLOW_INT BIT(6)
72
+
#define CIX_FIFO_UFLOW_INT BIT(7)
73
+
#define CIX_FIFO_N_EMPTY_INT BIT(8)
74
+
#define CIX_FAST_CH_INT(IDX) BIT((IDX)+9)
75
+
76
+
#define CIX_SHMEM_OFFSET 0x80
77
+
78
+
enum cix_mbox_chan_type {
79
+
CIX_MBOX_TYPE_DB,
80
+
CIX_MBOX_TYPE_REG,
81
+
CIX_MBOX_TYPE_FIFO,
82
+
CIX_MBOX_TYPE_FAST,
83
+
};
84
+
85
+
struct cix_mbox_con_priv {
86
+
enum cix_mbox_chan_type type;
87
+
struct mbox_chan *chan;
88
+
int index;
89
+
};
90
+
91
+
struct cix_mbox_priv {
92
+
struct device *dev;
93
+
int irq;
94
+
int dir;
95
+
void __iomem *base; /* region for mailbox */
96
+
struct cix_mbox_con_priv con_priv[CIX_MBOX_CHANS];
97
+
struct mbox_chan mbox_chans[CIX_MBOX_CHANS];
98
+
struct mbox_controller mbox;
99
+
bool use_shmem;
100
+
};
101
+
102
+
/*
103
+
* The CIX mailbox supports four types of transfers:
104
+
* CIX_MBOX_TYPE_DB, CIX_MBOX_TYPE_FAST, CIX_MBOX_TYPE_REG, and CIX_MBOX_TYPE_FIFO.
105
+
* For the REG and FIFO types of transfers, the message format is as follows:
106
+
*/
107
+
union cix_mbox_msg_reg_fifo {
108
+
u32 length; /* unit is byte */
109
+
u32 buf[CIX_MBOX_MSG_WORDS]; /* buf[0] must be the byte length of this array */
110
+
};
111
+
112
+
static struct cix_mbox_priv *to_cix_mbox_priv(struct mbox_controller *mbox)
113
+
{
114
+
return container_of(mbox, struct cix_mbox_priv, mbox);
115
+
}
116
+
117
+
static void cix_mbox_write(struct cix_mbox_priv *priv, u32 val, u32 offset)
118
+
{
119
+
if (priv->use_shmem)
120
+
iowrite32(val, priv->base + offset - CIX_SHMEM_OFFSET);
121
+
else
122
+
iowrite32(val, priv->base + offset);
123
+
}
124
+
125
+
static u32 cix_mbox_read(struct cix_mbox_priv *priv, u32 offset)
126
+
{
127
+
if (priv->use_shmem)
128
+
return ioread32(priv->base + offset - CIX_SHMEM_OFFSET);
129
+
else
130
+
return ioread32(priv->base + offset);
131
+
}
132
+
133
+
static bool mbox_fifo_empty(struct mbox_chan *chan)
134
+
{
135
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
136
+
137
+
return ((cix_mbox_read(priv, CIX_FIFO_STAS) & CIX_FIFO_STAS_EMPTY) ? true : false);
138
+
}
139
+
140
+
/*
141
+
*The transmission unit of the CIX mailbox is word.
142
+
*The byte length should be converted into the word length.
143
+
*/
144
+
static inline u32 mbox_get_msg_size(void *msg)
145
+
{
146
+
u32 len;
147
+
148
+
len = ((u32 *)msg)[0] & CIX_MBOX_MSG_LEN_MASK;
149
+
return DIV_ROUND_UP(len, 4);
150
+
}
151
+
152
+
static int cix_mbox_send_data_db(struct mbox_chan *chan, void *data)
153
+
{
154
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
155
+
156
+
/* trigger doorbell irq */
157
+
cix_mbox_write(priv, CIX_DB_INT_BIT, CIX_REG_DB_ACK);
158
+
159
+
return 0;
160
+
}
161
+
162
+
static int cix_mbox_send_data_reg(struct mbox_chan *chan, void *data)
163
+
{
164
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
165
+
union cix_mbox_msg_reg_fifo *msg = data;
166
+
u32 len, i;
167
+
168
+
if (!data)
169
+
return -EINVAL;
170
+
171
+
len = mbox_get_msg_size(data);
172
+
for (i = 0; i < len; i++)
173
+
cix_mbox_write(priv, msg->buf[i], CIX_REG_MSG(i));
174
+
175
+
/* trigger doorbell irq */
176
+
cix_mbox_write(priv, CIX_DB_INT_BIT, CIX_REG_DB_ACK);
177
+
178
+
return 0;
179
+
}
180
+
181
+
static int cix_mbox_send_data_fifo(struct mbox_chan *chan, void *data)
182
+
{
183
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
184
+
union cix_mbox_msg_reg_fifo *msg = data;
185
+
u32 len, val, i;
186
+
187
+
if (!data)
188
+
return -EINVAL;
189
+
190
+
len = mbox_get_msg_size(data);
191
+
cix_mbox_write(priv, len, CIX_FIFO_WM);
192
+
for (i = 0; i < len; i++)
193
+
cix_mbox_write(priv, msg->buf[i], CIX_FIFO_WR);
194
+
195
+
/* Enable fifo empty interrupt */
196
+
val = cix_mbox_read(priv, CIX_INT_ENABLE);
197
+
val |= CIX_FIFO_EMPTY_INT;
198
+
cix_mbox_write(priv, val, CIX_INT_ENABLE);
199
+
200
+
return 0;
201
+
}
202
+
203
+
static int cix_mbox_send_data_fast(struct mbox_chan *chan, void *data)
204
+
{
205
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
206
+
struct cix_mbox_con_priv *cp = chan->con_priv;
207
+
u32 *arg = (u32 *)data;
208
+
int index = cp->index;
209
+
210
+
if (!data)
211
+
return -EINVAL;
212
+
213
+
if (index < 0 || index > CIX_MBOX_FAST_IDX) {
214
+
dev_err(priv->dev, "Invalid Mbox index %d\n", index);
215
+
return -EINVAL;
216
+
}
217
+
218
+
cix_mbox_write(priv, arg[0], CIX_REG_F_INT(index));
219
+
220
+
return 0;
221
+
}
222
+
223
+
static int cix_mbox_send_data(struct mbox_chan *chan, void *data)
224
+
{
225
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
226
+
struct cix_mbox_con_priv *cp = chan->con_priv;
227
+
228
+
if (priv->dir != CIX_MBOX_TX) {
229
+
dev_err(priv->dev, "Invalid Mbox dir %d\n", priv->dir);
230
+
return -EINVAL;
231
+
}
232
+
233
+
switch (cp->type) {
234
+
case CIX_MBOX_TYPE_DB:
235
+
cix_mbox_send_data_db(chan, data);
236
+
break;
237
+
case CIX_MBOX_TYPE_REG:
238
+
cix_mbox_send_data_reg(chan, data);
239
+
break;
240
+
case CIX_MBOX_TYPE_FIFO:
241
+
cix_mbox_send_data_fifo(chan, data);
242
+
break;
243
+
case CIX_MBOX_TYPE_FAST:
244
+
cix_mbox_send_data_fast(chan, data);
245
+
break;
246
+
default:
247
+
dev_err(priv->dev, "Invalid channel type: %d\n", cp->type);
248
+
return -EINVAL;
249
+
}
250
+
return 0;
251
+
}
252
+
253
+
static void cix_mbox_isr_db(struct mbox_chan *chan)
254
+
{
255
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
256
+
u32 int_status;
257
+
258
+
int_status = cix_mbox_read(priv, CIX_INT_STATUS);
259
+
260
+
if (priv->dir == CIX_MBOX_RX) {
261
+
/* rx interrupt is triggered */
262
+
if (int_status & CIX_DB_INT) {
263
+
cix_mbox_write(priv, CIX_DB_INT, CIX_INT_CLEAR);
264
+
mbox_chan_received_data(chan, NULL);
265
+
/* trigger ack interrupt */
266
+
cix_mbox_write(priv, CIX_DB_ACK_INT_BIT, CIX_REG_DB_ACK);
267
+
}
268
+
} else {
269
+
/* tx ack interrupt is triggered */
270
+
if (int_status & CIX_ACK_INT) {
271
+
cix_mbox_write(priv, CIX_ACK_INT, CIX_INT_CLEAR);
272
+
mbox_chan_received_data(chan, NULL);
273
+
}
274
+
}
275
+
}
276
+
277
+
static void cix_mbox_isr_reg(struct mbox_chan *chan)
278
+
{
279
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
280
+
u32 int_status;
281
+
282
+
int_status = cix_mbox_read(priv, CIX_INT_STATUS);
283
+
284
+
if (priv->dir == CIX_MBOX_RX) {
285
+
/* rx interrupt is triggered */
286
+
if (int_status & CIX_DB_INT) {
287
+
u32 data[CIX_MBOX_MSG_WORDS], len, i;
288
+
289
+
cix_mbox_write(priv, CIX_DB_INT, CIX_INT_CLEAR);
290
+
data[0] = cix_mbox_read(priv, CIX_REG_MSG(0));
291
+
len = mbox_get_msg_size(data);
292
+
for (i = 1; i < len; i++)
293
+
data[i] = cix_mbox_read(priv, CIX_REG_MSG(i));
294
+
295
+
/* trigger ack interrupt */
296
+
cix_mbox_write(priv, CIX_DB_ACK_INT_BIT, CIX_REG_DB_ACK);
297
+
mbox_chan_received_data(chan, data);
298
+
}
299
+
} else {
300
+
/* tx ack interrupt is triggered */
301
+
if (int_status & CIX_ACK_INT) {
302
+
cix_mbox_write(priv, CIX_ACK_INT, CIX_INT_CLEAR);
303
+
mbox_chan_txdone(chan, 0);
304
+
}
305
+
}
306
+
}
307
+
308
+
static void cix_mbox_isr_fifo(struct mbox_chan *chan)
309
+
{
310
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
311
+
u32 int_status, status;
312
+
313
+
int_status = cix_mbox_read(priv, CIX_INT_STATUS);
314
+
315
+
if (priv->dir == CIX_MBOX_RX) {
316
+
/* FIFO waterMark interrupt is generated */
317
+
if (int_status & (CIX_FIFO_FULL_INT | CIX_FIFO_WM01_INT)) {
318
+
u32 data[CIX_MBOX_MSG_WORDS] = { 0 }, i = 0;
319
+
320
+
cix_mbox_write(priv, (CIX_FIFO_FULL_INT | CIX_FIFO_WM01_INT),
321
+
CIX_INT_CLEAR);
322
+
do {
323
+
data[i++] = cix_mbox_read(priv, CIX_FIFO_RD);
324
+
} while (!mbox_fifo_empty(chan) && i < CIX_MBOX_MSG_WORDS);
325
+
326
+
mbox_chan_received_data(chan, data);
327
+
}
328
+
/* FIFO underflow is generated */
329
+
if (int_status & CIX_FIFO_UFLOW_INT) {
330
+
status = cix_mbox_read(priv, CIX_FIFO_STAS);
331
+
dev_err(priv->dev, "fifo underflow: int_stats %d\n", status);
332
+
cix_mbox_write(priv, CIX_FIFO_UFLOW_INT, CIX_INT_CLEAR);
333
+
}
334
+
} else {
335
+
/* FIFO empty interrupt is generated */
336
+
if (int_status & CIX_FIFO_EMPTY_INT) {
337
+
u32 val;
338
+
339
+
cix_mbox_write(priv, CIX_FIFO_EMPTY_INT, CIX_INT_CLEAR);
340
+
/* Disable empty irq*/
341
+
val = cix_mbox_read(priv, CIX_INT_ENABLE);
342
+
val &= ~CIX_FIFO_EMPTY_INT;
343
+
cix_mbox_write(priv, val, CIX_INT_ENABLE);
344
+
mbox_chan_txdone(chan, 0);
345
+
}
346
+
/* FIFO overflow is generated */
347
+
if (int_status & CIX_FIFO_OFLOW_INT) {
348
+
status = cix_mbox_read(priv, CIX_FIFO_STAS);
349
+
dev_err(priv->dev, "fifo overlow: int_stats %d\n", status);
350
+
cix_mbox_write(priv, CIX_FIFO_OFLOW_INT, CIX_INT_CLEAR);
351
+
}
352
+
}
353
+
}
354
+
355
+
static void cix_mbox_isr_fast(struct mbox_chan *chan)
356
+
{
357
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
358
+
struct cix_mbox_con_priv *cp = chan->con_priv;
359
+
u32 int_status, data;
360
+
361
+
/* no irq will be trigger for TX dir mbox */
362
+
if (priv->dir != CIX_MBOX_RX)
363
+
return;
364
+
365
+
int_status = cix_mbox_read(priv, CIX_INT_STATUS);
366
+
367
+
if (int_status & CIX_FAST_CH_INT(cp->index)) {
368
+
cix_mbox_write(priv, CIX_FAST_CH_INT(cp->index), CIX_INT_CLEAR);
369
+
data = cix_mbox_read(priv, CIX_REG_F_INT(cp->index));
370
+
mbox_chan_received_data(chan, &data);
371
+
}
372
+
}
373
+
374
+
static irqreturn_t cix_mbox_isr(int irq, void *arg)
375
+
{
376
+
struct mbox_chan *chan = arg;
377
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
378
+
struct cix_mbox_con_priv *cp = chan->con_priv;
379
+
380
+
switch (cp->type) {
381
+
case CIX_MBOX_TYPE_DB:
382
+
cix_mbox_isr_db(chan);
383
+
break;
384
+
case CIX_MBOX_TYPE_REG:
385
+
cix_mbox_isr_reg(chan);
386
+
break;
387
+
case CIX_MBOX_TYPE_FIFO:
388
+
cix_mbox_isr_fifo(chan);
389
+
break;
390
+
case CIX_MBOX_TYPE_FAST:
391
+
cix_mbox_isr_fast(chan);
392
+
break;
393
+
default:
394
+
dev_err(priv->dev, "Invalid channel type: %d\n", cp->type);
395
+
return IRQ_NONE;
396
+
}
397
+
398
+
return IRQ_HANDLED;
399
+
}
400
+
401
+
static int cix_mbox_startup(struct mbox_chan *chan)
402
+
{
403
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
404
+
struct cix_mbox_con_priv *cp = chan->con_priv;
405
+
int index = cp->index, ret;
406
+
u32 val;
407
+
408
+
ret = request_irq(priv->irq, cix_mbox_isr, 0,
409
+
dev_name(priv->dev), chan);
410
+
if (ret) {
411
+
dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq);
412
+
return ret;
413
+
}
414
+
415
+
switch (cp->type) {
416
+
case CIX_MBOX_TYPE_DB:
417
+
/* Overwrite txdone_method for DB channel */
418
+
chan->txdone_method = TXDONE_BY_ACK;
419
+
fallthrough;
420
+
case CIX_MBOX_TYPE_REG:
421
+
if (priv->dir == CIX_MBOX_TX) {
422
+
/* Enable ACK interrupt */
423
+
val = cix_mbox_read(priv, CIX_INT_ENABLE);
424
+
val |= CIX_ACK_INT;
425
+
cix_mbox_write(priv, val, CIX_INT_ENABLE);
426
+
} else {
427
+
/* Enable Doorbell interrupt */
428
+
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
429
+
val |= CIX_DB_INT;
430
+
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
431
+
}
432
+
break;
433
+
case CIX_MBOX_TYPE_FIFO:
434
+
/* reset fifo */
435
+
cix_mbox_write(priv, CIX_FIFO_RST_BIT, CIX_FIFO_RST);
436
+
/* set default watermark */
437
+
cix_mbox_write(priv, CIX_FIFO_WM_DEFAULT, CIX_FIFO_WM);
438
+
if (priv->dir == CIX_MBOX_TX) {
439
+
/* Enable fifo overflow interrupt */
440
+
val = cix_mbox_read(priv, CIX_INT_ENABLE);
441
+
val |= CIX_FIFO_OFLOW_INT;
442
+
cix_mbox_write(priv, val, CIX_INT_ENABLE);
443
+
} else {
444
+
/* Enable fifo full/underflow interrupt */
445
+
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
446
+
val |= CIX_FIFO_UFLOW_INT|CIX_FIFO_WM01_INT;
447
+
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
448
+
}
449
+
break;
450
+
case CIX_MBOX_TYPE_FAST:
451
+
/* Only RX channel has intterupt */
452
+
if (priv->dir == CIX_MBOX_RX) {
453
+
if (index < 0 || index > CIX_MBOX_FAST_IDX) {
454
+
dev_err(priv->dev, "Invalid index %d\n", index);
455
+
ret = -EINVAL;
456
+
goto failed;
457
+
}
458
+
/* enable fast channel interrupt */
459
+
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
460
+
val |= CIX_FAST_CH_INT(index);
461
+
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
462
+
}
463
+
break;
464
+
default:
465
+
dev_err(priv->dev, "Invalid channel type: %d\n", cp->type);
466
+
ret = -EINVAL;
467
+
goto failed;
468
+
}
469
+
return 0;
470
+
471
+
failed:
472
+
free_irq(priv->irq, chan);
473
+
return ret;
474
+
}
475
+
476
+
static void cix_mbox_shutdown(struct mbox_chan *chan)
477
+
{
478
+
struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox);
479
+
struct cix_mbox_con_priv *cp = chan->con_priv;
480
+
int index = cp->index;
481
+
u32 val;
482
+
483
+
switch (cp->type) {
484
+
case CIX_MBOX_TYPE_DB:
485
+
case CIX_MBOX_TYPE_REG:
486
+
if (priv->dir == CIX_MBOX_TX) {
487
+
/* Disable ACK interrupt */
488
+
val = cix_mbox_read(priv, CIX_INT_ENABLE);
489
+
val &= ~CIX_ACK_INT;
490
+
cix_mbox_write(priv, val, CIX_INT_ENABLE);
491
+
} else if (priv->dir == CIX_MBOX_RX) {
492
+
/* Disable Doorbell interrupt */
493
+
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
494
+
val &= ~CIX_DB_INT;
495
+
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
496
+
}
497
+
break;
498
+
case CIX_MBOX_TYPE_FIFO:
499
+
if (priv->dir == CIX_MBOX_TX) {
500
+
/* Disable empty/fifo overflow irq*/
501
+
val = cix_mbox_read(priv, CIX_INT_ENABLE);
502
+
val &= ~(CIX_FIFO_EMPTY_INT | CIX_FIFO_OFLOW_INT);
503
+
cix_mbox_write(priv, val, CIX_INT_ENABLE);
504
+
} else if (priv->dir == CIX_MBOX_RX) {
505
+
/* Disable fifo WM01/underflow interrupt */
506
+
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
507
+
val &= ~(CIX_FIFO_UFLOW_INT | CIX_FIFO_WM01_INT);
508
+
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
509
+
}
510
+
break;
511
+
case CIX_MBOX_TYPE_FAST:
512
+
if (priv->dir == CIX_MBOX_RX) {
513
+
if (index < 0 || index > CIX_MBOX_FAST_IDX) {
514
+
dev_err(priv->dev, "Invalid index %d\n", index);
515
+
break;
516
+
}
517
+
/* Disable fast channel interrupt */
518
+
val = cix_mbox_read(priv, CIX_INT_ENABLE_SIDE_B);
519
+
val &= ~CIX_FAST_CH_INT(index);
520
+
cix_mbox_write(priv, val, CIX_INT_ENABLE_SIDE_B);
521
+
}
522
+
break;
523
+
524
+
default:
525
+
dev_err(priv->dev, "Invalid channel type: %d\n", cp->type);
526
+
break;
527
+
}
528
+
529
+
free_irq(priv->irq, chan);
530
+
}
531
+
532
+
static const struct mbox_chan_ops cix_mbox_chan_ops = {
533
+
.send_data = cix_mbox_send_data,
534
+
.startup = cix_mbox_startup,
535
+
.shutdown = cix_mbox_shutdown,
536
+
};
537
+
538
+
static void cix_mbox_init(struct cix_mbox_priv *priv)
539
+
{
540
+
struct cix_mbox_con_priv *cp;
541
+
int i;
542
+
543
+
for (i = 0; i < CIX_MBOX_CHANS; i++) {
544
+
cp = &priv->con_priv[i];
545
+
cp->index = i;
546
+
cp->chan = &priv->mbox_chans[i];
547
+
priv->mbox_chans[i].con_priv = cp;
548
+
if (cp->index <= CIX_MBOX_FAST_IDX)
549
+
cp->type = CIX_MBOX_TYPE_FAST;
550
+
if (cp->index == CIX_MBOX_DB_IDX)
551
+
cp->type = CIX_MBOX_TYPE_DB;
552
+
if (cp->index == CIX_MBOX_FIFO_IDX)
553
+
cp->type = CIX_MBOX_TYPE_FIFO;
554
+
if (cp->index == CIX_MBOX_REG_IDX)
555
+
cp->type = CIX_MBOX_TYPE_REG;
556
+
}
557
+
}
558
+
559
+
static int cix_mbox_probe(struct platform_device *pdev)
560
+
{
561
+
struct device *dev = &pdev->dev;
562
+
struct cix_mbox_priv *priv;
563
+
struct resource *res;
564
+
const char *dir_str;
565
+
int ret;
566
+
567
+
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
568
+
if (!priv)
569
+
return -ENOMEM;
570
+
571
+
priv->dev = dev;
572
+
priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
573
+
if (IS_ERR(priv->base))
574
+
return PTR_ERR(priv->base);
575
+
576
+
/*
577
+
* The first 0x80 bytes of the register space of the cix mailbox controller
578
+
* can be used as shared memory for clients. When this shared memory is in
579
+
* use, the base address of the mailbox is offset by 0x80. Therefore, when
580
+
* performing subsequent read/write operations, it is necessary to subtract
581
+
* the offset CIX_SHMEM_OFFSET.
582
+
*
583
+
* When the base address of the mailbox is offset by 0x80, it indicates
584
+
* that shmem is in use.
585
+
*/
586
+
priv->use_shmem = !!(res->start & CIX_SHMEM_OFFSET);
587
+
588
+
priv->irq = platform_get_irq(pdev, 0);
589
+
if (priv->irq < 0)
590
+
return priv->irq;
591
+
592
+
if (device_property_read_string(dev, "cix,mbox-dir", &dir_str)) {
593
+
dev_err(priv->dev, "cix,mbox_dir property not found\n");
594
+
return -EINVAL;
595
+
}
596
+
597
+
if (!strcmp(dir_str, "tx"))
598
+
priv->dir = 0;
599
+
else if (!strcmp(dir_str, "rx"))
600
+
priv->dir = 1;
601
+
else {
602
+
dev_err(priv->dev, "cix,mbox_dir=%s is not expected\n", dir_str);
603
+
return -EINVAL;
604
+
}
605
+
606
+
cix_mbox_init(priv);
607
+
608
+
priv->mbox.dev = dev;
609
+
priv->mbox.ops = &cix_mbox_chan_ops;
610
+
priv->mbox.chans = priv->mbox_chans;
611
+
priv->mbox.txdone_irq = true;
612
+
priv->mbox.num_chans = CIX_MBOX_CHANS;
613
+
priv->mbox.of_xlate = NULL;
614
+
615
+
platform_set_drvdata(pdev, priv);
616
+
ret = devm_mbox_controller_register(dev, &priv->mbox);
617
+
if (ret)
618
+
dev_err(dev, "Failed to register mailbox %d\n", ret);
619
+
620
+
return ret;
621
+
}
622
+
623
+
static const struct of_device_id cix_mbox_dt_ids[] = {
624
+
{ .compatible = "cix,sky1-mbox" },
625
+
{ },
626
+
};
627
+
MODULE_DEVICE_TABLE(of, cix_mbox_dt_ids);
628
+
629
+
static struct platform_driver cix_mbox_driver = {
630
+
.probe = cix_mbox_probe,
631
+
.driver = {
632
+
.name = "cix_mbox",
633
+
.of_match_table = cix_mbox_dt_ids,
634
+
},
635
+
};
636
+
637
+
static int __init cix_mailbox_init(void)
638
+
{
639
+
return platform_driver_register(&cix_mbox_driver);
640
+
}
641
+
arch_initcall(cix_mailbox_init);
642
+
643
+
MODULE_AUTHOR("Cix Technology Group Co., Ltd.");
644
+
MODULE_DESCRIPTION("CIX mailbox driver");
645
+
MODULE_LICENSE("GPL");
+279
include/dt-bindings/clock/cix,sky1.h
+279
include/dt-bindings/clock/cix,sky1.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright 2024-2025 Cix Technology Group Co., Ltd.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_CIX_SKY1_H
7
+
#define _DT_BINDINGS_CLK_CIX_SKY1_H
8
+
9
+
#define CLK_TREE_CPU_GICxCLK 0
10
+
#define CLK_TREE_CPU_PPUCLK 1
11
+
#define CLK_TREE_CPU_PERIPHCLK 2
12
+
#define CLK_TREE_DSU_CLK 3
13
+
#define CLK_TREE_DSU_PCLK 4
14
+
#define CLK_TREE_CPU_CLK_BC0 5
15
+
#define CLK_TREE_CPU_CLK_BC1 6
16
+
#define CLK_TREE_CPU_CLK_BC2 7
17
+
#define CLK_TREE_CPU_CLK_BC3 8
18
+
#define CLK_TREE_CPU_CLK_MC0 9
19
+
#define CLK_TREE_CPU_CLK_MC1 10
20
+
#define CLK_TREE_CPU_CLK_MC2 11
21
+
#define CLK_TREE_CPU_CLK_MC3 12
22
+
#define CLK_TREE_CPU_CLK_LC0 13
23
+
#define CLK_TREE_CPU_CLK_LC1 14
24
+
#define CLK_TREE_CPU_CLK_LC2 15
25
+
#define CLK_TREE_CPU_CLK_LC3 16
26
+
#define CLK_TREE_CSI_CTRL0_PCLK 17
27
+
#define CLK_TREE_CSI_CTRL1_PCLK 18
28
+
#define CLK_TREE_CSI_CTRL2_PCLK 19
29
+
#define CLK_TREE_CSI_CTRL3_PCLK 20
30
+
#define CLK_TREE_CSI_DMA0_PCLK 21
31
+
#define CLK_TREE_CSI_DMA1_PCLK 22
32
+
#define CLK_TREE_CSI_DMA2_PCLK 23
33
+
#define CLK_TREE_CSI_DMA3_PCLK 24
34
+
#define CLK_TREE_CSI_PHY0_PSM 25
35
+
#define CLK_TREE_CSI_PHY1_PSM 26
36
+
#define CLK_TREE_CSI_PHY0_APBCLK 27
37
+
#define CLK_TREE_CSI_PHY1_APBCLK 28
38
+
#define CLK_TREE_FCH_APB_CLK 29
39
+
#define CLK_TREE_GPU_CLK_400M 30
40
+
#define CLK_TREE_GPU_CLK_CORE 31
41
+
#define CLK_TREE_GPU_CLK_STACKS 32
42
+
#define CLK_TREE_DP0_PIXEL0 33
43
+
#define CLK_TREE_DP0_PIXEL1 34
44
+
#define CLK_TREE_DP1_PIXEL0 35
45
+
#define CLK_TREE_DP1_PIXEL1 36
46
+
#define CLK_TREE_DP2_PIXEL0 37
47
+
#define CLK_TREE_DP2_PIXEL1 38
48
+
#define CLK_TREE_DP3_PIXEL0 39
49
+
#define CLK_TREE_DP3_PIXEL1 40
50
+
#define CLK_TREE_DP4_PIXEL0 41
51
+
#define CLK_TREE_DP4_PIXEL1 42
52
+
#define CLK_TREE_DPU_CLK 43
53
+
#define CLK_TREE_DPU0_ACLK 44
54
+
#define CLK_TREE_DPU1_ACLK 45
55
+
#define CLK_TREE_DPU2_ACLK 46
56
+
#define CLK_TREE_DPU3_ACLK 47
57
+
#define CLK_TREE_DPU4_ACLK 48
58
+
#define CLK_TREE_DPC0_VIDCLK0 49
59
+
#define CLK_TREE_DPC0_VIDCLK1 50
60
+
#define CLK_TREE_DPC1_VIDCLK0 51
61
+
#define CLK_TREE_DPC1_VIDCLK1 52
62
+
#define CLK_TREE_DPC2_VIDCLK0 53
63
+
#define CLK_TREE_DPC2_VIDCLK1 54
64
+
#define CLK_TREE_DPC3_VIDCLK0 55
65
+
#define CLK_TREE_DPC3_VIDCLK1 56
66
+
#define CLK_TREE_DPC4_VIDCLK0 57
67
+
#define CLK_TREE_DPC4_VIDCLK1 58
68
+
#define CLK_TREE_DPC0_APBCLK 59
69
+
#define CLK_TREE_DPC1_APBCLK 60
70
+
#define CLK_TREE_DPC2_APBCLK 61
71
+
#define CLK_TREE_DPC3_APBCLK 62
72
+
#define CLK_TREE_DPC4_APBCLK 63
73
+
#define CLK_TREE_NPU_MEMCLK 64
74
+
#define CLK_TREE_NPU_SYSCLK 65
75
+
#define CLK_TREE_NPU_DBGCLK 66
76
+
#define CLK_TREE_VPU_APBCLK 67
77
+
#define CLK_TREE_ISP_ACLK 68
78
+
#define CLK_TREE_ISP_SCLK 69
79
+
#define CLK_TREE_AUDIO_CLK4 70
80
+
#define CLK_TREE_AUDIO_CLK5 71
81
+
#define CLK_TREE_CAMERA_MCLK0 72
82
+
#define CLK_TREE_CAMERA_MCLK1 73
83
+
#define CLK_TREE_CAMERA_MCLK2 74
84
+
#define CLK_TREE_CAMERA_MCLK3 75
85
+
#define CLK_TREE_AUDIO_CLK0 76
86
+
#define CLK_TREE_AUDIO_CLK1 77
87
+
#define CLK_TREE_AUDIO_CLK2 78
88
+
#define CLK_TREE_AUDIO_CLK3 79
89
+
#define CLK_TREE_MM_NI700_CLK 80
90
+
#define CLK_TREE_SYS_NI700_CLK 81
91
+
#define CLK_TREE_GMAC0_ACLK 82
92
+
#define CLK_TREE_GMAC1_ACLK 83
93
+
#define CLK_TREE_GMAC0_DIV_ACLK 84
94
+
#define CLK_TREE_GMAC0_DIV_TXCLK 85
95
+
#define CLK_TREE_GMAC0_RGMII0_TXCLK 86
96
+
#define CLK_TREE_GMAC1_DIV_ACLK 87
97
+
#define CLK_TREE_GMAC1_DIV_TXCLK 88
98
+
#define CLK_TREE_GMAC1_RGMII0_TXCLK 89
99
+
#define CLK_TREE_GMAC0_PCLK 90
100
+
#define CLK_TREE_GMAC1_PCLK 91
101
+
#define CLK_TREE_USB2_0_AXI_GATE 92
102
+
#define CLK_TREE_USB2_0_APB_GATE 93
103
+
#define CLK_TREE_USB2_1_AXI_GATE 94
104
+
#define CLK_TREE_USB2_1_APB_GATE 95
105
+
#define CLK_TREE_USB2_2_AXI_GATE 96
106
+
#define CLK_TREE_USB2_2_APB_GATE 97
107
+
#define CLK_TREE_USB2_3_AXI_GATE 98
108
+
#define CLK_TREE_USB2_3_APB_GATE 99
109
+
#define CLK_TREE_USB2_0_PHY_GATE 100
110
+
#define CLK_TREE_USB2_1_PHY_GATE 101
111
+
#define CLK_TREE_USB2_2_PHY_GATE 102
112
+
#define CLK_TREE_USB2_3_PHY_GATE 103
113
+
#define CLK_TREE_USB3C_DRD_AXI_GATE 104
114
+
#define CLK_TREE_USB3C_DRD_APB_GATE 105
115
+
#define CLK_TREE_USB3C_DRD_PHY2_GATE 106
116
+
#define CLK_TREE_USB3C_DRD_PHY3_GATE 107
117
+
#define CLK_TREE_USB3C_0_AXI_GATE 108
118
+
#define CLK_TREE_USB3C_0_APB_GATE 109
119
+
#define CLK_TREE_USB3C_0_PHY2_GATE 110
120
+
#define CLK_TREE_USB3C_0_PHY3_GATE 111
121
+
#define CLK_TREE_USB3C_1_AXI_GATE 112
122
+
#define CLK_TREE_USB3C_1_APB_GATE 113
123
+
#define CLK_TREE_USB3C_1_PHY2_GATE 114
124
+
#define CLK_TREE_USB3C_1_PHY3_GATE 115
125
+
#define CLK_TREE_USB3C_2_AXI_GATE 116
126
+
#define CLK_TREE_USB3C_2_APB_GATE 117
127
+
#define CLK_TREE_USB3C_2_PHY2_GATE 118
128
+
#define CLK_TREE_USB3C_2_PHY3_GATE 119
129
+
#define CLK_TREE_USB3A_0_AXI_GATE 120
130
+
#define CLK_TREE_USB3A_0_APB_GATE 121
131
+
#define CLK_TREE_USB3A_0_PHY2_GATE 122
132
+
#define CLK_TREE_USB3A_1_AXI_GATE 123
133
+
#define CLK_TREE_USB3A_1_APB_GATE 124
134
+
#define CLK_TREE_USB3A_1_PHY2_GATE 125
135
+
#define CLK_TREE_USB3A_PHY3_GATE 126
136
+
#define CLK_TREE_USB2_0_CLK_SOF 127
137
+
#define CLK_TREE_USB2_1_CLK_SOF 128
138
+
#define CLK_TREE_USB2_2_CLK_SOF 129
139
+
#define CLK_TREE_USB2_3_CLK_SOF 130
140
+
#define CLK_TREE_USB3C_DRD_CLK_SOF 131
141
+
#define CLK_TREE_USB3C_H0_CLK_SOF 132
142
+
#define CLK_TREE_USB3C_H1_CLK_SOF 133
143
+
#define CLK_TREE_USB3C_H2_CLK_SOF 134
144
+
#define CLK_TREE_USB3A_H0_CLK_SOF 135
145
+
#define CLK_TREE_USB3A_H1_CLK_SOF 136
146
+
#define CLK_TREE_USB2_0_CLK_LPM 137
147
+
#define CLK_TREE_USB2_1_CLK_LPM 138
148
+
#define CLK_TREE_USB2_2_CLK_LPM 139
149
+
#define CLK_TREE_USB2_3_CLK_LPM 140
150
+
#define CLK_TREE_USB3C_DRD_CLK_LPM 141
151
+
#define CLK_TREE_USB3C_H0_CLK_LPM 142
152
+
#define CLK_TREE_USB3C_H1_CLK_LPM 143
153
+
#define CLK_TREE_USB3C_H2_CLK_LPM 144
154
+
#define CLK_TREE_USB3A_H0_CLK_LPM 145
155
+
#define CLK_TREE_USB3A_H1_CLK_LPM 146
156
+
#define CLK_TREE_USB2_0_PHY_REF 147
157
+
#define CLK_TREE_USB2_1_PHY_REF 148
158
+
#define CLK_TREE_USB2_2_PHY_REF 149
159
+
#define CLK_TREE_USB2_3_PHY_REF 150
160
+
#define CLK_TREE_USB3C_DRD_PHY_REF 151
161
+
#define CLK_TREE_USB3C_H0_PHY_REF 152
162
+
#define CLK_TREE_USB3C_H1_PHY_REF 153
163
+
#define CLK_TREE_USB3C_H2_PHY_REF 154
164
+
#define CLK_TREE_USB3A_H0_PHY_REF 155
165
+
#define CLK_TREE_USB3A_H1_PHY_REF 156
166
+
#define CLK_TREE_USB3C_DRD_PHY_x4_REF 157
167
+
#define CLK_TREE_USB3C_H0_PHY_x4_REF 158
168
+
#define CLK_TREE_USB3C_H1_PHY_x4_REF 159
169
+
#define CLK_TREE_USB3C_H2_PHY_x4_REF 160
170
+
#define CLK_TREE_USB3A_PHY_x2_REF 161
171
+
#define CLK_TREE_PCIE_X8CTRL_APB 162
172
+
#define CLK_TREE_PCIE_X4CTRL_APB 163
173
+
#define CLK_TREE_PCIE_X2CTRL_APB 164
174
+
#define CLK_TREE_PCIE_X1_0CTRL_APB 165
175
+
#define CLK_TREE_PCIE_X1_1CTRL_APB 166
176
+
#define CLK_TREE_PCIE_X8_PHY_APB 167
177
+
#define CLK_TREE_PCIE_X4_PHY_APB 168
178
+
#define CLK_TREE_PCIE_X211_PHY_APB 169
179
+
#define CLK_TREE_PCIE_NI700_CLK 170
180
+
#define CLK_TREE_PCIE_CTRL0_CLK 171
181
+
#define CLK_TREE_PCIE_CTRL1_CLK 172
182
+
#define CLK_TREE_PCIE_CTRL2_CLK 173
183
+
#define CLK_TREE_PCIE_CTRL3_CLK 174
184
+
#define CLK_TREE_PCIE_CTRL4_CLK 175
185
+
#define CLK_TREE_CSI_CTRL0_SYSCLK 176
186
+
#define CLK_TREE_CSI_CTRL1_SYSCLK 177
187
+
#define CLK_TREE_CSI_CTRL2_SYSCLK 178
188
+
#define CLK_TREE_CSI_CTRL3_SYSCLK 179
189
+
#define CLK_TREE_CSI_CTRL0_PIXEL0_CLK 180
190
+
#define CLK_TREE_CSI_CTRL0_PIXEL1_CLK 181
191
+
#define CLK_TREE_CSI_CTRL0_PIXEL2_CLK 182
192
+
#define CLK_TREE_CSI_CTRL0_PIXEL3_CLK 183
193
+
#define CLK_TREE_CSI_CTRL1_PIXEL0_CLK 184
194
+
#define CLK_TREE_CSI_CTRL2_PIXEL0_CLK 185
195
+
#define CLK_TREE_CSI_CTRL2_PIXEL1_CLK 186
196
+
#define CLK_TREE_CSI_CTRL2_PIXEL2_CLK 187
197
+
#define CLK_TREE_CSI_CTRL2_PIXEL3_CLK 188
198
+
#define CLK_TREE_CSI_CTRL3_PIXEL0_CLK 189
199
+
#define CLK_TREE_CI700_GCLK0 190
200
+
#define CLK_TREE_DDRC0_ACLK_CLK 191
201
+
#define CLK_TREE_DDRC1_ACLK_CLK 192
202
+
#define CLK_TREE_DDRC2_ACLK_CLK 193
203
+
#define CLK_TREE_DDRC3_ACLK_CLK 194
204
+
#define CLK_TREE_DDRC0_DFICLK_CLK 195
205
+
#define CLK_TREE_DDRC1_DFICLK_CLK 196
206
+
#define CLK_TREE_DDRC2_DFICLK_CLK 197
207
+
#define CLK_TREE_DDRC3_DFICLK_CLK 198
208
+
#define CLK_TREE_PHY0_SYNC_CLK 199
209
+
#define CLK_TREE_PHY1_SYNC_CLK 200
210
+
#define CLK_TREE_PHY2_SYNC_CLK 201
211
+
#define CLK_TREE_PHY3_SYNC_CLK 202
212
+
#define CLK_TREE_PHY0_BYPASS_CLK 203
213
+
#define CLK_TREE_PHY1_BYPASS_CLK 204
214
+
#define CLK_TREE_PHY2_BYPASS_CLK 205
215
+
#define CLK_TREE_PHY3_BYPASS_CLK 206
216
+
#define CLK_TREE_DDRC_0_APB 207
217
+
#define CLK_TREE_DDRC_1_APB 208
218
+
#define CLK_TREE_DDRC_2_APB 209
219
+
#define CLK_TREE_DDRC_3_APB 210
220
+
#define CLK_TREE_TZC400_0_APB 211
221
+
#define CLK_TREE_TZC400_1_APB 212
222
+
#define CLK_TREE_TZC400_2_APB 213
223
+
#define CLK_TREE_TZC400_3_APB 214
224
+
#define CLK_TREE_S5_SENSOR_HUB_25M 215
225
+
#define CLK_TREE_S5_SENSOR_HUB_400M 216
226
+
#define CLK_TREE_S5_CSS600_100M 217
227
+
#define CLK_TREE_S5_DFD_800M 218
228
+
#define CLK_TREE_S5_CSU_SE_800M 219
229
+
#define CLK_TREE_S5_CSU_PM_800M 220
230
+
#define CLK_TREE_PCIE_REF_B0 221
231
+
#define CLK_TREE_PCIE_REF_B1 222
232
+
#define CLK_TREE_PCIE_REF_B2 223
233
+
#define CLK_TREE_PCIE_REF_B3 224
234
+
#define CLK_TREE_PCIE_REF_B4 225
235
+
#define CLK_TREE_PCIE_REF_PHY_X8 226
236
+
#define CLK_TREE_PCIE_REF_PHY_X4 227
237
+
#define CLK_TREE_PCIE_REF_PHY_X211 228
238
+
#define CLK_TREE_GMAC_REC_CLK 229
239
+
#define CLK_TREE_GPUTOP_PLL 230
240
+
#define CLK_TREE_GPUCORE_PLL 231
241
+
#define CLK_TREE_CPU_PLL_LIT 232
242
+
#define CLK_TREE_CPU_PLL0 233
243
+
#define CLK_TREE_CPU_PLL1 234
244
+
#define CLK_TREE_CPU_PLL2 235
245
+
#define CLK_TREE_CPU_PLL3 236
246
+
#define CLK_TREE_FCH_I3C0_FUNC 237
247
+
#define CLK_TREE_FCH_I3C1_FUNC 238
248
+
#define CLK_TREE_FCH_DMA_ACLK 239
249
+
#define CLK_TREE_FCH_XSPI_FUNC 240
250
+
#define CLK_TREE_FCH_XSPI_MACLK 241
251
+
#define CLK_TREE_FCH_TIMER_FUN 242
252
+
#define CLK_TREE_FCH_APB_IO_S0 243
253
+
#define CLK_TREE_FCH_I3C0_APB 244
254
+
#define CLK_TREE_FCH_I3C1_APB 245
255
+
#define CLK_TREE_FCH_UART0_APB 246
256
+
#define CLK_TREE_FCH_UART1_APB 247
257
+
#define CLK_TREE_FCH_UART2_APB 248
258
+
#define CLK_TREE_FCH_UART3_APB 249
259
+
#define CLK_TREE_FCH_SPI0_APB 250
260
+
#define CLK_TREE_FCH_SPI1_APB 251
261
+
#define CLK_TREE_FCH_XSPI_APB 252
262
+
#define CLK_TREE_FCH_I2C0_APB 253
263
+
#define CLK_TREE_FCH_I2C1_APB 254
264
+
#define CLK_TREE_FCH_I2C2_APB 255
265
+
#define CLK_TREE_FCH_I2C3_APB 256
266
+
#define CLK_TREE_FCH_I2C4_APB 257
267
+
#define CLK_TREE_FCH_I2C5_APB 258
268
+
#define CLK_TREE_FCH_I2C6_APB 259
269
+
#define CLK_TREE_FCH_I2C7_APB 260
270
+
#define CLK_TREE_FCH_TIMER_APB 261
271
+
#define CLK_TREE_FCH_GPIO_APB 262
272
+
#define CLK_TREE_FCH_UART0_FUNC 263
273
+
#define CLK_TREE_FCH_UART1_FUNC 264
274
+
#define CLK_TREE_FCH_UART2_FUNC 265
275
+
#define CLK_TREE_FCH_UART3_FUNC 266
276
+
/* 267~271 not used by AP, skip */
277
+
#define CLK_TREE_GPU_CLK_200M 272
278
+
279
+
#endif