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perf arm_spe: Improve SIMD flags setting

Fill in ASE and SME operations for the SIMD arch field.

Also set the predicate flags for SVE and SME, but differences between
them: SME does not have a predicate flag, so the setting is based on
events. SVE provides a predicate flag to indicate whether the predicate
is disabled, which allows it to be distinguished into four cases: full
predicates, empty predicates, fully predicated, and disabled predicates.

After:

perf report -s +simd
...
0.06% 0.06% sve-test sve-test [.] setz [p] SVE
0.06% 0.06% sve-test [kernel.kallsyms] [k] do_raw_spin_lock
0.06% 0.06% sve-test sve-test [.] getz [p] SVE
0.06% 0.06% sve-test [kernel.kallsyms] [k] timekeeping_advance
0.06% 0.06% sve-test sve-test [.] getz [d] SVE
0.06% 0.06% sve-test [kernel.kallsyms] [k] update_load_avg
0.06% 0.06% sve-test sve-test [.] getz [e] SVE
0.05% 0.05% sve-test sve-test [.] setz [e] SVE
0.05% 0.05% sve-test [kernel.kallsyms] [k] update_curr
0.05% 0.05% sve-test sve-test [.] setz [d] SVE
0.05% 0.05% sve-test [kernel.kallsyms] [k] do_raw_spin_unlock
0.05% 0.05% sve-test [kernel.kallsyms] [k] timekeeping_update_from_shadow.constprop.0
0.05% 0.05% sve-test sve-test [.] getz [f] SVE
0.05% 0.05% sve-test sve-test [.] setz [f] SVE

Reviewed-by: James Clark <james.clark@linaro.org>
Reviewed-by: Ian Rogers <irogers@google.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>

authored by

Leo Yan and committed by
Namhyung Kim
4e03d649 54940f15

+19 -5
+19 -5
tools/perf/util/arm-spe.c
··· 353 353 354 354 if (record->op & ARM_SPE_OP_SVE) 355 355 simd_flags.arch |= SIMD_OP_FLAGS_ARCH_SVE; 356 + else if (record->op & ARM_SPE_OP_SME) 357 + simd_flags.arch |= SIMD_OP_FLAGS_ARCH_SME; 358 + else if (record->op & (ARM_SPE_OP_ASE | ARM_SPE_OP_SIMD_FP)) 359 + simd_flags.arch |= SIMD_OP_FLAGS_ARCH_ASE; 356 360 357 - if (record->type & ARM_SPE_SVE_PARTIAL_PRED) 358 - simd_flags.pred |= SIMD_OP_FLAGS_PRED_PARTIAL; 359 - 360 - if (record->type & ARM_SPE_SVE_EMPTY_PRED) 361 - simd_flags.pred |= SIMD_OP_FLAGS_PRED_EMPTY; 361 + if (record->op & ARM_SPE_OP_SVE) { 362 + if (!(record->op & ARM_SPE_OP_PRED)) 363 + simd_flags.pred = SIMD_OP_FLAGS_PRED_DISABLED; 364 + else if (record->type & ARM_SPE_SVE_PARTIAL_PRED) 365 + simd_flags.pred = SIMD_OP_FLAGS_PRED_PARTIAL; 366 + else if (record->type & ARM_SPE_SVE_EMPTY_PRED) 367 + simd_flags.pred = SIMD_OP_FLAGS_PRED_EMPTY; 368 + else 369 + simd_flags.pred = SIMD_OP_FLAGS_PRED_FULL; 370 + } else { 371 + if (record->type & ARM_SPE_SVE_PARTIAL_PRED) 372 + simd_flags.pred = SIMD_OP_FLAGS_PRED_PARTIAL; 373 + else if (record->type & ARM_SPE_SVE_EMPTY_PRED) 374 + simd_flags.pred = SIMD_OP_FLAGS_PRED_EMPTY; 375 + } 362 376 363 377 return simd_flags; 364 378 }