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iommu/amd: Refactor persistent DTE bits programming into amd_iommu_make_clear_dte()

To help avoid duplicate logic when programing DTE for nested translation.

Note that this commit changes behavior of when the IOMMU driver is
switching domain during attach and the blocking domain, where DTE bit
fields for interrupt pass-through (i.e. Lint0, Lint1, NMI, INIT, ExtInt)
and System management message could be affected. These DTE bits are
specified in the IVRS table for specific devices, and should be persistent.

Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

authored by

Suravee Suthikulpanit and committed by
Joerg Roedel 4e1b09d9 757d2b1f

+13 -11
+13
drivers/iommu/amd/amd_iommu.h
··· 197 197 static inline void 198 198 amd_iommu_make_clear_dte(struct iommu_dev_data *dev_data, struct dev_table_entry *new) 199 199 { 200 + struct dev_table_entry *initial_dte; 201 + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev); 202 + 200 203 /* All existing DTE must have V bit set */ 201 204 new->data128[0] = DTE_FLAG_V; 202 205 new->data128[1] = 0; 206 + 207 + /* 208 + * Restore cached persistent DTE bits, which can be set by information 209 + * in IVRS table. See set_dev_entry_from_acpi(). 210 + */ 211 + initial_dte = amd_iommu_get_ivhd_dte_flags(iommu->pci_seg->id, dev_data->devid); 212 + if (initial_dte) { 213 + new->data128[0] |= initial_dte->data128[0]; 214 + new->data128[1] |= initial_dte->data128[1]; 215 + } 203 216 } 204 217 205 218 /* NESTED */
-11
drivers/iommu/amd/iommu.c
··· 2110 2110 { 2111 2111 u16 domid; 2112 2112 u32 old_domid; 2113 - struct dev_table_entry *initial_dte; 2114 2113 struct dev_table_entry new = {}; 2115 2114 struct protection_domain *domain = dev_data->domain; 2116 2115 struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; ··· 2166 2167 2167 2168 old_domid = READ_ONCE(dte->data[1]) & DTE_DOMID_MASK; 2168 2169 new.data[1] |= domid; 2169 - 2170 - /* 2171 - * Restore cached persistent DTE bits, which can be set by information 2172 - * in IVRS table. See set_dev_entry_from_acpi(). 2173 - */ 2174 - initial_dte = amd_iommu_get_ivhd_dte_flags(iommu->pci_seg->id, dev_data->devid); 2175 - if (initial_dte) { 2176 - new.data128[0] |= initial_dte->data128[0]; 2177 - new.data128[1] |= initial_dte->data128[1]; 2178 - } 2179 2170 2180 2171 set_dte_gcr3_table(iommu, dev_data, &new); 2181 2172