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spi: rzv2h-rspi: Fix max_speed_hz advertising prohibited bit rate

On RZ/V2H(P), RZ/G3E and RZ/G3L, RSPI_n_TCLK is fixed at 200MHz.
The max_speed_hz was computed using clk_round_rate(tclk, ULONG_MAX)
with SPR=0 and BRDV=0, resulting in 100Mbps - the exact combination
prohibited on these SoCs. This could cause the SPI framework to request
a speed that rzv2h_rspi_find_rate_fixed() would skip, potentially
leading to a clock selection failure.

On RZ/T2H and RZ/N2H the max_speed_hz was correctly calculated as
50Mbps for both the variable PCLKSPIn and fixed PCLK clock sources.

Since the maximum supported bit rate is 50Mbps across all supported SoC
variants, replace the clk_round_rate() based calculation with a define
RSPI_MAX_SPEED_HZ set to 50MHz and use it directly for max_speed_hz.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20260410080517.2405700-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Lad Prabhakar and committed by
Mark Brown 4e292cbf 591cd656

+3 -7
+3 -7
drivers/spi/spi-rzv2h-rspi.c
··· 77 77 78 78 #define RSPI_RESET_NUM 2 79 79 80 + #define RSPI_MAX_SPEED_HZ 50000000 81 + 80 82 struct rzv2h_rspi_best_clock { 81 83 struct clk *clk; 82 84 unsigned long clk_rate; ··· 773 771 RSPI_SPBR_SPR_MAX, 774 772 RSPI_SPCMD_BRDV_MAX); 775 773 776 - tclk_rate = clk_round_rate(rspi->tclk, ULONG_MAX); 777 - if (tclk_rate < 0) 778 - return tclk_rate; 779 - 780 - controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate, 781 - RSPI_SPBR_SPR_MIN, 782 - RSPI_SPCMD_BRDV_MIN); 774 + controller->max_speed_hz = RSPI_MAX_SPEED_HZ; 783 775 784 776 controller->dma_tx = devm_dma_request_chan(dev, "tx"); 785 777 if (IS_ERR(controller->dma_tx)) {