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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mmc: sdhci-of-dwcmshc: Change to dwcmshc_phy_init for reusing codes
dwcmshc_phy_1_8v_init and dwcmshc_phy_3_3v_init differ only by a few
lines of code. This allow us to reuse code depending on voltage.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20250131025406.1753513-1-jh80.chung@samsung.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
authored by
Jaehoon Chung
and committed by
Ulf Hansson
4e35c611
6bc02265
+15
-57
+15
-57
drivers/mmc/host/sdhci-of-dwcmshc.c
+15
-57
drivers/mmc/host/sdhci-of-dwcmshc.c
···
328
328
sdhci_request(mmc, mrq);
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}
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331
-
static void dwcmshc_phy_1_8v_init(struct sdhci_host *host)
331
+
static void dwcmshc_phy_init(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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+
u32 rxsel = PHY_PAD_RXSEL_3V3;
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u32 val;
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+
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+
if (priv->flags & FLAG_IO_FIXED_1V8 ||
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+
host->mmc->ios.timing & MMC_SIGNAL_VOLTAGE_180)
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+
rxsel = PHY_PAD_RXSEL_1V8;
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/* deassert phy reset & set tx drive strength */
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val = PHY_CNFG_RSTN_DEASSERT;
···
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sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
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/* configure phy pads */
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-
val = PHY_PAD_RXSEL_1V8;
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+
val = rxsel;
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val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
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val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
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val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
···
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val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
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sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
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-
val = PHY_PAD_RXSEL_1V8;
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+
val = rxsel;
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val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
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val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
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val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
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sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
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/* enable data strobe mode */
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-
sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL),
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-
PHY_DLLDL_CNFG_R);
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+
if (rxsel == PHY_PAD_RXSEL_1V8) {
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+
u8 sel = FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL);
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+
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+
sdhci_writeb(host, sel, PHY_DLLDL_CNFG_R);
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+
}
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/* enable phy dll */
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sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
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-
}
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-
static void dwcmshc_phy_3_3v_init(struct sdhci_host *host)
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-
{
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-
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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-
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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-
u32 val;
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-
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-
/* deassert phy reset & set tx drive strength */
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-
val = PHY_CNFG_RSTN_DEASSERT;
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-
val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);
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-
val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);
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-
sdhci_writel(host, val, PHY_CNFG_R);
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-
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-
/* disable delay line */
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-
sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
401
-
402
-
/* set delay line */
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-
sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
404
-
sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
405
-
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-
/* enable delay lane */
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-
val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
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-
val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
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-
sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
410
-
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-
/* configure phy pads */
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-
val = PHY_PAD_RXSEL_3V3;
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-
val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
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-
val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
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-
val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
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-
sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
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-
sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
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-
sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
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-
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-
val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
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-
val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
422
-
sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
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-
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-
val = PHY_PAD_RXSEL_3V3;
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-
val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
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-
val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
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-
val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
428
-
sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
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-
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-
/* enable phy dll */
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-
sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
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384
}
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386
static void th1520_sdhci_set_phy(struct sdhci_host *host)
···
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433
u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
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u16 emmc_ctrl;
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-
/* Before power on, set PHY configs */
399
-
if (priv->flags & FLAG_IO_FIXED_1V8)
400
-
dwcmshc_phy_1_8v_init(host);
401
-
else
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-
dwcmshc_phy_3_3v_init(host);
436
+
dwcmshc_phy_init(host);
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404
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if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
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emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
···
1121
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.get_max_clock = dwcmshc_get_max_clock,
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.reset = th1520_sdhci_reset,
1123
1165
.adma_write_desc = dwcmshc_adma_write_desc,
1124
-
.voltage_switch = dwcmshc_phy_1_8v_init,
1166
+
.voltage_switch = dwcmshc_phy_init,
1125
1167
.platform_execute_tuning = th1520_execute_tuning,
1126
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};
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