Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-new-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann:
"Two new SoC families are added here, with devicetree files and a
little bit of infrastructure to allow booting:
- Blaize BLZP1600 is an AI chip using custom GSP (Graph Streaming
Processor) cores for computation, and two small Cortex-A53 cores
that run the operating system.
- SpacemiT K1 is a 64-bit RISC-V chip, using eight custom RVA22
compatible CPU cores with vector support.
Also marketed at AI applications, it has a much slower NPU compared
to BLZP1600, but in turn focuses on the CPU performance"
* tag 'soc-new-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
riscv: dts: spacemit: move aliases to board dts
riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
riscv: defconfig: enable SpacemiT SoC
riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
riscv: dts: add initial SpacemiT K1 SoC device tree
riscv: add SpacemiT SoC family Kconfig support
dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
dt-bindings: timer: Add SpacemiT K1 CLINT
dt-bindings: riscv: add SpacemiT K1 bindings
dt-bindings: riscv: Add SpacemiT X60 compatibles
MAINTAINERS: setup support for SpacemiT SoC tree
MAINTAINER: Add entry for Blaize SoC
arm64: defconfig: Enable Blaize BLZP1600 platform
arm64: dts: Add initial support for Blaize BLZP1600 CB2
arm64: Add Blaize BLZP1600 SoC family
dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
dt-bindings: Add Blaize vendor prefix
+921
-1
+40
Documentation/devicetree/bindings/arm/blaize.yaml
+40
Documentation/devicetree/bindings/arm/blaize.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/blaize.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Blaize Platforms
8
+
9
+
maintainers:
10
+
- James Cowgill <james.cowgill@blaize.com>
11
+
- Matt Redfearn <matt.redfearn@blaize.com>
12
+
- Neil Jones <neil.jones@blaize.com>
13
+
- Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
14
+
15
+
description: |
16
+
Blaize Platforms using SoCs designed by Blaize Inc.
17
+
18
+
The products based on the BLZP1600 SoC:
19
+
20
+
- BLZP1600-SoM: SoM (System on Module)
21
+
- BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
22
+
23
+
BLZP1600 SoC integrates a dual core ARM Cortex A53 cluster
24
+
and a Blaize Graph Streaming Processor for AI and ML workloads,
25
+
plus a suite of connectivity and other peripherals.
26
+
27
+
properties:
28
+
$nodename:
29
+
const: '/'
30
+
compatible:
31
+
oneOf:
32
+
- description: Blaize BLZP1600 based boards
33
+
items:
34
+
- enum:
35
+
- blaize,blzp1600-cb2
36
+
- const: blaize,blzp1600
37
+
38
+
additionalProperties: true
39
+
40
+
...
+1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+1
Documentation/devicetree/bindings/riscv/cpus.yaml
+1
Documentation/devicetree/bindings/riscv/cpus.yaml
+28
Documentation/devicetree/bindings/riscv/spacemit.yaml
+28
Documentation/devicetree/bindings/riscv/spacemit.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/riscv/spacemit.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SpacemiT SoC-based boards
8
+
9
+
maintainers:
10
+
- Yangyu Chen <cyy@cyyself.name>
11
+
- Yixun Lan <dlan@gentoo.org>
12
+
13
+
description:
14
+
SpacemiT SoC-based boards
15
+
16
+
properties:
17
+
$nodename:
18
+
const: '/'
19
+
compatible:
20
+
oneOf:
21
+
- items:
22
+
- enum:
23
+
- bananapi,bpi-f3
24
+
- const: spacemit,k1
25
+
26
+
additionalProperties: true
27
+
28
+
...
+3
-1
Documentation/devicetree/bindings/serial/8250.yaml
+3
-1
Documentation/devicetree/bindings/serial/8250.yaml
+1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
+1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+18
MAINTAINERS
+18
MAINTAINERS
···
2309
2309
F: drivers/clk/clk-bm1880.c
2310
2310
F: drivers/pinctrl/pinctrl-bm1880.c
2311
2311
2312
+
ARM/BLAIZE ARCHITECTURE
2313
+
M: James Cowgill <james.cowgill@blaize.com>
2314
+
M: Matt Redfearn <matt.redfearn@blaize.com>
2315
+
M: Neil Jones <neil.jones@blaize.com>
2316
+
M: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
2317
+
S: Maintained
2318
+
F: Documentation/devicetree/bindings/arm/blaize.yaml
2319
+
F: arch/arm64/boot/dts/blaize/
2320
+
2312
2321
ARM/CALXEDA HIGHBANK ARCHITECTURE
2313
2322
M: Andre Przywara <andre.przywara@arm.com>
2314
2323
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
···
20282
20273
F: drivers/perf/riscv_pmu.c
20283
20274
F: drivers/perf/riscv_pmu_legacy.c
20284
20275
F: drivers/perf/riscv_pmu_sbi.c
20276
+
20277
+
RISC-V SPACEMIT SoC Support
20278
+
M: Yixun Lan <dlan@gentoo.org>
20279
+
L: linux-riscv@lists.infradead.org
20280
+
S: Maintained
20281
+
T: git https://github.com/spacemit-com/linux
20282
+
F: arch/riscv/boot/dts/spacemit/
20283
+
N: spacemit
20284
+
K: spacemit
20285
20285
20286
20286
RISC-V THEAD SoC SUPPORT
20287
20287
M: Drew Fustini <drew@pdp7.com>
+5
arch/arm64/Kconfig.platforms
+5
arch/arm64/Kconfig.platforms
···
101
101
help
102
102
This enables support for the Bitmain SoC Family.
103
103
104
+
config ARCH_BLAIZE
105
+
bool "Blaize SoC Platforms"
106
+
help
107
+
This enables support for the Blaize SoC family
108
+
104
109
config ARCH_EXYNOS
105
110
bool "Samsung Exynos SoC family"
106
111
select COMMON_CLK_SAMSUNG
+1
arch/arm64/boot/dts/Makefile
+1
arch/arm64/boot/dts/Makefile
+2
arch/arm64/boot/dts/blaize/Makefile
+2
arch/arm64/boot/dts/blaize/Makefile
+83
arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
+83
arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2024 Blaize, Inc. All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "blaize-blzp1600-som.dtsi"
9
+
10
+
/ {
11
+
model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
12
+
13
+
compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
14
+
15
+
aliases {
16
+
serial0 = &uart0;
17
+
};
18
+
19
+
chosen {
20
+
stdout-path = "serial0:115200";
21
+
};
22
+
};
23
+
24
+
&i2c0 {
25
+
clock-frequency = <100000>;
26
+
status = "okay";
27
+
};
28
+
29
+
&i2c1 {
30
+
clock-frequency = <100000>;
31
+
status = "okay";
32
+
};
33
+
34
+
&i2c3 {
35
+
clock-frequency = <100000>;
36
+
status = "okay";
37
+
38
+
gpio_expander: gpio@74 {
39
+
compatible = "ti,tca9539";
40
+
reg = <0x74>;
41
+
gpio-controller;
42
+
#gpio-cells = <2>;
43
+
gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
44
+
"RSP_PIN_11", /* GPIO_1 */
45
+
"RSP_PIN_13", /* GPIO_2 */
46
+
"RSP_PIN_15", /* GPIO_3 */
47
+
"RSP_PIN_27", /* GPIO_4 */
48
+
"RSP_PIN_29", /* GPIO_5 */
49
+
"RSP_PIN_31", /* GPIO_6 */
50
+
"RSP_PIN_33", /* GPIO_7 */
51
+
"RSP_PIN_37", /* GPIO_8 */
52
+
"RSP_PIN_16", /* GPIO_9 */
53
+
"RSP_PIN_18", /* GPIO_10 */
54
+
"RSP_PIN_22", /* GPIO_11 */
55
+
"RSP_PIN_28", /* GPIO_12 */
56
+
"RSP_PIN_32", /* GPIO_13 */
57
+
"RSP_PIN_36", /* GPIO_14 */
58
+
"TP31"; /* GPIO_15 */
59
+
};
60
+
61
+
gpio_expander_m2: gpio@75 {
62
+
compatible = "ti,tca9539";
63
+
reg = <0x75>;
64
+
gpio-controller;
65
+
#gpio-cells = <2>;
66
+
gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
67
+
"M2_W_DIS2_N", /* GPIO_1 */
68
+
"M2_UART_WAKE_N", /* GPIO_2 */
69
+
"M2_COEX3", /* GPIO_3 */
70
+
"M2_COEX_RXD", /* GPIO_4 */
71
+
"M2_COEX_TXD", /* GPIO_5 */
72
+
"M2_VENDOR_PIN40", /* GPIO_6 */
73
+
"M2_VENDOR_PIN42", /* GPIO_7 */
74
+
"M2_VENDOR_PIN38", /* GPIO_8 */
75
+
"M2_SDIO_RST_N", /* GPIO_9 */
76
+
"M2_SDIO_WAKE_N", /* GPIO_10 */
77
+
"M2_PETN1", /* GPIO_11 */
78
+
"M2_PERP1", /* GPIO_12 */
79
+
"M2_PERN1", /* GPIO_13 */
80
+
"UIM_SWP", /* GPIO_14 */
81
+
"UART1_TO_RSP"; /* GPIO_15 */
82
+
};
83
+
};
+23
arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
+23
arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2024 Blaize, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include "blaize-blzp1600.dtsi"
7
+
8
+
/ {
9
+
memory@0 {
10
+
device_type = "memory";
11
+
reg = <0x0 0x0 0x1 0x0>;
12
+
};
13
+
};
14
+
15
+
/* i2c4 bus is available only on the SoM, not on the board */
16
+
&i2c4 {
17
+
clock-frequency = <100000>;
18
+
status = "okay";
19
+
};
20
+
21
+
&uart0 {
22
+
status = "okay";
23
+
};
+205
arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
+205
arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2024 Blaize, Inc. All rights reserved.
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include <dt-bindings/gpio/gpio.h>
9
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
10
+
11
+
/ {
12
+
interrupt-parent = <&gic>;
13
+
#address-cells = <2>;
14
+
#size-cells = <2>;
15
+
16
+
cpus {
17
+
#address-cells = <2>;
18
+
#size-cells = <0>;
19
+
20
+
cpu0: cpu@0 {
21
+
compatible = "arm,cortex-a53";
22
+
reg = <0x0 0x0>;
23
+
device_type = "cpu";
24
+
enable-method = "psci";
25
+
next-level-cache = <&l2>;
26
+
};
27
+
28
+
cpu1: cpu@1 {
29
+
compatible = "arm,cortex-a53";
30
+
reg = <0x0 0x1>;
31
+
device_type = "cpu";
32
+
enable-method = "psci";
33
+
next-level-cache = <&l2>;
34
+
};
35
+
36
+
l2: l2-cache0 {
37
+
compatible = "cache";
38
+
cache-level = <2>;
39
+
cache-unified;
40
+
};
41
+
};
42
+
43
+
firmware {
44
+
scmi {
45
+
compatible = "arm,scmi-smc";
46
+
arm,smc-id = <0x82002000>;
47
+
#address-cells = <1>;
48
+
#size-cells = <0>;
49
+
50
+
shmem = <&scmi0_shm>;
51
+
52
+
scmi_clk: protocol@14 {
53
+
reg = <0x14>;
54
+
#clock-cells = <1>;
55
+
};
56
+
57
+
scmi_rst: protocol@16 {
58
+
reg = <0x16>;
59
+
#reset-cells = <1>;
60
+
};
61
+
};
62
+
};
63
+
64
+
pmu {
65
+
compatible = "arm,cortex-a53-pmu";
66
+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
67
+
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
68
+
interrupt-affinity = <&cpu0>, <&cpu1>;
69
+
};
70
+
71
+
psci {
72
+
compatible = "arm,psci-1.0", "arm,psci-0.2";
73
+
method = "smc";
74
+
};
75
+
76
+
reserved-memory {
77
+
#address-cells = <2>;
78
+
#size-cells = <2>;
79
+
ranges;
80
+
81
+
/* SCMI reserved buffer space on DDR space */
82
+
scmi0_shm: scmi-shmem@800 {
83
+
compatible = "arm,scmi-shmem";
84
+
reg = <0x0 0x800 0x0 0x80>;
85
+
};
86
+
};
87
+
88
+
timer {
89
+
compatible = "arm,armv8-timer";
90
+
interrupts = /* Physical Secure PPI */
91
+
<GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
92
+
IRQ_TYPE_LEVEL_LOW)>,
93
+
/* Physical Non-Secure PPI */
94
+
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
95
+
IRQ_TYPE_LEVEL_LOW)>,
96
+
/* Hypervisor PPI */
97
+
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
98
+
IRQ_TYPE_LEVEL_LOW)>,
99
+
/* Virtual PPI */
100
+
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
101
+
IRQ_TYPE_LEVEL_LOW)>;
102
+
};
103
+
104
+
soc@200000000 {
105
+
compatible = "simple-bus";
106
+
#address-cells = <1>;
107
+
#size-cells = <1>;
108
+
ranges = <0x0 0x2 0x0 0x850000>;
109
+
110
+
gic: interrupt-controller@410000 {
111
+
compatible = "arm,gic-400";
112
+
reg = <0x410000 0x20000>,
113
+
<0x420000 0x20000>,
114
+
<0x440000 0x20000>,
115
+
<0x460000 0x20000>;
116
+
#interrupt-cells = <3>;
117
+
#address-cells = <0>;
118
+
interrupt-controller;
119
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
120
+
IRQ_TYPE_LEVEL_LOW)>;
121
+
};
122
+
123
+
uart0: serial@4d0000 {
124
+
compatible = "ns16550a";
125
+
reg = <0x4d0000 0x1000>;
126
+
clocks = <&scmi_clk 59>;
127
+
resets = <&scmi_rst 59>;
128
+
reg-shift = <2>;
129
+
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
130
+
status = "disabled";
131
+
};
132
+
133
+
uart1: serial@4e0000 {
134
+
compatible = "ns16550a";
135
+
reg = <0x4e0000 0x1000>;
136
+
clocks = <&scmi_clk 60>;
137
+
resets = <&scmi_rst 60>;
138
+
reg-shift = <2>;
139
+
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
140
+
status = "disabled";
141
+
};
142
+
143
+
i2c0: i2c@4f0000 {
144
+
compatible = "snps,designware-i2c";
145
+
reg = <0x4f0000 0x1000>;
146
+
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
147
+
clocks = <&scmi_clk 54>;
148
+
resets = <&scmi_rst 54>;
149
+
#address-cells = <1>;
150
+
#size-cells = <0>;
151
+
status = "disabled";
152
+
};
153
+
154
+
i2c1: i2c@500000 {
155
+
compatible = "snps,designware-i2c";
156
+
reg = <0x500000 0x1000>;
157
+
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
158
+
clocks = <&scmi_clk 55>;
159
+
resets = <&scmi_rst 55>;
160
+
#address-cells = <1>;
161
+
#size-cells = <0>;
162
+
status = "disabled";
163
+
};
164
+
165
+
i2c2: i2c@510000 {
166
+
compatible = "snps,designware-i2c";
167
+
reg = <0x510000 0x1000>;
168
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
169
+
clocks = <&scmi_clk 56>;
170
+
resets = <&scmi_rst 56>;
171
+
#address-cells = <1>;
172
+
#size-cells = <0>;
173
+
status = "disabled";
174
+
};
175
+
176
+
i2c3: i2c@520000 {
177
+
compatible = "snps,designware-i2c";
178
+
reg = <0x520000 0x1000>;
179
+
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
180
+
clocks = <&scmi_clk 57>;
181
+
resets = <&scmi_rst 57>;
182
+
#address-cells = <1>;
183
+
#size-cells = <0>;
184
+
status = "disabled";
185
+
};
186
+
187
+
i2c4: i2c@530000 {
188
+
compatible = "snps,designware-i2c";
189
+
reg = <0x530000 0x1000>;
190
+
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
191
+
clocks = <&scmi_clk 58>;
192
+
resets = <&scmi_rst 58>;
193
+
#address-cells = <1>;
194
+
#size-cells = <0>;
195
+
status = "disabled";
196
+
};
197
+
198
+
arm_cc712: crypto@550000 {
199
+
compatible = "arm,cryptocell-712-ree";
200
+
reg = <0x550000 0x1000>;
201
+
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
202
+
clocks = <&scmi_clk 7>;
203
+
};
204
+
};
205
+
};
+1
arch/arm64/configs/defconfig
+1
arch/arm64/configs/defconfig
+5
arch/riscv/Kconfig.socs
+5
arch/riscv/Kconfig.socs
+1
arch/riscv/boot/dts/Makefile
+1
arch/riscv/boot/dts/Makefile
+2
arch/riscv/boot/dts/spacemit/Makefile
+2
arch/riscv/boot/dts/spacemit/Makefile
+26
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+26
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR MIT
2
+
/*
3
+
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
4
+
*/
5
+
6
+
#include "k1.dtsi"
7
+
#include "k1-pinctrl.dtsi"
8
+
9
+
/ {
10
+
model = "Banana Pi BPI-F3";
11
+
compatible = "bananapi,bpi-f3", "spacemit,k1";
12
+
13
+
aliases {
14
+
serial0 = &uart0;
15
+
};
16
+
17
+
chosen {
18
+
stdout-path = "serial0";
19
+
};
20
+
};
21
+
22
+
&uart0 {
23
+
pinctrl-names = "default";
24
+
pinctrl-0 = <&uart0_2_cfg>;
25
+
status = "okay";
26
+
};
+20
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+20
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR MIT
2
+
/*
3
+
* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
4
+
*/
5
+
6
+
#include <dt-bindings/gpio/gpio.h>
7
+
8
+
#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
9
+
10
+
&pinctrl {
11
+
uart0_2_cfg: uart0-2-cfg {
12
+
uart0-2-pins {
13
+
pinmux = <K1_PADCONF(68, 2)>,
14
+
<K1_PADCONF(69, 2)>;
15
+
16
+
bias-pull-up = <0>;
17
+
drive-strength = <32>;
18
+
};
19
+
};
20
+
};
+452
arch/riscv/boot/dts/spacemit/k1.dtsi
+452
arch/riscv/boot/dts/spacemit/k1.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR MIT
2
+
/*
3
+
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
4
+
*/
5
+
6
+
/dts-v1/;
7
+
/ {
8
+
#address-cells = <2>;
9
+
#size-cells = <2>;
10
+
model = "SpacemiT K1";
11
+
compatible = "spacemit,k1";
12
+
13
+
cpus {
14
+
#address-cells = <1>;
15
+
#size-cells = <0>;
16
+
timebase-frequency = <24000000>;
17
+
18
+
cpu-map {
19
+
cluster0 {
20
+
core0 {
21
+
cpu = <&cpu_0>;
22
+
};
23
+
core1 {
24
+
cpu = <&cpu_1>;
25
+
};
26
+
core2 {
27
+
cpu = <&cpu_2>;
28
+
};
29
+
core3 {
30
+
cpu = <&cpu_3>;
31
+
};
32
+
};
33
+
34
+
cluster1 {
35
+
core0 {
36
+
cpu = <&cpu_4>;
37
+
};
38
+
core1 {
39
+
cpu = <&cpu_5>;
40
+
};
41
+
core2 {
42
+
cpu = <&cpu_6>;
43
+
};
44
+
core3 {
45
+
cpu = <&cpu_7>;
46
+
};
47
+
};
48
+
};
49
+
50
+
cpu_0: cpu@0 {
51
+
compatible = "spacemit,x60", "riscv";
52
+
device_type = "cpu";
53
+
reg = <0>;
54
+
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
55
+
riscv,isa-base = "rv64i";
56
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
57
+
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
58
+
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
59
+
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
60
+
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
61
+
riscv,cbom-block-size = <64>;
62
+
riscv,cbop-block-size = <64>;
63
+
riscv,cboz-block-size = <64>;
64
+
i-cache-block-size = <64>;
65
+
i-cache-size = <32768>;
66
+
i-cache-sets = <128>;
67
+
d-cache-block-size = <64>;
68
+
d-cache-size = <32768>;
69
+
d-cache-sets = <128>;
70
+
next-level-cache = <&cluster0_l2_cache>;
71
+
mmu-type = "riscv,sv39";
72
+
73
+
cpu0_intc: interrupt-controller {
74
+
compatible = "riscv,cpu-intc";
75
+
interrupt-controller;
76
+
#interrupt-cells = <1>;
77
+
};
78
+
};
79
+
80
+
cpu_1: cpu@1 {
81
+
compatible = "spacemit,x60", "riscv";
82
+
device_type = "cpu";
83
+
reg = <1>;
84
+
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
85
+
riscv,isa-base = "rv64i";
86
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
87
+
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
88
+
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
89
+
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
90
+
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
91
+
riscv,cbom-block-size = <64>;
92
+
riscv,cbop-block-size = <64>;
93
+
riscv,cboz-block-size = <64>;
94
+
i-cache-block-size = <64>;
95
+
i-cache-size = <32768>;
96
+
i-cache-sets = <128>;
97
+
d-cache-block-size = <64>;
98
+
d-cache-size = <32768>;
99
+
d-cache-sets = <128>;
100
+
next-level-cache = <&cluster0_l2_cache>;
101
+
mmu-type = "riscv,sv39";
102
+
103
+
cpu1_intc: interrupt-controller {
104
+
compatible = "riscv,cpu-intc";
105
+
interrupt-controller;
106
+
#interrupt-cells = <1>;
107
+
};
108
+
};
109
+
110
+
cpu_2: cpu@2 {
111
+
compatible = "spacemit,x60", "riscv";
112
+
device_type = "cpu";
113
+
reg = <2>;
114
+
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
115
+
riscv,isa-base = "rv64i";
116
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
117
+
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
118
+
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
119
+
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
120
+
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
121
+
riscv,cbom-block-size = <64>;
122
+
riscv,cbop-block-size = <64>;
123
+
riscv,cboz-block-size = <64>;
124
+
i-cache-block-size = <64>;
125
+
i-cache-size = <32768>;
126
+
i-cache-sets = <128>;
127
+
d-cache-block-size = <64>;
128
+
d-cache-size = <32768>;
129
+
d-cache-sets = <128>;
130
+
next-level-cache = <&cluster0_l2_cache>;
131
+
mmu-type = "riscv,sv39";
132
+
133
+
cpu2_intc: interrupt-controller {
134
+
compatible = "riscv,cpu-intc";
135
+
interrupt-controller;
136
+
#interrupt-cells = <1>;
137
+
};
138
+
};
139
+
140
+
cpu_3: cpu@3 {
141
+
compatible = "spacemit,x60", "riscv";
142
+
device_type = "cpu";
143
+
reg = <3>;
144
+
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
145
+
riscv,isa-base = "rv64i";
146
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
147
+
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
148
+
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
149
+
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
150
+
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
151
+
riscv,cbom-block-size = <64>;
152
+
riscv,cbop-block-size = <64>;
153
+
riscv,cboz-block-size = <64>;
154
+
i-cache-block-size = <64>;
155
+
i-cache-size = <32768>;
156
+
i-cache-sets = <128>;
157
+
d-cache-block-size = <64>;
158
+
d-cache-size = <32768>;
159
+
d-cache-sets = <128>;
160
+
next-level-cache = <&cluster0_l2_cache>;
161
+
mmu-type = "riscv,sv39";
162
+
163
+
cpu3_intc: interrupt-controller {
164
+
compatible = "riscv,cpu-intc";
165
+
interrupt-controller;
166
+
#interrupt-cells = <1>;
167
+
};
168
+
};
169
+
170
+
cpu_4: cpu@4 {
171
+
compatible = "spacemit,x60", "riscv";
172
+
device_type = "cpu";
173
+
reg = <4>;
174
+
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
175
+
riscv,isa-base = "rv64i";
176
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
177
+
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
178
+
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
179
+
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
180
+
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
181
+
riscv,cbom-block-size = <64>;
182
+
riscv,cbop-block-size = <64>;
183
+
riscv,cboz-block-size = <64>;
184
+
i-cache-block-size = <64>;
185
+
i-cache-size = <32768>;
186
+
i-cache-sets = <128>;
187
+
d-cache-block-size = <64>;
188
+
d-cache-size = <32768>;
189
+
d-cache-sets = <128>;
190
+
next-level-cache = <&cluster1_l2_cache>;
191
+
mmu-type = "riscv,sv39";
192
+
193
+
cpu4_intc: interrupt-controller {
194
+
compatible = "riscv,cpu-intc";
195
+
interrupt-controller;
196
+
#interrupt-cells = <1>;
197
+
};
198
+
};
199
+
200
+
cpu_5: cpu@5 {
201
+
compatible = "spacemit,x60", "riscv";
202
+
device_type = "cpu";
203
+
reg = <5>;
204
+
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
205
+
riscv,isa-base = "rv64i";
206
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
207
+
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
208
+
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
209
+
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
210
+
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
211
+
riscv,cbom-block-size = <64>;
212
+
riscv,cbop-block-size = <64>;
213
+
riscv,cboz-block-size = <64>;
214
+
i-cache-block-size = <64>;
215
+
i-cache-size = <32768>;
216
+
i-cache-sets = <128>;
217
+
d-cache-block-size = <64>;
218
+
d-cache-size = <32768>;
219
+
d-cache-sets = <128>;
220
+
next-level-cache = <&cluster1_l2_cache>;
221
+
mmu-type = "riscv,sv39";
222
+
223
+
cpu5_intc: interrupt-controller {
224
+
compatible = "riscv,cpu-intc";
225
+
interrupt-controller;
226
+
#interrupt-cells = <1>;
227
+
};
228
+
};
229
+
230
+
cpu_6: cpu@6 {
231
+
compatible = "spacemit,x60", "riscv";
232
+
device_type = "cpu";
233
+
reg = <6>;
234
+
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
235
+
riscv,isa-base = "rv64i";
236
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
237
+
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
238
+
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
239
+
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
240
+
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
241
+
riscv,cbom-block-size = <64>;
242
+
riscv,cbop-block-size = <64>;
243
+
riscv,cboz-block-size = <64>;
244
+
i-cache-block-size = <64>;
245
+
i-cache-size = <32768>;
246
+
i-cache-sets = <128>;
247
+
d-cache-block-size = <64>;
248
+
d-cache-size = <32768>;
249
+
d-cache-sets = <128>;
250
+
next-level-cache = <&cluster1_l2_cache>;
251
+
mmu-type = "riscv,sv39";
252
+
253
+
cpu6_intc: interrupt-controller {
254
+
compatible = "riscv,cpu-intc";
255
+
interrupt-controller;
256
+
#interrupt-cells = <1>;
257
+
};
258
+
};
259
+
260
+
cpu_7: cpu@7 {
261
+
compatible = "spacemit,x60", "riscv";
262
+
device_type = "cpu";
263
+
reg = <7>;
264
+
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
265
+
riscv,isa-base = "rv64i";
266
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
267
+
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
268
+
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
269
+
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
270
+
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
271
+
riscv,cbom-block-size = <64>;
272
+
riscv,cbop-block-size = <64>;
273
+
riscv,cboz-block-size = <64>;
274
+
i-cache-block-size = <64>;
275
+
i-cache-size = <32768>;
276
+
i-cache-sets = <128>;
277
+
d-cache-block-size = <64>;
278
+
d-cache-size = <32768>;
279
+
d-cache-sets = <128>;
280
+
next-level-cache = <&cluster1_l2_cache>;
281
+
mmu-type = "riscv,sv39";
282
+
283
+
cpu7_intc: interrupt-controller {
284
+
compatible = "riscv,cpu-intc";
285
+
interrupt-controller;
286
+
#interrupt-cells = <1>;
287
+
};
288
+
};
289
+
290
+
cluster0_l2_cache: l2-cache0 {
291
+
compatible = "cache";
292
+
cache-block-size = <64>;
293
+
cache-level = <2>;
294
+
cache-size = <524288>;
295
+
cache-sets = <512>;
296
+
cache-unified;
297
+
};
298
+
299
+
cluster1_l2_cache: l2-cache1 {
300
+
compatible = "cache";
301
+
cache-block-size = <64>;
302
+
cache-level = <2>;
303
+
cache-size = <524288>;
304
+
cache-sets = <512>;
305
+
cache-unified;
306
+
};
307
+
};
308
+
309
+
soc {
310
+
compatible = "simple-bus";
311
+
interrupt-parent = <&plic>;
312
+
#address-cells = <2>;
313
+
#size-cells = <2>;
314
+
dma-noncoherent;
315
+
ranges;
316
+
317
+
uart0: serial@d4017000 {
318
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
319
+
reg = <0x0 0xd4017000 0x0 0x100>;
320
+
interrupts = <42>;
321
+
clock-frequency = <14857000>;
322
+
reg-shift = <2>;
323
+
reg-io-width = <4>;
324
+
status = "disabled";
325
+
};
326
+
327
+
uart2: serial@d4017100 {
328
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
329
+
reg = <0x0 0xd4017100 0x0 0x100>;
330
+
interrupts = <44>;
331
+
clock-frequency = <14857000>;
332
+
reg-shift = <2>;
333
+
reg-io-width = <4>;
334
+
status = "disabled";
335
+
};
336
+
337
+
uart3: serial@d4017200 {
338
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
339
+
reg = <0x0 0xd4017200 0x0 0x100>;
340
+
interrupts = <45>;
341
+
clock-frequency = <14857000>;
342
+
reg-shift = <2>;
343
+
reg-io-width = <4>;
344
+
status = "disabled";
345
+
};
346
+
347
+
uart4: serial@d4017300 {
348
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
349
+
reg = <0x0 0xd4017300 0x0 0x100>;
350
+
interrupts = <46>;
351
+
clock-frequency = <14857000>;
352
+
reg-shift = <2>;
353
+
reg-io-width = <4>;
354
+
status = "disabled";
355
+
};
356
+
357
+
uart5: serial@d4017400 {
358
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
359
+
reg = <0x0 0xd4017400 0x0 0x100>;
360
+
interrupts = <47>;
361
+
clock-frequency = <14857000>;
362
+
reg-shift = <2>;
363
+
reg-io-width = <4>;
364
+
status = "disabled";
365
+
};
366
+
367
+
uart6: serial@d4017500 {
368
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
369
+
reg = <0x0 0xd4017500 0x0 0x100>;
370
+
interrupts = <48>;
371
+
clock-frequency = <14857000>;
372
+
reg-shift = <2>;
373
+
reg-io-width = <4>;
374
+
status = "disabled";
375
+
};
376
+
377
+
uart7: serial@d4017600 {
378
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
379
+
reg = <0x0 0xd4017600 0x0 0x100>;
380
+
interrupts = <49>;
381
+
clock-frequency = <14857000>;
382
+
reg-shift = <2>;
383
+
reg-io-width = <4>;
384
+
status = "disabled";
385
+
};
386
+
387
+
uart8: serial@d4017700 {
388
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
389
+
reg = <0x0 0xd4017700 0x0 0x100>;
390
+
interrupts = <50>;
391
+
clock-frequency = <14857000>;
392
+
reg-shift = <2>;
393
+
reg-io-width = <4>;
394
+
status = "disabled";
395
+
};
396
+
397
+
uart9: serial@d4017800 {
398
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
399
+
reg = <0x0 0xd4017800 0x0 0x100>;
400
+
interrupts = <51>;
401
+
clock-frequency = <14857000>;
402
+
reg-shift = <2>;
403
+
reg-io-width = <4>;
404
+
status = "disabled";
405
+
};
406
+
407
+
pinctrl: pinctrl@d401e000 {
408
+
compatible = "spacemit,k1-pinctrl";
409
+
reg = <0x0 0xd401e000 0x0 0x400>;
410
+
};
411
+
412
+
plic: interrupt-controller@e0000000 {
413
+
compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
414
+
reg = <0x0 0xe0000000 0x0 0x4000000>;
415
+
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
416
+
<&cpu1_intc 11>, <&cpu1_intc 9>,
417
+
<&cpu2_intc 11>, <&cpu2_intc 9>,
418
+
<&cpu3_intc 11>, <&cpu3_intc 9>,
419
+
<&cpu4_intc 11>, <&cpu4_intc 9>,
420
+
<&cpu5_intc 11>, <&cpu5_intc 9>,
421
+
<&cpu6_intc 11>, <&cpu6_intc 9>,
422
+
<&cpu7_intc 11>, <&cpu7_intc 9>;
423
+
interrupt-controller;
424
+
#address-cells = <0>;
425
+
#interrupt-cells = <1>;
426
+
riscv,ndev = <159>;
427
+
};
428
+
429
+
clint: timer@e4000000 {
430
+
compatible = "spacemit,k1-clint", "sifive,clint0";
431
+
reg = <0x0 0xe4000000 0x0 0x10000>;
432
+
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
433
+
<&cpu1_intc 3>, <&cpu1_intc 7>,
434
+
<&cpu2_intc 3>, <&cpu2_intc 7>,
435
+
<&cpu3_intc 3>, <&cpu3_intc 7>,
436
+
<&cpu4_intc 3>, <&cpu4_intc 7>,
437
+
<&cpu5_intc 3>, <&cpu5_intc 7>,
438
+
<&cpu6_intc 3>, <&cpu6_intc 7>,
439
+
<&cpu7_intc 3>, <&cpu7_intc 7>;
440
+
};
441
+
442
+
sec_uart1: serial@f0612000 {
443
+
compatible = "spacemit,k1-uart", "intel,xscale-uart";
444
+
reg = <0x0 0xf0612000 0x0 0x100>;
445
+
interrupts = <43>;
446
+
clock-frequency = <14857000>;
447
+
reg-shift = <2>;
448
+
reg-io-width = <4>;
449
+
status = "reserved"; /* for TEE usage */
450
+
};
451
+
};
452
+
};