arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node

Move dma-controller node under simple-bus node to allow bus node specific
property able to be properly defined. This is require to fulfill Agilex5
bus limitation that is limited to 40-addressable-bit.

Update the compatible string for the DMA controller nodes in the Agilex5
device tree from the generic "snps,axi-dma-1.01a" to the platform-specific
"altr,agilex5-axi-dma". Add fallback capability to ensure driver is able
to initialize properly.

This change enables the use of platform-specific features and constraints
in the driver, such as setting a 40-bit DMA addressable mask through
dma-ranges, which is required for Agilex5. It also aligns with the updated
device tree bindings and driver support for this compatible string.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

authored by

Khairul Anuar Romli and committed by

Dinh Nguyen 3 months ago 4e6e93df e0f489a5

+43 -35

1 changed file

expand all

arch

arm64

boot

dts

intel

socfpga_agilex5.dtsi

+43 -35

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

··· 324 324 #size-cells = <1>; 325 325 }; 326 326 327 - dmac0: dma-controller@10db0000 { 328 - compatible = "snps,axi-dma-1.01a"; 329 - reg = <0x10db0000 0x500>; 330 - clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 331 - <&clkmgr AGILEX5_L4_MP_CLK>; 332 - clock-names = "core-clk", "cfgr-clk"; 333 - interrupt-parent = <&intc>; 334 - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 335 - #dma-cells = <1>; 336 - dma-channels = <4>; 337 - snps,dma-masters = <1>; 338 - snps,data-width = <2>; 339 - snps,block-size = <32767 32767 32767 32767>; 340 - snps,priority = <0 1 2 3>; 341 - snps,axi-max-burst-len = <8>; 342 - iommus = <&smmu 8>; 343 - dma-coherent; 344 - }; 327 + dma: dma-bus@10db0000 { 328 + compatible = "simple-bus"; 329 + #address-cells = <1>; 330 + #size-cells = <2>; 331 + ranges = <0x00 0x10db0000 0x00 0x20000>; 332 + dma-ranges = <0x00 0x00 0x100 0x00>; 345 333 346 - dmac1: dma-controller@10dc0000 { 347 - compatible = "snps,axi-dma-1.01a"; 348 - reg = <0x10dc0000 0x500>; 349 - clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 350 - <&clkmgr AGILEX5_L4_MP_CLK>; 351 - clock-names = "core-clk", "cfgr-clk"; 352 - interrupt-parent = <&intc>; 353 - interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 354 - #dma-cells = <1>; 355 - dma-channels = <4>; 356 - snps,dma-masters = <1>; 357 - snps,data-width = <2>; 358 - snps,block-size = <32767 32767 32767 32767>; 359 - snps,priority = <0 1 2 3>; 360 - snps,axi-max-burst-len = <8>; 361 - iommus = <&smmu 9>; 362 - dma-coherent; 334 + dmac0: dma-controller@0 { 335 + compatible = "altr,agilex5-axi-dma", 336 + "snps,axi-dma-1.01a"; 337 + reg = <0x0 0x0 0x500>; 338 + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 339 + <&clkmgr AGILEX5_L4_MP_CLK>; 340 + clock-names = "core-clk", "cfgr-clk"; 341 + interrupt-parent = <&intc>; 342 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 343 + #dma-cells = <1>; 344 + dma-channels = <4>; 345 + snps,dma-masters = <1>; 346 + snps,data-width = <2>; 347 + snps,block-size = <32767 32767 32767 32767>; 348 + snps,priority = <0 1 2 3>; 349 + snps,axi-max-burst-len = <8>; 350 + iommus = <&smmu 8>; 351 + }; 352 + 353 + dmac1: dma-controller@10000 { 354 + compatible = "altr,agilex5-axi-dma", 355 + "snps,axi-dma-1.01a"; 356 + reg = <0x10000 0x0 0x500>; 357 + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 358 + <&clkmgr AGILEX5_L4_MP_CLK>; 359 + clock-names = "core-clk", "cfgr-clk"; 360 + interrupt-parent = <&intc>; 361 + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 362 + #dma-cells = <1>; 363 + dma-channels = <4>; 364 + snps,dma-masters = <1>; 365 + snps,data-width = <2>; 366 + snps,block-size = <32767 32767 32767 32767>; 367 + snps,priority = <0 1 2 3>; 368 + snps,axi-max-burst-len = <8>; 369 + iommus = <&smmu 9>; 370 + }; 363 371 }; 364 372 365 373 rst: rstmgr@10d11000 {

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