Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: host1x: Complete stream ID entry tables
These tables contain fixed values to program the host1x hardware
with, so fill in the missing entries.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240425050238.2943404-3-cyndis@kapsi.fi
authored by
Mikko Perttunen
and committed by
Thierry Reding
4e90b03a
e436a408
+72
-78
+72
-78
drivers/gpu/host1x/dev.c
+72
-78
drivers/gpu/host1x/dev.c
···
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};
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static const struct host1x_sid_entry tegra186_sid_table[] = {
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-
{
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-
/* VIC */
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.base = 0x1af0,
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-
.offset = 0x30,
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-
.limit = 0x34
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-
},
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-
{
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/* NVDEC */
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.base = 0x1b00,
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-
.offset = 0x30,
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-
.limit = 0x34
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-
},
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+
{ /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 },
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+
{ /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 },
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+
{ /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 },
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+
{ /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 },
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+
{ /* ISP */ .base = 0x1ae8, .offset = 0x50, .limit = 0x50 },
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+
{ /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 },
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+
{ /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 },
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+
{ /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 },
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+
{ /* VI 0 */ .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 },
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+
{ /* VI 1 */ .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 },
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+
{ /* VI 2 */ .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 },
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+
{ /* VI 3 */ .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 },
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+
{ /* VI 4 */ .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 },
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+
{ /* VI 5 */ .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 },
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+
{ /* VI 6 */ .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 },
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+
{ /* VI 7 */ .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 },
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+
{ /* VI 8 */ .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 },
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+
{ /* VI 9 */ .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 },
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+
{ /* VI 10 */ .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 },
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+
{ /* VI 11 */ .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 },
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};
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static const struct host1x_info host1x06_info = {
···
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};
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static const struct host1x_sid_entry tegra194_sid_table[] = {
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-
{
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/* VIC */
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.base = 0x1af0,
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-
.offset = 0x30,
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-
.limit = 0x34
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},
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{
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/* NVDEC */
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.base = 0x1b00,
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-
.offset = 0x30,
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-
.limit = 0x34
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},
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{
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/* NVDEC1 */
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.base = 0x1bc0,
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.offset = 0x30,
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-
.limit = 0x34
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},
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+
{ /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 },
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+
{ /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 },
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+
{ /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 },
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+
{ /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 },
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+
{ /* ISP */ .base = 0x1ae8, .offset = 0x800, .limit = 0x800 },
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+
{ /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 },
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+
{ /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 },
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+
{ /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 },
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+
{ /* VI */ .base = 0x1b80, .offset = 0x800, .limit = 0x800 },
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+
{ /* VI_THI */ .base = 0x1b88, .offset = 0x30, .limit = 0x34 },
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+
{ /* ISP_THI */ .base = 0x1b90, .offset = 0x30, .limit = 0x34 },
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+
{ /* PVA0_CLUSTER */ .base = 0x1b98, .offset = 0x0, .limit = 0x0 },
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+
{ /* PVA0_CLUSTER */ .base = 0x1ba0, .offset = 0x0, .limit = 0x0 },
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+
{ /* NVDLA0 */ .base = 0x1ba8, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVDLA1 */ .base = 0x1bb0, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVENC1 */ .base = 0x1bb8, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVDEC1 */ .base = 0x1bc0, .offset = 0x30, .limit = 0x34 },
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};
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static const struct host1x_info host1x07_info = {
···
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* and firmware stream ID in the MMIO path table.
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*/
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static const struct host1x_sid_entry tegra234_sid_table[] = {
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{
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/* SE2 MMIO */
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.base = 0x1658,
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.offset = 0x90,
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.limit = 0x90
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},
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{
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/* SE4 MMIO */
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.base = 0x1660,
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.offset = 0x90,
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.limit = 0x90
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},
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{
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/* SE2 channel */
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.base = 0x1738,
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.offset = 0x90,
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.limit = 0x90
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},
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-
{
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/* SE4 channel */
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.base = 0x1740,
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.offset = 0x90,
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.limit = 0x90
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},
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-
{
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/* VIC channel */
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.base = 0x17b8,
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.offset = 0x30,
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.limit = 0x30
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},
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{
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/* VIC MMIO */
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.base = 0x1688,
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.offset = 0x34,
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.limit = 0x34
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},
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-
{
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/* NVDEC channel */
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.base = 0x17c8,
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.offset = 0x30,
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-
.limit = 0x30,
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-
},
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{
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/* NVDEC MMIO */
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.base = 0x1698,
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.offset = 0x34,
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-
.limit = 0x34,
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-
},
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+
{ /* SE1 MMIO */ .base = 0x1650, .offset = 0x90, .limit = 0x90 },
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{ /* SE1 ch */ .base = 0x1730, .offset = 0x90, .limit = 0x90 },
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{ /* SE2 MMIO */ .base = 0x1658, .offset = 0x90, .limit = 0x90 },
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+
{ /* SE2 ch */ .base = 0x1738, .offset = 0x90, .limit = 0x90 },
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{ /* SE4 MMIO */ .base = 0x1660, .offset = 0x90, .limit = 0x90 },
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{ /* SE4 ch */ .base = 0x1740, .offset = 0x90, .limit = 0x90 },
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{ /* ISP MMIO */ .base = 0x1680, .offset = 0x800, .limit = 0x800 },
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+
{ /* VIC MMIO */ .base = 0x1688, .offset = 0x34, .limit = 0x34 },
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{ /* VIC ch */ .base = 0x17b8, .offset = 0x30, .limit = 0x30 },
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+
{ /* NVENC MMIO */ .base = 0x1690, .offset = 0x34, .limit = 0x34 },
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+
{ /* NVENC ch */ .base = 0x17c0, .offset = 0x30, .limit = 0x30 },
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+
{ /* NVDEC MMIO */ .base = 0x1698, .offset = 0x34, .limit = 0x34 },
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+
{ /* NVDEC ch */ .base = 0x17c8, .offset = 0x30, .limit = 0x30 },
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+
{ /* NVJPG MMIO */ .base = 0x16a0, .offset = 0x34, .limit = 0x34 },
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+
{ /* NVJPG ch */ .base = 0x17d0, .offset = 0x30, .limit = 0x30 },
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+
{ /* TSEC MMIO */ .base = 0x16a8, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVJPG1 MMIO */ .base = 0x16b0, .offset = 0x34, .limit = 0x34 },
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+
{ /* NVJPG1 ch */ .base = 0x17a8, .offset = 0x30, .limit = 0x30 },
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+
{ /* VI MMIO */ .base = 0x16b8, .offset = 0x800, .limit = 0x800 },
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+
{ /* VI_THI MMIO */ .base = 0x16c0, .offset = 0x30, .limit = 0x34 },
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+
{ /* ISP_THI MMIO */ .base = 0x16c8, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVDLA MMIO */ .base = 0x16d8, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVDLA ch */ .base = 0x17e0, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVDLA1 MMIO */ .base = 0x16e0, .offset = 0x30, .limit = 0x34 },
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+
{ /* NVDLA1 ch */ .base = 0x17e8, .offset = 0x30, .limit = 0x34 },
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+
{ /* OFA MMIO */ .base = 0x16e8, .offset = 0x34, .limit = 0x34 },
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+
{ /* OFA ch */ .base = 0x1768, .offset = 0x30, .limit = 0x30 },
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+
{ /* VI2 MMIO */ .base = 0x16f0, .offset = 0x800, .limit = 0x800 },
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+
{ /* VI2_THI MMIO */ .base = 0x16f8, .offset = 0x30, .limit = 0x34 },
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};
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static const struct host1x_info host1x08_info = {